Semiconductor Devices

Abstract

To reduce the consumption power and operation delay in a semiconductor integrated circuit.SOLUTION: Each 21_x of a plurality of sequential circuits 21_1 to 21_n included in a storage circuit 10 includes a transistor 31 whose channel formation region is formed of an oxide semiconductor, and a capacitor element 332 that makes a node in a floating state when the transistor is turned off, the node being electrically connected to one electrode. By the channel formation region of the transistor formed of the oxide semiconductor, the transistor whose off current (leak current) is extremely low can be realized. Therefore, by turning off the transistor in a period for which the power source voltage is not supplied to the storage circuit, the potential of the node electrically connected to the one electrode of the capacitor element in that period can be kept constant or substantially constant.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor integrated circuit. In particular, the semiconductor integrated circuit is configured using a sequential circuit. The power supply voltage to the memory circuit is controlled (power gating). The present invention relates to a semiconductor integrated circuit capable of [Background technology]

[0002] The scale of semiconductor integrated circuits with logic circuits is expanding year by year. When the computer was created, it consisted of only a few elements, but now it is composed of a CPU (Central Processor). Processing Unit) and DSP (Digital Signal Processing Unit) Some devices, such as a semiconductor laser, are made up of tens of millions of elements. Although the power consumption per element has decreased due to the trend toward higher speed and lower voltage, As the number of chips increases, the power consumption of the entire integrated circuit is also increasing. As a method to reduce the clock frequency, clock gating is used to partially stop the clock. Methods have been developed to reduce the number of chips and to partially reduce the power supply voltage.

[0003] Power consumption also includes the charge generated by switching elements such as transistors. Not only the operating power due to discharge, but also the leakage current when the device is off This static power is almost non-existent in integrated circuits with a small number of elements. However, in integrated circuits with a huge number of elements, the magnitude becomes unignorable. In contrast, a method for controlling the supply of power supply voltage to a circuit included in an integrated circuit (power gate) This will reduce power consumption due to leakage current. It is possible.

[0004] For example, Patent Document 1 discloses a semiconductor integrated circuit capable of performing power gating. Specifically, a transistor is provided between the logic circuit and the power supply line, By controlling the switching of the transistor, the supply of power supply voltage to the logic circuit is A controllable semiconductor integrated circuit is disclosed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-268694 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the logic circuit may contain a memory circuit (such as a register) that is configured using multiple sequential circuits. When the power gating is performed, the contents stored in the memory circuit are erased. In fact, in the logic circuits included in current semiconductor integrated circuits, It is common sense to use a lot of circuits, and power gating can be used to In this case, when the supply of power supply voltage to the memory circuit is resumed, In other words, it is necessary to perform the same calculation twice. Therefore, the power consumption reduction effect obtained by power gating is diluted. Furthermore, the operation of the semiconductor integrated circuit cannot be resumed until the operation is completed. This causes a delay in the operation of the semiconductor integrated circuit.

[0007] In view of the above-described problems, one embodiment of the present invention provides a semiconductor integrated circuit having a power consumption reducing function. Another object of one embodiment of the present invention is to reduce a delay in operation of a semiconductor integrated circuit. An object of one embodiment of the present invention is to achieve at least one of the above-described objects. The objective is to solve the following. [Means for solving the problem]

[0008] At least one of the above-mentioned problems is that in each of a plurality of sequential circuits included in a memory circuit, a transistor in which a channel formation region is formed using an oxide semiconductor; When the node is turned off, the node to which one electrode is electrically connected is in a floating state. This problem can be solved by providing a capacitor. , it has a wider band gap than silicon and a lower intrinsic carrier density than silicon. The channel formation region of a transistor is formed of such an oxide semiconductor. This makes it possible to realize a transistor with extremely low off-state current (leakage current). Therefore, in a period when the power supply voltage is not supplied to the memory circuit, the transistor By turning off the capacitor, one electrode of the capacitor is electrically connected during the period. As a result, the potential of the memory circuit can be kept constant or nearly constant. Therefore, when the supply of the power supply voltage is resumed, it is not necessary to perform calculations again. In the semiconductor integrated circuit of the embodiment, there is no power consumption or operational delay associated with the calculation, etc. , it is possible to solve the above-mentioned problems.

[0009] In addition, the oxide semiconductor contains water or hydrogen, which can act as an electron donor. An i-type (intrinsic) semiconductor with reduced impurity concentration or an oxide semiconductor that is as close to i-type as possible (pu Specifically, the oxide semiconductor is preferably a secondary oxide semiconductor. Secondary Ion Mass Spectros (SIMS) The hydrogen concentration measured by the 19 (atoms / cm 3 )The following are preferred Or 5 x 10 18 (atoms / cm 3 ) or less, more preferably 5 × 10 17 (ato ms / cm 3 ) or less. In addition, the oxide semiconductor The carrier density is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 Less than, More preferably, 1×10 11 / cm 3 The band gap of oxide semiconductors is less than is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more.

[0010] Here, Secondary Ion Mass Spectrometry (SIMS) This section explains the analysis of hydrogen concentration using SIMS (Semiconductor Ion Microscopy). In principle, it is possible to obtain accurate data near the sample surface and near the interface between layers of different materials. Therefore, the distribution of hydrogen concentration in the film in the thickness direction is When analyzing by SIMS, there is no extreme fluctuation in the values ​​within the range where the target film exists. The average value in the region where a nearly constant value is obtained is used as the hydrogen concentration. When the thickness of the film to be measured is small, the hydrogen concentration in the adjacent film is affected and the thickness is almost uniform. In some cases, it may not be possible to find a region where a certain value can be obtained. The maximum or minimum value of the hydrogen concentration in the film is used as the hydrogen concentration in the film. In the region where the film exists, a mountain-shaped peak having a maximum value and a valley-shaped peak having a minimum value are formed. If no peak exists, the value at the inflection point is taken as the hydrogen concentration.

[0011] The oxide semiconductor is an In-Sn-Ga-Zn-O oxide, which is a quaternary metal oxide. Semiconductors, ternary metal oxides, In-Ga-Zn-O oxide semiconductors, In-Sn-Z nO-based oxide semiconductors, In-Al-Zn-O-based oxide semiconductors, Sn-Ga-Zn-O-based Oxide semiconductors, Al-Ga-Zn-O oxide semiconductors, Sn-Al-Zn-O oxide semiconductors Conductors, binary metal oxides such as In-Zn-O oxide semiconductors and Sn-Zn-O oxides Semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg-O oxide semiconductors, Sn-Mg- O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-Ga-O-based oxide semiconductors, and In-O based oxide semiconductors, Sn-O based oxide semiconductors, Zn-O based oxide semiconductors, etc. In this specification, for example, an In—Sn—Ga—Zn—O system Oxide semiconductors are made of indium (In), tin (Sn), gallium (Ga), and zinc (Zn). The composition ratio is not particularly limited. The semiconductor may include silicon.

[0012] In this specification, the oxide semiconductor is, for example, an oxide semiconductor represented by the chemical formula InMO3(ZnO) m ( m>0), where M is selected from Ga, Al, Mn, and Co. It refers to one or more metallic elements. [Effects of the Invention]

[0013] In the semiconductor integrated circuit of one embodiment of the present invention, In each of the plurality of sequential circuits included in the memory circuit, the potential of a specific node The potential held at the node can be held in the sequential circuit. In other words, the semiconductor device according to one aspect of the present invention can be In the integrated circuit, when the supply of power supply voltage to the memory circuit is resumed, the operation is restarted. As a result, the semiconductor integrated circuit according to one embodiment of the present invention can reduce power consumption. It is possible to reduce the number of operations and delays in operation. [Brief explanation of the drawings]

[0014] [Figure 1] 1A to 1C are diagrams showing configuration examples of a semiconductor integrated circuit. [Figure 2] 1A to 1H illustrate an example of a method for manufacturing a transistor. [Figure 3] 1A to 1C are diagrams illustrating a method for measuring the off-state current of a transistor. [Figure 4] (A) and (B) Transistor characteristics. [Figure 5] FIG. 10 is a diagram showing characteristics of a transistor. [Figure 6] FIG. 10 is a diagram showing characteristics of a transistor. [Figure 7] FIG. 10 is a diagram showing characteristics of a transistor. [Figure 8] FIG. 10 is a diagram showing characteristics of a transistor. [Figure 9] FIG. 1 is a diagram showing a specific example of a sequential circuit. [Figure 10] FIG. 10 is a diagram showing an example of the operation of a sequential circuit. [Figure 11] 1A to 1C illustrate specific examples of transistors. [Figure 12] 1A to 1H are diagrams illustrating an example of a specific manufacturing process of a transistor. [Figure 13] 1A to 1G illustrate an example of a specific manufacturing process of a transistor. [Figure 14] 1A to 1D are diagrams illustrating an example of a specific manufacturing process of a transistor. [Figure 15] 10A to 10C illustrate modified examples of a transistor. [Figure 16] 1A and 1B are diagrams showing modified examples of a transistor. [Figure 17] 1A and 1B are diagrams showing modified examples of a transistor. [Figure 18] 1A and 1B are diagrams showing modified examples of a transistor. [Figure 19] 10A to 10C illustrate modified examples of a transistor. [Figure 20] 10A to 10C illustrate modified examples of a transistor. [Figure 21] 10A to 10C are diagrams illustrating a modified example of the process for forming an oxide semiconductor layer. [Figure 22] FIG. 1 is a diagram showing a specific example of a CPU. [Figure 23] (A) to (E) Diagrams explaining the crystal structure of oxide materials. [Figure 24] (A) to (C) are diagrams illustrating the crystal structure of oxide materials. [Figure 25] (A) to (C) are diagrams illustrating the crystal structure of oxide materials. [Figure 26] FIG. 10 is a diagram illustrating the gate voltage dependence of mobility obtained by calculation. [Figure 27] 10A to 10C are diagrams illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 28] 1A to 1C are diagrams illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 29] 1A to 1C are diagrams illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 30] 1A and 1B are diagrams illustrating the cross-sectional structure of a transistor used in calculations. [Figure 31] 1A to 1C are graphs showing characteristics of a transistor including an oxide semiconductor. [Figure 32] 1A and 1B are graphs showing the characteristics of a transistor including an oxide semiconductor. [Figure 33] 1A and 1B are graphs showing the characteristics of a transistor including an oxide semiconductor. [Figure 34] XRD spectrum of oxide semiconductor. [Figure 35] 10A to 10C show characteristics of a transistor including an oxide semiconductor. [Figure 36] 10A to 10C show characteristics of a transistor including an oxide semiconductor. [Figure 37] 1A and 1B are graphs showing the characteristics of a transistor including an oxide semiconductor. [Figure 38] (A) and (B) are a cross-sectional view and a plan view of a transistor including an oxide semiconductor. [Figure 39] (A) and (B) are a cross-sectional view and a plan view of a transistor including an oxide semiconductor. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications may be made without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments.

[0016] <Configuration example of semiconductor integrated circuit> First, a configuration example of a semiconductor integrated circuit according to one embodiment of the present invention will be described with reference to FIGS. 1A to 1C. This will be explained in light of the above.

[0017] FIG. 1(A) is a block diagram showing an example of the configuration of a semiconductor integrated circuit. The semiconductor integrated circuit includes an arithmetic circuit 10 and data obtained by the arithmetic circuit 10. a power gate that controls the supply of power supply voltage to the memory circuit 11; and a control circuit 12.

[0018] FIG. 1B is a specific example of the memory circuit 11 and the power gate control circuit 12 shown in FIG. 1A. 1B is a diagram showing an example of a configuration of a memory circuit 11. The memory circuit 11 shown in FIG. A clock signal (CKB), a high power supply potential (VDD), and a low power supply potential (VSS) are supplied. sequential circuits 21_1 to 21_n (n is a natural number of 3 or more) that can operate in a state where , and can operate when high power supply potential (VDD) and low power supply potential (VSS) are supplied. The circuit has combinational circuits 22_1 to 22_n.

[0019] The sequential circuit 21_1 has an input terminal electrically connected to the input terminal of the memory circuit 11, The output terminal is electrically connected to the input terminal of the combinational circuit 22_1. 1_a (a is a natural number between 2 and n) is a combinational circuit 22_a-1 whose input terminal is the output terminal of the combinational circuit 22_a-1. The output terminal is electrically connected to the input terminal of the combinational circuit 22_a. The combinational circuit 22_n has an output terminal electrically connected to the output terminal of the storage circuit 11. are connected to the network.

[0020] The power gate control circuit 12 shown in FIG. 1B controls the gate of the power gate transistor 20. The sequential circuits 21_1 to 21_n are connected to the power gating control signal (PG) A set signal (SET), a reset signal (RES), and a first transfer signal ( It is possible to output a first transfer signal (TS1) and a second transfer signal (TS2). The gate transistor 20 has a drain connected to the sequential circuits 21_1 to 21_n and the combinational circuit 2 2_1 to 22_n are electrically connected to the wiring that supplies the low power supply potential (VSS) to each of them. The source is electrically connected to the low power supply potential (VSS). By switching on the power gate transistor 20, the sequential circuits 21_1 to 21_n and and supplying a low power supply potential (VSS) to each of the combinational circuits 22_1 to 22_n. The first transfer signal (TS1) can be controlled by the sequential circuits 21_1 to 21_2. The data stored in the 1_n channel is stored in the oxide semiconductor. The transistor configured in the The second transfer signal (TS2) is a signal for transferring the data from the node. This is a signal to

[0021] In FIG. 1B, sequential circuits 21_1 to 21_n and combinational circuits 22_ Regarding the configuration that controls the supply of low power supply potential (VSS) for each of 1 to 22_n However, the configuration for controlling the supply of high power supply potential (VDD) or low power supply potential (VSS) and It is also possible to configure the circuit to control the supply of the high power supply potential (VDD). Each of the introductory circuits 21_1 to 21_n and the combinational circuits 22_1 to 22_n and a high power supply A power gate transistor is provided between the power supply and the wiring that supplies the potential (VDD). It is also possible.

[0022] FIG. 1C shows a sequential circuit 21_x (x is a natural number between 1 and n) shown in FIG. 1B. 1C is a diagram illustrating an example of the configuration of a sequential circuit 21_x having an input terminal The sequential circuit 21_x has an input terminal electrically connected to the input terminal of the sequential circuit 21_x, and an output terminal electrically connected to the output terminal of the sequential circuit 21_x. a flip-flop 30 electrically connected to the input terminal, and a gate of the flip-flop 30 receiving a first transfer signal (TS1) The flip-flop 30 has one of its source and drain electrically connected to the wiring that supplies the The other of the source and drain is electrically connected to a first node, which is a node of the a transistor 31 electrically connected to a second node, which is a node within the flop 30; One electrode is electrically connected to the second node and the other to the source and drain of transistor 31. The other electrode is electrically connected to a wiring that supplies a fixed potential (Vcom). The transistor 31 has a channel formation region formed of an oxide semiconductor. The fixed potential (Vcom) is the power gate potential. It is sufficient if the potential always shows a constant value regardless of whether or not switching is performed. Apply high power supply potential (VDD) or low power supply potential (VSS) as the potential (Vcom). In this case, it is necessary to generate a new potential as a fixed potential (Vcom). It is preferable to use the low power supply potential (VSS) as the fixed potential (Vcom). In this case, the low power supply potential (Vcom) is supplied to the sequential circuit 21_x as a fixed potential (Vcom). VSS) provides power gating to the logic gates included in the flip-flop 30. It is necessary to control the sequential circuit 21_x so that it is supplied even during the period when the sequential circuit 21_x is being executed. The low power supply potential (VSS) is supplied as a fixed potential (Vcom) to the flip-flop. A separate supply path for the low power supply potential (VSS) supplied to the logic gates included in group 30 is provided. It would be better to provide such a system.

[0023] In addition, here, one of the source and drain (first node) of the transistor 31 is The high power supply voltage is applied through the transistors that make up the logic gates included in the flip-flop 30. It is electrically connected to the wiring that supplies the power supply potential (VDD) or the wiring that supplies the low power supply potential (VSS). The other of the source and drain of the transistor 31 and the capacitance element 3 One of the electrodes (second node) of the two electrodes cannot be electrically connected to these wirings. For example, the former is a logic gate included in at least flip-flop 30. The source or drain of one of the plurality of transistors constituting the gate is electrically connected to the gate. The latter is designed to electrically connect all of the sources and drains of the plurality of transistors. and electrically connected to at least one gate of the plurality of transistors. That is, in the sequential circuit 21_x shown in FIG. In this case, when the transistor 31 is turned off, the source and The other electrode of the drain and one electrode of the capacitance element 32 are electrically connected to a node (second node). It is possible to make the battery (or battery) floating.

[0024] That is, in the sequential circuit 21_x shown in FIG. 1C, the first transfer signal (TS1) When a high-level potential is supplied as The other of the source and drain of the transistor 31 and one of the electrodes of the capacitor element 32 are electrically connected. The data is transferred to a second node that is connected to the second node, and the data is stored in that node. It is possible to do so.

[0025] Here, each of the sequential circuits 21_1 to 21_n includes a transistor 31 and a capacitor Although the configuration in which the element 32 is provided has been shown, all of the sequential circuits 21_1 to 21_n are That is, the m sequential circuits 21_1 to 21_n included in the sequential circuits 21_1 to 21_n do not need to have the same configuration. A transistor 31 and a capacitance element 32 are provided only in the circuit (m is a natural number equal to or greater than 1 and less than n). In this case, the transistor 31 and the capacitor 32 For a sequential circuit that is not provided with a first transfer signal (TS1) and a second transfer signal Note that (TS2) does not need to be provided.

[0026] <Off-state current of a transistor whose channel formation region is formed using an oxide semiconductor> Here, the off-state current of a transistor in which a channel formation region is formed using an oxide semiconductor is The results of measuring the leakage current are shown below.

[0027] First, a method for manufacturing the transistor used in the above measurement will be described with reference to FIGS.

[0028] First, a silicon nitride layer having a thickness of 100 nm and an oxide layer having a thickness of 150 nm were formed on a glass substrate 50. An underlayer 51 consisting of a stack of silicon nitride layers was formed by CVD (see FIG. 2(A)). ).

[0029] Next, a tungsten layer having a thickness of 100 nm is formed on the underlayer 51 by sputtering. Furthermore, the tungsten layer was selectively etched using photolithography. The gate layer 52 was formed by etching (see FIG. 2(B)).

[0030] Next, a silicon oxynitride layer having a thickness of 100 nm is deposited on the underlayer 51 and the gate layer 52. A gate insulating layer 53 made of SiO 2 was formed by the CVD method (see FIG. 2(C)).

[0031] Next, a 25 nm thick oxide semiconductor layer was formed on the gate insulating layer 53 by sputtering. The oxide semiconductor layer was formed by the following method. A metal oxide target of 1:1:2 [mol] was used. The composition was carried out under the conditions of a substrate temperature of 200°C, a chamber pressure of 0.6 Pa, a DC power supply of 5 kW, and oxygen and Argon mixed atmosphere (oxygen flow rate 50sccm, argon flow rate 50sccm) Furthermore, the oxide semiconductor layer is selectively formed by photolithography. The oxide semiconductor layer 54 was formed by selectively etching the silicon dioxide film 51 (see FIG. 2D).

[0032] Then, the mixture was heated at 450°C for 1 hour in a mixed atmosphere of nitrogen and oxygen (80% nitrogen, 20% oxygen). The heat treatment was carried out.

[0033] Next, the gate insulating layer 53 was selectively etched using photolithography ( (Not shown). Note that this etching step is performed to remove the gate layer 52 and the conductive layer to be formed later. This is a process for forming the contact holes.

[0034] Next, a titanium layer having a thickness of 100 nm is formed on the gate insulating layer 53 and the oxide semiconductor layer 54. A 200 nm thick aluminum layer and a 100 nm thick titanium layer are sputtered. Furthermore, the stacked layer was selectively etched using a photolithography method. By this, a source layer 55a and a drain layer 55b were formed (see FIG. 2(E)).

[0035] Next, a heat treatment was carried out in a nitrogen atmosphere at 300° C. for 1 hour.

[0036] Next, the gate insulating layer 53, the oxide semiconductor layer 54, the source layer 55a, and the drain layer 55 A protective insulating layer 56 made of a silicon oxide layer having a thickness of 300 nm was formed on the insulating layer 5b. The protective insulating layer 56 was selectively etched using photolithography (see FIG. 2(F)). (See reference). The etching process is performed to remove the gate layer, source layer, drain layer, and the subsequent This is a step for forming contact holes with the conductive layer to be formed.

[0037] Next, an acrylic layer having a thickness of 1.5 μm is applied onto the protective insulating layer 56, and the acrylic layer is A planarization insulating layer 57 was formed by selectively exposing the film to light (see FIG. 2(G)). Heat treatment at 250°C for 1 hour in a nitrogen atmosphere creates a flat insulating film made of an acrylic layer. Layer 57 was baked.

[0038] Next, a titanium layer having a thickness of 200 nm is formed on the planarizing insulating layer 57 by sputtering. Furthermore, the titanium layer was selectively etched using photolithography. This allows for a conductive layer (not shown) connected to the gate layer 52 and a conductive layer (not shown) connected to the source layer 55a. A conductive layer 58b connected to the drain layer 55b and the gate electrode 58a was formed (see FIG. 2H).

[0039] Next, a heat treatment was carried out in a nitrogen atmosphere at 250° C. for 1 hour.

[0040] The transistor used in the above measurement was fabricated through the above steps.

[0041] Furthermore, the calculation method for the off-state current value using the characteristic evaluation circuit used in the above measurement is as follows: will be explained.

[0042] The current measurement using the characteristic evaluation circuit will be explained using Figure 3. FIG. 1 is a diagram for explaining a circuit.

[0043] First, the circuit configuration of the characteristic evaluation circuit will be explained using FIG. 3(A). 1 is a circuit diagram showing the circuit configuration of a characteristic evaluation circuit.

[0044] The characteristic evaluation circuit shown in FIG. 3A includes a plurality of measurement systems 801. 1 are connected in parallel to each other. In this example, eight measurement systems 801 are connected in parallel. By using multiple measurement systems 801, multiple measurements can be performed simultaneously. .

[0045] The measurement system 801 includes a transistor 811, a transistor 812, a capacitance element 813, and The transistor 814 and the transistor 815 are included.

[0046] Transistor 811, transistor 812, transistor 814, and transistor 8 15 is an N-channel field effect transistor.

[0047] A voltage V1 is input to one of the source and drain of the transistor 811. A voltage Vext_a is input to the gate of the transistor 811. The transistor 811 This is an injection transistor.

[0048] One of the source and drain of the transistor 812 is connected to the source and drain of the transistor 811. The other of the source and drain of the transistor 812 is connected to a voltage The voltage V2 is input to the gate of the transistor 812, and the voltage Vext_b is input to the gate of the transistor 813. The transistor 812 is a transistor for evaluating the leakage current. The current is a leakage current including an off-state current of the transistor.

[0049] One electrode of the capacitor 813 is connected to the other of the source and the drain of the transistor 811. The other electrode of the capacitor 813 is connected to the capacitor 814, and a voltage V2 is input to the other electrode of the capacitor 813. The voltage V2 is 0V.

[0050] A voltage V3 is input to one of the source and drain of the transistor 814. The gate of the transistor 814 is connected to the other of the source and drain of the transistor 811 . The gate of the transistor 814 and the other of the source and drain of the transistor 811 , one of the source and drain of the transistor 812, and one electrode of the capacitor 813 The connection point is also referred to as node A. Here, voltage V3 is 5V.

[0051] One of the source and drain of the transistor 815 is connected to the source and drain of the transistor 814. The other of the source and drain of the transistor 815 is connected to a voltage V4 is input, and the voltage Vext_c is input to the gate of the transistor 815. Here, the voltage Vext_c is 0.5V.

[0052] Furthermore, the measurement system 801 detects the other of the source and drain of the transistor 814 and the The voltage at the connection point between the source and the drain of the resistor 815 is the output voltage Vout. Output.

[0053] Here, the transistor 811 is formed by the manufacturing method described with reference to FIG. A transistor having a channel length L=10 μm and a channel width W=10 μm is used.

[0054] The transistors 814 and 815 are the transistors fabricated using the transistors fabricated in accordance with the method described with reference to FIG. A transistor having a channel length L=3 μm and a channel width W=100 μm formed by the method. Use Sta.

[0055] At least the transistor 812 has a gate layer 52 and a semiconductor layer 53 as shown in FIG. The source layer 55a does not overlap the gate layer 52 and the drain layer 55b, and is offset by a width of 1 μm. By providing the offset region, it is possible to reduce the parasitic capacitance. Furthermore, the transistor 812 can be made of six transistors having different channel lengths L and channel widths W. A sample of three transistors (also called SMP) is used (see Table 1).

[0056] [Table 1]

[0057] As shown in Figure 3(A), a transistor for charge injection and a transistor for leakage current evaluation are By providing the transistor for leak current evaluation separately, It can always be left off.

[0058] In addition, a transistor for charge injection and a transistor for leak current evaluation are provided separately. This allows each transistor to be sized appropriately. The channel width W of the transistor for evaluating the current is set to the channel width W of the transistor for charge injection. By making it larger than the leakage current evaluation transistor, it is possible to evaluate characteristics other than the leakage current. As a result, the leakage current component of the valence circuit can be relatively small. The leakage current of the transistor can be measured with high accuracy. In addition, since there is no need to turn on the transistor for leak current evaluation, There is no effect of voltage fluctuations at node A due to some of the charge in the region flowing into node A.

[0059] Next, we will explain the leakage current measurement method for the characteristic evaluation circuit shown in Figure 3(A) using Figure 3(C). FIG. 3(C) shows the leakage current measurement method using the characteristic evaluation circuit shown in FIG. 3(A). 10 is a timing chart for explaining the method.

[0060] The leakage current measurement method using the characteristic evaluation circuit shown in FIG. 3(A) is performed during the write period and the hold period. The operation in each period is explained below.

[0061] During the write period, the voltage Vext_b is set so that the transistor 812 is in an off state. Input the voltage VL (-3V) as shown below. Also, input the write voltage Vw as the voltage V1. Then, the voltage Vext_a is set to a voltage that turns on the transistor 811 for a certain period of time. This causes a charge to accumulate at node A, and the voltage at node A After that, the voltage Vext_a is set to a value equivalent to the write voltage Vw. Then, a voltage VL is input so that the capacitor 811 is turned off. Input SS (0V).

[0062] During the retention period, the voltage at node A changes due to the change in the amount of charge held by node A. The amount of change in voltage is measured. From the amount of change in voltage, the source and drain of the transistor 812 are determined. The current flowing between node A and node B can be calculated. It is possible to measure the amount of change in voltage at node A.

[0063] At this time, the charge accumulation at node A and the change in the voltage at node A are measured (accumulation and measurement operations). First, the first accumulation and measurement operation is repeated 15 times. In the accumulation and measurement operation of 1, a voltage of 5 V is input as the write voltage Vw during the write period. The holding period is then held for one hour. Next, the second accumulation and measurement operation is repeated twice. In the second accumulation and measurement operation, a voltage of 3.5 V was applied as the write voltage Vw during the write period. Then, the third accumulation and measurement operation is performed once. In the third accumulation and measurement operation, a voltage of 4.5 V is applied as the write voltage Vw during the write period. The data is stored for 10 hours. It can be confirmed that the measured current value is a value in a steady state. Then, the current I flowing through node A A Among these, the transient current (which decreases over time after measurement begins) As a result, leakage current can be measured with higher accuracy. It is possible.

[0064] In general, the voltage at node A, V A is expressed as a function of the output voltage Vout as shown in equation (1). can be.

[0065]

number

[0066] Also, the charge Q at node A A is the voltage at node A, VA , capacitance C connected to node A A , Using a constant (const), it is expressed as in equation (2). Capacity C A is the sum of the capacitance of the capacitor 813 and the capacitance components other than the capacitor 813.

[0067]

number

[0068] Current I at node A A is the charge flowing into (or out of) node A Since this is the time derivative of the current I A is expressed as in equation (3).

[0069]

number

[0070] In this example, Δt is set to approximately 54,000 seconds. Capacity C A and the leakage current I at node A from the output voltage Vout A Seeking This allows the leakage current of the characteristic evaluation circuit to be determined.

[0071] Next, the output voltage measurement results using the above characteristic evaluation circuit and the results of the measurement The leakage current value of the characteristic evaluation circuit calculated using this method will be explained with reference to FIG.

[0072] Figure 4(A) shows the results of the above measurements of transistors in SMP4, SMP5, and SMP6. 1 shows the relationship between the elapsed time Time and the output voltage Vout in the first accumulation and measurement operation. 4B shows the elapsed time Time for the above measurement and the current I calculated by the measurement. A The output voltage Vout fluctuates from the start of measurement, and the It turns out that more than 10 hours are required to achieve this.

[0073] In addition, Figure 5 shows the estimated values ​​for SMP1 to SMP6 from the values ​​obtained by the above measurements. In Figure 5, the relationship between the voltage at node A and the leakage current is shown. When the voltage of node A is 3.0V, the leakage current is 28yA / μm. Since the off-current of the transistor 812 is also included, the off-current of the transistor 812 is also 28 yA. / μm or less.

[0074] 6 to 8 show the results of the measurements at 85°C, 125°C, and 150°C. The relationship between the voltage at node A and the leakage current in SMP1 to SMP6 is shown in FIG. As shown in Fig. 8, even at 150°C, the leakage current was less than 100 zA / µm. It turns out to be below.

[0075] As described above, a transistor in which a channel formation region is formed using an oxide semiconductor is used. In the characteristic evaluation circuit, the leakage current was sufficiently low, so the off-state current of the transistor In addition, the off-state current of the transistor is However, it is clear that this is sufficiently low.

[0076] <Regarding the semiconductor integrated circuit disclosed in this specification> The semiconductor integrated circuit disclosed in this specification is configured to operate when a power supply voltage is not supplied to a memory circuit. In each of the plurality of sequential circuits included in the memory circuit, a specific node ( The other of the source and the drain of the transistor 31 and one of the capacitors 32 shown in FIG. The potential of the node (the node to which the other electrode is electrically connected) can be maintained. The potential held at the node can be made to correspond to the data held in the sequential circuit. That is, in the semiconductor integrated circuit disclosed in this specification, the memory circuit When the supply of power voltage is resumed, there is no need to perform calculations again. The semiconductor integrated circuit disclosed in the specification aims to reduce power consumption and operational delay. It is possible to do this.

[0077] <Example> Specific examples of the above-mentioned semiconductor integrated circuit will be described with reference to FIGS.

[0078] <Sequential circuit 21_x> FIG. 9 is a diagram showing a specific example of the sequential circuit 21_x shown in FIG. 1(C). The circuit 21_x includes a transistor 31, a capacitance element 32, and NAND gates 210a to 210b. 10f, AND gates 211a and 211b, and switches 212a to 212d. The connection relationships between the two circuits are self-evident when referring to FIG. 9. A detailed description of the connection relationship between the source and drain of the transistor 31 will be omitted. A node electrically connected to the other electrode of the capacitor 32 and one electrode of the capacitor 32 is referred to as a node N. The data holding operation at the node N will be explained below.

[0079] FIG. 10 shows a data storage state at the node N of the sequential circuit 21_x shown in FIG. 10 is a diagram illustrating an example of an operation when the period T1 and T3 are periods during which the power gating signal (PG) indicates a high level potential (power supply The period T1 is a period during which the power gating signal (PG) indicates a low level potential. This is the period during which power is cut off.

[0080] During the period T1, the data held by the sequential circuit 21_x is read out prior to clock gating. In order to determine the data, a clock signal (CK) is supplied to the sequential circuit 21_x. Then, a high-level potential is supplied as the first transfer signal (TS1). As a result, the data held by the sequential circuit 21_x is transferred to the node N.

[0081] During the period T2, the power supply voltage is supplied to each logic gate of the sequential circuit 21_x. Therefore, the data of the sequential circuit 21_x is in an undefined state (Z). The data held in node N will not be lost.

[0082] In the period T3, a high-level potential is supplied as the second transfer signal (TS2). As a result, the data in the sequential circuit 21_x is restored. By restarting the supply of the sequential circuit 21_x, the operation of the semiconductor integrated circuit having the sequential circuit 21_x is restarted early. It is possible.

[0083] <Transistor> The above-mentioned semiconductor integrated circuit is composed of a large number of transistors. The number of transistors required for each transistor is It is possible to select an appropriate value depending on the characteristics, etc. For example, in the above-mentioned semiconductor integrated circuit, The logic included in the sequential circuits 21_1 to 21_n and the combinational circuits 22_1 to 22_n is The transistor that constitutes the gate is required to operate at high speed. Examples of the material include single crystal silicon, polycrystalline silicon, and gallium arsenide (GaAs). It is preferable to use a transistor in which a channel forming region is formed of a compound semiconductor. In addition, the power gate transistor 20 is required to have a low off-current (leak current). Therefore, the transistor has a channel formed of the above-described oxide semiconductor. It is preferable to apply a transistor in which a formation region is configured.

[0084] In view of the above, an example of a transistor included in a semiconductor integrated circuit will be described. In general, transistors and semiconductor devices formed using substrates containing semiconductor materials such as single crystal silicon and an example of a semiconductor integrated circuit including a transistor formed using an oxide semiconductor. show.

[0085] FIG. 11 is a diagram illustrating an example of a transistor included in a semiconductor integrated circuit. The transistor 160 includes a channel forming region 11 provided in a substrate 100 including a semiconductor material. 6 and a pair of impurity regions 114a and 116 provided on either side of the channel forming region 116. 4b and a pair of high concentration impurity regions 120a and 120b (collectively referred to as impurity regions a gate insulating layer 108 provided on the channel forming region 116; A gate layer 110 provided on the insulating layer 108 and a semiconductor layer electrically connected to the impurity region 114a are provided. and a drain layer 130b electrically connected to the impurity region 114b. do.

[0086] Sidewall insulating layers 118 are provided on the side surfaces of the gate layer 110. In the region of the substrate 100 including the semiconductor material that does not overlap with the sidewall insulating layer 118, There are a pair of high concentration impurity regions 120a and 120b. A pair of metal compound regions 124a and 124b are present on the substrate 100. An element isolation insulating layer 106 is provided on the transistor 160 so as to surround the transistor. The interlayer insulating layer 126 and the interlayer insulating layer 128 are provided to cover the resistor 160. The source layer 130a and the drain layer 130b are formed between the interlayer insulating layer 126 and the interlayer insulating layer 128. The metal compound regions 124a and 124b are electrically connected to one of the pair of metal compound regions 124a and 124b through an opening formed in the metal compound region 124a. That is, the source layer 130a is connected to the high concentration The drain layer 130b is electrically connected to the impurity region 120a and the impurity region 114a. The high concentration impurity region 120b and the impurity region 114b are connected via the metal compound region 124b. b is electrically connected to

[0087] The transistor 164 shown in FIG. 11 includes a gate layer 136 provided on an interlayer insulating layer 128. d, a gate insulating layer 138 provided on the gate layer 136d, and an oxide semiconductor layer 140 provided on the oxide semiconductor layer 140; The source layer 142a and the drain layer 142b are electrically connected to the layer 140. .

[0088] Here, the gate layer 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate layer 136d, the transistor 160 is formed in the The electrode layer 136a contacts the source layer 130a and the electrode layer 136b contacts the drain layer 130b. 136b is formed.

[0089] In addition, a protective film is provided on the transistor 164 so as to be in contact with part of the oxide semiconductor layer 140. A protective insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with the source layer 142a and An opening is provided that reaches the drain layer 142b, and the source layer 1 An electrode layer 150d in contact with the drain layer 142a and an electrode layer 150e in contact with the drain layer 142b are formed. In addition, the gate insulating layer 138, the protective insulating layer 138, and the electrode layer 150d and the electrode layer 150e are An electrode contacting the electrode layer 136a through an opening provided in the edge layer 144 and the interlayer insulating layer 146 is formed. An electrode layer 150b is formed in contact with the layer 150a and the electrode layer 136b.

[0090] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is highly purified. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 19 (atoms / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 18 (atoms / cm 3 ) or less, and 5 × 10 17 (atoms / cm 3 ) or less It is more preferable that the hydrogen concentration in the oxide semiconductor layer 140 is determined by the secondary ion mass. Secondary Ion Mass Spectroscop (SIMS) y).

[0091] An insulating layer 152 is provided on the interlayer insulating layer 146, and a semiconductor device is embedded in the insulating layer 152. Electrode layers 154a, 154b, and 154d are provided so as to be enclosed within the electrode layer 154a. The electrode layer 154a is in contact with the electrode layer 150a, and the electrode layer 154b is in contact with the electrode layer 150b. and electrode layer 150d, and electrode layer 154d is in contact with electrode layer 150e.

[0092] As shown in FIG. 11, the drain layer 130b of the transistor 160 has an upper layer region. Through the electrode layer 136b, the electrode layer 150b, the electrode layer 154b, and the electrode layer 150d The gate electrode 142 is electrically connected to the source layer 142 a of the transistor 164 .

[0093] <Example of manufacturing process> Next, an example of a method for manufacturing the transistor 160 and the transistor 164 will be described. First, a method for fabricating the P-type transistor 160 will be described below with reference to FIG. Then, a method for manufacturing the transistor 164 will be described with reference to FIGS. 13 and 14. do.

[0094] First, a substrate 100 containing a semiconductor material is prepared (see FIG. 12(A)). The substrate 100 may be a single crystal semiconductor substrate or a multi-crystal substrate such as silicon or silicon carbide. A crystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, or an SOI substrate is suitable. Here, a single crystal silicon substrate can be used as the substrate 100 containing a semiconductor material. In general, an "SOI substrate" is an insulating surface. The term "substrate" refers to a substrate having a silicon semiconductor layer on its surface. This also includes substrates having a semiconductor layer made of a material other than silicon on the surface. In other words, the semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. In addition, the SOI substrate has a semiconductor layer provided on an insulating substrate such as a glass substrate via an insulating layer. This also includes configurations in which

[0095] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 12(A)). The protective layer 102 is made of, for example, silicon oxide or silicon nitride. An insulating layer made of silicon nitride or silicon oxide can be used. Before and after, n-type conductivity is imparted to control the threshold voltage of the transistor. An impurity element or an impurity element that imparts p-type conductivity may be added to the substrate 100. In the case of silicon, impurities that give n-type conductivity include, for example, phosphorus and arsenic. In addition, impurities that impart p-type conductivity include, for example, boron, arsenic, and the like. Aluminum, gallium, etc. can be used.

[0096] Next, etching is performed using the protective layer 102 as a mask. The part of the substrate 100 in the area where the metal is not present (exposed area) is removed. The semiconductor region 104 is formed (see FIG. 12(B)). Although it is preferable to use etching gas, wet etching may also be used. The etching solution can be appropriately selected depending on the material to be etched.

[0097] Next, an insulating layer is formed so as to cover the semiconductor region 104, and an insulating layer is formed in a region overlapping the semiconductor region 104. The insulating layer in the region is selectively removed to form an element isolation insulating layer 106 (FIG. 12(B) The insulating layer is made of silicon oxide, silicon nitride, silicon nitride oxide, etc. The insulating layer is removed by chemical mechanical polishing (CMP). There are various processes such as polishing (e.g., polishing) and etching. After the semiconductor region 104 is formed or after the element isolation insulating layer 106 is formed, Afterwards, the protective layer 102 is removed.

[0098] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0099] The insulating layer will later become the gate insulating layer, and is formed using CVD or sputtering methods. Obtained silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide It is preferable to use a single layer or a laminated structure of a film containing tungsten oxide, tantalum oxide, etc. The surface of the semiconductor region 104 is oxidized or nitrided by plasma treatment or thermal oxidation treatment. The insulating layer may be formed by the high density plasma treatment. It is performed using a mixture of rare gases such as Xe and oxygen, nitrogen oxide, ammonia, nitrogen, etc. The thickness of the insulating layer is not particularly limited, but may be, for example, 1 nm or more and 100 nm or less. m or less.

[0100] The layer containing the conductive material is made of a metal material such as aluminum, copper, titanium, tantalum, or tungsten. The insulating layer can be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. The method for forming the conductive material is not particularly limited, and examples thereof include vapor deposition, Various film formation methods such as CVD, sputtering, and spin coating can be used. Here, an example in which a layer containing a conductive material is formed using a metal material will be described. This shall be shown.

[0101] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 10. 8. The gate layer 110 is formed (see FIG. 12(C)).

[0102] Next, an insulating layer 112 is formed to cover the gate layer 110 (see FIG. 12(C)). The semiconductor region 104 is doped with boron (B), phosphorus (P), arsenic (As), etc. to form a shallow junction. A pair of impurity regions 114a and 114b having the same length are formed (see FIG. 12(C)). By forming the impurity regions 114a and 114b, the gate insulating layer 108 of the semiconductor region 104 A channel forming region 116 is formed in the lower part (see FIG. 12(C)). The concentration of impurities can be set appropriately, but when transistors are highly miniaturized, In this case, it is desirable to increase the concentration of the insulating layer 112 after forming the insulating layer 112. The method employs a process for forming a pair of impurity regions 114a and 114b. The insulating layer 112 may be formed after the regions 114a and 114b are formed.

[0103] Next, the sidewall insulating layer 118 is formed (see FIG. 12(D)). The insulating layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then anisotropically insulating the insulating layer. By applying a highly efficient etching process, it is possible to form the film in a self-aligned manner. At this time, the insulating layer 112 is partially etched to expose the top surface of the gate layer 110 and a pair of impurities. Preferably, the upper surfaces of the object regions 114a and 114b are exposed.

[0104] Next, the gate layer 110, the pair of impurity regions 114a and 114b, and the sidewall insulating layer An insulating layer is formed to cover the pair of impurity regions 114a and 114b. Adding boron (B), phosphorus (P), arsenic (As), etc. to a part of b creates a pair of high-concentration Impurity regions 120a and 120b are formed (see FIG. 12(E)). The gate layer 110, the sidewall insulating layer 118, and the pair of high concentration impurity regions 120 are removed. A metal layer 122 is formed to cover the metal layers 120a, 120b, etc. (see FIG. 12(E)). 2 is formed using various film formation methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 can react with the semiconductor material that makes up the semiconductor region 104. It is desirable to form the metal layer using a metal material that forms a low-resistance metal compound. Examples of materials include titanium, tantalum, tungsten, nickel, cobalt, and platinum. be.

[0105] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A pair of metal compound regions 124a and 124b are in contact with the high concentration impurity regions 120a and 120b. The gate layer 110 is formed by using polycrystalline silicon or the like (see FIG. 12(F)). When using the metal compound region, the metal compound region is also formed in the portion of the gate layer 110 that contacts the metal layer 122. will be formed.

[0106] The heat treatment may be, for example, a heat treatment using a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is To improve the controllability of the reaction, it is necessary to use a method that can realize heat treatment for a very short time. It is desirable that the metal compound region is formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed by the metal compound. By doing so, the electrical resistance can be sufficiently reduced and the device characteristics can be improved. After forming the metal compound regions 124a and 124b, the metal layer 122 is removed.

[0107] Next, an interlayer insulating layer 126 and an interlayer insulating film 128 are formed to cover the respective components formed by the above-described steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by an oxide film. silicon oxide, silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, The insulating layer can be formed using a material containing an inorganic insulating material such as tantalum chloride. It is also possible to form the layer using organic insulating materials such as acrylic or the like. The structure is a two-layer structure of an interlayer insulating layer 126 and an interlayer insulating layer 128. After the interlayer insulating layer 128 is formed, the surface may be subjected to a process such as CMP or etching. It is desirable to flatten the surface by using a method such as

[0108] Thereafter, openings are formed in the interlayer insulating layer, reaching the pair of metal compound regions 124a and 124b. In the openings, a source layer 130a and a drain layer 130b are formed (FIG. 12( The source layer 130a and the drain layer 130b are formed by, for example, forming a P After forming a conductive layer using VD or CVD methods, etching and CMP are used. The insulating layer can be formed by removing a part of the conductive layer using a method.

[0109] When forming the source layer 130a and the drain layer 130b, the surfaces of the layers must be flat. For example, a titanium film or titanium nitride film is formed in the region including the opening. When a tungsten film is formed to fill the opening after forming a thin layer, By using CMP, unnecessary tungsten, titanium, titanium nitride, etc. are removed, and In this way, the flatness of the surface of the source layer 130a and the drain layer 130b can be improved. By planarizing the surface including the layer 130b, it is possible to form good electrodes, wiring, It is possible to form an insulating layer, a semiconductor layer, etc.

[0110] Here, the source layer 130 in contact with the pair of metal compound regions 124a and 124b is Although only the a and drain layers 130b are shown, in this process, An electrode layer and the like may also be formed. There is no particular limitation on the material that can be used as the conductive material, and various conductive materials can be used. For example, molybdenum, titanium, chromium, tantalum, tungsten, aluminum, Conductive materials such as copper, neodymium, and scandium can be used.

[0111] In this manner, the transistor 160 is formed using the substrate 100 containing a semiconductor material. After the above steps, electrodes, wiring, an insulating layer, etc. may be further formed. By adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, A highly integrated circuit can be provided.

[0112] Next, a transistor 164 is fabricated on the interlayer insulating layer 128 using FIGS. 13 and 14. 13 and 14 show the steps of forming various electrodes on the interlayer insulating layer 128. Since the manufacturing process of the electrode layer and the transistor 164 is shown, the transistor 164 The transistor 160 and other components present below are omitted.

[0113] First, an insulating layer 13 is formed on the interlayer insulating layer 128, the source layer 130a, and the drain layer 130b. The insulating layer 132 is formed by using a PVD method, a CVD method, or the like. In addition, silicon oxide, silicon nitride oxide, silicon nitride, and hafnium oxide can be used. The insulating layer is formed using a material containing an inorganic insulating material such as tungsten, aluminum oxide, or tantalum oxide. It is possible.

[0114] Next, the insulating layer 132 is doped with a material that reaches the source layer 130a and the drain layer 130b. At this time, an opening is also formed in the region where the gate layer 136d will be formed later. Then, a conductive layer 134 is formed so as to fill the opening (see FIG. 13(B)). The opening can be formed by etching using a mask. The mask can be formed by a method such as exposure using a photomask. Either wet etching or dry etching may be used for the etching. From the viewpoint of process efficiency, dry etching is preferably used. This can be done by using a film formation method such as a PVD method or a CVD method. Materials that can be used include molybdenum, titanium, chromium, tantalum, tungsten, Conductive materials such as aluminum, copper, neodymium, and scandium, as well as their alloys and compounds (e.g. nitrides) and the like.

[0115] More specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and C After forming a thin titanium nitride film by the VD method, a tungsten film is deposited to fill the opening. The titanium film formed by the PVD method can be formed by the following method. The oxide film at the interface is reduced, and the lower electrode layer (here, the source layer 130a and the drain layer 130b) is It also functions to reduce the contact resistance with the titanium nitride film formed thereafter. It has a barrier function that suppresses the diffusion of conductive materials. After forming the barrier film, a copper film may be formed by plating.

[0116] After the conductive layer 134 is formed, the conductive layer 134 is removed by a method such as etching or CMP. 134 is removed to expose the insulating layer 132, and the electrode layers 136a, 136b, A gate layer 136d is formed (see FIG. 13C). When the electrode layer 136a, the electrode layer 136b, and the gate layer 136d are formed by removing the In this way, the insulating layer 132, the electrode layer 136a, By planarizing the surfaces of the electrode layer 136b and the gate layer 136d, It becomes possible to form good electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0117] Next, a layer is formed on the insulating layer 132, the electrode layer 136a, the electrode layer 136b, and the gate layer 136d so as to cover the insulating layer 132, the electrode layer 136a, the electrode layer 136b, and the gate layer 136d. The gate insulating layer 138 is formed on the insulating layer 138 (see FIG. 13(D)). The gate insulating layer 138 can be formed by a deposition method, a sputtering method, or the like. , silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide It is preferable to form the film so as to contain aluminum, tantalum oxide, gallium oxide, etc. The insulating layer 138 may have a single layer structure or a multilayer structure. Silicon oxynitride was produced by plasma CVD using silane (SiH4), oxygen, and nitrogen. The gate insulating layer 138 can be formed from a material other than silicon. The thickness of the gate insulating layer 138 is particularly Although not limited thereto, it can be, for example, 10 nm or more and 500 nm or less. In this case, for example, a first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less and a first gate insulating layer having a film thickness of 100 nm or more and a second gate insulating layer having a film thickness of 100 nm or more and a film thickness of 100 nm or less are provided. It is preferable to form a second gate insulating layer having a thickness of 5 nm to 300 nm on the gate insulating layer. be.

[0118] Next, an oxide semiconductor layer is formed over the gate insulating layer 138 and etched using a mask. The oxide semiconductor layer is processed by a method such as etching to form an island-shaped oxide semiconductor layer 140. (See FIG. 13(E)).

[0119] The oxide semiconductor used contains at least indium (In) or zinc (Zn). It is preferable that the oxide semiconductor contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of transistors In addition, it is preferable to contain gallium (Ga). Also, tin (S) is used as a stabilizer. It is preferable that the stabilizer contains hafnium (Hf). It is also preferable that the stabilizer contains aluminum (Al). It's nice.

[0120] Other stabilizers include lanthanides such as lanthanum (La) and cerium. (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium Eu, Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), aluminium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), It may contain one or more of lutetium (Lu).

[0121] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. oxides such as In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, and Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metals In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides Oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides oxides, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides , In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, I n-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide, which is an oxide of a quaternary metal, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn-based oxides, In-Sn-Hf-Zn-based oxides, In-Hf-Al-Zn-based oxides It can be used.

[0122] Here, for example, In-Ga-Zn oxide refers to an oxide containing In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. Metal elements other than Ga and Zn may be included.

[0123] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer ) may be used, where M is selected from Ga, Fe, Mn and Co. In addition, the oxide semiconductor is In3SnO 5(ZnO) n A material expressed as (n>0 and n is an integer) may be used.

[0124] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In: In-Ga-Zn system with an atomic ratio of Ga:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) The oxide or an oxide having a similar composition can be used. 1:1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3: 1 / 6:1 / 2) or In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is preferable to use an In-Sn-Zn oxide having an atomic ratio of 100% or an oxide having a composition close to that.

[0125] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In order to obtain the required semiconductor properties, a material with an appropriate composition can be used. Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to set the degree etc. appropriately.

[0126] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, even in In-Ga-Zn oxides, the mobility can be improved by reducing the defect density in the bulk. It can be raised.

[0127] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b +c=1), the atomic ratio of the oxide is In:Ga:Zn=A:B:C (A+B+ C=1) is close to the oxide composition when a, b, and c are (a―A) 2 +(b-B) 2 +(c-C) 2 ≦r 2 The above expression means that the oxide satisfies the above condition, and r can be set to, for example, 0.05. The same applies to other oxides. .

[0128] The oxide semiconductor may be single-crystal or non-single-crystal. In the latter case, it may be amorphous or polycrystalline. It may also be a structure containing a crystalline portion in an amorphous state, or a non-amorphous It can also be a s.

[0129] Amorphous oxide semiconductors can be easily flattened. This can reduce interface scattering when a transistor is fabricated using this material, and can be fabricated relatively easily and relatively easily. High mobility can be obtained.

[0130] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced, and By improving the flatness of the surface, it is possible to obtain a mobility higher than that of an amorphous oxide semiconductor. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably Preferably, it is formed on the surface to a thickness of 0.1 nm or less.

[0131] Note that Ra is the centerline average roughness defined in JIS B0601 applied to the surface. It is a three-dimensional extension of the method, which calculates the average absolute value of the deviation from the reference surface to the specified surface. This can be expressed as the "value obtained by dividing the total number of times the

[0132]

number

[0133] In the above, S0 is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y 1) The area of ​​the rectangular region bounded by four points (x2, y2), Z0 indicates the average height of the measurement surface. Ra is measured by an atomic force microscope (AFM). It can be evaluated using a microscope.

[0134] Here, an In-Ga-Zn-O metal oxide target is used as the oxide semiconductor layer. In this case, an amorphous oxide semiconductor layer is formed by a sputtering method.

[0135] The oxide semiconductor layer 140 can be formed by sputtering using a target such as For example, a metal oxide target containing zinc oxide as a main component can be used. Metal oxide target containing In, Ga, and Zn (composition ratio: In2O3:Ga 2O3:ZnO=1:1:1[mol ratio], In:Ga:Zn=1:1:0.5[ato In addition, metal oxides containing In, Ga, and Zn can be used. The target is In:Ga:Zn=1:1:1 [atom ratio] or In:Ga:Z A target having a composition ratio of n=1:1:2 (atom ratio) may also be used. The filling rate of the oxide target is 90% or more and 100% or less, preferably 95% or more (for example, 99 By using a metal oxide target with a high filling rate, a dense oxide A semiconductor layer is formed.

[0136] When an In—Zn—O-based material is used for the oxide semiconductor layer 140, the substrate to be used The composition ratio of the get is In:Zn=50:1 to 1:2 in atomic ratio (converted to molar ratio). In2O3:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 ( In terms of molar ratio, In2O3:ZnO=10:1 to 1:2), more preferably In Zn = 15:1 to 1.5:1 (converted to a molar ratio of In2O3:ZnO = 15:2 to 3:4) For example, the metal oxide substrate used to form an In-Zn-O oxide semiconductor The get is that when the atomic ratio is In:Zn:O=X:Y:Z, Z>1.5X+Y.

[0137] In addition, In-Sn-Zn oxide can be called ITZO, and the target used is The composition ratio of In:Sn:Zn is 1:2:2, 2:1:3, 1:1:1, or An oxide target with a ratio of 20:45:35 is used.

[0138] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or Alternatively, it is preferable to use a mixed atmosphere of a rare gas (typically argon) and oxygen. Specifically, impurities such as hydrogen, water, hydroxyl groups, and hydrides are preferably present at a level of several ppm. It is preferable to use a high-purity gas in which the concentration has been reduced to about several ppb.

[0139] When forming the oxide semiconductor layer, the substrate is held in a treatment chamber maintained in a reduced pressure state. The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating, the impurity concentration in the oxide semiconductor layer can be reduced. Also, damage caused by sputtering can be reduced. The residual moisture in the chamber is removed and sputtering gas from which hydrogen and water have been removed is introduced to form a metal oxide. The oxide semiconductor layer is formed using the target as a target. It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump A pump or a titanium sublimation pump can be used as an exhaust means. A cryopump with a cold trap may be used. The vapor deposition chamber is filled with, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (preferably Since oxide semiconductors formed in the film formation chamber are exhausted, The concentration of impurities contained in the layer can be reduced.

[0140] The formation conditions are, for example, a distance of 100 mm between the substrate and the target and a pressure of 0. 6 Pa, direct current (DC) power 0.5 kW, oxygen atmosphere (oxygen flow rate 100%) If a pulsed direct current (DC) power supply is used, This is preferable because it reduces the damage and makes the film thickness distribution uniform. The thickness is set to 200 nm or more, preferably 5 nm or more and 30 nm or less. The appropriate thickness varies depending on the semiconductor material, so the thickness should be selected appropriately depending on the material used. That's fine.

[0141] Before forming the oxide semiconductor layer by a sputtering method, argon gas is introduced. The reverse sputtering is performed to generate plasma, and the It is preferable to remove dust. Here, reverse sputtering means that in normal sputtering, Instead of bombarding the sputtering target with ions, the ions are bombarded onto the surface to be treated. This refers to a method of modifying the surface by bombarding the surface with ions. In this method, a high frequency voltage is applied to the surface to be treated in an argon atmosphere to generate plasma near the substrate. In addition, nitrogen, helium, oxygen, etc. can be used instead of argon atmosphere. You can use it.

[0142] The oxide semiconductor layer can be etched by either dry etching or wet etching. Of course, both can be used in combination. To etch the material, the etching conditions (etching gas, etching solution, etc.) are adjusted to suit the material. The etching time, temperature, etc. are set appropriately.

[0143] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas , such as chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), tetrachloride Carbon (CCl4, etc.) and gases containing fluorine (fluorine-based gases, for example, tetrachloroethylene). Carbon fluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane Hydrogen bromide (HBr), oxygen (O2), and these gases with helium ( A gas containing a rare gas such as argon (Ar) or argon (He) may also be used.

[0144] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) hing method and ICP (Inductively Coupled Plasma) Inductively coupled plasma etching can be used. It can be etched into the desired shape. As shown in the figure, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) The amount of power used, the temperature of the electrode on the substrate, etc. are set appropriately.

[0145] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. In addition, etching solutions such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. It's fine.

[0146] Next, the oxide semiconductor layer is preferably subjected to first heat treatment. The temperature of the first heat treatment is The temperature is set to 300° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the strain point of the substrate. The substrate is placed in an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heated in a nitrogen atmosphere. During this time, the oxide semiconductor layer 140 is heated in the atmosphere at 450° C. for 1 hour. No contact with the product and no recontamination of water or hydrogen is permitted.

[0147] The heat treatment device is not limited to an electric furnace, and may be any other device that uses heat conduction from a medium such as heated gas, or The heating element may be a device that heats the object to be treated by thermal radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas such as a rare gas like argon or nitrogen that does not react with the material to be treated by heat treatment. Sexual gases are used.

[0148] For example, as the first heat treatment, the substrate is heated to a high temperature of 650°C to 700°C in an inert gas atmosphere. After heating for a few minutes, the substrate is removed from the inert gas and the GRTA process is carried out. GRTA treatment allows high-temperature heat treatment in a short time. Since this is a heat treatment, it can be applied even under temperature conditions exceeding the distortion point of the substrate.

[0149] The first heat treatment is performed in a gas atmosphere mainly composed of nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to carry out the process in an atmosphere that is free from water, hydrogen, etc. For example, the purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment equipment can be , 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. That is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0150] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may become crystalline. For example, the crystallinity may be 90% or more, or 8% or more. In some cases, the oxide semiconductor layer has a crystallinity of 0% or more. Depending on the material of the oxide semiconductor layer, the oxide semiconductor layer may be an amorphous oxide semiconductor layer that does not contain crystalline components. There are cases like this.

[0151] In addition, microcrystals (grain size 1 nm) are formed on the amorphous oxide semiconductor (for example, on the surface of the oxide semiconductor layer). and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed. In some cases, this may be the case.

[0152] In addition, the electrical properties of the oxide semiconductor layer can be changed by arranging microcrystals in the amorphous state. For example, it is possible to use an In-Ga-Zn-O metal oxide target. When forming an oxide semiconductor layer, the crystal of In2Ga2ZnO7, which has electrical anisotropy, is used. By forming a microcrystalline portion in which grains are oriented, the electrical characteristics of the oxide semiconductor layer can be changed. can be done.

[0153] More specifically, for example, the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer. By orienting the oxide semiconductor layer in a desired direction, the conductivity in the direction parallel to the surface of the oxide semiconductor layer can be improved. This can improve the insulating properties in a direction perpendicular to the surface of the oxide semiconductor layer. Such microcrystalline portions have the function of suppressing the penetration of impurities such as water and hydrogen into the oxide semiconductor layer. Possess the ability.

[0154] Note that the oxide semiconductor layer having the above-described microcrystalline portion is an oxide semiconductor layer obtained by GRTA treatment. It can be formed by surface heating. In addition, the content of Zn is By using a sputtering target smaller than the amount of .

[0155] Here, the c-axis is oriented and the ab plane, the surface or the interface is triangular or hexagonal when viewed from the direction of the interface. The metal atoms are layered or the metal atoms and oxygen atoms are arranged in a rectangular shape along the c-axis. The layers are arranged in layers, and the orientation of the a-axis or b-axis is different on the ab plane (rotation around the c-axis). C-Axis Aligned Crystal (CAAC) An oxide containing the compound will be described.

[0156] In a broad sense, oxides containing CAAC are non-single crystals that are perpendicular to the ab plane. When viewed from the outside, the atomic arrangement is triangular, hexagonal, equilateral triangular, or equilateral hexagonal, and perpendicular to the c-axis direction. When viewed from any direction, it contains a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. It refers to oxides.

[0157] CAAC is not a single crystal, but it is not composed of only amorphous material. AAC contains crystallized parts (crystalline parts), but the boundary between one crystalline part and another crystalline part is Sometimes it is not possible to clearly distinguish.

[0158] When CAAC contains oxygen, a part of the oxygen may be replaced by nitrogen. The c-axis of each crystalline part that constitutes C is aligned in a certain direction (for example, the substrate surface supporting the CAAC, The CAAC may be aligned in a direction perpendicular to the surface of the CAAC. The normal of the ab plane of each crystal part is in a certain direction (e.g., the substrate surface supporting the CAAC, It may be oriented in a direction perpendicular to the surface of C, etc.

[0159] CAAC can be a conductor, a semiconductor, or an insulator depending on its composition. Depending on the composition, they may be transparent or opaque to visible light. Or something like that.

[0160] An example of such a CAAC is a film-like CAAC that is perpendicular to the film surface or the supporting substrate surface. When observed from various directions, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, Then, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Crystals such as these can also be mentioned.

[0161] An example of a crystal structure contained in CAAC will be described in detail with reference to FIGS. 23 to 25. 23 to 25, the upward direction is the c-axis direction, and the direction perpendicular to the c-axis direction is the The intersecting plane is the ab plane. When simply referring to the upper half and the lower half, it means that the ab plane is the boundary. The upper and lower halves of the

[0162] Figure 23(A) shows one hexacoordinated In atom and six tetracoordinated oxygen atoms (hereafter referred to as The structure shown has four-coordinated oxygen atoms. Here, one metal atom has four adjacent oxygen atoms. The structure showing only atoms is called a small group. The structure in Figure 23(A) has an octahedral structure, For simplicity, the structure is shown in a plane. There are three tetracoordinated O atoms in each group. The small group shown in Figure 23(A) has a zero charge.

[0163] Figure 23(B) shows one pentacoordinate Ga atom and three tricoordinate oxygen atoms (hereafter referred to as The structure has a tricoordinated O atom and two tetracoordinated O atoms adjacent to Ga. , both of which exist on the ab plane. There is one each in the upper and lower halves of Figure 23(B). There is a tetracoordinate O. In addition, since In also has a pentad, it can take the structure shown in Figure 23(B). The small group shown in Figure 23(B) has a charge of 0.

[0164] FIG. 23(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The structure of Figure 23(C) shows one tetracoordinate O in the upper half and three tetracoordinate O in the lower half. Or, in Figure 23(C), there are three tetracoordinate O atoms in the upper half and one in the lower half. There may be four-coordinated O atoms. The small group shown in Figure 23(C) has a zero charge.

[0165] FIG. 23(D) shows a structure having one hexacoordinate Sn atom and six tetracoordinate O atoms adjacent to the Sn atom. The structure of Figure 23(D) shows three tetracoordinate O atoms in the upper half and three tetracoordinate O atoms in the lower half. The small group shown in Figure 23(D) has a charge of +1.

[0166] Figure 23(E) shows a small group containing two Zn atoms. The upper half of Figure 23(E) shows one Zn atom. The small group shown in Figure 23(E) has four tetrahedral O atoms, and the lower half has one tetrahedral O atom. The charge of the atom is -1.

[0167] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a is called a large group (also called a unit cell).

[0168] Here, we will explain the rules for combining these small groups. The three O atoms in the upper half of the hexacoordinated In have three neighboring In atoms in the downward direction, The three O atoms in each have three neighboring In atoms in the upward direction. Each O has one neighboring Ga in the downward direction, and each O in the lower half has one neighboring Ga in the upward direction. One O atom in the upper half of the tetrahedral Zn has one neighboring Zn atom in the downward direction, and the three O atoms in the lower half Each O has three neighboring Zn atoms in the upward direction. The number of O atoms is equal to the number of adjacent metal atoms below the O atoms. The number of tetrahedral O atoms is equal to the number of neighboring metal atoms above the O atoms. The sum of the number of neighboring metal atoms in the downward direction and the number of neighboring metal atoms in the upward direction is 4. Therefore, the number of tetrahedral O atoms above a metal atom and the number of tetrahedral O atoms below another metal atom are When the sum of the number of O and the number of metal atoms is 4, two small groups containing metal atoms can bond together. For example, a hexacoordinated metal atom (In or Sn) is bonded via a tetracoordinated O atom in the lower half. In this case, since there are three tetrahedral O atoms, the five-coordinate metal atom (Ga or In) or the four It will bond to one of the coordinated metal atoms (Zn).

[0169] Metal atoms with these coordination numbers are bonded via tetracoordinated oxygen atoms in the c-axis direction. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. The medium group is composed of these.

[0170] Figure 24(A) shows a model diagram of the middle group that constitutes the In-Sn-Zn-O system layer structure. FIG. 24(B) shows a large group consisting of three medium groups. (C) shows the atomic arrangement when the layer structure of FIG. 24(B) is observed from the c-axis direction.

[0171] In FIG. 24(A), for simplicity, the tricoordinate O atoms are omitted, and only the number of the tetracoordinate O atoms is shown. For example, the upper and lower halves of Sn each contain three tetrahedral O atoms. Similarly, in FIG. 24(A), the upper and lower halves of In are Each of the has one tetracoordinated O atom, which is shown as a circled 1. Similarly, in Figure 2 In 4(A), the bottom half has one tetrahedral O atom, and the top half has three tetrahedral O atoms. A Zn atom has one tetrahedral O atom in the top half and three tetrahedral O atoms in the bottom half. n.

[0172] In FIG. 24(A), the middle group, which constitutes the In-Sn-Zn-O system layer structure, is Sn has three tetrahedral O atoms in the upper half and one in the lower half, and It bonds to In in the upper and lower halves, and the In has three tetracoordinate O atoms in the upper half. It bonds to Zn, and three tetracoordinate O atoms are attached to the upper half of the Zn via one tetracoordinate O atom in the lower half. In is bonded to a Zn atom with one tetracoordinate O atom in the upper half. It bonds to a small group of two atoms via a tetracoordinate O atom in the lower half of this small group. The structure is such that three tetracoordinate O atoms are bonded to the Sn atoms in the upper and lower halves. Multiple groups combine to form a larger group.

[0173] Here, for tricoordinated O and tetracoordinated O, the charge per bond is -0. 667, -0.5. For example, In (6-coordinate or 5-coordinate), Zn ( The charges of Sn (four-coordinated), Sn (five-coordinated or six-coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, when a layer structure containing Sn is formed, To achieve this, a charge of -1 is required to cancel out the charge of +1. As shown in 23(E), there is a small group containing two Zn atoms. For example, If there is one small group containing two Zn atoms for every small group containing one Zn atom, the charges will be cancelled out. Therefore, the total charge of the layer structure can be set to zero.

[0174] Specifically, the large group shown in FIG. 24(B) is repeated to form an In-Sn-Z InO-based crystals (In2SnZn3O8) can be obtained. The n-Zn-O layer structure is In2SnZn2O7(ZnO) m (m is 0 or a natural number. ) can be expressed by the composition formula:

[0175] In addition to these, there are also oxides of quaternary metals such as In-Sn-Ga-Zn oxides, In-Ga-Zn oxide (also called IGZO), which is a ternary metal oxide, -Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn- Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In- Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-S m-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb -Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er- Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Z n-based oxides, binary metal oxides such as In-Zn-based oxides, Sn-Zn-based oxides, and A l-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, The same applies when an In-Ga oxide is used.

[0176] For example, in Figure 25(A), a middle group model consisting of an In-Ga-Zn-O system layer structure is shown. A diagram is shown.

[0177] In FIG. 25(A), the middle group, which is made up of an In-Ga-Zn-O-based layer structure, is In the upper half and lower half, there are three tetrahedral O atoms, and in the lower half, there is one tetrahedral O atom. It bonds to the Zn in the molecule, and through the three tetracoordinate O atoms in the lower half of the Zn, the tetracoordinate O atoms Each bond to a Ga atom in the upper half and the lower half, and one tetracoordinate O atom in the lower half of the Ga atom Three tetracoordinate O atoms are bonded to the In atoms in the upper and lower halves via the Several of these medium groups combine to form large groups.

[0178] Figure 25(B) shows a large group consisting of three medium groups. shows the atomic arrangement when the layer structure of FIG. 25(B) is observed from the c-axis direction.

[0179] Here, the charges of In (6- or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are +3, +2, and +3, respectively, so they are in a small group that includes either In, Zn, or Ga. The charge is 0. Therefore, if these small groups are combined, The total charge is always zero.

[0180] The middle group, which constitutes the In-Ga-Zn-O layer structure, is shown in FIG. The combination of different middle groups, In, Ga, and Zn, is not limited to the same middle group. Large groups are also possible.

[0181] The first heat treatment on the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In this case, the first heat treatment may be performed on the oxide semiconductor layer before the first heat treatment. The substrate is then removed from the mold and subjected to a photolithography process.

[0182] The heat treatment described above has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. It can also be called dehydration treatment, dehydrogenation treatment, etc. The oxidation treatment is carried out by forming a source layer and a drain layer on the oxide semiconductor layer 140 after the oxide semiconductor layer is formed. or after forming a protective insulating layer on the source and drain layers. In addition, such dehydration and dehydrogenation treatments can be carried out in the following manner: This may be done not only once but multiple times.

[0183] Next, the source layer 142a and the drain layer 142b are formed in contact with the oxide semiconductor layer 140. The source layer 142a and the drain layer 142b are formed by oxidation (see FIG. 13(F)). After forming a conductive layer to cover the compound semiconductor layer 140, the conductive layer is selectively etched. It can be formed by

[0184] The conductive layer is formed by PVD methods such as sputtering and plasma CVD methods. The conductive layer can be formed by using a CVD method. An element selected from chromium, copper, tantalum, titanium, molybdenum, tungsten, or any of the above. Alloys containing the elements manganese, magnesium, zirconium, etc. can be used. Alternatively, a material selected from one or more of aluminum, beryllium, and thorium may be used. In addition, aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium A material containing a single element selected from the group consisting of aluminum and scandium, or a combination of multiple elements, may also be used. The conductive layer may have a single layer structure or a laminated structure of two or more layers. Single layer structure of aluminum film containing silicon, two-layer structure of titanium film laminated on aluminum film and a three-layer structure in which a titanium film, an aluminum film, and another titanium film are laminated.

[0185] When etching the conductive layer, the oxide semiconductor layer 140 is not removed. The materials and etching conditions are adjusted as appropriate. Therefore, in this step, a part of the oxide semiconductor layer 140 is etched, and a groove (a recess) is formed. In some cases, the oxide semiconductor layer has a thin film.

[0186] In addition, the oxide semiconductor layer 140 and the source layer 142a or the oxide semiconductor layer 140 and the drain layer 142b may be formed on the oxide semiconductor layer 140. An oxide conductive layer may be formed between the drain layer 142b and the source layer 142b. The metal layer for forming the drain layer 142a and the drain layer 142b is formed continuously (continuously). The oxide conductive layer can function as a source or drain region. By providing such an oxide conductive layer, the resistance of the source region or the drain region can be reduced. This allows high-speed operation of the transistor.

[0187] In order to reduce the number of masks used and the number of processes, the exposure process is performed so that the transmitted light has multiple intensities. A resist mask is formed using a multi-tone optical mask, and etching is performed using this. The resist mask formed using the multi-tone mask has a plurality of thicknesses. The shape becomes stepped, and the shape can be further deformed by ashing. It can be used in multiple etching processes to process different patterns. By using the multi-tone mask, resist masks corresponding to at least two different patterns can be formed. Therefore, the number of exposure masks can be reduced, and the corresponding The photolithography process can also be eliminated, simplifying the process.

[0188] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. It is preferable to perform the plasma treatment. Water and other substances adhering to the surface are removed. In addition, plasma treatment is performed using a mixture of oxygen and argon gas. may be performed.

[0189] Next, the protective insulating layer 11 in contact with a part of the oxide semiconductor layer 140 is removed without exposing it to the air. 44 is formed (see FIG. 13(G)).

[0190] The protective insulating layer 144 is formed by removing impurities such as water and hydrogen from the protective insulating layer 144 by a method such as sputtering. The thickness of the film can be at least The thickness is 1 nm or more. Materials that can be used for the protective insulating layer 144 include silicon oxide, nitride, and the like. Silicon nitride, silicon oxynitride, silicon nitride oxide, etc. Also, the structure can be a single layer structure. The substrate temperature when forming the protective insulating layer 144 is set to room temperature or higher. The temperature is preferably 300°C or less, and the atmosphere is a rare gas (typically argon) atmosphere, an acid atmosphere, or the like. A nitrogen atmosphere or a mixed atmosphere of a rare gas (typically argon) and oxygen is preferred. do.

[0191] If hydrogen is contained in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer 140 or The hydrogen extracts oxygen from the oxide semiconductor layer 140, and the oxide semiconductor layer 14 The back channel side of 0 becomes low resistance, which may result in the formation of a parasitic channel. Therefore, in order to prevent the protective insulating layer 144 from containing as much hydrogen as possible, the formation method is It is important not to use

[0192] In addition, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. This is because the oxide semiconductor layer 140 and the protective insulating layer 144 contain hydrogen, hydroxyl groups, or moisture. This is to prevent this.

[0193] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The deposition chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H 2O) and other compounds containing hydrogen atoms are removed, The concentration of impurities contained in the edge layer 144 can be reduced.

[0194] The sputtering gas used when forming the protective insulating layer 144 may be hydrogen, water, a hydroxyl group, or Impurities such as hydrides are removed to a few ppm (preferably a few ppb). It is preferable to use a high purity gas.

[0195] Then, a second heat treatment (preferably 2 It is desirable to carry out the heating at a temperature between 00°C and 400°C, for example, between 250°C and 350°C. For example, a second heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. The variation in the electrical characteristics of the transistors can be reduced.

[0196] In addition, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature, or by heating from room temperature to 100°C. Repeat the heating process from 200°C to room temperature several times. This heat treatment may be carried out under reduced pressure before the formation of the protective insulating layer. If the heat treatment is carried out under reduced pressure, the heating time can be shortened. This may be carried out instead of the second heat treatment, or may be carried out before or after the second heat treatment.

[0197] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 14(A)). The interlayer insulating layer 146 can be formed by using a PVD method, a CVD method, or the like. Silicon, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide The interlayer insulating layer 146 can be formed using a material containing an inorganic insulating material such as tantalum. After formation, the surface can be flattened by methods such as CMP or etching. desirable.

[0198] Next, an electrode is formed on the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. Openings reaching the layer 136a, the electrode layer 136b, the source layer 142a, and the drain layer 142b Then, a conductive layer 148 is formed to fill the opening (see FIG. 14B). The opening can be formed by etching or other methods using a mask. It can be formed by a method such as exposure using a photomask. Either wet etching or dry etching may be used. From this viewpoint, it is preferable to use dry etching. The conductive layer 148 can be formed by a deposition method such as a deposition method or a CVD method. Materials that can be used include molybdenum, titanium, chromium, tantalum, tungsten, and aluminum. Conductive materials such as tungsten, copper, neodymium, and scandium, as well as their alloys and compounds (e.g., nitrides).

[0199] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then CVD is performed. After forming a thin titanium nitride film by the method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method has a high interfacial The oxide film of the lower electrode (here, the electrode layer 136a, the electrode layer 136b, and the source layer 136b) is reduced. 42a, drain layer 142b). The titanium nitride film thus formed has a barrier function that suppresses the diffusion of conductive materials. Even if a copper film is formed by plating after forming a barrier film using titanium or titanium nitride, good.

[0200] After the conductive layer 148 is formed, the conductive layer 14 is removed by a method such as etching or CMP. 8 is removed to expose the interlayer insulating layer 146, and the electrode layers 150a, 150b, Electrode layers 150d and 150e are formed (see FIG. 14(C)). 48 is removed to form electrode layers 150a, 150b, 150d, and 150e. When forming the layer e, it is desirable to process it so that the surface is flat. The interlayer insulating layer 146, the electrode layer 150a, the electrode layer 150b, the electrode layer 150d, and the electrode layer 150e By flattening the surface, it is possible to form good electrodes, wiring, insulating layers, and semiconductor layers in subsequent processes. It is possible to form the following.

[0201] Furthermore, an insulating layer 152 is formed, and the electrode layers 150a, 150b, Openings reaching the electrode layers 150d and 150e are formed, and a metal layer is embedded in the openings. After forming the conductive layer, a part of the conductive layer is removed by a method such as etching or CMP to form an insulating layer. The edge layer 152 is exposed to form the electrode layers 154a, 154b, and 154d. (See FIG. 14(D)). This process is the same as that for forming the electrode layer 150a, etc. , details are omitted.

[0202] <Modification of Transistor> 15 to 18 are diagrams showing modifications of the transistor 164. FIG.

[0203] 15, a gate layer 136d is provided under the oxide semiconductor layer 140, and a source layer 142a and the drain layer 142b are in contact with the lower surface of the oxide semiconductor layer 140. 164 is shown.

[0204] The major difference between the configuration shown in FIG. 15 and the configuration shown in FIG. 11 is the source layer 142a and the drain layer 142b. The position of the connection between the drain layer 142b and the oxide semiconductor layer 140 is one example. In the configuration shown in FIG. 1, the source layer 142a and the drain layer 142b are formed on the upper surface of the oxide semiconductor layer 140. 15, the oxide semiconductor layer 140 is in contact with the oxide semiconductor layer 142b. The lower surface of the semiconductor layer 140 contacts the source layer 142a and the drain layer 142b. Due to the difference in contact, the arrangement of other electrode layers, insulating layers, etc. is also different. The details of each component are the same as those in FIG.

[0205] Specifically, the transistor 164 shown in FIG. 15 has a gate insulating film formed on the interlayer insulating layer 128. a gate insulating layer 138 provided on the gate layer 136d; A source layer 142a and a drain layer 142b are provided on the layer 138, and the source layer 142 and an oxide semiconductor layer 140 in contact with the upper surfaces of the drain layer 142a and the drain layer 142b. A protective insulating layer 144 is formed on the transistor 164 so as to cover the oxide semiconductor layer 140. is provided.

[0206] FIG. 16 shows a transistor 16 having a gate layer 136d on an oxide semiconductor layer 140. 16A shows the source layer 142a and the drain layer 142b. 10 is a diagram showing an example of a configuration in which the lower surface of the compound semiconductor layer 140 is in contact with the oxide semiconductor layer 140. 16B shows a case where the source layer 142a and the drain layer 142b are formed on the oxide semiconductor layer 1. 4 is a diagram showing an example of a configuration in which the upper surface of the oxide semiconductor layer 40 is in contact with the oxide semiconductor layer 140. FIG.

[0207] 11 or 15 and the configuration shown in FIG. 16 is that the oxide semiconductor layer 1 16(A) and 16(B) are different in that the gate layer 136d is provided on the gate electrode 40. The main difference in the configuration shown in (B) is that the source layer 142a and the drain layer 142b are oxidized. The question is whether the contact is at the lower surface or the upper surface of the compound semiconductor layer 140. Due to these differences, the arrangement of other electrode layers, insulating layers, etc. may differ. The details of each component are the same as those in FIG. 11 etc.

[0208] Specifically, the transistor 164 shown in FIG. 16A is provided over the interlayer insulating layer 128. The source layer 142a and the drain layer 142b are formed by the 2b, and an oxide semiconductor layer 140 provided on the oxide semiconductor layer 140. The gate insulating layer 138 and the oxide semiconductor layer 140 on the gate insulating layer 138 and a gate layer 136d.

[0209] 16B. The transistor 164 shown in FIG. 16B has an oxide film formed over the interlayer insulating layer 128. The oxide semiconductor layer 140 and the source electrode 143 are provided so as to be in contact with the upper surface of the oxide semiconductor layer 140. the oxide semiconductor layer 140, the source layer 142a, and the drain layer 142b; a gate insulating layer 138 provided on the drain layer 142b; and a gate layer 136d provided in a region overlapping with the oxide semiconductor layer 140.

[0210] In the configuration shown in FIG. 16, some components are omitted compared to the configuration shown in FIG. 11. In this case, the electrode layer 150a, the electrode layer 154a, etc. may be formed. Of course, in the configuration shown in FIG. It goes without saying that non-essential components can be omitted.

[0211] FIG. 17 shows a case where the size of the element is relatively large, and The transistor 164 has a gate layer 136d. Since the requirement for coverage is relatively low, wiring and electrodes can be easily embedded in the insulating layer. It is not necessary to form the conductive layer so as to be buried. For example, patterning can be performed after forming the conductive layer. With this, it is possible to form the gate layer 136d and the like.

[0212] The major difference between the configuration shown in FIG. 17(A) and the configuration shown in FIG. 17(B) is the source layer 142 a and the drain layer 142b are formed on either the lower surface or the upper surface of the oxide semiconductor layer 140. These differences lead to the question of whether the other electrode layers The arrangement of the insulating layers is different. is the same as:

[0213] Specifically, the transistor 164 shown in FIG. 17A is provided over the interlayer insulating layer 128. a gate insulating layer 138 provided on the gate layer 136d; A source layer 142a and a drain layer 142b are provided on the insulating layer 138. and an oxide semiconductor layer 140 in contact with the upper surfaces of the drain layer 142a and the drain layer 142b. .

[0214] 17B is a transistor 164 having a gate insulating layer formed over the interlayer insulating layer 128. a gate insulating layer 138 provided on the gate layer 136d; an oxide semiconductor layer 140 provided in a region overlapping with the gate layer 136d on the layer 138; The source layer 142a and the drain layer 142b are provided in contact with the upper surface of the nitride semiconductor layer 140. and layer 142b.

[0215] In addition, the configuration shown in FIG. 17 also has fewer components than the configuration shown in FIG. 11. In this case, too, the effect of simplifying the manufacturing process can be obtained.

[0216] FIG. 18 shows a case where the size of the element is relatively large, and the oxide semiconductor layer 140 is Transistor 164 is shown configured with gate layer 136d. Again, the surface planarity Since the requirements for performance and coverage are relatively low, wiring and electrodes can be easily covered by insulating layers. It is not necessary to form the conductive layer so as to be embedded in the conductive layer. For example, the conductive layer may be patterned after being formed. This makes it possible to form the gate layer 136d and the like.

[0217] The major difference between the configuration shown in FIG. 18(A) and the configuration shown in FIG. 18(B) is that the source layer 142 a and the drain layer 142b are formed on either the lower surface or the upper surface of the oxide semiconductor layer 140. These differences lead to the question of whether the other electrode layers The arrangement of the insulating layers is different. is the same as:

[0218] Specifically, the transistor 164 shown in FIG. 18A is provided over the interlayer insulating layer 128. The source layer 142a and the drain layer 142b are formed by the The oxide semiconductor layer 140 contacting the upper surface of the source layer 142a and the drain layer 142b b, and the gate insulating layer 138 provided on the oxide semiconductor layer 140, and the gate insulating layer 13 and a gate layer 136d provided in a region overlapping with the oxide semiconductor layer 140 on the gate electrode 136. .

[0219] 18B is a transistor 164 having an oxide film formed over the interlayer insulating layer 128. The oxide semiconductor layer 140 and the source electrode 143 are provided so as to be in contact with the upper surface of the oxide semiconductor layer 140. and a source layer 142a, a drain layer 142b, and a A gate insulating layer 138 is provided on the oxide semiconductor layer 140. The gate layer 136d is formed by insulating the gate insulating layer 13 The insulating film 120 is provided in a region overlapping with the oxide semiconductor layer 140 with the insulating film 120 interposed therebetween.

[0220] The configuration shown in FIG. 18 also has fewer components than the configuration shown in FIG. 11. In this case, too, the effect of simplifying the manufacturing process can be obtained.

[0221] 11, the oxide semiconductor layer 140, the source layer 142a, and the drain layer 142b An oxide conductive layer serving as a source region and a drain region is provided between the 19 and 20 show a transistor in which an oxide conductive layer is provided in the transistor 164 of FIG. FIG.

[0222] The transistor 164 in FIGS. 19 and 20 includes an oxide semiconductor layer 140, a source layer 142a, Between the drain layer 142b and the oxide conductive layer 142a, the oxide conductive layer 142b functions as a source region and a drain region. The difference between the transistor 164 in FIGS. The shape of the oxide conductive layers 162a and 162b differs depending on the manufacturing process.

[0223] In the transistor 164 in FIG. 19, a stack of an oxide semiconductor layer and an oxide conductive layer is formed. The laminated layer of the oxide semiconductor layer and the oxide conductive layer are shaped using the same photolithography process. The oxide semiconductor layer 140 and the oxide conductive layer are formed by the above-mentioned process. After forming the source layer 142a and the drain layer 142b on the conductive layer, The island-shaped oxide conductive layer is etched using the drain layer 142b as a mask to form the source region and Then, oxide conductive layers 162a and 162b which will become the gate and drain regions are formed.

[0224] In the transistor 164 in FIG. 20, an oxide conductive layer is formed over the oxide semiconductor layer 140. A metal conductive layer is formed thereon, and the oxide conductive layer and the metal conductive layer are formed by the same photolithography. The oxide conductive layers 162a and 162b are processed to become the source and drain regions. 62b, a source layer 142a, and a drain layer 142b are formed.

[0225] Note that during etching treatment for processing the shape of the oxide conductive layer, the oxide semiconductor layer may be overetched. To prevent excessive etching, the etching conditions (type of etching material, concentration, etching Adjust the time (e.g., training time) as appropriate.

[0226] The oxide conductive layers 162a and 162b are formed by a sputtering method or a vacuum deposition method (electron The method is to use the arc discharge ion plating method or the spray method. The materials for the conductive layer include zinc oxide, zinc aluminum oxide, and zinc aluminum oxynitride. , zinc gallium oxide, indium tin oxide, etc. can be used. Silicon oxide may be contained in the above.

[0227] The oxide conductive layer is formed as a source region and a drain region by forming an oxide semiconductor layer 140 and a source layer By providing the layer 142a between the drain layer 142b, the low This allows for resistance and allows the transistor 164 to operate at high speed.

[0228] In addition, by adopting such a configuration, the withstand voltage of the transistor 164 can be improved. This can be done.

[0229] 19 and 20, the oxide semiconductor layer 140 of the transistor 164 shown in FIG. Regarding a structure in which an oxide conductive layer is provided between the source layer 142a and the drain layer 142b, However, the oxide semiconductor layer 1 of the transistor 164 shown in FIGS. 40, and an oxide conductive layer is provided between the source layer 142a and the drain layer 142b. It is also possible to do this.

[0230] Note that in this example, the transistor 164 is stacked over the transistor 160. However, the configuration of the transistor 160 and the transistor 164 is not limited to this. For example, the transistor 160 and the transistor 164 are formed on the same plane. Furthermore, the transistor 160 and the transistor 164 can be overlapped. It's okay to do that.

[0231] <Modification of the Process for Forming Oxide Semiconductor Layer> A manufacturing process of an oxide semiconductor layer, which is different from the manufacturing process of the above-described transistor, is shown in FIG. This will be used to explain.

[0232] The oxide semiconductor layer includes a first crystalline oxide semiconductor layer and a second crystalline oxide semiconductor layer. The second crystalline oxide semiconductor layer is thicker than the first crystalline oxide semiconductor layer.

[0233] An insulating layer 437 is formed on the insulating layer 400. Here, the insulating layer 437 is made of PECV. Oxide insulation with a thickness of 50 nm to 600 nm is formed using the D method or sputtering method. For example, the oxide insulating layer may be a silicon oxide layer, a gallium oxide layer, or an oxide layer. an aluminum nitride layer, a silicon oxynitride layer, an aluminum oxynitride layer, or a silicon nitride oxide layer; A single layer selected from silicon layers or a laminate of these layers can be used.

[0234] Next, a first oxide semiconductor layer having a thickness of 1 nm to 10 nm is formed over the insulating layer 437. The first oxide semiconductor layer is formed by a sputtering method. The substrate temperature during film formation is set to 200° C. or higher and 400° C. or lower.

[0235] Here, a metal oxide target (In-Ga-Zn-O system metal oxide target (I The substrate and target were prepared using a ZnO / GaO / ZnO (molar ratio: 1:1:2). The distance between the substrate and the board was 170 mm, the substrate temperature was 250°C, the pressure was 0.4 Pa, and the DC power supply was 0 0.5kW, oxygen only, argon only, or argon and oxygen atmosphere, 5nm thick film An oxide semiconductor layer is formed.

[0236] Next, the atmosphere in the chamber in which the substrate is placed is changed to nitrogen or dry air, and the first heating process is performed. The temperature of the first heat treatment is 400°C or higher and 750°C or lower. Thus, a first crystalline oxide semiconductor layer 450a is formed (see FIG. 21A).

[0237] Although it depends on the substrate temperature during film formation and the temperature of the first heat treatment, Therefore, crystallization occurs from the film surface, and crystals grow from the surface to the inside of the film, resulting in c-axis orientation. The first heat treatment causes zinc and oxygen to gather on the surface of the film, resulting in a flat crystal. A graphene-type two-dimensional crystal consisting of zinc and oxygen with hexagonal faces is formed on the top surface. The film is formed in multiple layers, which grow in the film thickness direction and overlap to form a laminate. When this occurs, crystal growth progresses from the surface to the inside, and then from the inside to the bottom.

[0238] By the first heat treatment, oxygen in the insulating layer 437, which is an oxide insulating layer, is converted into a first crystalline oxide. Diffusion at the interface with the nitride semiconductor layer 450a or in the vicinity thereof (within ±5 nm from the interface) As a result, oxygen vacancies in the first crystalline oxide semiconductor layer are reduced. The insulating layer 437 used has a thickness of 1000 nm and a thickness of 1000 nm. The interface of the insulating layer 437 has oxygen in an amount exceeding the stoichiometric ratio. It is preferable.

[0239] Next, a second oxide semiconductor layer having a thickness of more than 10 nm is formed on the first crystalline oxide semiconductor layer 450a. The conductive layer is formed. The second oxide semiconductor layer is formed by sputtering. The substrate temperature during film formation is set to 200°C or higher and 400°C or lower. By setting the temperature to 0° C. or higher and 400° C. or lower, The precursors are aligned in the oxide semiconductor layer to be formed, and so-called order can be imparted to the layer. do.

[0240] Here, a metal oxide target (In-Ga-Zn-O system metal oxide target (I The substrate and target were prepared using a ZnO / GaO / ZnO (molar ratio: 1:1:2). The distance between the substrate and the substrate was 170 mm, the substrate temperature was 400°C, the pressure was 0.4 Pa, and the DC power was 0 0.5kW, oxygen only, argon only, or argon and oxygen atmosphere, 25nm thick film An oxide semiconductor layer 2 is formed.

[0241] Next, the atmosphere in the chamber in which the substrate is placed is changed to nitrogen or dry air, and a second heating process is performed. The temperature of the second heat treatment is 400°C or higher and 750°C or lower. Thus, a second crystalline oxide semiconductor layer 450b is formed (see FIG. 21B). Heat treatment should be carried out in a nitrogen atmosphere, an oxygen atmosphere, or a mixed atmosphere of nitrogen and oxygen. This increases the density of the second crystalline oxide semiconductor layer and reduces the number of defects. According to this theory, the first crystalline oxide semiconductor layer 450a is used as a core and the first crystalline oxide semiconductor layer 450b is grown in the thickness direction, that is, from the bottom to the inside. Crystal growth progresses in the portion, and a second crystalline oxide semiconductor layer 450b is formed.

[0242] In addition, the steps from the formation of the insulating layer 437 to the second heat treatment are performed continuously without exposure to the air. The steps from the formation of the insulating layer 437 to the second heat treatment are preferably performed without using hydrogen and In an atmosphere containing almost no moisture (inert atmosphere, reduced pressure atmosphere, dry air atmosphere, etc.) For example, the moisture content is preferably below a dew point of -40°C, more preferably below a dew point of -5 The atmosphere should be dry nitrogen at 0°C or below.

[0243] Next, the first crystalline oxide semiconductor layer 450a and the second crystalline oxide semiconductor layer 450b The oxide semiconductor layer 4 is formed by processing the oxide semiconductor layer 4 into an island-shaped oxide semiconductor layer. 21C). In FIG. 21C, the first crystalline oxide semiconductor layer 450a and the second crystalline oxide semiconductor layer 53 are formed. The interface of the second crystalline oxide semiconductor layer 450b is indicated by a dotted line, and the oxide semiconductor stack is described as a stack of oxide semiconductor layers. However, there is no clear interface, and the diagram is only for the purpose of easy understanding. It shows.

[0244] The oxide semiconductor stack is processed by forming a mask having a desired shape on the oxide semiconductor stack. The mask can be formed by etching the stack of oxide semiconductor layers. The conductive layer can be formed by a method such as photolithography. The mask may be formed by a method such as a photolithography method.

[0245] The oxide semiconductor stack can be etched by either dry etching or wet etching. Of course, these may be used in combination.

[0246] Further, the first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer obtained by the above manufacturing method One of the features of the nitride semiconductor layer is that it has a c-axis orientation. The crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer do not have a single crystal structure but have an amorphous structure. It is not a crystal structure, but a crystal with c-axis orientation (C Axis Aligned Crystal). The first crystalline oxide semiconductor has an oxide containing stal (also called CAAC). The oxide layer and the second crystalline oxide semiconductor layer partially have grain boundaries.

[0247] The first and second crystalline oxide semiconductor layers are made of an oxide material containing at least Zn. There are quaternary metal oxides, such as In-Al-Ga-Zn-O and In-Sn-G a-Zn-O based materials, ternary metal oxide In-Ga-Zn-O based materials, In -Al-Zn-O based materials, In-Sn-Zn-O based materials, Sn-Ga-Zn-O based materials Materials, Al-Ga-Zn-O based materials, Sn-Al-Zn-O based materials, and binary metal oxides In-Zn-O based materials, Sn-Zn-O based materials, and Al-Zn-O based materials are oxides. Zn-Mg-O based materials and Zn-O based materials. In addition, In-Si-Ga- Zn-O based materials, In-Ga-B-Zn-O based materials, In-B-Zn-O based materials Alternatively, the above materials may contain SiO2. n-Ga-Zn-O materials are made of indium (In), gallium (Ga), and zinc (Zn ) and the composition ratio is not particularly limited. It may contain elements other than Zn.

[0248] Also, a two-layer structure in which a second crystalline oxide semiconductor layer is formed on a first crystalline oxide semiconductor layer is also available. The structure is not limited to the above, and a third crystalline oxide semiconductor layer may be formed after the second crystalline oxide semiconductor layer is formed. The process of film formation and heat treatment is repeated to form a laminated structure of three or more layers. Good too.

[0249] The first crystalline oxide semiconductor layer such as the oxide semiconductor layer 453 and the second crystalline oxide semiconductor layer By using stacked layers in transistors, it is possible to achieve stable electrical characteristics and high reliability. High-performance transistors can be realized.

[0250] <cpu> A specific example of a CPU having the above-mentioned semiconductor integrated circuit will be described with reference to FIG. 22. .

[0251] 22 is a block diagram showing a specific configuration of a CPU. Arithmetic logic unit (ALU) 90 on board 900 1, ALU Controller902, Instruction Decoder9 03, Interrupt Controller904, Timing Control ller905, Register906, Register Controller9 07, bus interface (Bus I / F) 908, rewritable ROM 909, It mainly has a ROM interface (ROM I / F) 920. The ROM I / F 920 may be provided on a separate chip. This is just a simplified example of the configuration of the CPU. Actual CPUs have a wide variety of configurations depending on their applications. It has the structure.

[0252] The instructions input to the CPU via Bus I / F 908 are The signal is input to Decoder 903, decoded, and then passed to ALU Controller 9. 02, Interrupt Controller904, Register Cont. The signal is input to roller 907 and timing controller 905.

[0253] ALU Controller902, Interrupt Controller9 04, Register Controller907, Timing Control The ler905 performs various controls based on the decoded instructions. The controller 902 generates signals to control the operation of the ALU 901. The interrupt controller 904 also Interrupt requests from external input / output devices and peripheral circuits are determined based on their priority and mask status. The Register Controller 907 determines and processes the Generates the address of 906 and reads or writes the register 906 depending on the CPU state. Perform writing.

[0254] In addition, the Timing Controller 905 controls the ALU 901, ALU Con troller902, Instruction Decoder903, Interr upt Controller904, Register Controller907 It generates a signal to control the timing of the operation of er905 generates an internal clock signal CLK2 based on the reference clock signal CLK1. It has an internal clock generator that supplies a clock signal CLK2 to the various circuits mentioned above.

[0255] In the CPU shown in FIG. 22, the memory circuit 11 shown in FIG. 1 is set in the register 906. The Register Controller 907 also has the registers shown in FIG. In the CPU shown in FIG. The star controller 907 follows the instructions from the ALU 901 and The register 906 selects the hold operation. In the storage circuit 11, sequential circuits 21_1 to 21_n are used to hold data, or The node electrically connected to one electrode of the capacitance element 32 is selected to hold data. When the sequential circuits 21_1 to 21_n are selected to hold data, the The power supply voltage is supplied to the memory circuit 11 in the transistor 906. If data retention is selected for the node electrically connected to one electrode, Re Therefore, the supply of the power supply voltage to the memory circuit 11 in the register 906 can be stopped.

[0256] In this way, when the CPU operation is temporarily stopped and the supply of power voltage is stopped, Even if the power is turned off, data can be retained, and power consumption can be reduced. For example, a user of a personal computer inputs information into an input device such as a keyboard. The CPU can be stopped even while input is stopped, thereby reducing power consumption. It is possible.

[0257] Although the CPU has been used as an example in the description, the semiconductor integrated circuit of the present invention is not limited to a CPU. DSP, custom LSI, FPGA (Field Programmable Gate Array) It can also be applied to LSIs such as LSIs (Large Scale Integration Arrays). [Example]

[0258] The field-effect mobility of insulated gate transistors, not limited to oxide semiconductors, is actually measured. The mobility of electrons is lower than the original mobility due to various reasons. There are defects inside the semiconductor and defects at the interface between the semiconductor and the insulating film. Using this method, we can theoretically derive the field-effect mobility assuming that there are no defects inside the semiconductor. I can.

[0259] Let μ0 be the intrinsic mobility of the semiconductor, and μ be the measured field-effect mobility. Assuming that there is a potential barrier (grain boundary, etc.),

[0260]

number

[0261] where E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. Also, assuming that the potential barrier originates from defects, Levin In the son model,

[0262]

number

[0263] where e is the elementary charge and N is the average defect density per unit area in the channel. , ε is the dielectric constant of the semiconductor, n is the number of carriers contained in the channel per unit area, C ox teeth Capacitance per unit area, V g is the gate voltage, and t is the channel thickness. If the semiconductor layer is less than 100 nm, the channel thickness can be considered to be the same as the semiconductor layer thickness. The drain current in the linear region, I d teeth,

[0264]

number

[0265] Here, L is the channel length and W is the channel width, where L=W=10μ m. Also, V d is the drain voltage. g Divide by and then take the logarithm of both sides When you take

[0266]

number

[0267] The right side of number 8 is V g As can be seen from this equation, the vertical axis is a function of ln(I d / V g ), the horizontal axis is 1 / V g From the slope of the line on the graph obtained by plotting the measured values ​​as The defect density N is calculated. That is, the I d -V g The defect density is evaluated based on the characteristics. As oxide semiconductors, indium (In), tin (Sn), and zinc (Zn) When the ratio is In:Sn:Zn=1:1:1, the defect density N is 1×10 12 / cm 2 Process degrees.

[0268] Based on the defect density thus obtained, using equations 5 and 6, μ0 = 120 cm 2 / V The mobility measured in the defective In-Sn-Zn oxide is 40 cm 2 / However, the oxide layer is free of defects inside the semiconductor and at the interface between the semiconductor and the insulating film. The semiconductor mobility μ0 is 120 cm 2 It can be expected that / Vs.

[0269] However, even if there are no defects inside the semiconductor, the electrons may be scattered at the interface between the channel and the gate insulating layer. The transport characteristics of the transistor are affected by the distance x from the gate insulating layer interface. The mobility μ1 at the location is

[0270]

number

[0271] where D is the electric field in the gate direction, and B and l are constants. From the above measurement results, B = 4.75 × 10 7 cm / s, l=10 nm (depth of interface scattering). As the pressure increases, the second term in equation 9 increases, and the mobility μ1 decreases.

[0272] Transistor transfer using an ideal oxide semiconductor channel with no internal defects The calculation results of the degree μ2 are shown in Figure 26. The calculation was performed using a Synopsys device simulator. Sentaurus Device is a software application for bandgap measurement of oxide semiconductors. The gap, electron affinity, relative permittivity, and thickness are 2.8 eV and 4.7 eV, respectively. These values ​​were measured for thin films formed by sputtering. This was obtained by doing so.

[0273] Furthermore, the work functions of the gate layer, source, and drain are set to 5.5 eV and 4. The gate insulating layer was 100 nm thick and the specific dielectric constant was 4.6 eV and 4.6 eV. The dielectric constant was set to 4.1. The channel length and width were both 10 μm, and the drain voltage V d is 0.1V.

[0274] As shown in Figure 26, the mobility is 100 cm at a gate voltage of just over 1 V. 2 Peaks above / Vs However, if the gate voltage is increased further, the interface scattering increases and the mobility decreases. In order to reduce interface scattering, it is necessary to flatten the semiconductor layer surface at the atomic level (A Atomic Layer Flatness is preferred.

[0275] When a miniaturized transistor is manufactured using an oxide semiconductor having such mobility, The results of calculating the characteristics are shown in Figures 27 to 29. The cross section of the transistor used in the calculations is The structure is shown in Figure 30. The transistor shown in Figure 30 has an n-type oxide semiconductor layer. + Conductivity type The semiconductor region 503a and the semiconductor region 503c are The resistivity of the conductor region 503c is 2×10 -3 Let it be Ωcm.

[0276] The transistor shown in FIG. 30A has a base insulating layer 501 and a layer embedded in the base insulating layer 501. The insulating layer 502 is formed on the buried insulating layer 502 made of aluminum oxide. The transistor is made up of a semiconductor region 503a, a semiconductor region 503c, and a channel region sandwiched between them. The gate layer 505 includes an intrinsic semiconductor region 503b that serves as a channel forming region. The width of 05 is 33 nm.

[0277] Between the gate layer 505 and the semiconductor region 503b, a gate insulating layer 504 is provided. The gate layer 505 is provided on both sides with sidewall insulators 506a and 506b. On the top of the gate layer 505 is an insulator 507 to prevent short circuits between the gate layer 505 and other wiring. The width of the sidewall insulator is set to 5 nm. The transistor has a source layer 508a and a drain layer 508b in contact with the transistor c. The channel width in the stator is set to 40 nm.

[0278] The transistor shown in FIG. 30B has a base insulating layer 501 and a A semiconductor region 503a, a semiconductor region 503c, and the semiconductor region 503b are formed on the buried insulator 502. Sandwiched between these are an intrinsic semiconductor region 503b, a 33 nm wide gate layer 505 and a gate insulating layer. The layer 504, the sidewall insulator 506a, the sidewall insulator 506b, the insulator 507, and the source layer 50 30(A) in that it has a drain layer 508a and a drain layer 508b. do.

[0279] The difference between the transistor shown in FIG. 30(A) and the transistor shown in FIG. 30(B) is that the sidewall The conductivity type of the semiconductor region under the insulator 506a and the sidewall insulator 506b. In the transistor shown in FIG. 1, the semiconductor under the sidewall insulator 506a and the sidewall insulator 506b The area is n + The semiconductor regions 503a and 503c have the same conductivity type. In the transistor shown in FIG. 30(B), the intrinsic semiconductor region 503b is the intrinsic semiconductor region 503b. In the semiconductor layer shown in FIG. 1(B), the semiconductor region 503a (semiconductor region 503c) and the gate There is an area where the layer 505 does not overlap by Loff. This area is called the offset area. The width Loff is called the offset length. As is clear from the figure, the offset length is It is the same as the width of the insulator 506a (sidewall insulator 506b).

[0280] The other parameters used in the calculation are as described above. We used the Sentaurus Device, a chair simulation software. , the drain current (I d , solid line) and movement Degree (μ, dotted line) of gate voltage (V g , the gate-source potential difference) dependence. current I d The drain voltage (potential difference between the drain and source) is set to +1V, and the mobility μ is The calculation was done with the input voltage set at +0.1V.

[0281] FIG. 27(A) shows the gate insulating layer with a thickness of 15 nm, and FIG. 27(B) shows the gate insulating layer with a thickness of 10 In Figure 27(C), the thickness is 5 nm. The drain current I d On the other hand, the off-state current (OFF current) is significantly reduced. The peak value of the temperature μ and the drain current I d There is no noticeable change in the on-state current. It was shown that the drain current exceeded 10 μA at a gate voltage of around 1 V.

[0282] FIG. 28 shows the offset length Loff of the transistor having the structure shown in FIG. 30(B). nm, the drain current I d (solid line) and mobility μ (dotted line) at gate voltage V g Depends The drain current I d The drain voltage is +1V, and the mobility μ is The calculation was performed with the gate insulating layer thickness set to 15 nm. FIG. 28(B) is for 10 nm, and FIG. 28(C) is for 5 nm. This is what was done.

[0283] FIG. 29 shows the offset length Lof The drain current I d (solid line) and the mobility μ (dotted line) The drain current I d The drain voltage is +1V, and the mobility μ is The calculation was performed with the voltage set to +0.1V. 29(B) is 10 nm, and FIG. 29(C) is 5 nm. The value is m.

[0284] In both cases, the thinner the gate insulating layer, the more significantly the off-state current decreases, while the peak of the mobility μ There is no noticeable change in the peak value or on-state current.

[0285] The peak of the mobility μ is 80 cm in FIG. 2 / Vs, but in Figure 28, 0cm 2 / Vs, 40cm in Figure 29 2 / Vs, the offset length Loff increases The off-current also shows a similar trend. On the other hand, the on-current also decreases with increasing offset length. It decreases with increasing Loff, but the decrease is much slower than the decrease in off-state current. In addition, it was shown that the drain current exceeded 10 μA at a gate voltage of around 1 V. It was.

[0286] A transistor with a channel formation region made of an oxide semiconductor containing In, Sn, and Zn as its main components The oxide semiconductor film is formed by heating the substrate or by forming the oxide semiconductor film. By performing heat treatment after forming the film, good properties can be obtained. An element that is contained in an amount of 5 atomic % or more by composition ratio.

[0287] Intentionally heating the substrate after forming an oxide semiconductor film containing In, Sn, and Zn as its main components This makes it possible to improve the field effect mobility of the transistor. This makes it possible to shift the threshold voltage of the transistor in a positive direction and make it normally off.

[0288] For example, FIGS. 31(A) to 31(C) show a semiconductor device having In, Sn, and Zn as main components, and a channel The length L is 3 μm, the channel width W is 10 μm, and the gate electrode is 100 nm thick. These are the characteristics of a transistor using a thin insulating layer. d was set to 10V.

[0289] Figure 31(A) shows a film made of In, Sn, and Zn as the main components by sputtering without intentionally heating the substrate. The figure shows the characteristics of a transistor when an oxide semiconductor film is formed as a component. Movement is 18.8cm 2 On the other hand, by intentionally heating the substrate, In, Forming an oxide semiconductor film containing Sn and Zn as its main components improves field-effect mobility. Fig. 31(B) shows the structure of the substrate heated to 200°C, which is mainly composed of In, Sn, and Zn. The transistor characteristics are shown for the case where an oxide semiconductor film is formed, and the field-effect mobility is 32. 2cm 2 / Vsec is obtained.

[0290] The field-effect mobility was measured by forming an oxide semiconductor film mainly composed of In, Sn, and Zn and then heating it. The effect can be further enhanced by further treatment. An oxide semiconductor film mainly composed of n was formed by sputtering at 200°C, and then heated at 650°C. The transistor characteristics after the treatment are shown below. At this time, the field effect mobility is 34.5 cm 2 / Vsec is obtained.

[0291] By intentionally heating the substrate, moisture is absorbed into the oxide semiconductor film during sputtering. In addition, by performing heat treatment after film formation, Hydrogen, a hydroxyl group, or moisture can be released and removed from the oxide semiconductor film. The field effect mobility can be improved as follows. In addition to removing impurities through hydration and dehydrogenation, the interatomic distance is shortened by densification. It is also estimated that crystallization can be achieved by removing impurities from oxide semiconductors and purifying them. Such a highly purified non-single-crystal oxide semiconductor can be ideally 00cm 2 It is estimated that it will be possible to achieve a field-effect mobility of more than 1 / Vsec. .

[0292] Oxygen ions are implanted into an oxide semiconductor whose main components are In, Sn, and Zn, and then the oxide semiconductor is heated to form a Hydrogen, hydroxyl groups, or moisture contained in the oxide semiconductor is released, and the heat treatment is performed simultaneously or simultaneously. The oxide semiconductor may be crystallized by subsequent heat treatment. By the crystallization treatment, a non-single-crystal oxide semiconductor with good crystallinity can be obtained.

[0293] The effect of intentionally heating the substrate during film formation and / or heat treatment after film formation is This not only improves field effect mobility but also contributes to making the transistor normally off. The oxides, mainly composed of In, Sn, and Zn, were formed without intentionally heating the substrate. The threshold voltage of a transistor that uses a semiconductor film as a channel formation region is shifted negatively. However, when an oxide semiconductor film is used that is formed by intentionally heating the substrate, In this case, the negative shift of the threshold voltage is eliminated. This tendency is shown in Figure 31(A) and Figure 31(B). This can also be confirmed by comparing B).

[0294] The threshold voltage can also be controlled by changing the ratio of In, Sn, and Zn. By setting the composition ratio to In:Sn:Zn=2:1:3, Normally-off can be expected. In addition, the composition ratio of the target is In:Sn:Z When n=2:1:3, an oxide semiconductor film with high crystallinity can be obtained.

[0295] The intentional substrate heating temperature or heat treatment temperature is 150°C or higher, preferably 200°C or higher. The temperature is preferably 400° C. or higher, and the temperature is preferably higher than 400° C. by forming the film or by heat treating it at a higher temperature. This makes it possible to make the resistor normally off.

[0296] In addition, by intentionally heating the substrate during film formation and / or by performing heat treatment after film formation, the gate barrier This can improve stability against bias stress. For example, 2MV / cm, 150 Under the conditions of 1 hour application at 20°C, the drift is less than ±1.5V, preferably 1.0 Less than V can be obtained.

[0297] In fact, Sample 1 was not subjected to heat treatment after the oxide semiconductor film formation, and Sample 2 was subjected to heat treatment at 650°C. The treated transistor of sample 2 was subjected to a BT test.

[0298] First, the substrate temperature is set to 25°C, and V ds is set to 10V, and the V of the transistor g -I d Measurement of characteristics The V ds indicates the drain voltage (potential difference between the drain and source). The substrate temperature was set to 150°C, and V ds Next, the voltage applied to the gate insulating layer was set to 0.1 V. V so that the field strength is 2MV / cm g A voltage of 20 V was applied to the electrode and the electrode was maintained for 1 hour. To, V g Next, the substrate temperature was set to 25°C, and V ds is set to 10V, and the transistor V g -I d This measurement was called the Plus BT test.

[0299] Similarly, first set the substrate temperature to 25°C, and then V ds is set to 10V, and the V of the transistor g -I d Next, the substrate temperature was set to 150°C, and V ds was set to 0.1 V. Next, V so that the electric field strength applied to the gate insulating layer is -2MV / cm g Apply -20V to Then, V g Next, the substrate temperature was set to 25°C, and V ds is set to 10V, and the V of the transistor g -I d This is called the minus BT test. Call.

[0300] The results of the positive BT test for sample 1 are shown in Figure 32(A), and the results of the negative BT test are shown in Figure 32(B). The results of the positive BT test for sample 2 are shown in Figure 33(A), and the results of the negative BT test for sample 2 are shown in Figure 33(B). The results are shown in Figure 33(B).

[0301] The threshold voltage fluctuations of sample 1 due to the positive BT test and the negative BT test are as follows: The positive and negative BT tests for sample 2 were 1.80V and -0.42V, respectively. The threshold voltage shifts due to the BT test were 0.79 V and 0.76 V, respectively. In both Sample 1 and Sample 2, the change in threshold voltage before and after the BT test was small. It is clear that it is highly reliable.

[0302] The heat treatment can be carried out in an oxygen atmosphere, but it is first necessary to use nitrogen or an inert gas, or a reducing gas. It is also possible to perform heat treatment under pressure and then in an oxygen-containing atmosphere. By adding oxygen to the oxide semiconductor after dehydrogenation, the effect of the heat treatment can be further enhanced. To add oxygen later, oxygen ions can be accelerated by an electric field to form a thin film on the oxide semiconductor. A method of injecting the film may also be applied.

[0303] Defects due to oxygen vacancies occur in the oxide semiconductor and at the interface between the oxide semiconductor and the film. However, by such heat treatment, excess oxygen is contained in the oxide semiconductor. In this case, the oxygen deficiency that is constantly generated can be compensated for by excess oxygen. The element is mainly oxygen present between lattices, and the oxygen concentration is 1×10 16 / cm 3 2x1 or more 0 20 / cm 3 If the following conditions are met, the oxide semiconductor can be incorporated without causing distortion to the crystal. It is possible.

[0304] Furthermore, the heat treatment is performed so that at least a part of the oxide semiconductor contains crystals. For example, a more stable oxide semiconductor film can be obtained when the composition ratio is In:Sn:Zn= Acid film formed by sputtering using a 1:1:1 target without intentionally heating the substrate The compound semiconductor film was found to have halo patterns by X-ray diffraction (XRD). The oxide semiconductor film thus formed is crystallized by heat treatment. The heat treatment temperature can be any temperature, but for example, by performing heat treatment at 650°C, X Clear diffraction peaks can be observed by X-ray diffraction.

[0305] In fact, XRD analysis of the In-Sn-Zn-O film was carried out. r Using the AXS D8 ADVANCE X-ray diffractometer, out-of-plane method was measured.

[0306] Samples A and B were prepared for XRD analysis. The method for preparing sample B will be described.

[0307] An In-Sn-Zn-O film was formed to a thickness of 100 nm on a dehydrogenated quartz substrate. Ta.

[0308] The In-Sn-Zn-O film was prepared using a sputtering system in an oxygen atmosphere at a power of 100 W. The target was In:Sn:Zn=1:1:1 [atomic ratio]. An In-Sn-Zn-O target was used. The substrate heating temperature during film formation was 200°C. The sample prepared in this manner was designated as Sample A.

[0309] Next, a sample prepared in the same manner as sample A was subjected to heat treatment at a temperature of 650°C. The heat treatment is first performed in a nitrogen atmosphere for 1 hour, and then in an oxygen atmosphere without lowering the temperature. The sample was then subjected to a further heat treatment at 400 K for 1 hour.

[0310] Figure 34 shows the XRD spectra of sample A and sample B. In sample A, peaks derived from crystals In sample B, the 2θ was observed around 35 deg and 37 deg to 38 deg. Peaks derived from crystals were observed in eg.

[0311] In this way, oxide semiconductors containing In, Sn, and Zn as their main components are formed on a substrate intentionally. Improving transistor characteristics by heating and / or heat treatment after film formation It is possible.

[0312] This substrate heating and heat treatment removes hydrogen and hydroxyl groups, which are harmful impurities for oxide semiconductors, from the film. It has the effect of preventing oxides from being included in the film or removing them from the film. High purity can be achieved by removing hydrogen, which acts as a donor impurity in semiconductors. This allows the transistor to be normally off, and the oxide semiconductor is highly purified. By doing so, the off-current can be reduced to 1 aA / μm or less. The unit indicates the current value per 1 μm of channel width.

[0313] Figure 35 shows the relationship between the off-state current of a transistor and the reciprocal of the substrate temperature (absolute temperature) at the time of measurement. For simplicity, the value obtained here is the reciprocal of the substrate temperature during measurement multiplied by 1000 (1000 Specifically, as shown in FIG. 35, when the substrate temperature is 125°C, 1aA / μm (1×10 -18 A / μm) or less, 100zA / μm at 85℃ (1×10 -19 A / μm) or less, and at room temperature (27°C) 1zA / μm (1×10 - 21 Preferably, the resistance can be 0.1 aA / μm at 125°C. m(1×10 -19 A / μm) or less at 85°C, -20 A / μm) or less at room temperature, -22 A / μm or less It is possible.

[0314] However, in order to prevent hydrogen and moisture from being mixed into the oxide semiconductor film during the film formation, Leaks from the nozzle and outgassing from the inner walls of the deposition chamber are sufficiently suppressed, achieving high purity of sputtering gas. For example, the sputtering gas should have a dew point of -70°C so that moisture is not contained in the film. It is preferable to use a gas that is equal to or less than the above. It is preferable to use a highly purified target so that it does not contain impurities. Oxide semiconductors whose main components are In, Sn, and Zn can be thermally treated to remove moisture from the film. However, the moisture release temperature is higher than that of oxide semiconductors whose main components are In, Ga, and Zn. Therefore, it is preferable to form a film that does not contain moisture from the beginning.

[0315] In addition, the transistor using sample B, which was subjected to a heat treatment at 650°C after the oxide semiconductor film formation, The relationship between the substrate temperature and the electrical characteristics was evaluated.

[0316] The transistor used for the measurement has a channel length L of 3 μm, a channel width W of 10 μm, and v is 0 μm and dW is 0 μm. ds The voltage was set to 10V. The substrate temperature was -4 The experiments were carried out at 0°C, -25°C, 25°C, 75°C, 125°C and 150°C. In the gate electrode, the overlap width between the gate layer and the pair of electrodes is called Lov, and the oxide semiconductor film The protrusion of the pair of electrodes is called dW.

[0317] In Figure 36, I d (solid line) and field-effect mobility (dotted line) g The dependency is shown in Fig. Figure 37(A) shows the relationship between the substrate temperature and the threshold voltage, and Figure 37(B) shows the relationship between the substrate temperature and the field effect mobility. Shows the relationship of degrees.

[0318] From FIG. 37(A), it can be seen that the higher the substrate temperature, the lower the threshold voltage. The voltage range was 1.09V to -0.23V from -40℃ to 150℃.

[0319] Furthermore, it can be seen from FIG. 37(B) that the higher the substrate temperature, the lower the field-effect mobility. The temperature range is -40℃ to 150℃ and 36cm 2 / Vs~32cm 2 / Vs Therefore, it can be seen that the fluctuation of the electrical characteristics is small within the above temperature range.

[0320] The above-mentioned oxide semiconductor containing In, Sn, and Zn as main components is used for the channel formation region. According to the transistor, the field effect mobility is increased to 30 while the off-current is kept below 1 aA / μm. cm 2 / Vsec or more, preferably 40cm 2 / Vsec or more, preferably 60cm 2 / Vsec or more, and the on-current value required by the LSI can be satisfied. For example, FET with L / W=33nm / 40nm, gate voltage 2.7V, drain voltage 1.0V When the on-state current is 12 μA or more, the transistor can operate at a constant voltage. Even in a wide temperature range, sufficient electrical characteristics can be ensured. In this case, a transistor made of oxide semiconductor can be mixed into an integrated circuit made of Si semiconductor. Even if the chip is mounted on a semiconductor device, it is possible to realize an integrated circuit with new functions without sacrificing operating speed. can. [Example]

[0321] In this example, an example of a transistor using an In-Sn-Zn-O film as an oxide semiconductor film is described. This will be explained with reference to FIG.

[0322] Figure 38 shows the structure of a coplanar top-gate / top-contact transistor. 38A shows a top view of a transistor. (B) shows a cross section AB corresponding to the dashed line AB in FIG. 38(A).

[0323] The transistor shown in FIG. 38B includes a substrate 600 and a base insulating film provided on the substrate 600. The insulating film 602, the protective insulating film 604 provided around the insulating base film 602, and the insulating base film 604 are 02 and a high resistance region 606a and a low resistance region 606 provided on the protective insulating film 604. an oxide semiconductor film 606 having b and a gate insulating layer provided over the oxide semiconductor film 606; 608, a gate insulating layer 608 provided to overlap with the oxide semiconductor film 606 with the gate insulating layer 608 interposed therebetween. a sidewall insulating film 612 provided in contact with the side surface of the gate layer 610; a pair of electrodes 614 provided in contact with the low resistance region 606b; and an interlayer insulating film 616 provided to cover the film 606, the gate layer 610, and the pair of electrodes 614; and at least one of a pair of electrodes 614 through an opening provided in the interlayer insulating film 616. and a wiring 618 provided in connection therewith.

[0324] Although not shown, a protective film provided to cover the interlayer insulating film 616 and the wiring 618 is By providing the protective film, the surface conduction of the interlayer insulating film 616 can be prevented. The minute leakage current that occurs due to the semiconductor device can be reduced, and the off-state current of the transistor can be reduced. can be done. [Example]

[0325] In this example, a transistor using an In-Sn-Zn-O film as an oxide semiconductor film, which is different from the above, was used. Another example of a transistor will be described.

[0326] FIG. 39 is a top view and a cross-sectional view showing the structure of the transistor fabricated in this example. 39(A) is a top view of a transistor. Also, FIG. 39(B) is a diagram of a point on FIG. 39(A). FIG. 2 is a cross-sectional view corresponding to the dashed line AB.

[0327] The transistor shown in FIG. 39B includes a substrate 700 and a base insulating film provided over the substrate 700. an insulating film 702, an oxide semiconductor film 706 provided on the base insulating film 702, and an oxide semiconductor A pair of electrodes 714 in contact with the oxide semiconductor film 706 and a pair of electrodes 714 a gate insulating layer 708 provided between the oxide semiconductor film 706 and the gate insulating layer 708; a gate insulating layer 708 and a gate layer 710 provided to overlap the gate insulating layer 708; The insulating interlayer 716 is formed by the insulating film 716 and a pair of insulating films 716 are formed by the insulating film 716 through an opening. The wiring 718 connected to the electrode 714 is provided to cover the interlayer insulating film 716 and the wiring 718. and a protective film 720 formed thereon.

[0328] The substrate 700 is a glass substrate, the underlying insulating film 702 is a silicon oxide film, and the oxide The semiconductor film 706 is an In—Sn—Zn—O film, and the pair of electrodes 714 is a tongue. a stainless film as the gate insulating layer 708, a silicon oxide film as the gate layer 710, and a nitride film as the gate insulating layer 710. The interlayer insulating film 716 is a layered structure of a tantalum nitride film and a tungsten film. The laminated structure of the conductor film and polyimide film is made of titanium film, aluminum film, The laminated structure in which the titanium film is formed in this order is a polyimide film as a protective film 720, and Each was used.

[0329] In the transistor having the structure shown in FIG. 39A, the gate layer 710 and the pair of electrodes The width of the overlap with the oxide semiconductor film 706 is referred to as Lov. The protrusion of pole 714 is called dW. [Explanation of symbols]

[0330] 10 Arithmetic circuit 11 Memory circuit 12 Power gate control circuit 20 Power gate transistor 21_1~21_n Sequential circuit 21_x sequential circuit 22_1~22_n Combinational Circuits 30 Flip-Flop 31 Transistor 32 Capacitor element 50 boards 51 Base layer 52 Gate Layer 53 Gate insulating layer 54 Oxide semiconductor layer 55a Source Layer 55b drain layer 56 Protective insulation layer 57 Planarizing insulating layer 58a conductive layer 58b Conductive layer 100 boards 102 Protective layer 104 Semiconductor Area 106 Element isolation insulating layer 108 Gate insulating layer 110 Gate Layer 112 Insulating layer 114a Impurity region 114b Impurity region 116 Channel formation region 118 Sidewall insulating layer 120a High concentration impurity region 120b High concentration impurity region 122 Metal layer 124a Metal compound area 124b Metal compound area 126 Interlayer insulation layer 128 Interlayer Insulation Layer 130a Source Layer 130b drain layer 132 Insulating layer 134 Conductive Layer 136a Electrode layer 136b Electrode layer 136d Gate layer 138 Gate insulating layer 140 Oxide semiconductor layer 142a Source Layer 142b Drain layer 144 Protective Insulation Layer 146 Interlayer insulation layer 148 Conductive Layer 150a electrode layer 150b electrode layer 150d electrode layer 150e electrode layer 152 Insulating layer 154a Electrode layer 154b Electrode layer 154d electrode layer 160 transistors 162a Oxide conductive layer 162b Oxide conductive layer 164 transistors 210a NAND gate 210b NAND gate 210c NAND gate 210d NAND gate 210e NAND gate 210f NAND gate 211a AND Gate 211b AND gate 212a switch 212b switch 212c switch 212d Switch 400 insulating layer 437 Insulating Layer 450a Crystalline oxide semiconductor layer 450b Crystalline oxide semiconductor layer 453 Oxide semiconductor layer 501 Undercoat insulation layer 502 Embedded insulator 503a Semiconductor area 503b Semiconductor area 503c Semiconductor field 504 Gate insulating layer 505 Gate Layer 506a Sidewall insulator 506b Sidewall insulator 507 Insulators 508a Source Layer 508b Drain layer 600 boards 602 Undercoat insulating film 604 Protective insulating film 606 Oxide semiconductor film 606a High resistance area 606b Low resistance region 608 Gate insulating layer 610 Gate Layer 612 Sidewall insulating film 614 Electrode 616 Interlayer insulating film 618 Interlayer insulating film 700 boards 702 Undercoat insulating film 706 Oxide semiconductor film 708 Gate insulating layer 710 Gate Layer 714 Electrode 716 Interlayer insulating film 718 Wiring 720 Protective film 801 Measurement System 811 Transistor 812 transistors 813 Capacitor element 814 transistors 815 Transistor 900 boards 901 ALU 902 ALU Controller 903 Instruction Decoder 904 Interrupt Controller 905 Timing Controller 906 Register 907 Register Controller 908 Bus I / F 909 ROM 920 ROM interface< / cpu>

Claims

1. a first transistor including silicon in a channel formation region and a second transistor including an oxide semiconductor in a channel formation region; a semiconductor device in which one of a source or a drain of the first transistor is always electrically connected to one of a source or a drain of the second transistor, a first conductive film having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating film having a region disposed above the first conductive film; a second conductive film having a region disposed above the first insulating film and functioning as a gate electrode of the second transistor; a third conductive film having a region disposed above the first insulating film; a second insulating film having a region disposed above the second conductive film and a region disposed above the third conductive film; a semiconductor film having a region disposed above the second insulating film and having a channel formation region of the second transistor; a third insulating film having a region disposed above the semiconductor film; a fourth conductive film having a region disposed above the third insulating film; a fifth conductive film having a region disposed above the third insulating film and always in electrical conduction with the third conductive film; the second conductive film has a region in contact with an upper surface of the first insulating film, the third conductive film has a region in contact with an upper surface of the first insulating film, the fourth conductive film is always electrically connected to one of the source and drain of the first transistor and is always electrically connected to one of the source and drain of the second transistor; when the third conductive film is electrically connected to the fourth conductive film at least through a channel formation region of the first transistor, the fifth conductive film is electrically connected to the fourth conductive film; Semiconductor device.

2. a first transistor including silicon in a channel formation region and a second transistor including an oxide semiconductor in a channel formation region; a semiconductor device in which one of a source or a drain of the first transistor is always electrically connected to one of a source or a drain of the second transistor, a first conductive film having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating film having a region disposed above the first conductive film; a second conductive film having a region disposed above the first insulating film and functioning as a gate electrode of the second transistor; a third conductive film having a region disposed above the first insulating film; a second insulating film having a region disposed above the second conductive film and a region disposed above the third conductive film; a semiconductor film having a region disposed above the second insulating film and having a channel formation region of the second transistor; a third insulating film having a region disposed above the semiconductor film; a fourth conductive film having a region disposed above the third insulating film; a fifth conductive film having a region disposed above the third insulating film and always in electrical conduction with the third conductive film; the third conductive film overlaps with the fifth conductive film; the second conductive film has a region in contact with an upper surface of the first insulating film, the third conductive film has a region in contact with an upper surface of the first insulating film, the fourth conductive film is always electrically connected to one of the source and drain of the first transistor and is always electrically connected to one of the source and drain of the second transistor; when the third conductive film is electrically connected to the fourth conductive film at least through a channel formation region of the first transistor, the fifth conductive film is electrically connected to the fourth conductive film; Semiconductor device.

3. a first transistor including silicon in a channel formation region and a second transistor including an oxide semiconductor in a channel formation region; a semiconductor device in which one of a source or a drain of the first transistor is always electrically connected to one of a source or a drain of the second transistor, a first conductive film having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating film having a region disposed above the first conductive film; a second conductive film having a region disposed above the first insulating film and functioning as a gate electrode of the second transistor; a third conductive film having a region disposed above the first insulating film; a second insulating film having a region disposed above the second conductive film and a region disposed above the third conductive film; a semiconductor film having a region disposed above the second insulating film and having a channel formation region of the second transistor; a third insulating film having a region disposed above the semiconductor film; a fourth conductive film having a region disposed above the third insulating film; a fifth conductive film having a region disposed above the third insulating film and always in electrical conduction with the third conductive film; the third conductive film overlaps with the fifth conductive film; the second conductive film has a region in contact with an upper surface of the first insulating film, the third conductive film has a region in contact with an upper surface of the first insulating film, the fourth conductive film has a region in contact with an upper surface of the third insulating film, the fifth conductive film has a region in contact with an upper surface of the third insulating film, the fourth conductive film is always electrically connected to one of the source and drain of the first transistor and is always electrically connected to one of the source and drain of the second transistor; when the third conductive film is electrically connected to the fourth conductive film at least through a channel formation region of the first transistor, the fifth conductive film is electrically connected to the fourth conductive film; Semiconductor device.

4. a first transistor including silicon in a channel formation region and a second transistor including an oxide semiconductor in a channel formation region; a semiconductor device in which one of a source or a drain of the first transistor is always electrically connected to one of a source or a drain of the second transistor, a first conductive film having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating film having a region disposed above the first conductive film; a second conductive film having a region disposed above the first insulating film and functioning as a gate electrode of the second transistor; a third conductive film having a region disposed above the first insulating film; a second insulating film having a region disposed above the second conductive film and a region disposed above the third conductive film; a semiconductor film having a region disposed above the second insulating film and having a channel formation region of the second transistor; a third insulating film having a region disposed above the semiconductor film; a fourth conductive film having a region disposed above the third insulating film; a fifth conductive film having a region disposed above the third insulating film and always in electrical conduction with the third conductive film; the second conductive film has a region in contact with an upper surface of the first insulating film, the third conductive film has a region in contact with an upper surface of the first insulating film, the fourth conductive film has a region in contact with an upper surface of the third insulating film, the fifth conductive film has a region in contact with an upper surface of the third insulating film, the fourth conductive film is always electrically connected to one of the source and drain of the first transistor and is always electrically connected to one of the source and drain of the second transistor; when the third conductive film is electrically connected to the fourth conductive film at least through a channel formation region of the first transistor, the fifth conductive film is electrically connected to the fourth conductive film; Semiconductor device.

5. In any one of claims 1 to 4, a channel formation region of the first transistor is disposed in a silicon semiconductor film on an insulating surface; Semiconductor device.

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