Imaging device and camera

Abstract

To provide an imaging device capable of suppressing dark current.SOLUTION: An imaging device according to one aspect of the present disclosure includes: a photoelectric conversion unit 12 which converts light into a signal charge; a first conductivity-type first diffusion region 67n to which the signal charge is input; a first conductivity-type second diffusion region 68bn; a contact plug cp1 having a first surface in contact with the first diffusion region 67n; a contact plug cp3 having a second surface in contact with the second diffusion region 68bn; a reset transistor 26 including the first diffusion region 67n as one of a source and a drain and including a gate electrode 26e; and an amplifier transistor 22 including the second diffusion region 68bn as one of the source and the drain and including a gate electrode 22e. In a plan view, a distance between the first surface of the contact plug cp1 and the gate electrode 26e is shorter than a distance between the second surface of the contact plug cp3 and the gate electrode 22e.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to an imaging device. [Background technology]

[0002] Charge-coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors are widely used in digital cameras, etc. These image sensors have photodiodes formed on a semiconductor substrate.

[0003] On the other hand, as disclosed in Patent Document 1, for example, an imaging device has been proposed that has a structure in which a photoelectric conversion unit having a photoelectric conversion layer is disposed above a semiconductor substrate. An imaging device having such a structure is sometimes called a stacked imaging device. In a stacked imaging device, charges generated by photoelectric conversion are accumulated in a charge accumulation region provided in the semiconductor substrate. A signal corresponding to the amount of charge accumulated in the charge accumulation region is read out via a CCD circuit or a CMOS circuit formed on the semiconductor substrate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2012 / 147302 Summary of the Invention [Problem to be solved by the invention]

[0005] In imaging devices having charge storage regions formed on a semiconductor substrate, dark current, which is leakage current from or to the charge storage region, can degrade the image obtained. It would be beneficial to be able to reduce such leakage current.

[0006] Therefore, the present disclosure provides an imaging device that can suppress dark current. [Means for solving the problem]

[0007] According to certain non-limiting exemplary embodiments of the present disclosure, the following is provided:

[0008] An imaging device according to one embodiment of the present disclosure includes a photoelectric conversion unit that converts light into signal charges, a first diffusion region of a first conductivity type to which the signal charges are input, a second diffusion region of the first conductivity type, a first plug having a first surface in contact with the first diffusion region, a second plug having a second surface in contact with the second diffusion region, a first transistor including the first diffusion region as one of its source and drain and including a first gate, and a second transistor including the second diffusion region as one of its source and drain and including a second gate, wherein, in a planar view, the distance between the first surface of the first plug and the first gate is smaller than the distance between the second surface of the second plug and the second gate.

[0009] An imaging device according to another aspect of the present disclosure includes a photoelectric conversion unit that converts light into signal charges, a first diffusion region of a first conductivity type to which the signal charges are input, a second diffusion region of the first conductivity type, a first plug including a first contact in contact with the first diffusion region, a second plug including a second contact in contact with the second diffusion region, a first transistor including the first diffusion region as one of its source and drain and including a first gate, and a second transistor including the second diffusion region as one of its source and drain and including a second gate, wherein in a planar view, the distance between the first contact and the first gate is smaller than the distance between the second contact and the second gate.

[0010] An imaging device according to another aspect of the present disclosure includes a photoelectric conversion unit that converts light into signal charges, a first diffusion region of a first conductivity type to which the signal charges are input, a second diffusion region of the first conductivity type, a first plug having a first surface in contact with the first diffusion region, a second plug having a second surface in contact with the second diffusion region, a first transistor including the first diffusion region as one of a source and a drain and a first gate, and a second transistor including the second diffusion region as one of a source and a drain and a second gate, wherein the dimension of the first surface in the length direction of the first gate of the first transistor is smaller than the dimension of the second surface in the length direction of the second gate of the second transistor.

[0011] An imaging device according to another aspect of the present disclosure includes a photoelectric conversion unit that converts light into signal charges, a first diffusion region of a first conductivity type to which the signal charges are input, a second diffusion region of the first conductivity type, a first plug including a first contact in contact with the first diffusion region, a second plug including a second contact in contact with the second diffusion region, a first transistor including the first diffusion region as one of a source and a drain and including a first gate, and a second transistor including the second diffusion region as one of a source and a drain and including a second gate, wherein the dimension of the first contact in the length direction of the first gate of the first transistor is smaller than the dimension of the second contact in the length direction of the second gate of the second transistor.

[0012] Furthermore, a camera according to one aspect of the present disclosure includes the imaging device according to any one of the above aspects.

[0013] Furthermore, the general or specific aspects may be realized as an element, a device, a module, a system, or a method. Furthermore, the general or specific aspects may be realized as any combination of an element, a device, a module, a system, and a method.

[0014] Additionally, additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings. The benefits and / or advantages may be provided individually by the various embodiments or features disclosed in the specification and drawings, and not all are required to obtain one or more of them. [Effects of the Invention]

[0015] According to the present disclosure, it is possible to provide an imaging device capable of suppressing dark current. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a diagram showing a configuration of an imaging device according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing a circuit configuration of the imaging device according to the first embodiment. [Figure 3] FIG. 3 is a plan view showing a layout within a pixel of the imaging device according to the first embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view showing the device structure of a pixel of the imaging device according to the first embodiment. [Figure 5] FIG. 5 is an enlarged cross-sectional view showing the vicinity of two contact plugs of the imaging device according to the first embodiment. [Figure 6] FIG. 6 is a diagram showing the concentration distribution of electrons and holes near the contact plug of the imaging device according to the first embodiment for each pad width. [Figure 7] FIG. 7 is a plan view showing a layout within a pixel of an imaging device according to Modification 1 of Embodiment 1. In FIG. [Figure 8] FIG. 8 is a plan view showing a layout within a pixel of an imaging device according to Modification 2 of Embodiment 1. In FIG. [Figure 9] FIG. 9 is a plan view showing the layout within a pixel of the imaging device according to the second embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a device structure of a pixel of the imaging device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] (Summary of the Disclosure) An outline of one aspect of the present disclosure is as follows.

[0018] An imaging device according to one aspect of the present disclosure includes a semiconductor substrate including a first diffusion region of a first conductivity type and a second diffusion region of the first conductivity type, a first plug connected to the first diffusion region and including a semiconductor, a second plug connected to the second diffusion region and including a semiconductor, and a photoelectric conversion unit electrically connected to the first plug, wherein when viewed from a direction perpendicular to the semiconductor substrate, an area of ​​the second plug is larger than an area of ​​the first plug.

[0019] Leakage current due to crystal defects is likely to flow on the surface of a semiconductor substrate. The larger the depletion layer that spreads along the surface of the semiconductor substrate, the more likely this leakage current will flow. In contrast, with the imaging device according to this aspect, the area of ​​the first plug electrically connected to the photoelectric conversion unit is reduced, thereby narrowing the range on the surface of the semiconductor substrate that is affected by the potential of the first plug. This makes it possible to suppress the spread of the depletion layer from the first diffusion region along the surface of the semiconductor substrate. As a result, with the imaging device according to this aspect, it is possible to suppress leakage current, i.e., dark current.

[0020] Also, for example, an imaging device according to one aspect of the present disclosure may further include an insulating film located on the semiconductor substrate, wherein the first plug includes a first contact in contact with the first diffusion region and penetrating the insulating film, and a first pad located on the first contact and having a larger area than the first contact when viewed in a direction perpendicular to the semiconductor substrate; the second plug includes a second contact in contact with the second diffusion region and penetrating the insulating film, and a second pad located on the second contact and having a larger area than the second contact when viewed in a direction perpendicular to the semiconductor substrate; and the area of ​​the second pad may be larger than the area of ​​the first pad when viewed in a direction perpendicular to the semiconductor substrate.

[0021] This reduces the area of ​​the first pad of the first plug connected to the first diffusion region, narrowing the range affected by the potential of the first pad. This makes it possible to suppress the expansion of the depletion layer from the first diffusion region along the surface of the semiconductor substrate. This also makes it possible to suppress leakage current from or to the first diffusion region.

[0022] Also, for example, an imaging device according to one aspect of the present disclosure may further include a first transistor including the first diffusion region as one of a source and a drain and including a first gate, and a second transistor including the second diffusion region as one of a source and a drain and including a second gate, wherein the length of the second pad in a direction parallel to the width direction of the second gate may be longer than the length of the first pad in a direction parallel to the width direction of the first gate.

[0023] This allows the area of ​​the first pad to be easily reduced by shortening the width.

[0024] Furthermore, for example, the distance between the second pad and the second gate may be longer than the distance between the first pad and the first gate.

[0025] This reduces the distance between the first pad and the gate electrode, thereby suppressing the expansion of the depletion layer formed on the gate electrode side, and therefore suppressing leakage current from or to the first diffusion region.

[0026] Furthermore, for example, when viewed in a direction perpendicular to the semiconductor substrate, the area of ​​the second contact may be larger than the area of ​​the first contact.

[0027] This reduces the contact area between the first contact of the first plug and the first diffusion region, thereby reducing the amount of impurities contained in the first contact that diffuse into the first diffusion region. This reduces the impurity concentration at the junction of the first diffusion region, thereby reducing the electric field strength at the junction. This reduces the expansion of the depletion layer from the first diffusion region, thereby reducing leakage current.

[0028] Also, for example, the first plug and the second plug may contain impurities of the first conductivity type, and the concentration of the impurities of the first conductivity type in the second plug may be higher than the concentration of the impurities of the first conductivity type in the first plug.

[0029] This reduces the concentration of impurities contained in the first plug, thereby reducing the amount of impurities contained in the first plug that diffuse into the first diffusion region. This reduces the concentration of impurities at the junction of the first diffusion region, thereby reducing the electric field strength at the junction. This reduces the expansion of the depletion layer from the first diffusion region, thereby reducing leakage current.

[0030] Furthermore, for example, the semiconductor device may further include a first transistor including a first gate and the first diffusion region as one of a source and a drain, and a second transistor including a second gate and the second diffusion region as one of a source and a drain, wherein the length of the second pad in a direction parallel to the length of the second gate is longer than the length of the first pad in a direction parallel to the length of the first gate. Note that, when viewed from a direction perpendicular to the semiconductor substrate, the length of the gate is a direction perpendicular to the width of the gate.

[0031] In this disclosure, all or part of a circuit, unit, device, component, or part, or all or part of a functional block in a block diagram, may be implemented by one or more electronic circuits, including a semiconductor device, a semiconductor integrated circuit (IC), or an LSI (large scale integration). An LSI or IC may be integrated on a single chip or may be configured by combining multiple chips. For example, functional blocks other than memory elements may be integrated on a single chip. While the terms LSI and IC are used here, the term may be changed depending on the degree of integration, and may be referred to as a system LSI, a VLSI (very large scale integration), or an ULSI (ultra large scale integration). A field programmable gate array (FPGA), which is programmable after LSI fabrication, or a reconfigurable logic device, which can reconfigure connections within an LSI or set up circuit partitions within an LSI, may also be used for the same purpose.

[0032] Furthermore, all or part of the functions or operations of a circuit, unit, device, component, or section can be implemented by software processing. In this case, the software is recorded on one or more non-transitory recording media such as ROMs, optical disks, hard disk drives, etc., and when the software is executed by a processor, the functions specified in the software are performed by the processor and peripheral devices. A system or device may include one or more non-transitory recording media on which software is recorded, a processor, and necessary hardware devices, such as interfaces.

[0033] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, and step orders shown in the following embodiments are merely examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as no contradiction occurs. Furthermore, among the components in the following embodiments, components not recited in independent claims are described as optional components. In each drawing, components having substantially the same functions are designated by common reference symbols, and redundant descriptions may be omitted or simplified.

[0034] Furthermore, the various elements shown in the drawings are merely shown schematically to facilitate understanding of the present disclosure, and the dimensional ratios and appearances may differ from the actual objects. In other words, each drawing is a schematic diagram and is not necessarily an accurate depiction. Therefore, for example, the scales of the drawings do not necessarily match.

[0035] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or coincident, terms indicating the shape of elements, such as circular or rectangular, and numerical ranges are not expressions that only express the strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0036] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upper direction (vertically upper) and lower direction (vertically lower) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in the stacked structure. Specifically, the light-receiving side of the imaging device is referred to as "upper," and the side opposite the light-receiving side is referred to as "lower." Similarly, the "upper surface" and "lower surface" of each component refer to the surface facing the light-receiving side of the imaging device as the "upper surface" and the surface facing the opposite side of the light-receiving side as the "lower surface." Note that the terms "upper," "lower," "upper surface," and "lower surface" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device during use. Furthermore, the terms "upper" and "lower" apply not only to cases where two components are arranged with a gap between them and another component is present between them, but also to cases where two components are arranged closely together and the two components are in contact with each other. Furthermore, in this specification, "plan view" refers to a view perpendicular to the semiconductor substrate.

[0037] (Embodiment 1) Fig. 1 is a diagram showing the configuration of an imaging device according to the present embodiment. As shown in Fig. 1, the imaging device 100 according to the present embodiment has a plurality of pixels 10 and a peripheral circuit 40 formed on a semiconductor substrate 60. Each pixel 10 includes a photoelectric conversion unit 12 arranged above the semiconductor substrate 60. In other words, a stacked imaging device 100 will be described as an example of an imaging device according to the present disclosure.

[0038] In the example shown in FIG. 1 , pixels 10 are arranged in a matrix of m rows and n columns. Here, m and n are each integers equal to or greater than 2. The pixels 10 are arranged, for example, two-dimensionally on the semiconductor substrate 60 to form an imaging region R1. As described above, each pixel 10 includes a photoelectric conversion unit 12 arranged above the semiconductor substrate 60. Therefore, the imaging region R1 is defined as the region of the semiconductor substrate 60 that is covered by the photoelectric conversion units 12. Note that, in FIG. 1 , the photoelectric conversion units 12 of each pixel 10 are shown spatially separated from one another for ease of explanation; however, the photoelectric conversion units 12 of multiple pixels 10 may be arranged on the semiconductor substrate 60 without any spacing between them.

[0039] The number and arrangement of the pixels 10 are not limited to the example shown in the figure. For example, the number of pixels 10 included in the imaging device 100 may be one. In this example, the center of each pixel 10 is located on a lattice point of a square lattice, but the arrangement of the pixels 10 does not have to be like that. For example, multiple pixels 10 may be arranged so that each center is located on a lattice point of a triangular lattice, a hexagonal lattice, or the like. Furthermore, for example, if the pixels 10 are arranged one-dimensionally, the imaging device 100 can be used as a line sensor.

[0040] In the configuration illustrated in FIG. 1 , the peripheral circuit 40 includes a vertical scanning circuit 46 and a horizontal signal readout circuit 48. The vertical scanning circuit 46, also called a row scanning circuit, is connected to address signal lines 34 provided corresponding to each row of the plurality of pixels 10. The horizontal signal readout circuit 48, also called a column scanning circuit, is connected to vertical signal lines 35 provided corresponding to each column of the plurality of pixels 10. As schematically illustrated in FIG. 1 , these circuits are arranged in a peripheral region R2 outside the imaging region R1. The peripheral circuit 40 may further include a signal processing circuit, an output circuit, a control circuit, a power supply that supplies a predetermined voltage to each pixel 10, and the like. A portion of the peripheral circuit 40 may be arranged on a substrate other than the semiconductor substrate 60 on which the pixels 10 are formed.

[0041] Fig. 2 is a diagram showing the circuit configuration of the imaging device 100 according to the present embodiment. In order to avoid complicating the drawing, Fig. 2 shows four pixels 10 arranged in two rows and two columns out of the plurality of pixels 10 shown in Fig. 1.

[0042] The photoelectric conversion unit 12 of each pixel 10 generates positive and negative charges, typically hole-electron pairs, in response to incident light. The photoelectric conversion unit 12 of each pixel 10 is connected to an accumulation control line 39, and a predetermined voltage is applied to the accumulation control line 39 during operation of the imaging device 100. By applying a predetermined voltage to the accumulation control line 39, one of the positive and negative charges generated by photoelectric conversion can be selectively accumulated in the charge accumulation region. The following describes an example in which the positive charge, of the positive and negative charges generated by photoelectric conversion, is used as a signal charge.

[0043] Each pixel 10 includes a signal detection circuit 14 electrically connected to the photoelectric conversion unit 12. In the configuration illustrated in FIG. 2, the signal detection circuit 14 includes an amplification transistor 22 and a reset transistor 26. In this example, the signal detection circuit 14 further includes an address transistor 24. As will be described in detail later with reference to the drawings, the amplification transistor 22, reset transistor 26, and address transistor 24 of the signal detection circuit 14 are typically field effect transistors (FETs) formed on a semiconductor substrate 60 that supports the photoelectric conversion unit 12. Unless otherwise noted, the following description will focus on an example in which an N-channel metal oxide semiconductor FET (MOSFET) is used as the transistor. Note that which of the two diffusion layers of the FET corresponds to the source and drain is determined by the polarity of the FET and the current potential. Therefore, which corresponds to the source and drain may vary depending on the operating state of the FET.

[0044] 2, the gate of the amplification transistor 22 is electrically connected to the photoelectric conversion unit 12. The signal charge generated by the photoelectric conversion unit 12 is accumulated in a charge accumulation region connected to a charge accumulation node ND between the photoelectric conversion unit 12 and the amplification transistor 22. The charge accumulation node ND corresponds to the wiring electrically connecting the charge accumulation region, the gate of the amplification transistor 22, and the lower electrode of the photoelectric conversion unit 12, and the charge accumulation region.

[0045] The drain of the amplification transistor 22 is connected to a power supply wiring 32 that supplies a predetermined power supply voltage VDD to each pixel 10 when the imaging device 100 is in operation. A power supply (not shown) connected to the power supply wiring 32 is also called a source follower power supply. The power supply voltage VDD is, for example, about 3.3 V, but is not limited to this. The amplification transistor 22 outputs a signal voltage corresponding to the amount of signal charge generated by the photoelectric conversion unit 12. The source of the amplification transistor 22 is connected to the drain of the address transistor 24.

[0046] A vertical signal line 35 is connected to the source of the address transistor 24. As shown in FIGS. 1 and 2, a vertical signal line 35 is provided for each column of pixels 10, and a load circuit 42 and a column signal processing circuit 44 are connected to each vertical signal line 35. The load circuit 42 and the amplification transistor 22 form a source follower circuit.

[0047] An address signal line 34 is connected to the gate of the address transistor 24. One address signal line 34 is provided for each row of pixels 10. The address signal line 34 is connected to a vertical scanning circuit 46, which applies a row selection signal to the address signal line 34 to control the on / off state of the address transistor 24. This causes the row to be read out to be scanned in the vertical direction, i.e., the column direction, and the row to be read out is selected. The vertical scanning circuit 46 controls the on / off state of the address transistor 24 via the address signal line 34, thereby reading out the output of the amplifier transistor 22 of the selected pixel 10 to the corresponding vertical signal line 35. The location of the address transistor 24 is not limited to the example shown in FIG. 2 , and may be between the drain of the amplifier transistor 22 and the power supply wiring 32.

[0048] The signal voltage from the pixel 10 output to the vertical signal line 35 via the address transistor 24 is input to a corresponding one of a plurality of column signal processing circuits 44 provided for each column of a plurality of pixels 10 corresponding to the vertical signal line 35. The column signal processing circuit 44 and the load circuit 42 may be part of the peripheral circuit 40 described above.

[0049] The column signal processing circuits 44 perform noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion. The column signal processing circuits 44 are connected to a horizontal signal readout circuit 48. The horizontal signal readout circuit 48 sequentially reads out signals from the multiple column signal processing circuits 44 to a horizontal common signal line 49.

[0050] In the configuration illustrated in FIG. 2 , the signal detection circuit 14 includes a reset transistor 26 whose drain is connected to the charge storage node ND. A reset signal line 36, which is connected to the vertical scanning circuit 46, is connected to the gate of the reset transistor 26. Like the address signal lines 34, the reset signal lines 36 are provided for each row of pixels 10. The vertical scanning circuit 46 can select the pixels 10 to be reset row by row by applying a row selection signal to the address signal line 34. The vertical scanning circuit 46 can also turn on the reset transistor 26 of the selected row by applying a reset signal that controls the on / off of the reset transistor 26 to the gate of the reset transistor 26 via the reset signal line 36. Turning on the reset transistor 26 resets the potential of the charge storage node ND.

[0051] In this example, the source of the reset transistor 26 is connected to one of the feedback lines 53 provided for each column of the pixels 10. That is, in this example, the voltage of the feedback line 53 is supplied to the charge storage node ND as a reset voltage for initializing the charge of the photoelectric conversion unit 12. Here, the above-mentioned feedback line 53 is connected to the output terminal of a corresponding one of the inverting amplifiers 50 provided for each column of the pixels 10. The inverting amplifier 50 may be part of the above-mentioned peripheral circuit 40.

[0052] Consider one column of pixels 10. As shown in FIG. 2, the inverting input terminal of the inverting amplifier 50 is connected to the vertical signal line 35 of that column. The output terminal of the inverting amplifier 50 is connected to one or more pixels 10 in that column via a feedback line 53. During operation of the imaging device 100, a predetermined voltage Vref is supplied to the non-inverting input terminal of the inverting amplifier 50. By selecting one of the pixels 10 in that column and turning on the address transistor 24 and reset transistor 26, a feedback path can be formed that negatively feeds back the output of that pixel 10. The formation of the feedback path causes the voltage of the vertical signal line 35 to converge to the input voltage Vref to the non-inverting input terminal of the inverting amplifier 50. In other words, the formation of the feedback path resets the voltage of the charge storage node ND to a voltage that causes the voltage of the vertical signal line 35 to become Vref. The voltage Vref can be any voltage between the power supply voltage and the ground voltage. For example, the voltage Vref is between 0 V and 3.3 V. As an example, the voltage Vref is a positive voltage of 1 V or close to 1 V. The inverting amplifier 50 may be called a feedback amplifier. Thus, the imaging device 100 has a feedback circuit 16 that includes the inverting amplifier 50 in part of the feedback path.

[0053] As is well known, thermal noise called kTC noise occurs when a transistor is turned on or off. The noise generated when the reset transistor 26 is turned on or off is called reset noise. After resetting the potential of the charge storage region, the reset noise generated by turning off the reset transistor 26 remains in the charge storage region before the signal charge is accumulated. However, the reset noise generated when the reset transistor 26 is turned off can be reduced by using a feedback circuit 16. Details of suppressing reset noise using the feedback circuit 16 are described in Patent Document 1, the entire disclosure of which is incorporated herein by reference.

[0054] 2, the formation of a feedback path causes the AC component of the thermal noise to be fed back to the source of the reset transistor 26. In the configuration illustrated in FIG. 2, the feedback path is formed until just before the reset transistor 26 is turned off, so it is possible to reduce the reset noise that occurs when the reset transistor 26 is turned off.

[0055] Fig. 3 is a plan view showing the layout within a pixel 10 of an imaging device 100 according to the present embodiment. Fig. 3 schematically shows the arrangement of elements formed on a semiconductor substrate 60 when the pixel 10 shown in Fig. 4 is viewed from a direction perpendicular to the semiconductor substrate 60. Specifically, Fig. 3 shows the arrangement of an amplifier transistor 22, an address transistor 24, and a reset transistor 26 included in the pixel 10. Here, the amplifier transistor 22 and the address transistor 24 are arranged linearly along the vertical direction on the page.

[0056] Fig. 4 is a schematic cross-sectional view showing the device structure of the pixel 10 of the imaging device 100 according to the present embodiment. Fig. 4 is a cross-sectional view of the pixel 10 cut along line IV-IV in Fig. 3 and expanded in the direction of the arrows.

[0057] 3 and 4, the first diffusion region 67n, which is an n-type impurity region, is the drain region of the reset transistor 26 and is a charge storage region.

[0058] 3 and 4, the pixel 10 in the imaging device 100 according to the present embodiment includes a reset transistor 26 that includes, as one of a source and a drain, a first diffusion region 67n containing impurities of a first conductivity type and that accumulates signal charges converted by the photoelectric conversion unit 12, and a second diffusion region 68an containing impurities of the first conductivity type as the other of the source and drain. The reset transistor 26 is an example of a first transistor that includes the first diffusion region as one of a source and a drain and has a first gate.

[0059] In this embodiment, the first conductivity type is n-type. That is, the first diffusion region 67n and the second diffusion region 68an are n-type impurity regions. For example, the concentration of n-type impurities in the first diffusion region 67n is lower than the concentration of n-type impurities in the second diffusion region 68an. The first diffusion region 67n and the second diffusion region 68an are provided at different positions in the semiconductor substrate 60.

[0060] The pixel 10 further includes an amplifier transistor 22 and an address transistor 24. The amplifier transistor 22 and the address transistor 24 are examples of second transistors that include a second diffusion region as one of a source and a drain and a second gate. The amplifier transistor 22 includes a second diffusion region 68bn containing n-type impurities as one of a source and a drain, and a third diffusion region 68cn containing n-type impurities as the other of a source and a drain. The address transistor 24 includes a second diffusion region 68dn containing n-type impurities as one of a source and a drain, and a third diffusion region 68cn containing n-type impurities as the other of a source and a drain. The second diffusion region 68bn, the second diffusion region 68dn, and the third diffusion region 68cn are each examples of n-type impurity regions provided at different positions in the semiconductor substrate 60.

[0061] In this case, the n-type impurity concentration of the first diffusion region 67n may be lower than the n-type impurity concentration of the second diffusion region 68bn, the second diffusion region 68dn, and the third diffusion region 68cn. This reduces the junction concentration at the junction between the first diffusion region 67n and the semiconductor substrate 60, thereby reducing the electric field strength at the junction. This reduces leakage current from or to the first diffusion region 67n, which is a charge storage region.

[0062] In the imaging device 100 according to this embodiment, the semiconductor substrate 60 contains impurities of a second conductivity type. The second conductivity type is a conductivity type different from the first conductivity type, and is p-type in this embodiment. The concentrations of the n-type impurities contained in the first diffusion region 67n and the p-type impurities contained in the semiconductor substrate 60 are, for example, 1×1016 atoms / cm 3 5x10 or more 16 atoms / cm 3 This reduces the junction concentration between the first diffusion region 67n and the semiconductor substrate 60, making it possible to suppress an increase in the electric field strength at the junction, thereby reducing the leakage current at the junction.

[0063] As shown in FIG. 4, the pixel 10 generally includes a portion of a semiconductor substrate 60, a photoelectric conversion unit 12 disposed above the semiconductor substrate 60, and a wiring structure 80. The wiring structure 80 is disposed in an interlayer insulating layer 90 formed between the photoelectric conversion unit 12 and the semiconductor substrate 60, and includes a structure that electrically connects the photoelectric conversion unit 12 to the amplification transistor 22 formed in the semiconductor substrate 60. Here, the interlayer insulating layer 90 has a stacked structure including four insulating layers: an insulating layer 90a, an insulating layer 90b, an insulating layer 90c, and an insulating layer 90d. The wiring structure 80 includes four wiring layers: an insulating layer 80a, an insulating layer 80b, an insulating layer 80c, and an insulating layer 80d, and plugs pa1, pa2, pa3, pa4, pa5, pa6, pa7, pb, pc, and pd disposed between these wiring layers.

[0064] Furthermore, the wiring layer 80a is the layer closest to the semiconductor substrate 60 among the multiple wiring layers included in the wiring structure 80. Specifically, the wiring layer 80a includes contact plugs cp1, cp2, cp3, and cp4, as well as gate electrodes 22e, 24e, and 26e. Needless to say, the number of insulating layers in the interlayer insulating layer 90 and the number of wiring layers in the wiring structure 80 are not limited to this example and can be set arbitrarily.

[0065] The photoelectric conversion unit 12 is disposed on the interlayer insulating layer 90. The photoelectric conversion unit 12 includes a pixel electrode 12a formed on the interlayer insulating layer 90, a transparent electrode 12c facing the pixel electrode 12a, and a photoelectric conversion layer 12b disposed between the pixel electrode 12a and the transparent electrode 12c. The photoelectric conversion layer 12b of the photoelectric conversion unit 12 is formed from an organic material or an inorganic material such as amorphous silicon. It receives incident light through the transparent electrode 12c and generates positive and negative charges through photoelectric conversion. The photoelectric conversion layer 12b is typically formed continuously across multiple pixels 10. In plan view, the photoelectric conversion layer 12b is formed as a single flat plate that covers most of the imaging region R1 of the semiconductor substrate 60. In other words, the photoelectric conversion layer 12b is shared by multiple pixels 10. In other words, the photoelectric conversion unit 12 provided for each pixel 10 has a different portion of the photoelectric conversion layer 12b for each pixel 10. The photoelectric conversion layer 12b may include a layer made of an organic material and a layer made of an inorganic material. The photoelectric conversion layer 12b may be provided separately for each pixel 10.

[0066] The transparent electrode 12c is formed of a transparent conductive material such as ITO (Indium Tin Oxide) and is disposed on the light-receiving surface side of the photoelectric conversion layer 12b. The transparent electrode 12c is typically formed continuously across multiple pixels 10, similar to the photoelectric conversion layer 12b. That is, the transparent electrode 12c is shared by multiple pixels 10. In other words, the photoelectric conversion unit 12 provided for each pixel 10 has a different portion of the transparent electrode 12c for each pixel 10. The transparent electrode 12c may be provided separately for each pixel 10.

[0067] Although not shown in FIG. 4, the transparent electrode 12c is connected to the aforementioned accumulation control line 39. During operation of the imaging device 100, the potential of the accumulation control line 39 is controlled to make the potential of the transparent electrode 12c different from the potential of the pixel electrode 12a, thereby allowing the pixel electrode 12a to collect signal charges generated by photoelectric conversion. For example, the potential of the accumulation control line 39 is controlled so that the potential of the transparent electrode 12c is higher than the potential of the pixel electrode 12a. Specifically, a positive voltage of approximately 10 V is applied to the accumulation control line 39. This allows the holes, of the hole-electron pairs generated in the photoelectric conversion layer 12b, to be collected as signal charges by the pixel electrode 12a. The signal charges collected by the pixel electrode 12a are accumulated in the first diffusion region 67n via the wiring structure 80.

[0068] The pixel electrode 12a is an electrode formed from a metal such as aluminum or copper, a metal nitride, or polysilicon doped with impurities to make it conductive. The pixel electrode 12a is spatially separated from the pixel electrodes 12a of other adjacent pixels 10, and is thereby electrically isolated from the pixel electrodes 12a of other pixels 10.

[0069] 4, the semiconductor substrate 60 includes a support substrate 61 and one or more semiconductor layers formed on the support substrate 61. Here, a p-type silicon (Si) substrate is exemplified as the support substrate 61. In this example, the semiconductor substrate 60 has a p-type semiconductor layer 61p on the support substrate 61, an n-type semiconductor layer 62n on the p-type semiconductor layer 61p, a p-type semiconductor layer 63p on the n-type semiconductor layer 62n, and a p-type semiconductor layer 65p on the p-type semiconductor layer 63p. The p-type semiconductor layer 63p is formed over the entire surface of the support substrate 61. The p-type semiconductor layer 65p has a p-type impurity region 66p having a lower impurity concentration than the p-type semiconductor layer 65p, a first diffusion region 67n formed in the p-type impurity region 66p, a second diffusion region 68an, a second diffusion region 68bn, a second diffusion region 68dn, a third diffusion region 68cn, and an element isolation region 69.

[0070] Each of the p-type semiconductor layer 61p, the n-type semiconductor layer 62n, the p-type semiconductor layer 63p, and the p-type semiconductor layer 65p is typically formed by ion implantation of impurities into a semiconductor layer formed by epitaxial growth. The impurity concentrations of the p-type semiconductor layer 63p and the p-type semiconductor layer 65p are approximately the same and higher than the impurity concentration of the p-type semiconductor layer 61p. The n-type semiconductor layer 62n disposed between the p-type semiconductor layer 61p and the p-type semiconductor layer 63p suppresses the inflow of minority carriers from the support substrate 61 or the peripheral circuit 40 into the first diffusion region 67n, which is a charge accumulation region that accumulates signal charges. During operation of the imaging device 100, the potential of the n-type semiconductor layer 62n is controlled via a well contact (not shown) provided outside the imaging region R1 shown in FIG. 1.

[0071] In this example, the semiconductor substrate 60 also has a p-type region 64 provided between the p-type semiconductor layer 63p and the support substrate 61 so as to penetrate the p-type semiconductor layer 61p and the n-type semiconductor layer 62n. The p-type region 64 has a higher impurity concentration than the p-type semiconductor layer 63p and the p-type semiconductor layer 65p, and electrically connects the p-type semiconductor layer 63p and the support substrate 61. During operation of the imaging device 100, the potentials of the p-type semiconductor layer 63p and the support substrate 61 are controlled via a substrate contact (not shown) provided outside the imaging region R1. By arranging the p-type semiconductor layer 65p so as to be in contact with the p-type semiconductor layer 63p, the potential of the p-type semiconductor layer 65p can be controlled via the p-type semiconductor layer 63p during operation of the imaging device 100.

[0072] An amplifier transistor 22, an address transistor 24, and a reset transistor 26 are formed on the semiconductor substrate 60. The reset transistor 26 includes a first diffusion region 67n, a second diffusion region 68an, a portion of an insulating layer 70 formed on the semiconductor substrate 60, and a gate electrode 26e on the insulating layer 70. The gate electrode 26e is an example of a first gate and specifically functions as the gate of the reset transistor 26. The first diffusion region 67n and the second diffusion region 68an function as the drain region and source region, respectively, of the reset transistor 26. The first diffusion region 67n functions as a charge accumulation region that temporarily accumulates signal charges generated by the photoelectric conversion unit 12.

[0073] The amplifier transistor 22 includes a second diffusion region 68bn, a third diffusion region 68cn, a part of the insulating layer 70, and a gate electrode 22e on the insulating layer 70. The gate electrode 22e is an example of a second gate, and specifically functions as the gate of the amplifier transistor 22. The second diffusion region 68bn and the third diffusion region 68cn function as the drain region and source region of the amplifier transistor 22, respectively.

[0074] An element isolation region 69 is disposed between the second diffusion region 68bn and the first diffusion region 67n. The element isolation region 69 is, for example, a p-type impurity diffusion region. The impurity concentration of the element isolation region 69 is higher than the impurity concentrations of the p-type semiconductor layer 65p and the p-type impurity region 66p. The element isolation region 69 electrically isolates the amplifier transistor 22 from the reset transistor 26.

[0075] As shown in FIG. 4, the first diffusion region 67n and the isolation region 69 are arranged so as not to contact each other because the first diffusion region 67n is formed in the p-type impurity region 66p. For example, when a p-type impurity region is used as the isolation region 69, if the first diffusion region 67n and the isolation region 69 are in contact with each other, both the p-type impurity concentration and the n-type impurity concentration at the junction become high. Therefore, a leakage current due to this high junction concentration is likely to occur around the junction between the first diffusion region 67n and the isolation region 69. In other words, by arranging the first diffusion region 67n and the isolation region 69 so as not to contact each other, even if a high-concentration p-type impurity region is used for the isolation region 69, an increase in the pn junction concentration can be suppressed, thereby suppressing leakage current. There is also a method of using STI (Shallow Trench Isolation) as the element isolation region 69, but in this case too, the first diffusion region 67n and the STI may be arranged so as not to be in contact with each other in order to reduce leakage current caused by crystal defects on the sidewall of the STI.

[0076] The element isolation regions 69 are also disposed between adjacent pixels 10, electrically isolating the signal detection circuits 14 therebetween. Here, the element isolation regions 69 are provided around the pair of the amplification transistor 22 and the address transistor 24 and around the reset transistor 26.

[0077] The address transistor 24 includes a third diffusion region 68cn, a second diffusion region 68dn, a portion of the insulating layer 70, and a gate electrode 24e on the insulating layer 70. The gate electrode 24e is an example of a second gate, and specifically functions as the gate of the address transistor 24. In this example, the address transistor 24 shares the third diffusion region 68cn with the amplifier transistor 22, thereby being electrically connected to the amplifier transistor 22. The third diffusion region 68cn functions as the drain region of the address transistor 24, and the second diffusion region 68dn functions as the source region of the address transistor 24.

[0078] In this example, an insulating layer 71 is provided to cover the gate electrode 26e of the reset transistor 26, the gate electrode 22e of the amplifier transistor 22, and the gate electrode 24e of the address transistor 24. The insulating layer 71 is, for example, a silicon oxide film. The insulating layer 71 may have a stacked structure including multiple insulating layers.

[0079] 4 and 5, a sidewall 73 of the contact plug cp1 and a sidewall 74 of the gate electrode 26e are located on the insulating layer 71. The sidewalls 73 and 74 are formed of, for example, a silicon nitride film. The sidewalls 73 and 74 fill the space between the contact plug cp1 and the gate electrode 26e. That is, in the portion between the contact plug cp1 and the gate electrode 26e, the sidewalls 73 and 74 cover the first diffusion region 67n in a plan view.

[0080] Therefore, compared to when the first diffusion region 67n is covered only with the insulating layer 70 and the insulating layer 71, damage to the first diffusion region 67n and contamination due to metal diffusion can be reduced in the portion between the contact plug cp1 and the gate electrode 26e. Damage to the first diffusion region 67n may be caused, for example, by plasma used in a process after the formation of the first diffusion region 67n. Plasma damage may be physical damage caused by collisions of accelerated ions and defect generation caused by light. The light may be, for example, ultraviolet light. In this embodiment, as described below, the pad cp1b and the gate electrode 26e are spaced apart. This facilitates filling the portion between the contact plug cp1 and the gate electrode 26e with sidewalls 73 and 74. The portion between the contact plug cp1 and the gate electrode 26e may be filled only with the sidewall 74 without providing the sidewall 73. Sidewalls may also be used to fill the portions between other contact plugs and gate electrodes. In this case, similar effects can be obtained for other impurity regions.

[0081] The insulating layer 70 and the insulating layer 71 have a plurality of contact holes. Here, as shown in FIG. 4, the insulating layer 70 and the insulating layer 71 are provided with contact holes h1, h2, h3, h4, h5, h6, h7, h8, h9, h10, and h11. When viewed perpendicularly to the semiconductor substrate 60, the contact holes h1-h4 are formed at positions overlapping the first diffusion region 67n, the second diffusion region 68an, the second diffusion region 68bn, and the second diffusion region 68dn. The contact holes h1-h4 are through holes that penetrate the insulating layer 70. Contact plugs cp1-cp4 are disposed at the positions of the contact holes h1-h4, respectively. The insulating layer 70 has a thickness of, for example, 10 nm, but is not limited to this.

[0082] Contact holes h5-h7 are formed at positions overlapping gate electrode 26e, gate electrode 22e, and gate electrode 24e, respectively, when viewed from a direction perpendicular to semiconductor substrate 60. Contact holes h5-h7 are through holes that penetrate insulating layer 71. Plugs pa3, pa2, and pa4 are disposed at the positions of contact holes h5-h7, respectively.

[0083] Contact holes h8-h11 are formed at positions overlapping with contact plugs cp1-cp4, respectively, when viewed from a direction perpendicular to semiconductor substrate 60. Contact holes h8-h11 are through holes that penetrate insulating layer 71. Plugs pa1, pa5, pa6, and pa7 are disposed at the positions of contact holes h8-h11, respectively.

[0084] 4, the wiring layer 80a is a layer including the contact plugs cp1-cp4, and the gate electrodes 22e, 24e, and 26e, and is typically a polysilicon layer doped with n-type impurities. Of the wiring layers included in the wiring structure 80, the wiring layer 80a is disposed closest to the semiconductor substrate 60.

[0085] The wiring layer 80b and the plugs pa1-pa7 are disposed in the insulating layer 90a. The wiring layer 80b is disposed in the insulating layer 90a and may include the vertical signal lines 35, the address signal lines 34, the power supply lines 32, the reset signal lines 36, and the feedback lines 53.

[0086] The plug pa1 connects the contact plug cp1 and the wiring layer 80b. The plug pa2 connects the gate electrode 22e and the wiring layer 80b. That is, the first diffusion region 67n and the gate electrode 22e of the amplification transistor 22 are electrically connected to each other via the contact plug cp1, the plug pa1, the plug pa2, and the wiring layer 80b.

[0087] The plug pa3 connects the reset signal line 36 included in the wiring layer 80b to the gate electrode 26e. The plug pa4 connects the address signal line 34 included in the wiring layer 80b to the gate electrode 24e. The plug pa5 connects the feedback line 53 included in the wiring layer 80b to the contact plug cp2. The plug pa6 connects the power supply line 32 (not shown in FIG. 4) included in the wiring layer 80b to the contact plug cp3. The plug pa7 connects the vertical signal line 35 included in the wiring layer 80b to the contact plug cp4.

[0088] With this configuration, the vertical signal line 35 is connected to the second diffusion region 68dn via the plug pa7 and the contact plug cp4. The address signal line 34 is connected to the gate electrode 24e via the plug pa4. The power supply wiring 32 is connected to the second diffusion region 68bn via the plug pa6 and the contact plug cp3. The reset signal line 36 is connected to the gate electrode 26e via the plug pa3. The feedback line 53 is connected to the second diffusion region 68an via the plug pa5 and the contact plug cp2.

[0089] At least one of the vertical signal line 35, the address signal line 34, the power supply line 32, the reset signal line 36, and the feedback line 53 may be included in the wiring layer 80c or 80d instead of the wiring layer 80b.

[0090] A plug pb disposed in the insulating layer 90b connects the wiring layer 80b to the wiring layer 80c. Similarly, a plug pc disposed in the insulating layer 90c connects the wiring layer 80c to the wiring layer 80d. A plug pd disposed in the insulating layer 90d connects the wiring layer 80d to the pixel electrode 12a of the photoelectric conversion unit 12. The wiring layers 80b-80d, as well as the plugs pa1-pa7 and plugs pb-pd, are typically formed from a metal such as copper or tungsten, a metal nitride, or a metal compound such as a metal oxide.

[0091] The plugs pa1, pa2, plugs pb-pd, wiring layers 80b-80d, and contact plug cp1 electrically connect the photoelectric conversion unit 12 and the signal detection circuit 14 formed on the semiconductor substrate 60. The plugs pa1, plugs pa2, plugs pb-pd, wiring layers 80b-80d, contact plug cp1, the pixel electrode 12a of the photoelectric conversion unit 12, the gate electrode 22e of the amplifying transistor 22, and the first diffusion region 67n function as a charge accumulation node that accumulates the signal charge generated by the photoelectric conversion unit 12.

[0092] Here, attention is focused on the n-type impurity region formed in the semiconductor substrate 60. Of the n-type impurity regions formed in the semiconductor substrate 60, a first diffusion region 67n is disposed in a p-type impurity region 66p formed in a p-type semiconductor layer 65p serving as a p-well. The first diffusion region 67n is formed near the surface of the semiconductor substrate 60, with at least a portion of it located on the surface of the semiconductor substrate 60. A junction capacitance formed by a pn junction between the p-type impurity region 66p and the first diffusion region 67n functions as a capacitance that stores at least a portion of the signal charge and constitutes a part of the charge storage node.

[0093] 4, the first diffusion region 67n includes a first region 67a and a second region 67b. The impurity concentration of the first region 67a of the first diffusion region 67n is lower than that of the second diffusion region 68an, the second diffusion region 68bn, the second diffusion region 68dn, and the third diffusion region 68cn. The second region 67b of the first diffusion region 67n is formed within the first region 67a and has a higher impurity concentration than that of the first region 67a. A contact hole h1 is located on the second region 67b, and a contact plug cp1 is connected to the second region 67b via the contact hole h1.

[0094] As described above, by arranging the p-type semiconductor layer 65p adjacent to the p-type semiconductor layer 63p, it is possible to control the potential of the p-type semiconductor layer 65p via the p-type semiconductor layer 63p during operation of the imaging device 100. By employing such a structure, it is possible to arrange the first region 67a of the first diffusion region 67n and the p-type impurity region 66p, which are regions with relatively low impurity concentrations, around the second region 67b of the first diffusion region 67n, which is the portion where the contact plug cp1, electrically connected to the photoelectric conversion unit 12, contacts the semiconductor substrate 60. By relatively increasing the impurity concentration of the second region 67b, which is the portion where the contact plug cp1 and the semiconductor substrate 60 are connected, a depletion layer spreads around the portion where the contact plug cp1 and the semiconductor substrate 60 are connected, thereby achieving the effect of suppressing depletion.

[0095] In this way, by suppressing depletion around the contact portion between the contact plug cp1 and the semiconductor substrate 60, it is possible to suppress leakage current caused by defect levels in the semiconductor substrate 60 at the interface between the contact plug cp1 and the semiconductor substrate 60. Furthermore, by connecting the contact plug cp1 to the second region 67b having a relatively high impurity concentration, an effect of reducing contact resistance can be obtained.

[0096] The contact plug cp1 is an example of a first plug including a semiconductor, and is connected to the first diffusion region 67n. The contact plug cp1 is electrically connected to the photoelectric conversion unit 12. Here, being electrically connected means that the potential is substantially equal to that of the pixel electrode 12a of the photoelectric conversion unit 12. Note that wiring resistance is not taken into consideration.

[0097] The contact plug cp2, the contact plug cp3, and the contact plug cp4 are each an example of a second plug containing a semiconductor. The contact plug cp2 is connected to the second diffusion region 68an. The contact plug cp3 is connected to the second diffusion region 68bn. The contact plug cp4 is connected to the second diffusion region 68dn. The contact plugs cp3 and cp4 are not electrically connected to the photoelectric conversion unit 12. In this embodiment, the contact plugs cp2, cp3, and cp4 have the same configuration. The specific configurations of the contact plugs cp1 and cp3 will be described below with reference to FIG. 5.

[0098] Fig. 5 is an enlarged cross-sectional view showing the vicinity of two contact plugs in the imaging device according to the present embodiment. Specifically, Fig. 5 shows an enlarged view of the area including the contact plug cp1 and the contact plug cp3 in the cross-sectional view shown in Fig. 4.

[0099] As shown in FIG. 5, the contact plug cp1 has a contact cp1a and a pad cp1b. The contact cp1a and the pad cp1b are each part of the contact plug cp1. The contact plug cp1 is formed using a conductive semiconductor material such as polysilicon. The contact plug cp1 contains a first conductivity type impurity. The first conductivity type impurity is, for example, an n-type impurity such as phosphorus.

[0100] The contact cp1a is an example of a first contact, and is in contact with the first diffusion region 67n and penetrates the insulating layer 70. Specifically, the contact cp1a is provided so as to fill the contact hole h1. The shape of the contact cp1a in a plan view matches the shape of the contact hole h1 in a plan view. As shown in FIG. 3, the shape of the contact cp1a in a plan view is, for example, circular, but may also be rectangular.

[0101] The pad cp1b is an example of a first pad, is located on the contact cp1a, and has a larger area than the contact cp1a when viewed in a direction perpendicular to the semiconductor substrate 60. As shown in FIG. 3, the pad cp1b completely covers the contact cp1a in a plan view. The contact cp1a is located at the center of the pad cp1b. The shape of the pad cp1b in a plan view is, for example, rectangular, but is not limited to this. The shape of the pad cp1b in a plan view matches the shape of the contact plug cp1 in a plan view.

[0102] As shown in FIG. 5, the contact plug cp3 has a contact cp3a and a pad cp3b. The contact cp3a and the pad cp3b are each part of the contact plug cp3. The contact plug cp3 is formed using a conductive semiconductor material such as polysilicon. The contact plug cp3 contains a first conductivity type impurity. The first conductivity type impurity is, for example, an n-type impurity such as phosphorus. In this embodiment, the impurity concentration of the contact plug cp3 is equal to the impurity concentration of the contact plug cp1.

[0103] The contact cp3a is an example of a second contact, and is in contact with the second diffusion region 68bn and penetrates the insulating layer 70. Specifically, the contact cp3a is provided so as to fill the contact hole h3. The shape of the contact cp3a in a plan view matches the shape of the contact hole h3 in a plan view. As shown in FIG. 3, the shape of the contact cp3a in a plan view is, for example, circular, but may also be rectangular.

[0104] The pad cp3b is an example of a second pad, is located on the contact cp3a, and has a larger area than the contact cp3a when viewed in a direction perpendicular to the semiconductor substrate 60. As shown in FIG. 3, the pad cp3b completely covers the contact cp3a in a plan view. The contact cp3a is located at the center of the pad cp3b. The shape of the pad cp3b in a plan view is, for example, rectangular, but is not limited to this. The shape of the pad cp3b in a plan view matches the shape of the contact plug cp3 in a plan view.

[0105] 3, in a plan view, the area of ​​contact plug cp1 is smaller than the areas of contact plugs cp2, cp3, and cp4. In other words, when viewed in a direction perpendicular to the semiconductor substrate 60, the areas of contact plugs cp2, cp3, and cp4 are each larger than the area of ​​contact plug cp1. For example, in a plan view, contact plug cp1 has the smallest area among the multiple plugs included in pixel 10.

[0106] For example, in a plan view, the area of ​​the pad cp1b is smaller than the area of ​​the pad cp3b, and in this embodiment, the area of ​​the contact cp1a is equal to the area of ​​the contact cp3a.

[0107] 3, the width W3 of the pad cp3b is longer than the width W1 of the pad cp1b. The width W1 is the length of the pad cp1b in a direction parallel to the width direction of the gate electrode 26e of the reset transistor 26. The width W3 is the length of the pad cp3b in a direction parallel to the width direction of the gate electrode 22e of the amplification transistor 22. For example, the width W1 is shorter than the width of any of the other pads, namely, the contact plug cp2, the contact plug cp3, and the contact plug cp4, included in the pixel 10.

[0108] As described above, the contact plug cp1 is connected to the second region 67b of the first diffusion region 67n. The second region 67b contains impurities thermally diffused from the contact plug cp1 through the contact hole h1. The impurities are, for example, n-type impurities. The n-type impurities are, for example, phosphorus. As described above, in a plan view, the area of ​​the contact plug cp1 is smaller than the areas of the contact plugs cp2, cp3, and cp4. Therefore, the amount of impurity contained in the contact plug cp1 can be smaller than the amount of impurity contained in the contact plugs cp2, cp3, and cp4. Therefore, the impurity concentration of the second region 67b formed below the contact plug cp1 can be made lower than the impurity concentrations of the regions formed below the contact plugs cp2, cp3, and cp4. This makes it possible to suppress junction leakage around the second region 67b.

[0109] In this example, a first region 67a having a lower impurity concentration than the second region 67b is interposed between the second region 67b and the p-type impurity region 66p, and a first region 67a is also interposed between the second region 67b and the p-type semiconductor layer 65p. By arranging the first region 67a having a relatively low impurity concentration around the second region 67b, the strength of the electric field formed by the p-n junction between the first diffusion region 67n and the p-type semiconductor layer 65p or the p-type impurity region 66p can be reduced. This reduction in the electric field strength suppresses leakage current caused by the electric field formed by the p-n junction.

[0110] FIG. 6 illustrates the concentration distribution of electrons and holes near the contact plug cp1 when the width of the pad cp1b of the imaging device 100 according to the present embodiment is varied. The concentration distribution shown in portion (a) of FIG. 6 illustrates the case where the contact plug cp1 does not have the pad cp1b, in other words, the case where the width W1 of the pad cp1b is equal to the width of the contact cp1a. In portion (a) of FIG. 6, the width of the contact cp1a is 90 nm. The concentration distributions shown in portions (b), (c), and (d) of FIG. 6 illustrate the cases where the distance between the pad cp1b and the surface of the semiconductor substrate 60 is 50 nm and the width W1 of the pad cp1b is 200 nm, 300 nm, and 400 nm, respectively. The concentration distribution shown in portion (e) of FIG. 6 illustrates the case where the width W1 of the pad cp1b is sufficiently larger than the width of the contact cp1a, specifically, the case where it can be considered infinite in simulation. 6 show the concentration distributions when the distance between the pad cp1b and the surface of the semiconductor substrate 60 is 10 nm and the width W1 of the pad cp1b is 200 nm, 300 nm, and 400 nm, respectively. In the example shown in FIG. 6, a voltage of 0.5 V is applied to each pad.

[0111] In each concentration distribution in Figure 6, regions containing many electrons are shaded with high density dots, and regions containing many holes are shaded with low density dots. The solid lines drawn in each region are isoconcentration lines of electrons or holes. Specifically, regions containing many electrons are those where the electron concentration is 1 x 10 14 / cm 3 Specifically, the region containing many holes is the region where the hole concentration is 1×10 14 / cm 3 It can be seen that the region containing a large number of electrons extends from the contact cp1a of the contact plug cp1 into the inside of the first diffusion region 67n.

[0112] The area between the region containing many electrons and the region containing many holes corresponds to the depletion layer. The width of the depletion layer on the surface of the semiconductor substrate 60 is indicated by a double-headed arrow, and the width of the depletion layer in each distribution diagram is shown numerically.

[0113] As shown in FIG. 6, it can be seen that the width of the depletion layer increases as the width of the pad cp1b increases, i.e., as the area of ​​the pad cp1b increases. In other words, the width of the depletion layer decreases as the width of the pad cp1b decreases, i.e., as the area of ​​the pad cp1b decreases. The same tendency is observed whether the distance between the pad cp1b and the surface of the semiconductor substrate 60 is 50 nm or 10 nm. Therefore, by reducing the area of ​​the contact plug cp1, the area of ​​the depletion layer on the surface of the semiconductor substrate 60 decreases.

[0114] The reason why the width of the depletion layer decreases as the area of ​​the pad cp1b decreases is presumed to be as follows: Of the charges generated in the photoelectric conversion unit 12, signal charges are accumulated in the first diffusion region 67n via the contact plug cp1. When the signal charges are, for example, holes, the contact plug cp1 becomes positively charged. In other words, the potential of the contact plug cp1 increases. At this time, a positive electric field is applied from the pad cp1b to the surface of the semiconductor substrate 60. Due to the influence of the positive electric field, holes, which are majority carriers in the semiconductor substrate 60, are pushed outward from the pad cp1b in a planar view. This increases the area of ​​the depletion layer on the surface of the semiconductor substrate 60.

[0115] 3, in this embodiment, distance L3 is longer than distance L1. Distance L1 is the distance between pad cp1b and gate electrode 26e. Distance L3 is the distance between pad cp3b and gate electrode 22e. For example, distance L1 is shorter than the distance between each of the pads of contact plug cp2, contact plug cp3, and contact plug cp4 included in pixel 10 and the gate electrode closest to each pad.

[0116] By shortening the distance between the contact plug cp1 connected to the first diffusion region 67n, which functions as a charge storage region, and the gate electrode 26e of the reset transistor 26, which includes the first diffusion region 67n as a drain or source, it is possible to prevent the depletion layer from spreading toward the gate electrode 26e.

[0117] In this way, a depletion layer region is formed between the first diffusion region 67n and the p-type impurity region 66p. Generally, the crystal defect density is higher near the surface of the semiconductor substrate 60 than inside the semiconductor substrate 60. Therefore, of the depletion layer regions formed at the pn junction, which is the portion where the first diffusion region 67n and the p-type impurity region 66p are joined, the depletion layer region formed at the junction near the surface of the semiconductor substrate 60 has a larger leakage current than the depletion layer region formed at the pn junction inside the semiconductor substrate 60.

[0118] Furthermore, if the area of ​​the depletion layer region (hereinafter referred to as the "interface depletion layer") formed at the junction on the surface of the semiconductor substrate 60 increases, the leakage current is likely to increase. In other words, the leakage current can be suppressed by reducing the area of ​​the interface depletion layer exposed on the surface of the semiconductor substrate 60. For example, the area of ​​the interface depletion layer may be minimized.

[0119] In this embodiment, as described above, the area of ​​the contact plug cp1 connected to the first diffusion region 67n is smaller than the area of ​​the contact plug cp3 connected to the second diffusion region 68bn in a plan view. This reduces the area of ​​the interface depletion layer that spreads near the first diffusion region 67n, as shown in FIG. 6. This therefore makes it possible to suppress leakage current from or to the first diffusion region 67n.

[0120] To reduce the area of ​​the interface depletion layer, the first diffusion region 67n may be formed to have a smaller area than the second diffusion region 68an when viewed perpendicular to the semiconductor substrate 60. For example, the area of ​​the first diffusion region 67n may be half or less of the area of ​​the second diffusion region 68an when viewed perpendicular to the semiconductor substrate 60. The width of the first diffusion region 67n in the channel width direction may be half or less of the width of the second diffusion region 68an when viewed perpendicular to the semiconductor substrate 60. The first diffusion region 67n and the second diffusion region 68an may have the same width in the channel width direction or the same length in the channel length direction. The area of ​​the first diffusion region 67n may be formed to be smaller than the areas of the second diffusion region 68bn, second diffusion region 68dn, and third diffusion region 68cn when viewed perpendicular to the semiconductor substrate 60.

[0121] Consider the case where an isolation region 69 is formed around the first diffusion region 67n and the p-type impurity region 66p after the formation of the gate and contact plug. The isolation region 69 is formed after the formation of the first diffusion region 67n and the contact plug cp1. The isolation region 69 is formed outside the contact plug cp1 relative to the first diffusion region 67n. Therefore, if the area of ​​the contact plug cp1 is large, the distance between the first diffusion region 67n and the p-type impurity region 66p and the isolation region 69 increases. This increases the depletion layer region and increases junction leakage. Furthermore, impurities of the opposite polarity to that of the contact plug cp1 may be introduced into the contact plug cp1 to form the isolation region 69. This can cause problems such as increased contact resistance. If the area of ​​the contact plug cp1 is large, the amount of impurities introduced also increases, which is likely to increase the degree of increase in contact resistance. On the other hand, reducing the area of ​​the contact plug cp1 can suppress increases in junction leakage and contact resistance.

[0122] The areas of the first diffusion region 67n and the second diffusion region 68an may be calculated excluding the areas of their portions overlapping with the gate electrode 26e of the reset transistor 26 when viewed perpendicular to the semiconductor substrate 60. Similarly, the areas of the second diffusion region 68bn and the second diffusion region 68dn, and the third diffusion region 68cn may be calculated excluding the areas of their portions overlapping with the gate electrode 22e of the amplifier transistor 22 and the gate electrode 24e of the address transistor 24 when viewed perpendicular to the semiconductor substrate 60. When viewed perpendicular to the semiconductor substrate 60, the portions overlapping with the gate electrode 22e, the gate electrode 24e, and the gate electrode 26e are less susceptible to damage during manufacturing than the portions not overlapping with the gate electrode 22e, the gate electrode 24e, and the gate electrode 26e. Examples of damage during manufacturing include damage caused by plasma processing used in the dry etching process and by ashing processing performed when removing the resist. For this reason, leakage current is unlikely to occur in the portions overlapping with the gate electrodes 22e, 24e, and 26e. Therefore, in reducing the area of ​​the interface depletion layer, it is sufficient to consider only the influence of the areas of the portions of the first diffusion region 67n, the second diffusion region 68bn, the second diffusion region 68dn, and the third diffusion region 68cn that are not overlapped with the gate electrodes 22e, 24e, and 26e.

[0123] Furthermore, by reducing the area of ​​the first diffusion region 67n, the distance between the contact hole h1 formed in the first diffusion region 67n and the gate electrode 26e becomes shorter than, for example, the distance between the contact hole h2 formed in the second diffusion region 68an and the gate electrode 26e. That is, as shown in FIG. 3, the distance L1 between the pad cp1b of the contact plug cp1 and the gate electrode 26e becomes shorter than the distance between the pad of the contact plug cp2 and the gate electrode 26e. As described above, the first diffusion region 67n has a lower impurity concentration and therefore a higher resistance value than the second diffusion region 68an. Therefore, by reducing the distance between the contact hole h1 and the gate electrode 26e, the current path in the first diffusion region 67n becomes shorter, thereby reducing the resistance value in the first diffusion region 67n.

[0124] The distance between contact hole h1 formed in first diffusion region 67n and gate electrode 26e may be shorter than the distance between contact hole h3 formed in second diffusion region 68bn and gate electrode 22e, or may be shorter than the distance between contact hole h4 formed in second diffusion region 68dn and gate electrode 24e. In other words, distance L1 may be shorter than distance L3 between pad cp3b of contact plug cp3 and gate electrode 22e. Alternatively, distance L1 may be shorter than the distance between the pad of contact plug cp4 and gate electrode 24e.

[0125] (Variation 1) Next, a first modification of the present embodiment will be described. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0126] 7 is a plan view showing the layout inside a pixel 10A of the imaging device according to this modification. The pixel 10A differs from the pixel 10 according to the first embodiment in the area of ​​the contact cp1Aa.

[0127] 7, the pixel 10A includes a contact plug cp1A instead of the contact plug cp1 compared to the pixel 10 according to the first embodiment. The contact plug cp1A includes a contact cp1Aa and a pad cp1b.

[0128] When viewed in a direction perpendicular to the semiconductor substrate 60, the area of ​​the contact cp1Aa is smaller than the area of ​​the contact cp3a. For example, the area of ​​the contact cp1Aa may be half or less of the area of ​​the contact cp3. Furthermore, the area of ​​the contact cp1Aa may be smaller than the area of ​​each of the contacts of the contact plugs cp2 and cp4. In other words, the area of ​​the contact cp1Aa may be the smallest area among the contacts of all the contact plugs included in the pixel 10A.

[0129] By making the contact cp1Aa smaller than the contacts of the other contact plugs cp2, cp3, and cp4, the concentration of impurities thermally diffused into the first diffusion region 67n via the contact cp1Aa can be reduced. This suppresses the spread of the region where the impurities contained in the contact plug cp1A diffuse within the first diffusion region 67n directly below the contact plug cp1A. Specifically, the high-concentration n-type impurity region is less likely to spread within the first diffusion region 67n. Therefore, even if the p-type isolation region 69 is positioned closer to the first diffusion region 67n, the electric field strength at the interface between the high-concentration n-type impurity region in the first diffusion region 67n and the p-type isolation region 69 can be suppressed to a certain level or less. Therefore, while suppressing the electric field strength at the interface between the high-concentration n-type impurity region in the first diffusion region 67n and the p-type isolation region 69 to a certain level or less, the distance between the high-concentration n-type impurity region and the p-type isolation region 69 can be kept to a certain level or less. This suppresses the spread of the interface depletion layer, thereby suppressing an increase in leakage current.

[0130] (Variation 2) Next, a second modification of the present embodiment will be described. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0131] 8 is a plan view showing the layout inside a pixel 10B of an imaging device according to this modification. The pixel 10B differs from the pixel 10 according to the first embodiment in the concentration of impurities in the contact plug cp1.

[0132] Specifically, as shown in FIG. 8, pixel 10B includes contact plug cp1B instead of contact plug cp1, as compared to pixel 10 according to embodiment 1. The impurity concentration in contact plug cp1B is lower than the impurity concentration in contact plug cp3. Furthermore, for example, the impurity concentration in contact plug cp1B may be lower than the impurity concentrations in contact plug cp2 and contact plug cp4. In other words, the impurity concentration in contact plug cp1B may be the minimum concentration among the impurity concentrations in all contact plugs included in pixel 10B.

[0133] In this way, by making the impurity concentration in the contact plug cp1 lower than the impurity concentrations in the other contact plugs cp2, cp3, and cp4, the concentration of impurities thermally diffused from the contact plug cp1 to the first diffusion region 67n can be reduced, thereby suppressing an increase in leakage current for the same reason as in Modification 1.

[0134] (Embodiment 2) Next, a description will be given of embodiment 2. The following description will focus on the differences from embodiment 1, and the description of commonalities will be omitted or simplified.

[0135] Fig. 9 is a plan view showing the internal layout of a pixel 10C of an imaging device according to the present embodiment. Fig. 10 is a schematic cross-sectional view showing the device structure of pixel 10C of an imaging device according to the present embodiment. Fig. 10 is a cross-sectional view of pixel 10C cut along line XX in Fig. 9 and expanded in the direction of the arrow. The main difference between pixel 10C shown in Fig. 10 and pixel 10 shown in Fig. 4 is that the gate electrode and the contact plug are formed in different wiring layers.

[0136] Specifically, as shown in Figures 9 and 10, pixel 10C differs from pixel 10 in embodiment 1 in that it additionally includes contact plug cp5, contact plug cp6, and contact plug cp7, as well as insulating layer 72.

[0137] The insulating layer 72 is provided on the insulating layer 71. In this embodiment, the contact holes h1-h7 are through holes that penetrate not only the insulating layer 71 but also the insulating layer 72. Contact plugs cp5, cp6, and cp7 are disposed at the positions of the contact holes h5, h6, and h7, respectively. The insulating layer 72 is, for example, a silicon oxide film. The insulating layer 72 may have a stacked structure including multiple insulating layers.

[0138] The contact plug cp5 connects the plug pa3 and the gate electrode 26e. As shown in Fig. 9, the contact plug cp5 is provided at a position overlapping the gate electrode 26e in plan view.

[0139] The contact plug cp6 connects the plug pa2 and the gate electrode 22e. As shown in Fig. 9, the contact plug cp6 is provided at a position overlapping the gate electrode 22e in plan view.

[0140] The contact plug cp7 connects the plug pa4 and the gate electrode 24e. As shown in Fig. 9, the contact plug cp7 is provided at a position overlapping the gate electrode 24e in plan view.

[0141] For example, in the first embodiment, the contact plugs cp1-cp4, the gate electrodes 22e, 24e, and 26e are formed in the same wiring layer and made of the same material containing the impurities, whereas in the present embodiment, the contact plugs cp1-cp7, the gate electrodes 22e, 24e, and 26e are formed in different wiring layers.

[0142] The material of the contact plugs cp1-cp7 may be the same as or different from the material of the gate electrodes 22e, 24e, and 26e. For example, when the contact plugs cp1-cp7 and the gate electrodes 22e, 24e, and 26e are made of polysilicon, the impurity concentrations in the polysilicon may be different.

[0143] In the present embodiment, similarly to the first embodiment, the area of ​​the contact plug cp1 is made smaller than those of the contact plugs cp2, cp3, and cp4 in plan view, thereby reducing the effect of the electric field caused by the contact plug cp1 and reducing the area of ​​the interface depletion layer of the semiconductor substrate 60. This makes it possible to reduce the leakage current from or to the first diffusion region 67n.

[0144] (Other embodiments) While the imaging device according to the present disclosure has been described above based on the embodiments and modifications, the present disclosure is not limited to these embodiments and modifications. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the embodiments and modifications, as well as other forms constructed by combining some of the components of the embodiments and modifications, are also included within the scope of the present disclosure.

[0145] For example, the photoelectric conversion unit 12 may be a photodiode formed in the semiconductor substrate 60. In other words, the imaging device 100 does not have to be a stacked type imaging device.

[0146] Furthermore, for example, the width W1 of the pad cp1b of the contact plug cp1 connected to the first diffusion region 67n and the width W3 of the pad cp3b of the contact plug cp3 connected to the second diffusion region 68bn may be equal. In this case, the length of the pad cp1b may be shorter than the length of the pad cp3b. Here, the length of the pad cp1b is the length of the pad cp1b in a direction parallel to the longitudinal direction of the gate electrode 26e. The length of the pad cp3b is the length of the pad cp3b in a direction parallel to the longitudinal direction of the gate electrode 22e. As a result, the area of ​​the pad cp1b may be smaller than the area of ​​the pad cp3b. Furthermore, both the width W1 and the length of the pad cp1b may be shorter than the width W3 and the length of the pad cp3b, respectively. A similar relationship may also be established between the pad cp1b and each of the contact plugs cp2 and cp4.

[0147] Furthermore, for example, the multiple pixels included in the imaging device 100 do not have to have the same configuration. For example, the imaging device 100 may include at least two of the pixel 10, the pixel 10A, the pixel 10B, and the pixel 10C.

[0148] Furthermore, according to the embodiments and modifications of the present disclosure, the effects of leakage current can be reduced, thereby providing an imaging device capable of capturing high-quality images. Each of the above-described amplifier transistor 22, address transistor 24, and reset transistor 26 may be an N-channel MOSFET or a P-channel MOSFET. When each transistor is a P-channel MOSFET, the first conductivity type impurity is a P-type impurity, and the second conductivity type impurity is an N-type impurity. It is not necessary for all of these transistors to be unified as either an N-channel MOSFET or a P-channel MOSFET. When each transistor in a pixel is an N-channel MOSFET and electrons are used as signal charge, the source and drain locations of each of these transistors can be interchanged.

[0149] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to each of the above-described embodiments within the scope of the claims or their equivalents. [Industrial Applicability]

[0150] According to the present disclosure, an imaging device capable of capturing high-quality images by suppressing the effects of dark current is provided. The imaging device of the present disclosure is useful, for example, in image sensors and digital cameras. The imaging device of the present disclosure can be used in medical cameras, robot cameras, security cameras, cameras mounted on vehicles, and the like. [Explanation of symbols]

[0151] 10, 10A, 10B, 10C pixels 12 Photoelectric conversion unit 12a Pixel electrode 12b Photoelectric conversion layer 12c transparent electrode 14 Signal detection circuit 16 Feedback Circuit 22 Amplifying transistor 22e, 24e, 26e Gate electrodes 24 address transistor 26 Reset transistor 32 Power wiring 34 Address signal line 35 Vertical signal line 36 Reset signal line 39 Storage control line 40 Peripheral Circuits 42 Load circuit 44 Column signal processing circuit 46 Vertical scanning circuit 48 Horizontal signal readout circuit 49 Horizontal common signal line 50 Inverting amplifier 53 Feedback Line 60 Semiconductor substrate 61 Support substrate 61p, 63p, 65p p-type semiconductor layer 62n n-type semiconductor layer 64 p-type region 66p p-type impurity region 67a 1st area 67b 2nd area 67n First diffusion region 68an, 68bn, 68dn Second diffusion region 68cm Third diffusion region 69 Element isolation region 70, 71, 72, 90a, 90b, 90c, 90d Insulation layers 73, 74 Sidewall 80 Wiring structure 80a, 80b, 80c, 80d wiring layer 90 Interlayer insulation layer 100 Imaging device R1 imaging area R2 surrounding area cp1, cp1A, cp1B, cp2, cp3, cp4, cp5, cp6, cp7, cp8 contact plugs cp1a, cp1Aa, cp3a Contact cp1b, cp3b pads h1, h2, h3, h4, h5, h6, h7, h8, h9, h10, h11 contact holes pa1, pa2, pa3, pa4, pa5, pa6, pa7, pb, pc, pd plug

Claims

1. a photoelectric conversion unit that converts light into a signal charge; a first diffusion region of a first conductivity type to which the signal charge is input; a second diffusion region of the first conductivity type; a first plug having a first surface in contact with the first diffusion region; a second plug having a second surface in contact with the second diffusion region; a first transistor including the first diffusion region as one of a source and a drain and including a first gate; a second transistor including the second diffusion region as one of a source and a drain and including a second gate; Equipped with In a plan view, a distance between the first surface of the first plug and the first gate is smaller than a distance between the second surface of the second plug and the second gate. Imaging device.

2. a photoelectric conversion unit that converts light into a signal charge; a first diffusion region of a first conductivity type to which the signal charge is input; a second diffusion region of the first conductivity type; a first plug including a first contact in contact with the first diffusion region; a second plug including a second contact in contact with the second diffusion region; a first transistor including the first diffusion region as one of a source and a drain and including a first gate; a second transistor including the second diffusion region as one of a source and a drain and including a second gate; Equipped with In a plan view, a distance between the first contact and the first gate is smaller than a distance between the second contact and the second gate. Imaging device.

3. the first plug includes a first pad located on the first contact; the second plug includes a second pad located on the second contact; In a plan view, an area of ​​the first pad is larger than an area of ​​the first contact; In a plan view, the area of ​​the second pad is larger than the area of ​​the second contact. The imaging device according to claim 2 .

4. a photoelectric conversion unit that converts light into a signal charge; a first diffusion region of a first conductivity type to which the signal charge is input; a second diffusion region of the first conductivity type; a first plug having a first surface in contact with the first diffusion region; a second plug having a second surface in contact with the second diffusion region; a first transistor including the first diffusion region as one of a source and a drain and including a first gate; a second transistor including the second diffusion region as one of a source and a drain and including a second gate; Equipped with a dimension of the first surface in a length direction of the first gate of the first transistor is smaller than a dimension of the second surface in a length direction of the second gate of the second transistor; Imaging device.

5. a photoelectric conversion unit that converts light into a signal charge; a first diffusion region of a first conductivity type to which the signal charge is input; a second diffusion region of the first conductivity type; a first plug including a first contact in contact with the first diffusion region; a second plug including a second contact in contact with the second diffusion region; a first transistor including the first diffusion region as one of a source and a drain and including a first gate; a second transistor including the second diffusion region as one of a source and a drain and including a second gate; Equipped with a dimension of the first contact in a length direction of the first gate of the first transistor is smaller than a dimension of the second contact in a length direction of the second gate of the second transistor; Imaging device.

6. the first plug includes a first pad located on the first contact; the second plug includes a second pad located on the second contact; In a plan view, an area of ​​the first pad is larger than an area of ​​the first contact; In a plan view, the area of ​​the second pad is larger than the area of ​​the second contact. The imaging device according to claim 5 .

7. the second gate is electrically connected to the first diffusion region; The imaging device according to claim 1 .

8. the first plug and the second plug contain impurities of the first conductivity type; a concentration of the impurity of the first conductivity type in the first plug is lower than a concentration of the impurity of the first conductivity type in the second plug; The imaging device according to claim 1 .

9. A plurality of pixels are provided, the photoelectric conversion unit, the first diffusion region, the second diffusion region, the first plug, and the second plug are included in one pixel of the plurality of pixels; The imaging device according to claim 1 .

10. An imaging device comprising: an imaging device according to any one of claims 1 to 9; camera.

Images