Power Conversion Device

Abstract

To provide a power converter that can sample a current easily at timings when there are fewer current ripples.SOLUTION: The power converter includes: a dielectric load; a switching element; and a controller for sampling a current flowing in the dielectric load and controlling the switching element. The controller determines the difference between the timing of sampling and the timing of a pulse, determines the inclination of a current from the inductance value of the dielectric load and an output voltage, determines a current correction amount from the difference and the inclination of the current, and performs control on the basis of the value of the current acquired by sampling and the current correction amount.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power conversion device. [Background technology]

[0002] As background art in this technical field, Patent Document 1 states that "a carrier wave source is provided for each phase, and a phase difference is given to the carrier waves of each phase" (see paragraph 0009). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-248419 Summary of the Invention [Problem to be solved by the invention]

[0004] The technology disclosed in Patent Document 1 is effective in reducing the zero-phase current, but care must be taken in controlling it. That is, the peak of the current ripple must be sampled during sampling.

[0005] Therefore, if we try to match the sampling timing to the peaks and valleys of a triangular wave carrier with little current ripple, the design of the sampling timing and the design of the control task processing become complicated.In particular, the dead time of the sampling timing relative to the control period differs depending on the phase, which reduces responsiveness and stability when designing a control system.

[0006] The object of the present invention is to In a power conversion device that uses interleaved PWM control, the effects of ripple current are suppressed and the control of the power conversion device is realized. The reason is that. [Means for solving the problem]

[0007] One example of the present invention is a power conversion device having an inductive load, a switching element, and a control unit that samples a current flowing through the inductive load and controls the switching element, wherein the control unit calculates a difference between the timing of the sampling and a pulse, The gradient of the current is calculated from the inductance value of the inductive load and the output voltage. The power conversion device calculates a current correction amount from the difference and the gradient of the current, and performs control based on the current value acquired by sampling and the current correction amount. [Effects of the Invention]

[0008] According to the present invention, A power conversion device that uses interleaved PWM control to suppress the effects of ripple current. Provide do. [Brief explanation of the drawings]

[0009] [Figure 1] 1 shows the overall configuration of a UPS and an inverter circuit according to a first embodiment. [Figure 2] FIG. 1 is a diagram illustrating a comparison between synchronous carrier PWM and interleaved PWM. [Figure 3] This is a comparison of the sampling timing, PWM waveform, and current waveform for synchronous carrier PWM and interleaved PWM. [Figure 4] FIG. 3 is a conceptual diagram of current correction in the first embodiment. [Figure 5] 10 is a diagram (part 1) for explaining in detail current correction in the first embodiment. FIG. [Figure 6] FIG. 10 is a diagram (part 2) for explaining in detail the current correction in the first embodiment. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0010] 1 is a configuration diagram of an uninterruptible power supply (hereinafter referred to as UPS), in which an inverter circuit and its control unit as a first embodiment are shown enlarged at the bottom of FIG.

[0011] A UPS is a power supply device that protects data in large-scale data centers by continuing to supply power to servers 4 even during power outages.

[0012] As shown in Figure 1, the UPS operates by first converting three-phase AC power supplied from the grid into DC power using a converter circuit 1, then converting this DC power back into three-phase AC power using an inverter circuit 2, and supplying the power to a server 4 as a load.

[0013] In the converter circuit 1, which converts power from AC to DC, and the inverter circuit 2, which converts power from DC to AC, AC-DC power conversion is achieved by changing the output voltage and current over time through high-frequency (several kHz) switching by power semiconductor devices.

[0014] In Figure 1, the flow of power 10 during normal operation is from the grid to the converter circuit 1, inverter circuit 2, and server 4. During a power outage, the flow of power 11 is from the storage battery 5 to the chopper 6, inverter circuit 2, and server 4. The diagram shows a case where a filter capacitor is connected in a Y connection to the output side of the filter reactor 7 of the inverter circuit 2. Depending on the circuit configuration, the filter capacitor may also be connected in a Delta connection.

[0015] The current detector 8 detects the current flowing through the filter reactor 7, which serves as an inductive load. In FIG. 1, the current detector 8 detects the current in the three phases U, V, and W. The voltage detector 9 detects the instantaneous output voltage of the inverter circuit 2. In FIG. 1, the voltage detector 9 detects the voltage in the three phases U, V, and W.

[0016] The control unit 3 detects the current detected by the current detector 8, the output voltage detected by the voltage detector 9, and the voltage V dcThe control unit 3 receives data from various sensors, such as the above. Based on the received data, the control unit 3 supplies signals to the inverter circuit 2 that control the switching elements S1, S2, S3, S4, S5, S6, S7, S8, and S9 of the inverter circuit, thereby controlling the output voltage and current of the inverter circuit 2. Power semiconductor devices are used as the switching elements. While Figure 1 shows an example in which there are nine switching elements, existing technology may be used to reduce the number of switching elements to six, for example.

[0017] The control unit 3 has hardware such as a processor and a recording device, and a program recorded in the recording device, and can be configured so that the processor reads the program and executes the predetermined program. The control unit 3 is configured, for example, by a microcomputer.

[0018] The switching operation of this power semiconductor device superimposes a pulsating zero-phase component on the output voltage and current. This zero-phase component not only increases the loss of the UPS, but also has an adverse effect on connected equipment if the power with the superimposed zero-phase component is directly sent to the grid or server 4, so the UPS has a built-in filter reactor to suppress the zero-phase component.

[0019] This filter reactor was able to reduce the distortion rate to 2.5% or less by smoothing out the voltage distortion in the output. However, the volume of a conventional filter reactor was approximately 20% of the volume of the UPS panel, so it was necessary to downsize this filter reactor to realize a space-saving UPS.

[0020] To achieve a smaller filter reactor, it is necessary to reduce the zero-phase current, which causes temperature rise.The zero-phase current is generated by the superposition of voltage and current between different phases, which occurs in conventional switching control.

[0021] In the inverter circuit 2 shown in FIG. 1, three-phase AC voltage is generated from DC by switching switches S1 to S9 connected to three phases, namely, U, V, and W. In the conventional switching control method, for the convenience of designing the control software, the pulses of each phase are set with a period T S This controls the generation of synchronization.

[0022] Figure 2 shows a comparison between synchronous carrier PWM and interleaved PWM. When using conventional synchronous carrier PWM (shown on the left side of Figure 2), the U-phase PWM voltage pulse, the V-phase PWM voltage pulse, and the W-phase PWM voltage pulse are added together to form a zero-phase voltage with a period T S As a result, a zero-phase current I0 is generated whose magnitude is proportional to the size of the area of ​​the shaded portion of the zero-phase voltage.

[0023] This zero-phase current I0 is smoothed by flowing through a filter reactor, but because losses occur in the resistance component of the reactor (copper loss) and in the magnetic circuit (iron loss), a large reactor with sufficient volume for heat dissipation is required, which also poses the problem of reduced efficiency.

[0024] To reduce this zero-phase current, we adopted the interleaved PWM described in Patent Document 1, which uses the basic principle of three-phase AC. Interleaved PWM is a technology that shifts the PWM carrier for each phase. In three-phase AC, the voltages (or currents) of the U, V, and W phases are shifted in phase by 120 degrees, so when the voltages and currents of each phase are added together, they cancel each other out and become zero. Therefore, in this embodiment, we apply this principle to the control of the inverter circuit and shift the switching voltage to reduce the zero-phase voltage generated and combined in the U, V, and W phases.

[0025] Interleaved PWM, which is characterized by shifting the pulse voltage, is shown on the right side of Figure 2. With this interleaved PWM control, the pulse cycle of each of the U, V, and W phases is shifted by one-third relative to each other when switching, so that when the pulse voltages of each phase are added together, they cancel each other out, just as in the case of three-phase AC, reducing the amplitude of the combined ripple voltage and making it possible to reduce the area of ​​the shaded area.

[0026] Analysis of the zero-phase current reduction effect showed that the current amplitude can be reduced by approximately half compared to synchronous carrier PWM control. This reduction effect makes it possible to keep the ripple level to a level that satisfies the required power quality even if the inductance value of the filter reactor is reduced, making it possible to achieve both ripple reduction and a more compact filter reactor. Furthermore, reducing the zero-phase current also contributes to improving the conversion efficiency of the entire UPS.

[0027] In the case of general synchronous carrier PWM, the triangular wave carrier cycle and control cycle for all three phases are synchronized, so it is easy to design a timer counter so that sampling occurs at the peaks and valleys of the triangular wave carrier, which minimizes current ripple caused by PWM, simply by sampling all phases simultaneously at regular time intervals.

[0028] On the other hand, in interleaved PWM, sampling all phases simultaneously at fixed time intervals creates the problem of sampling the peaks of the current ripple during sampling. Therefore, in interleaved PWM, the sampling timing must either be changed for each phase, or correction must be made after sampling.

[0029] If you try to match the sampling timing to the peaks and valleys of a triangular wave carrier with little current ripple, you need to set the sampling timing for each of the three phases, which complicates the design of the sampling timing and the design of the control task processing.In particular, because the dead time of the sampling timing relative to the control period differs depending on the phase, responsiveness and stability are lower than with synchronous carrier PWM when designing the control system.

[0030] In this embodiment, the sampling timing is determined based on the control period, and a method is adopted in which the current value at the peaks and valleys of the triangular wave carrier is estimated by simple calculation. In addition, by setting the estimated peak and valley timing forward (in the immediate future), dead time is reduced.

[0031] Figure 3 shows a comparison of the sampling timing and PWM voltage and current waveforms for synchronous carrier PWM and interleaved PWM.

[0032] The left side of Figure 3 shows the voltage pulse waveform V of the U phase in synchronous carrier PWM. U , V-phase voltage pulse waveform V V , W-phase voltage pulse waveform V W The right side of Figure 3 shows the sampling timing of the U-phase voltage pulse waveform V U , V-phase voltage pulse waveform V V , W-phase voltage pulse waveform V W The arrows in the interleaved PWM indicate the peaks of the current ripples.

[0033] Synchronous carrier PWM allows easy sampling at timings where the current ripple is small. Interleaved PWM shows that sampling can sometimes be performed at timings where the current ripple is large.

[0034] FIG. 4 shows the concept of current correction for interleaved PWM in this embodiment. In this figure, the W-phase voltage V W , W-phase current I W This is an example using the waveform.

[0035] In the next steps (1), (2), and (3), the control unit 3 calculates the correction amount ΔI. (1) The time difference Δt from the sampling timing to the center of the pulse is calculated. (2) Calculate the current gradient from the reactor inductance value and output voltage. (3) The correction amount ΔI is obtained from the time difference Δt in (1) and the current gradient in (2).

[0036] These steps allow the amount of ripple to be corrected for the current values ​​sampled by interleaved PWM. Then, the control unit 3 can control PWM with reduced influence of ripple current based on the sampled current values ​​and the corrected current.

[0037] 5 and 6 show the relationship between the upper carrier or the lower carrier and the signal voltage V * FIG. 10 is a diagram showing how a PWM signal is generated from

[0038] 5 is a diagram (part 1) for explaining in detail the current correction in the embodiment 1. In FIG. 5, the cases of sampling timing A, sampling timing B, sampling timing C, and sampling timing D are shown.

[0039] The sampling timing A is before the timing of the valley of the upper carrier, and τ is (T S / 2)·D P A longer case is shown.

[0040] The sampling timing B is before the timing of the valley of the upper carrier, and τ is (T S / 2)·D P A shorter case is shown.

[0041] The sampling timing C is before the timing of the upper carrier peak, and τ is (T S / 2)·D P A longer case is shown.

[0042] The sampling timing D is before the timing of the upper carrier peak, and τ is (T S / 2)·D P A shorter case is shown.

[0043] In this embodiment, the corrected current (the sum of I and ΔI) is calculated by adding the correction current to the current at sampling timing A and sampling timing B. Therefore, even at sampling timing A and sampling timing B, the current value at the timing when the sampling timing is the valley of the upper carrier can be estimated.

[0044] Furthermore, the corrected current (the sum of I and ΔI) is calculated by adding the correction current to the current at sampling timing C and sampling timing D. Therefore, even at sampling timing C and sampling timing D, the current value at the timing when the sampling timing corresponds to the peak of the upper carrier can be estimated.

[0045] 6 is a diagram (part 2) for explaining in detail the current correction in the embodiment 1. In FIG. 6, the cases of sampling timing E, sampling timing F, sampling timing G, and sampling timing H are shown.

[0046] The sampling timing E is before the timing of the valley of the lower carrier, and τ is (T S / 2)·D N A longer case is shown.

[0047] The sampling timing F is before the timing of the valley of the lower carrier, and τ is (T S / 2)·D N A shorter case is shown.

[0048] The sampling timing G is before the timing of the lower carrier peak, and τ is (T S / 2)·D N A longer case is shown.

[0049] The sampling timing H is before the timing of the lower carrier peak, and τ is (T S / 2)·D N A shorter case is shown.

[0050] In this embodiment, a corrected current (the sum of I and ΔI) is calculated by adding a correction current to the current at sampling timing E and sampling timing F. Therefore, even at sampling timing E and sampling timing F, the current value at the timing when the sampling timing is a valley of the lower carrier can be estimated.

[0051] Furthermore, the corrected current (the sum of I and ΔI) is calculated by adding the correction current to the current at sampling timing G and sampling timing H. Therefore, even at sampling timing G and sampling timing H, the current value at the timing when the sampling timing corresponds to the peak of the lower carrier can be estimated.

[0052] In Figures 5 and 6, the sampling timing is set to a duty ratio D P , duty ratio D N The cases were classified into eight types, from Case A to Case H, according to their relative relationship with the

[0053] Here, the duty ratio D P is V * The first duty cycle is generated by comparing with the upper triangular wave carrier when V > 0. * is the signal wave voltage.

[0054] Duty ratio D N is V * <0 is the second duty cycle generated in comparison with the lower triangular carrier.

[0055] Cases A to D in Figure 5 are V * >0, i.e., duty ratio D P Cases E to H in FIG. * <0, i.e., duty ratio D N FIG.

[0056] The current value Δi for correcting the current detection value at each sampling timing in each of cases A to H is expressed by equations (1) to (8).

[0057] In Cases A, B, C, D, E, F, and G, H, the estimated timing is set ahead of (in the immediate future) the timing of the peaks and valleys of the upper or lower carrier, thereby minimizing wasted time.

[0058] In case A, the correction current value Δi is calculated by the formula (1).

[0059]

number

[0060] where Δi is the correction current, Vo is the instantaneous output voltage of each phase, and V DC is the capacitor voltage of the inverter circuit, τ is the time from the sampling timing to the nearest future carrier peak or trough, L is the reactor inductance, Ts is the PWM period, D P is the first duty ratio, and Dτ is the value of τ expressed as a duty ratio (τ / (Ts / 2)).

[0061] In case B, the correction current value Δi is calculated by equation (2).

[0062]

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[0063] In case C, the correction current value Δi is calculated by equation (3).

[0064]

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[0065] In case D, the correction current value Δi is calculated by equation (4).

[0066]

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[0067] In case E, the correction current value Δi is calculated by equation (5).

[0068]

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[0069] In case F, the correction current value Δi is calculated by equation (6).

[0070]

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[0071] In case G, the correction current value Δi is calculated by equation (7).

[0072]

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[0073] In case H, the correction current value Δi is calculated by equation (8).

[0074]

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[0075] In this embodiment, the ripple component is corrected after sampling. In this embodiment, the dead time of the control system is the same for each phase, so the timing design, stability, and responsiveness of the control system can be ensured.

[0076] Although the above embodiment has been described using interleaved PWM control as an example, the embodiment can also be applied to synchronous carrier PWM control, which has the effect of enabling sampling at the timing of the peaks and valleys of a triangular wave carrier with little current pulsation.

[0077] The present invention is not limited to the above-described embodiments and various modifications are possible. The above-described embodiments are provided as examples to facilitate understanding of the present invention and are not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. It is also possible to delete part of the configuration of each embodiment, or to add or replace other configurations. Furthermore, the control lines and information lines shown in the figures are those considered necessary for explanation, and do not necessarily represent all control lines and information lines necessary for the product. In reality, it is safe to assume that almost all configurations are interconnected. [Explanation of symbols]

[0078] 1 Converter circuit 2. Inverter circuit 3. Control Unit 4 Server 5. Storage battery 6 Chopper 7 Filter reactor 8 Current Detector 9 Voltage detector 10 Normal current flow 11 Current flow during a power outage

Claims

1. A filter reactor; A switching element; A power conversion device having a control unit that controls the switching elements and performs control by interleaved PWM, The control unit sampling a current value of a current flowing through the filter reactor at a sampling timing determined based on a control period; A time difference between the sampling timing and the pulse center of the output voltage is calculated. An inductance value of the filter reactor and a current gradient of a current flowing from an output voltage to the filter reactor are obtained; obtaining a current correction amount from the time difference and the current gradient; The power conversion device estimates a current value that is less affected by ripple current using the sum of the sampled current value and the current correction amount, and performs the interleaved PWM control.

2. The power conversion device according to claim 1, A power conversion device in which a capacitive filter capacitor is connected to the filter reactor.

3. The power conversion device according to claim 2, The power conversion device, wherein the filter capacitors are connected in a Y-connection.

4. The power conversion device according to claim 2, The power conversion device, wherein the filter capacitor is connected in a delta connection.

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