Power semiconductor element and its manufacturing method

Abstract

To provide a power semiconductor device of silicon carbide, achieving an improvement in channel density, and a method of fabricating the same.SOLUTION: A power semiconductor device 100-1 includes: a semiconductor layer 105 of silicon carbide; a gate insulating layer 118 and a gate electrode layer 120 in the semiconductor layer; a drift region 107 having a first conductivity type; a well region 110 including a first well region 110a in contact with a protruding portion 107a in the drift region and a second well region 110b formed in the semiconductor layer outside the gate electrode layer and connected to the first well region, the well region having a second conductivity type; a source region 112 including a first source region 112a formed in the first well region and a second source region 112b formed in the second well region 110b and connected to the first source region, the source region having the first conductivity type; and a channel region 110c which is arranged under the gate electrode layer, which is formed in the semiconductor layer between the protruding portion in the drift region and the first source region, and in which an inversion channel is formed, the channel region having the first conductivity type.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to power semiconductor devices for switching power transfer and methods for manufacturing the same. [Background technology]

[0002] Power semiconductor devices are semiconductor devices that operate in high-voltage and high-current environments. Such power semiconductor devices are used in fields requiring high-power switching, such as power conversion, power converters, and inverters. Examples of power semiconductor devices include insulated gate bipolar transistors (IGBTs) and power mosfets (metal oxide semiconductor field effect transistors). Such power semiconductor devices are fundamentally required to withstand high voltages, and recently have also been required to perform high-speed switching operations.

[0003] For this reason, research is being conducted into power semiconductor elements that use silicon carbide (SiC) instead of the existing silicon (Si). Silicon carbide (SiC) is a wide-gap semiconductor material with a higher band gap than silicon, and is able to maintain stability at higher temperatures than silicon. Furthermore, silicon carbide has a much higher breakdown field than silicon, allowing it to operate stably even at high voltages. Therefore, silicon carbide has a higher breakdown voltage than silicon, yet is excellent at dissipating heat, demonstrating the ability to operate at high temperatures.

[0004] In the case of power semiconductor devices using such silicon carbide, negative charges caused by the formation of carbon clusters in the gate insulating layer increase the band gap of the silicon carbide surface, resulting in higher threshold voltages and higher channel resistance. Furthermore, because a source contact structure is placed between the gate electrodes and it is difficult to reduce the spacing between the gate electrodes, there is a limit to how much the channel density can be reduced. Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made to solve the above-mentioned problems, and aims to provide a silicon carbide power semiconductor device capable of increasing channel density and a method for manufacturing the same, however, these problems are merely examples and are not intended to limit the scope of the present invention. [Means for solving the problem]

[0006] a first well region formed in the semiconductor layer below the gate electrode layer and in contact with the at least one protruding portion of the drift region, and a second well region formed in the semiconductor layer outside the gate electrode layer and coupled to the first well region, the well region having the second conductivity type; a first source region formed in the first well region and a second source region formed in the second well region and coupled to the first source region; and a channel region having the first conductivity type disposed below the gate electrode layer and formed in the semiconductor layer between the at least one protruding portion of the drift region and the first source region, the channel region having the first conductivity type and disposed below the gate electrode layer and formed in the semiconductor layer between the at least one protruding portion of the drift region and the first source region, the channel region having the first conductivity type.

[0007] The power semiconductor device may further include a source electrode layer connected to the second source region outside the gate electrode layer. The power semiconductor device may include a well contact region having a second conductivity type within the second source region, extending from the second well region through the second source region and connected to the source electrode layer, the well contact region being doped at a higher concentration than the well region.

[0008] According to the power semiconductor device, the at least one protruding portion of the drift region, the first well region, and the first source region can extend in one direction.

[0009] In the power semiconductor device, the first well region, the first source region, and the channel region may be formed in the semiconductor layer on both sides of the at least one protruding portion of the drift region, and the channel region may be a part of the well region.

[0010] In the power semiconductor device, the at least one protruding portion may include a plurality of protruding portions whose sidewalls are surrounded by the first well region, and the channel region may be formed between the plurality of protruding portions and the first source region. In the power semiconductor device, the plurality of protruding portions may extend side by side in one direction.

[0011] According to the power semiconductor device, the first well region may be formed symmetrically with respect to the second well region, the first source region may be formed symmetrically with respect to the second source region, and the channel region may be formed symmetrically with respect to the second well region or the second source region.

[0012] According to the power semiconductor device, the at least one protruding portion may include a plurality of protruding portions arranged symmetrically with respect to the second well region or the second source region, and the plurality of protruding portions may extend in one direction.

[0013] According to the power semiconductor device, the gate electrode layer may be formed to expose the second source region and to cover the first source region, the channel region, and the at least one protruding portion of the drift region.

[0014] The power semiconductor device may further include a drain region having a first conductivity type in the semiconductor layer below the drift region, the drain region being doped at a higher concentration than the drift region.

[0015] According to another aspect of the present invention, there is provided a method for manufacturing a power semiconductor device, the method comprising: forming a drift region having a first conductivity type in a semiconductor layer of silicon carbide (SiC); forming a well region having a second conductivity type in the semiconductor layer, the well region including a first well region defining the at least one protruding portion and a second well region connected to the first well region, such that the drift region includes at least one protruding portion; forming a source region having the first conductivity type, the source region including a first source region formed in the first well region and a second source region formed in the second well region and connected to the first source region; forming a channel region having the first conductivity type in the semiconductor layer between the at least one protruding portion of the drift region and the first source region, wherein an inversion channel is formed; forming a gate insulating layer at least on the channel region and the at least one protruding portion of the drift region; and forming at least one gate electrode layer on the gate insulating layer, the second well region being formed in the semiconductor layer outside the gate electrode layer.

[0016] The method for manufacturing the power semiconductor device may further include forming a well contact region having a second conductivity type in the second source region outside the gate electrode layer, extending from the second well region through the second source region and connected to the source electrode layer, wherein the well contact region may be doped at a higher concentration than the well region.

[0017] The method for manufacturing the power semiconductor device may further include forming a source electrode layer on the semiconductor layer to be connected to the second source region and the well contact region.

[0018] According to the manufacturing method of the power semiconductor element, the step of forming the well region and the channel region is performed by injecting impurities of a second conductivity type into the semiconductor layer, and the step of forming the source region is performed by injecting impurities of a first conductivity type into the well region.

[0019] According to the manufacturing method of the power semiconductor element, the at least one protruding portion includes a plurality of protruding portions whose sidewalls are surrounded by the first well region, and the channel region can be formed between the plurality of protruding portions and the source region.

[0020] According to the method for manufacturing the power semiconductor device, the first well region may be formed symmetrically with respect to the second well region, the first source region may be formed symmetrically with respect to the second source region, and the channel region may be formed symmetrically with respect to the second well region or the second source region.

[0021] According to the method for manufacturing the power semiconductor device, the drift region may be formed on a drain region having a first conductivity type, and the drift region may be formed on the drain region using an epitaxial layer. [Effects of the Invention]

[0022] According to the power semiconductor device and the manufacturing method thereof according to an embodiment of the present invention, it is possible to increase the channel density and the degree of integration. Of course, these effects are merely examples, and the scope of the present invention is not limited to these effects. [Brief explanation of the drawings]

[0023] [Figure 1] 1 is a schematic perspective view showing a power semiconductor element according to an embodiment of the present invention; [Figure 2] 2 is a plan view showing the power semiconductor element taken along line II-II in FIG. 1. [Figure 3] 3 is a cross-sectional view showing the power semiconductor element taken along line III-III in FIG. 2. [Figure 4] 4 is a cross-sectional view showing the power semiconductor element taken along line IV-IV in FIG. 2. [Figure 5] 3 is a cross-sectional view showing the power semiconductor element taken along line VV in FIG. 2. [Figure 6] 6 is a cross-sectional view showing the power semiconductor element taken along line VI-VI in FIG. 2. [Figure 7] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 8] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 9] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 10] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 11] 1 is a schematic perspective view showing a power semiconductor element according to an embodiment of the present invention; [Figure 12] 12 is a plan view showing the power semiconductor element taken along line II-II in FIG. 11. [Figure 13] 13 is a cross-sectional view showing the power semiconductor element taken along line III-III in FIG. 12. [Figure 14] 13 is a cross-sectional view showing the power semiconductor element taken along line IV-IV in FIG. 12. [Figure 15] 13 is a cross-sectional view showing the power semiconductor element taken along line VV in FIG. 12. [Figure 16] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 17] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 18] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 19] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 20] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 21] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 22] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 23] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 24] 10 is a graph showing an electric field depending on a junction structure in a power semiconductor element according to an embodiment of the present invention. [Figure 25] 1 is a schematic perspective view showing a power semiconductor element according to an embodiment of the present invention; [Figure 26] 26 is a plan view showing the power semiconductor element taken along line II-II in FIG. 25. FIG. [Figure 27] 27 is a cross-sectional view showing the power semiconductor element taken along line III-III in FIG. 26. [Figure 28] 27 is a cross-sectional view showing the power semiconductor element taken along line IV-IV in FIG. 26. [Figure 29] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 30] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 31] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 32] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 33] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 34] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 35] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 36] 10 is a graph showing a change in electric field depending on the depth of a power semiconductor element according to an embodiment of the present invention. [Figure 37] 1 is a schematic perspective view showing a power semiconductor element according to an embodiment of the present invention; [Figure 38] 38 is a plan view showing the power semiconductor element taken along line II-II in FIG. 37. [Figure 39] 39 is a cross-sectional view showing the power semiconductor element taken along line III-III in FIG. 38. [Figure 40] 40 is a cross-sectional view showing the power semiconductor element taken along line IV-IV in FIG. 38. [Figure 41] 39 is a cross-sectional view showing the power semiconductor element taken along line VV in FIG. 38. [Figure 42] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 43] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 44] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 45] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 46]1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 47] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 48] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 49] 1 is a schematic perspective view showing a power semiconductor element according to an embodiment of the present invention; [Figure 50] 50 is a plan view showing the power semiconductor element taken along line II-II in FIG. 49. [Figure 51] 51 is a cross-sectional view showing the power semiconductor element taken along line III-III in FIG. 50. [Figure 52] 51 is a cross-sectional view showing the power semiconductor element taken along line IV-IV in FIG. 50. [Figure 53] 51 is a cross-sectional view showing the power semiconductor element taken along line VV in FIG. 50. [Figure 54] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 55] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 56] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 57] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 58] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 59] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 60] 1 is a schematic perspective view showing a power semiconductor element according to an embodiment of the present invention; [Figure 61] 61 is a plan view showing the power semiconductor element taken along line II-II in FIG. 60. [Figure 62]62 is a cross-sectional view showing the power semiconductor element taken along line III-III in FIG. 61. [Figure 63] 62 is a cross-sectional view showing the power semiconductor element taken along line IV-IV in FIG. 61. [Figure 64] 62 is a cross-sectional view showing the power semiconductor element taken along line VV in FIG. 61. [Figure 65] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 66] FIG. 10 is a cross-sectional view showing a power semiconductor element according to another embodiment of the present invention. [Figure 67] FIG. 10 is a cross-sectional view showing a power semiconductor device according to still another embodiment of the present invention. [Figure 68] FIG. 10 is a cross-sectional view showing a power semiconductor device according to still another embodiment of the present invention. [Figure 69] FIG. 10 is a cross-sectional view showing a power semiconductor device according to still another embodiment of the present invention. [Figure 70] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 71] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 72] 1 is a schematic perspective view showing a method for manufacturing a power semiconductor device according to an embodiment of the present invention. [Figure 73] 10 is a graph showing characteristics of a diode of a power semiconductor element according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be realized in various different forms. The following embodiments are provided to complete the disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art. Also, for the convenience of explanation, the size of at least some components may be exaggerated or reduced in the drawings. In the drawings, the same reference numerals refer to the same elements.

[0025] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for illustrative purposes and are therefore provided to illustrate the general structure of the present invention.

[0026] Like reference numerals refer to like elements. When one feature, such as a layer, region, or substrate, is referred to as being on another feature, it is understood to be directly on top of the other feature, or that there may be other intervening features therebetween. Conversely, when one feature is referred to as being "directly on" another feature, it is understood that there are no intervening features therebetween.

[0027] FIG. 1 is a schematic perspective view showing a power semiconductor element 100-1 according to one embodiment of the present invention, FIG. 2 is a plan view showing the power semiconductor element 100-1 cut along line II-II in FIG. 1, FIG. 3 is a cross-sectional view showing the power semiconductor element 100-1 cut along line III-III in FIG. 2, FIG. 4 is a cross-sectional view showing the power semiconductor element 100-1 cut along line IV-IV in FIG. 2, FIG. 5 is a cross-sectional view showing the power semiconductor element 100-1 cut along line VV in FIG. 2, and FIG. 6 is a cross-sectional view showing the power semiconductor element 100-1 cut along line VI-VI in FIG. 2.

[0028] 1 to 6, the power semiconductor device 100-1 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-1 may have a power MOSFET structure.

[0029] The semiconductor layer 105 can refer to one or more layers of semiconductor material, such as one or more epitaxial layers, and can also refer to one or more epitaxial layers on a semiconductor substrate.

[0030] For example, the semiconductor layer 105 may be made of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0031] Silicon carbide (SiC) has a wider band gap than silicon, and therefore can maintain stability at higher temperatures than silicon. Furthermore, silicon carbide has a much higher breakdown field than silicon, and therefore can operate stably even at high voltages. Therefore, the power semiconductor element 100-1 using silicon carbide as the semiconductor layer 105 has a higher breakdown voltage than silicon, while also having excellent heat dissipation characteristics, and can exhibit stable operating characteristics even at high temperatures.

[0032] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type into a silicon carbide epitaxial layer.

[0033] Furthermore, the drift region 107 may include at least one protruding portion 107a disposed under the gate electrode layer 120. During operation of the power semiconductor device 100-1, the protruding portion 107a may provide a vertical transfer path for charges.

[0034] The well region 110 may be formed in the semiconductor layer 105 to contact at least a portion of the drift region 107 and may have a second conductivity type. For example, the well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type in the drift region 107.

[0035] For example, the well region 110 may include a first well region 110a formed in the semiconductor layer 105 below the gate electrode layer 120 and in contact with the protruding portion 107a of the drift region 107, and a second well region 110b formed in the semiconductor layer 105 outside the gate electrode layer 120. The first well region 110a and the second well region 110b may be connected to each other. The protruding portion 107a of the drift region 107 may be substantially defined by the first well region 110a, and more specifically, may be in contact with a sidewall of the first well region 110a.

[0036] The source region 112 may be formed in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping impurities of the first conductivity type into the well region 110. The source region 112 may be doped with impurities of the first conductivity type at a higher concentration than the drift region 107.

[0037] For example, the source region 112 may include a first source region 112a formed in the first well region 110a and a second source region 112b formed in the second well region 110b. The first source region 112a and the second source region 112b may be connected to each other. The first source region 112a may be disposed under the gate electrode layer 120, and the second source region 112b may be disposed outside the gate electrode layer 120.

[0038] The second source region 112b may include a source contact region 113 connected to the source electrode layer 140 outside the gate electrode layer 120. For example, the source contact region 113 may refer to a portion of the second source region 112b to which the source electrode layer 140 is connected.

[0039] The well contact region 114 may be formed in the second source region 112b, more specifically, in the source contact region 113. For example, the well contact region 114 may extend from the second well region 110b through the second source region 112b and have the second conductivity type. One or more well contact regions 114 may be formed in the source contact region 113.

[0040] The well contact region 114 may be connected to the source electrode layer 140, and may be doped with a second conductivity type impurity at a higher concentration than the well region 110 in order to reduce contact resistance when connected to the source electrode layer 140.

[0041] The channel region 110c may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. The channel region 110c may have the second conductivity type such that an inversion channel is formed.

[0042] The channel region 110c has a doping type opposite to that of the source region 112 and the drift region 107, so that the channel region 110c can form a diode junction with the source region 112 and the drift region 107. Thus, the channel region 110c does not allow charge movement under normal circumstances, but when an operating voltage is applied to the gate electrode layer 120, an inversion channel is formed therein, allowing charge movement.

[0043] For example, the channel region 110c may be a part of the well region 110. In this case, the channel region 110c may be formed to be continuously connected to the well region 110. The doping concentration of the second conductivity type impurity in the channel region 110c may be the same as that in other parts of the well region 110 or may be different to adjust the threshold voltage.

[0044] In some embodiments, the protruding portion 107a of the drift region 107, the first well region 110a, the channel region 110c, and / or the first source region 112a may extend in one direction, such as the direction of line VV or line VI-VI in FIG.

[0045] In some embodiments, the first well region 110a, the channel region 110c, and the first source region 112a may be formed symmetrically around the protruding portion 107a of the drift region 107. For example, the first well region 110a, the channel region 110c, and the first source region 112a may be formed in the semiconductor layer 105 on both sides of the protruding portion 107a of the drift region 107, respectively.

[0046] In some embodiments, the drift region 107 may include a plurality of protruding portions 107a whose sidewalls are surrounded by the first well region 110a. For example, the first well region 110a may be formed in a stripe pattern extending in one direction, and the protruding portions 107a may also be formed in a stripe pattern. In this case, the protruding portions 107a may extend side by side in one direction.

[0047] The first source region 112a may be formed in a stripe pattern within the first well region 110a, and the channel region 110c may be formed between the protruding portion 107a and the first source region 112a.

[0048] In some embodiments, the first well region 110a may be formed symmetrically with respect to the second well region 110b, and the first source region 112a may be formed symmetrically with respect to the second source region 112b. In this case, the protruding portion 107a of the drift region 107 and the channel region 110c may be formed symmetrically with respect to the second well region 110b or the second source region 112b.

[0049] Furthermore, the first well regions 110a and the second well regions 110b may be alternately and repeatedly formed in one direction, and in this case, the first source regions 112a and the second source regions 112b may also be repeatedly formed.

[0050] Additionally, a drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be more highly doped than the drift region 107.

[0051] In some embodiments, the drain region 102 may be provided as a silicon carbide substrate having the first conductivity type, in which case the drain region 102 may be understood as part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105.

[0052] The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c. More specifically, the gate insulating layer 118 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107.

[0053] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, oxide of silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stacked structure thereof.

[0054] At least one gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed on at least the channel region 110c. More specifically, the gate electrode layer 120 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107. Furthermore, the second well region 110b, the second source region 112b, and the well contact region 114 may be disposed outside the gate electrode layer 120 and may be exposed from the gate electrode layer 120.

[0055] For example, the gate electrode layer 120 may include a suitable conductive material, such as polysilicon, a metal, a metal nitride, a metal silicide, or a stacked structure thereof.

[0056] An interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulator, such as an oxide layer, a nitride layer, or a stacked structure thereof.

[0057] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112, more specifically, the second source region 112b. Furthermore, the source electrode layer 140 may be commonly connected to the second source region 112b and the well contact region 114. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, etc.

[0058] In the above-described power semiconductor element 100-1, the first conductivity type and the second conductivity type are opposite to each other, but may be either n-type or p-type. For example, if the first conductivity type is n-type, the second conductivity type may be p-type, or vice versa.

[0059] More specifically, if the power semiconductor element 100-1 is an N-type mosfet, the drift region 107 may be an N-region, the source region 112 and the drain region 102 may be N+regions, the well region 110 and the channel region 110c may be P-regions, and the well contact region 114 may be a P+region.

[0060] During operation of the power semiconductor device 100-1, current can flow generally vertically from the drain region 102 along the protruding portion 107a of the drift region 107 and then through the channel region 110c to the source region 112.

[0061] In the above-described power semiconductor device 100-1, the source contact region 113 and the well contact region 114 may be separately disposed outside the gate electrode layer 120. Therefore, the first well region 110a and the first source region 112a may be formed so that the protruding portion 107a of the drift region 107 is densely disposed, and thus the channel region 110c may be densely formed below the gate electrode layer 120. Therefore, the power semiconductor device 100-1 may have a high degree of integration.

[0062] 7 to 10 are schematic perspective views showing a method for manufacturing a power semiconductor element 100-1 according to one embodiment of the present invention. 7, a drift region 107 having a first conductivity type may be formed in a silicon carbide (SiC) semiconductor layer 105. For example, the drift region 107 may be formed on a drain region 102 having the first conductivity type. In some embodiments, the drain region 102 may be provided as a substrate of the first conductivity type, and the drift region 107 may be formed of one or more epitaxial layers on such a substrate.

[0063] Next, a well region 110 having the second conductivity type can be formed in the semiconductor layer 105 so as to be in contact with at least a portion of the drift region 107. For example, the step of forming the well region 110 can be performed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0064] For example, the well region 110 may be formed in the semiconductor layer 105 such that the drift region 107 includes at least one protruding portion 107a at least partially surrounded by the well region 11. More specifically, the well region 110 may be formed by doping the drift region 107 with an impurity opposite to that of the drift region 107.

[0065] The well region 110 may be divided into a first well region 110a in which a channel region 110c is formed and a second well region 110b in which a well contact region 114 is formed. For example, the first well region 110a may define a protruding portion 107a of the drift region 107. The first well region 110a and the second well region 110b may be connected to each other.

[0066] 8, a source region 112 having a first conductivity type may be formed in the well region 110. For example, the step of forming the source region 112 may be performed by implanting impurities of the first conductivity type into the well region 110.

[0067] For example, the step of forming the source region 112 may include forming a first source region 112a in the first well region 110a and a second source region 112b in the second well region 110b. A portion of the second source region 112b may be allocated to a source contact region 113 coupled to the source electrode layer 140. The first source region 112a and the second source region 112b may be coupled to each other.

[0068] Along with the formation of the source region 112, an inversion channel may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107, forming a channel region 110c having the second conductivity type. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a.

[0069] Optionally, a well contact region 114 extending from the second well region 110b through the second source region 112b can be formed in the second source region 112b. For example, the well contact region 114 can be formed by implanting a second conductivity type impurity into a part of the well region 110 at a higher concentration than the well region 110.

[0070] In the above-described manufacturing method, the implantation or doping of impurities can be performed by ion-implanting impurities into the semiconductor layer 105 or by incorporating impurities into the epitaxial layer during formation. However, implantation of impurities into selective regions can be performed using an ion implantation method using a mask pattern. Optionally, the ion implantation can be followed by a heat treatment step to activate or diffuse the impurities.

[0071] 9, a gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c and the protruding portion 107a of the drift region 107.

[0072] For example, the gate insulating layer 118 may be formed as an oxide by oxidizing the semiconductor layer 105, or may be formed by depositing an insulating material such as an oxide or nitride on the semiconductor layer 105.

[0073] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0074] The patterning process can be performed using photolithography and etching processes. The photolithography process includes forming a photoresist pattern as a mask layer using a photolithography process and a development process, and the etching process includes selectively etching the underlying structure using the photoresist pattern.

[0075] 10, an interlayer insulating layer 130 may be formed on the gate electrode layer 120. Optionally, when the interlayer insulating layer 130 is formed entirely on the underlying structure, a process of forming contact hole patterns to expose the source contact region 113 and the well contact region 114 may follow.

[0076] Then, a source electrode layer 140 may be formed on the semiconductor layer 105 to be connected to the second source region 112b and the well contact region 114. For example, the source electrode layer 140 may be formed by forming a conductive layer, for example, a metal layer, on the interlayer insulating layer 130 and then patterning or planarizing the conductive layer.

[0077] According to the above-described manufacturing method, the semiconductor layer 105 is made of silicon carbide, and the highly integrated power semiconductor element 100-1 can be manufactured economically using the same processes as those used for existing silicon substrates.

[0078] FIG. 11 is a schematic perspective view showing a power semiconductor element 100-2 according to one embodiment of the present invention, FIG. 12 is a plan view showing the power semiconductor element 100-2 cut along line II-II in FIG. 11, FIG. 13 is a cross-sectional view showing the power semiconductor element 100-2 cut along line III-III in FIG. 12, FIG. 14 is a cross-sectional view showing the power semiconductor element 100-2 cut along line IV-IV in FIG. 12, and FIG. 15 is a cross-sectional view showing the power semiconductor element cut along line VV in FIG. 12.

[0079] 11 to 15, the power semiconductor device 100-2 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-2 may have a power MOSFET structure.

[0080] The semiconductor layer 105 can refer to one or more layers of semiconductor material, such as one or more epitaxial layers, and can also refer to one or more epitaxial layers on a semiconductor substrate.

[0081] For example, the semiconductor layer 105 may be made of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0082] Silicon carbide (SiC) has a wider band gap than silicon, and therefore can maintain stability at higher temperatures than silicon. Furthermore, silicon carbide has a much higher breakdown field than silicon, and therefore can operate stably even at high voltages. Therefore, the power semiconductor element 100-2 using silicon carbide as the semiconductor layer 105 has a higher breakdown voltage than silicon, while also having excellent heat dissipation characteristics, and can exhibit stable operating characteristics even at high temperatures.

[0083] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type into a silicon carbide epitaxial layer.

[0084] The drift region 107 can provide a vertical transfer path for charges. Furthermore, the drift region 107 can include at least one protruding portion 107a disposed under the gate electrode layer 120. The protruding portion 107a can extend substantially above the surface of the semiconductor layer 105.

[0085] The well region 110 may be formed in the semiconductor layer 105 to contact at least a portion of the drift region 107 and may have a second conductivity type. For example, the well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type in the semiconductor layer 105 or the drift region 107.

[0086] For example, the well region 110 may include a first well region 110a formed in the semiconductor layer 105 below the gate electrode layer 120 and in contact with the protruding portion 107a of the drift region 107, and a second well region 110b formed in the semiconductor layer 105 outside the gate electrode layer 120. The first well region 110a and the second well region 110b may be connected to each other. Essentially, the lower portion of the protruding portion 107a of the drift region 107 may be defined by the first well region 110a, and more specifically, may be in contact with a sidewall of the first well region 110a.

[0087] The source region 112 may be formed on or in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping the semiconductor layer 105 or the well region 110 with impurities of the first conductivity type. The source region 112 may be doped with impurities of the first conductivity type at a higher concentration than the drift region 107.

[0088] For example, the source region 112 may include a first source region 112a formed on or within the first well region 110a and a second source region 112b formed in or above the second well region 110b. The first source region 112a and the second source region 112b may be connected to each other. The first source region 112a may be disposed under the gate electrode layer 120, and the second source region 112b may be disposed outside the gate electrode layer 120.

[0089] The second source region 112b may include a source contact region 112b1 outside the gate electrode layer 120 and connected to the source electrode layer 140. For example, the source contact region 112b1 may refer to a portion of the second source region 112b to which the source electrode layer 140 is connected.

[0090] The avalanche induction region 115 may be formed to contact the drift region 107 via the second well region 110b and to have the second conductivity type. The avalanche induction region 115 may be doped with impurities of the second conductivity type at a higher concentration than the well region 110. The avalanche induction region 115 may be connected to the source electrode layer 140.

[0091] The well contact region 114 may be formed in the second source region 112b, more specifically, in the source contact region 112b1. For example, the well contact region 114 may be connected to the second well region 110b through the second source region 112b and have the second conductivity type. One or more well contact regions 114 may be formed in the source contact region 112b1.

[0092] The well contact region 114 may be connected to the source electrode layer 140, and may be doped with a second conductivity type impurity at a higher concentration than the well region 110 in order to reduce contact resistance when connected to the source electrode layer 140.

[0093] In some embodiments, the well contact region 114 and the avalanche inducing region 115 may be formed as an integrated structure. In this case, the well contact region 114 may refer to a portion of the integrated structure that connects the second well region 110b and the source electrode layer 140, and the avalanche inducing region 115 may refer to a portion of the integrated structure that contacts the drift region 107 and is connected to the well contact region 114 or the source electrode layer 140.

[0094] The channel region 110c may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a.

[0095] For example, the channel region 110c can have the second conductivity type such that an inversion channel is formed. Because the channel region 110c has an opposite doping type to the source region 112 and the drift region 107, the channel region 110c can form a diode junction with the source region 112 and the drift region 107. Thus, although the channel region 110c does not allow charge transfer under normal circumstances, when an operating voltage is applied to the gate electrode layer 120, an inversion channel is formed therein, allowing charge transfer.

[0096] For example, the channel region 110c may be a part of the well region 110. More specifically, the channel region 110c may be a part of the well region 110 adjacent to the bottom of the gate electrode layer 120. In this case, the channel region 110c may be formed integrally or continuously connected to the well region 110. The doping concentration of the second conductive type impurity in the channel region 110c may be the same as that in other parts of the well region 110 or may be different to adjust the threshold voltage.

[0097] In some embodiments, the protruding portion 107a of the drift region 107, the first well region 110a, the channel region 110c, and / or the first source region 112a may extend in one direction. Here, the one direction may refer to the direction of line IV-IV in Figure 12. The extension direction of the channel region 110c does not imply a direction of charge movement.

[0098] In some embodiments, the first well region 110a, the channel region 110c, and the first source region 112a may be formed symmetrically around the protruding portion 107a of the drift region 107. For example, the first well region 110a, the channel region 110c, and the first source region 112a may be formed in the semiconductor layer 105 on both sides of the protruding portion 107a of the drift region 107, respectively.

[0099] In some embodiments, the drift region 107 may include a plurality of protruding portions 107a arranged in one direction. For example, the first well region 110a may be formed in a striped pattern extending in one direction, and the protruding portions 107a may also be formed in a striped pattern. The first source region 112a may be formed in a striped pattern on the first well region 110a. The channel region 110c may be formed between the protruding portions 107a of the drift region 107 and the first source region 112a.

[0100] In some embodiments, the first well region 110a may be formed symmetrically with respect to the second well region 110b, and the first source region 112a may be formed symmetrically with respect to the second source region 112b. In this case, the protruding portion 107a of the drift region 107 may include a plurality of protruding portions 107a formed symmetrically with respect to the second well region 110b or the second source region 112b.

[0101] Furthermore, the first well regions 110a and the second well regions 110b may be alternately and repeatedly formed in one direction, and in this case, the first source regions 112a and the second source regions 112b may also be repeatedly formed.

[0102] Additionally, a drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be more highly doped than the drift region 107.

[0103] In some embodiments, the drain region 102 may be provided as a silicon carbide substrate having the first conductivity type, in which case the drain region 102 may be understood as part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105.

[0104] The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c. More specifically, the gate insulating layer 118 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107.

[0105] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, oxide of silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stacked structure thereof.

[0106] At least one gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed on at least the channel region 110c. More specifically, the gate electrode layer 120 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107. The second well region 110b, the second source region 112b, and the well contact region 114 may be disposed outside the gate electrode layer 120 and may be exposed from the gate electrode layer 120.

[0107] For example, the gate electrode layer 120 may include a suitable conductive material, such as polysilicon, a metal, a metal nitride, a metal silicide, or a stacked structure thereof.

[0108] An interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include an insulator, such as an oxide layer, a nitride layer, or a laminated structure thereof, as appropriate.

[0109] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112, more specifically, the second source region 112b or the source contact region 112b1. Furthermore, the source electrode layer 140 may be commonly connected to the second source region 112b, the well contact region 114, and the avalanche inducing region 115. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, etc.

[0110] In the above-described power semiconductor element 100-2, the first conductivity type and the second conductivity type are opposite to each other, but may be either n-type or p-type. For example, if the first conductivity type is n-type, the second conductivity type may be p-type, or vice versa.

[0111] More specifically, if the power semiconductor element 100-2 is an N-type mosfet, the drift region 107 may be an N-region, the source region 112 and the drain region 102 may be N+regions, the well region 110 and the channel region 110c may be P-regions, and the well contact region 114 and the avalanche inducing region 115 may be P+regions.

[0112] During operation of the power semiconductor device 100-2, current can flow generally vertically from the drain region 102 along the protruding portion 107a of the drift region 107 and then through the channel region 110c to the source region 112.

[0113] In the power semiconductor device 100-2, the source contact region 112b1, the well contact region 114, and the avalanche inducing region 115 may be separately disposed outside the gate electrode layer 120. Therefore, the first well region 110a and the first source region 112a may be formed so that the protruding portions 107a of the drift region 107 are densely arranged, and thus the channel region 110c may be densely formed below the gate electrode layer 120. Therefore, the power semiconductor device 100-2 may have a high degree of integration.

[0114] In the power semiconductor device 100-2, the avalanche inducing region 115 can induce avalanche breakdown to occur through the second well region 110b rather than the first well region 110a when a latch occurs in the power semiconductor device 100-2. The corners of the first well region 110a are vulnerable portions where an electric field is concentrated, and if avalanche breakdown occurs through these corners, a problem occurs in that the current increases abnormally.

[0115] 24, it can be seen that a stronger electric field is applied to the junction structure G1 between the avalanche inducing region 115 and the drift region 107 than to the junction structure G2 between the first well region 110a and the drift region 107. Therefore, before avalanche breakdown occurs through the first well region 110a, avalanche breakdown can be induced in the second well region 110b through the avalanche inducing region 115. This avalanche current can flow to the ground through the source electrode layer 140.

[0116] Therefore, it is possible to suppress the occurrence of avalanche breakdown in the first well region 110a and to suppress the occurrence of latching, thereby improving the operational reliability of the power semiconductor element 100-2.

[0117] 16 to 20 are cross-sectional views showing power semiconductor elements 100a-2, 100b-2, 100c-2, 100d-2, and 100e-2 according to other embodiments of the present invention. The power semiconductor elements 100a-2, 100b-2, 100c-2, 100d-2, and 100e-2 are obtained by modifying or adding some of the configuration of the power semiconductor element 100 shown in FIGS. 11 to 15, and therefore the embodiments may refer to each other, and redundant explanations will be omitted.

[0118] 16, the power semiconductor device 100a-2 may include at least one trench 138 that penetrates the second source region 112b and exposes the second well region 110b. The trench 138 may expose the surface of the second well region 110b or may be recessed to a predetermined depth in the second well region 110b.

[0119] The well contact region 114a may be formed in contact with the second well region 110b at the bottom of the trench 138. For example, a sidewall of the well contact region 114a may be in contact with the second well region 110b. The avalanche inducing region 115a may be formed in contact with the drift region 107 at the bottom of the trench 138.

[0120] For example, well contact region 114a and avalanche inducing region 115a can be formed by doping impurities of the second conductivity type at a high concentration from second well region 110b exposed by trench 138 to a predetermined depth in drift region 107. Avalanche inducing region 115a can be formed so as to be recessed to a predetermined depth within drift region 107.

[0121] The source electrode layer 140 may be formed to fill the groove 138 and may be connected to the well contact region 114a, the avalanche inducing region 115a, the second well region 110b, and / or the second source region 112b. For example, the avalanche inducing region 115a and the well contact region 114a may be formed as an integral structure to contact the drift region 107, the second well region 110b, and the source electrode layer 140.

[0122] In some embodiments, the well contact region 114a may be formed entirely on the surface of the second well region 110b exposed by the trench 138. Thus, the well contact region 114a may be formed on the second well region 110b exposed from the bottom and sidewalls of the trench 138. This structure of the well contact region 114a may serve to further reduce the contact resistance between the source electrode layer 140 and the second well region 110b.

[0123] 17, a power semiconductor device 100b-2 may represent a modification of the structure of FIG. 15. In the power semiconductor device 100b-2, the avalanche inducing region 115 and the well contact region 114 may be formed to be separated from each other.

[0124] For example, the well contact region 114 may be formed to penetrate the second source region 112b and be connected to the second well region 110b, and the avalanche inducing region 115 may be formed to penetrate the second source region 112b and the second well region 110b and be in contact with the drift region 107. The avalanche inducing region 115 and the well contact region 114 may be commonly connected to the source electrode layer 140.

[0125] 18, in the power semiconductor device 100c-2, the channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. The channel region 107b may have a first conductivity type such that an accumulation channel is formed.

[0126] For example, the channel region 107b may have the same doping type as the source region 112 and the drift region 107. In this case, the source region 112, the channel region 107b, and the drift region 107 are normally electrically connected. However, in the silicon carbide semiconductor layer 105, negative charges generated as carbon clusters form in the gate insulating layer 118 cause the bands in the channel region 107b to bend upward, forming a potential barrier. As a result, when an operating voltage is applied to the gate electrode layer 120, an accumulation channel that allows charge or current flow may be formed in the channel region 107b.

[0127] Therefore, the threshold voltage that must be applied to the gate electrode layer 120 to form an accumulation channel in the channel region 107b may be significantly lower than the threshold voltage that must be applied to the gate electrode layer 120 to form a normal inversion channel.

[0128] In some embodiments, channel region 107b may be part of drift region 107. More specifically, channel region 107b may be part of protruding portion 107a of drift region 107. For example, channel region 107b may be integrally formed with drift region 107.

[0129] The drift region 107 may be connected to the source region 112 via the channel region 107b. More specifically, the protruding portion 107a of the drift region 107 and the first source region 112a may contact each other at the channel region 107b.

[0130] For example, the doping concentration of the first conductivity type impurity in the channel region 107b may be the same as that in the other parts of the drift region 107, or may be different to adjust the threshold voltage.

[0131] In some embodiments, the first well region 110a may be formed below the first source region 112a, protruding further toward the protruding portion 107a of the drift region 107 than the first source region 112a. The channel region 107b may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the protruding portion 107a of the drift region 107 may further extend into a groove portion between the first well region 110a and the gate electrode layer 120, and the channel region 107b may be formed in this portion. This structure may allow the channel region 107b to be limited between the gate electrode layer 120 and the well region 110.

[0132] In some embodiments, the first well region 110a and the first source region 112a may have the same width, in which case the first source region 112a contacts the protruding portion 107a of the drift region 107, and the channel region 107b may be defined in the contact portion of the protruding portion 107a.

[0133] Referring to FIG. 19, in the power semiconductor element 100d-2, the first well region 110a protrudes from the first source region 112a toward the protruding portion 107a of the drift region 107, and can include a tap portion at its end extending toward the gate electrode layer 120.

[0134] The channel region 107b1 may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the channel region 107b1 may be formed in a bent shape on the protruding portion and the tap portion of the first well region 110a. Such a structure may allow the channel region 107b1 to be further confined between the gate electrode layer 120 and the first well region 110a.

[0135] 20, in the power semiconductor device 100e-2, the first well region 110a protrudes from the first source region 112a toward the protruding portion 107a of the drift region 107 and may include a tap portion at its end. Furthermore, the protruding portion 107a of the drift region 107 may further extend between the bottom of the first source region 112a and the first well region 110a.

[0136] The channel region 107b2 may be formed to extend further into the semiconductor layer 105 between the lower portion of the first source region 112a and the first well region 110a. For example, the channel region 107b2 may be formed in a bent shape from above the tap portion of the first well region 110a to the lower portion of the first source region 112a. Such a structure may contribute to increasing the contact area between the channel region 107b2 and the first source region 112a.

[0137] 21 to 23 are schematic perspective views illustrating a method for manufacturing a power semiconductor device 100-2 according to an embodiment of the present invention. Referring to FIG. 21, a drift region 107 having a first conductivity type may be formed in a silicon carbide (SiC) semiconductor layer 105 to provide a vertical transfer path for charges. For example, the drift region 107 may be formed on a drain region 102 having the first conductivity type. In some embodiments, the drain region 102 may be provided as a substrate of the first conductivity type, and the drift region 107 may be formed of one or more epitaxial layers on such a substrate.

[0138] Then, a well region 110 having the second conductivity type may be formed in the semiconductor layer 105 so as to contact at least a portion of the drift region 107. More specifically, the well region 110 may be formed in the semiconductor layer 105 so as to contact the protruding portion 107a of the drift region 107 and define the at least one protruding portion 107a of the drift region 107. More specifically, the well region 110 may be formed by doping the drift region 107 or the semiconductor layer 105 with impurities of the opposite conductivity type to that of the drift region 107, for example, impurities of the second conductivity type.

[0139] The well region 110 may be divided into a first well region 110a below the gate electrode layer 120 and a second well region 110b outside the gate electrode layer 120. For example, the first well region 110a defines the protruding portion 107a of the drift region 107, and a well contact region 114 may be subsequently formed in the second well region 110b. The first well region 110a and the second well region 110b may be connected to each other.

[0140] Furthermore, a source region 112 having the first conductivity type may be formed on or in the well region 110. For example, the step of forming the source region 112 may be performed by implanting impurities of the first conductivity type into the well region 110 or into the semiconductor layer 105.

[0141] For example, the step of forming the source region 112 may include forming a first source region 112a on or in the first well region 110a and forming a second source region 112b on or in the second well region 110b. A portion of the second source region 112b may be assigned to a source contact region 112b1 connected to the source electrode layer 140. The first source region 112a and the second source region 112b may be connected to each other. The source region 112 may be formed at a predetermined depth within or above the well region 110, substantially from the surface of the semiconductor layer 105.

[0142] Simultaneously with the formation of the source region 112, a channel region 110c having the second conductivity type may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107 so that an inversion channel is formed. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. For example, the channel region 110c may not be formed separately as part of the first well region 110a, but may be formed together with the first well region 110a.

[0143] Furthermore, an avalanche inducing region 115 can be formed by doping the well region 110 with impurities of the second conductivity type at a concentration higher than that of the well region 110 so as to be in contact with the drift region 107 via the second well region 110b.

[0144] In addition, a well contact region 114 may be formed in the second source region 112b, penetrating the second source region 112b and connected to the second well region 110b. For example, the well contact region 114 may be formed by implanting second conductivity type impurities into a portion of the second well region 110b at a concentration higher than that of the well region 110b.

[0145] In a variation of this embodiment, the doping order of the impurities in the well region 110, the source region 112, the channel region 110c, the well contact region 114, and the avalanche inducing region 115 may be changed appropriately.

[0146] In the above-described manufacturing method, the implantation or doping of impurities can be performed by ion-implanting impurities into the semiconductor layer 105 or by incorporating impurities into the epitaxial layer during formation. However, implantation of impurities into selective regions can be performed using an ion implantation method using a mask pattern. Optionally, the ion implantation can be followed by a heat treatment step to activate or diffuse the impurities.

[0147] 21 , a gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c and the protruding portion 107a of the drift region 107.

[0148] For example, the gate insulating layer 118 may be formed as an oxide by oxidizing the semiconductor layer 105, or may be formed by depositing an insulating material such as an oxide or nitride on the semiconductor layer 105.

[0149] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0150] The patterning process can be performed using photolithography and etching processes. The photolithography process includes forming a photoresist pattern as a mask layer using a photolithography process and a development process, and the etching process includes selectively etching the underlying structure using the photoresist pattern.

[0151] 22, an interlayer insulating layer 130 may be formed on the gate electrode layer 120. Optionally, when the interlayer insulating layer 130 is formed entirely on the lower structure, a process of forming contact hole patterns to expose the source contact region 112b1 and the well contact region 114 may follow.

[0152] Then, a source electrode layer 140 may be formed on the semiconductor layer 105 so as to be connected to the second source region 112b, the well contact region 114, and the avalanche inducing region 115. For example, the source electrode layer 140 may be formed by forming a conductive layer, for example, a metal layer, on the interlayer insulating layer 130 and then patterning or planarizing the conductive layer.

[0153] On the other hand, the power semiconductor element 100a-2 of FIG. 16 can be manufactured by adding or modifying some steps in the manufacturing process for the power semiconductor element 100-2 described above.

[0154] The manufacturing of the power semiconductor element 100a-2 of FIG. 16 can include the additional step of forming at least one trench 138 in the second source region 112b, penetrating the second source region 112b and exposing the second well region 110b, forming a well contact region 114a in contact with the second well region 110b and an avalanche inducing region 115a in contact with the drift region 107 at the bottom of the trench 138, and forming a source electrode layer 140 to fill the trench 138 and be connected to the source region 112, the well contact region 114, and the avalanche inducing region 115a.

[0155] 18 to 20, the channel regions 107b, 107b1, and 107b2 may be formed to have the first conductivity type so as to form an accumulation channel. For example, the channel regions 107b, 107b1, and 107b2 may be formed as part of the drift region 107.

[0156] According to the above-described manufacturing method, the semiconductor layer 105 is made of silicon carbide, and the highly integrated power semiconductor element 100-2 can be manufactured economically using the same processes as those used for existing silicon substrates.

[0157] Figure 25 is a schematic perspective view showing a power semiconductor element 100-3 according to one embodiment of the present invention, Figure 26 is a plan view showing the power semiconductor element 100-3 cut along line II-II in Figure 25, Figure 27 is a cross-sectional view showing the power semiconductor element 100-3 cut along line III-III in Figure 26, and Figure 28 is a cross-sectional view showing the power semiconductor element 100-3 cut along line IV-IV in Figure 26.

[0158] 25 to 28, the power semiconductor device 100-3 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-3 may have a power MOSFET structure.

[0159] The semiconductor layer 105 can refer to one or more layers of semiconductor material, such as one or more epitaxial layers, and can also refer to one or more epitaxial layers on a semiconductor substrate.

[0160] For example, the semiconductor layer 105 may be made of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0161] Silicon carbide (SiC) has a wider band gap than silicon, and therefore can maintain stability at higher temperatures than silicon. Furthermore, silicon carbide has a much higher breakdown field than silicon, and therefore can operate stably even at high voltages. Therefore, the power semiconductor element 100-3 using silicon carbide as the semiconductor layer 105 has a higher breakdown voltage than silicon, while also having excellent heat dissipation characteristics, and can exhibit stable operating characteristics even at high temperatures.

[0162] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type into a silicon carbide epitaxial layer.

[0163] The drift region 107 can provide a vertical transfer path for charges. Furthermore, the drift region 107 can include at least one protruding portion 107a disposed under the gate electrode layer 120. The protruding portion 107a can extend substantially above the surface of the semiconductor layer 105.

[0164] The well region 110 may be formed in the semiconductor layer 105 to contact at least a portion of the drift region 107 and may have a second conductivity type. For example, the well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type in the semiconductor layer 105 or the drift region 107.

[0165] For example, the well region 110 may include a first well region 110a formed in the semiconductor layer 105 below the gate electrode layer 120 and in contact with the protruding portion 107a of the drift region 107, and a second well region 110b formed in the semiconductor layer 105 outside the gate electrode layer 120. The first well region 110a and the second well region 110b may be connected to each other. Essentially, the lower portion of the protruding portion 107a of the drift region 107 may be defined by the first well region 110a, and more specifically, may be in contact with a sidewall of the first well region 110a.

[0166] The pillar region 111 may be formed in the semiconductor layer 105 to have a different conductivity type from that of the drift region 107 so as to form a superjunction with the drift region 107. For example, the pillar region 111 may have the second conductivity type and be formed in contact with the well region 110 in the semiconductor layer 105 below the well region 110. The pillar region 111 may also be referred to as a deep well region.

[0167] For example, the pillar region 111 may be formed to contact or surround the sidewall of the drift region 107. As another example, the pillar region 111 may be divided into a plurality of regions and formed to contact the drift region 107 alternately.

[0168] In some embodiments, the pillar regions 111 may be narrower than the well region 110 and recessed inward from the end of the well region 110 to expose at least a portion of the bottom surface of the well region 110. As a result, the well region 110 may be formed to protrude further in the direction of the protruding portion 107a of the drift region 107 than the pillar regions 111.

[0169] The source region 112 may be formed on or in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping the semiconductor layer 105 or the well region 110 with impurities of the first conductivity type. The source region 112 may be doped with impurities of the first conductivity type at a higher concentration than the drift region 107.

[0170] For example, the source region 112 may include a first source region 112a formed on the first well region 110a and a second source region 112b formed on the second well region 110b. The first source region 112a and the second source region 112b may be connected to each other. The first source region 112a may be disposed under the gate electrode layer 120, and the second source region 112b may be disposed outside the gate electrode layer 120.

[0171] The second source region 112b may include a source contact region 112b1 outside the gate electrode layer 120 and connected to the source electrode layer 140. For example, the source contact region 112b1 may refer to a portion of the second source region 112b to which the source electrode layer 140 is connected.

[0172] The well contact region 114 may be formed in the second source region 112b, more specifically, in the source contact region 112b1. For example, the well contact region 114 may extend from the second well region 110b through the second source region 112b and have the second conductivity type. One or more well contact regions 114 may be formed in the source contact region 112b1.

[0173] The well contact region 114 may be connected to the source electrode layer 140, and may be doped with a second conductivity type impurity at a higher concentration than the well region 110 in order to reduce contact resistance when connected to the source electrode layer 140.

[0174] The channel region 110c may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a.

[0175] For example, the channel region 110c can have the second conductivity type such that an inversion channel is formed. Because the channel region 110c has an opposite doping type to the source region 112 and the drift region 107, the channel region 110c can form a diode junction with the source region 112 and the drift region 107. Thus, although the channel region 110c does not allow charge transfer under normal circumstances, when an operating voltage is applied to the gate electrode layer 120, an inversion channel is formed therein, allowing charge transfer.

[0176] For example, the channel region 110c may be a part of the well region 110. More specifically, the channel region 110c may be a part of the well region 110 adjacent to the bottom of the gate electrode layer 120. In this case, the channel region 110c may be formed integrally or continuously connected to the well region 110. The doping concentration of the second conductive type impurity in the channel region 110c may be the same as that in other parts of the well region 110 or may be different to adjust the threshold voltage.

[0177] In some embodiments, the protruding portion 107a of the drift region 107, the first well region 110a, the channel region 110c, and / or the first source region 112a may extend in one direction. For example, the direction of line IV-IV in FIG. 26 may be one direction. Here, the extension direction of the channel region 110c does not mean the direction of charge movement.

[0178] In some embodiments, the first well region 110a, the channel region 110c, and the first source region 112a may be formed symmetrically around the protruding portion 107a of the drift region 107. For example, the first well region 110a, the channel region 110c, and the first source region 112a may be formed in the semiconductor layer 105 on both sides of the protruding portion 107a of the drift region 107, respectively. Furthermore, the pillar regions 111 may also be formed in the lower portions of the first well region 110a on both sides of the protruding portion 107a of the drift region 107.

[0179] In some embodiments, the drift region 107 may include a plurality of protruding portions 107a arranged in one direction. For example, the first well region 110a may be formed in a striped pattern extending in one direction, and the protruding portions 107a may also be formed in a striped pattern. The first source region 112a may be formed in a striped pattern on the first well region 110a. The channel region 110c may be formed between the protruding portions 107a of the drift region 107 and the first source region 112a.

[0180] In some embodiments, the first well region 110a may be formed symmetrically with respect to the second well region 110b, and the first source region 112a may be formed symmetrically with respect to the second source region 112b. In this case, the protruding portion 107a of the drift region 107 may include a plurality of protruding portions 107a formed symmetrically with respect to the second well region 110b or the second source region 112b.

[0181] Furthermore, the first well regions 110a and the second well regions 110b may be alternately and repeatedly formed in one direction, and in this case, the first source regions 112a and the second source regions 112b may also be repeatedly formed.

[0182] Additionally, a drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be more highly doped than the drift region 107.

[0183] In some embodiments, the drain region 102 may be provided as a silicon carbide substrate having the first conductivity type, in which case the drain region 102 may be understood as part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105.

[0184] The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c. More specifically, the gate insulating layer 118 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107.

[0185] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, oxide of silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stacked structure thereof.

[0186] At least one gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed on at least the channel region 110c. More specifically, the gate electrode layer 120 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107. The second well region 110b, the second source region 112b, and the well contact region 114 may be disposed outside the gate electrode layer 120 and may be exposed from the gate electrode layer 120.

[0187] For example, the gate electrode layer 120 may include a suitable conductive material, such as polysilicon, a metal, a metal nitride, a metal silicide, or a stacked structure thereof.

[0188] An interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include an insulator, such as an oxide layer, a nitride layer, or a laminated structure thereof, as appropriate.

[0189] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112, more specifically, the second source region 112b or the source contact region 112b1. Furthermore, the source electrode layer 140 may be commonly connected to the second source region 112b and the well contact region 114. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, etc.

[0190] In the above-described power semiconductor element 100-3, the first conductivity type and the second conductivity type are opposite to each other, but may be either n-type or p-type. For example, if the first conductivity type is n-type, the second conductivity type may be p-type, or vice versa.

[0191] More specifically, if the power semiconductor element 100-3 is an N-type mosfet, the drift region 107 may be an N-region, the source region 112 and the drain region 102 may be N+regions, the well region 110, the channel region 110c, and the pillar region 111 may be P-regions, and the well contact region 114 may be a P+region.

[0192] During operation of the power semiconductor device 100-3, current can flow generally vertically from the drain region 102 along the protruding portion 107a of the drift region 107 and then through the channel region 110c to the source region 112.

[0193] In the above-described power semiconductor device 100-3, the source contact region 112b1 and the well contact region 114 may be separately disposed outside the gate electrode layer 120. Therefore, the first well region 110a and the first source region 112a may be formed so that the protruding portion 107a of the drift region 107 is densely disposed, and thus the channel region 110c may be densely formed below the gate electrode layer 120. Therefore, the power semiconductor device 100-3 may have a high degree of integration.

[0194] On the other hand, the power semiconductor device 100-3 is required to have high breakdown voltage characteristics because it is used for high-power switching. When a high voltage is applied to the drain region 102, a depletion region expands from the semiconductor layer 105 adjacent to the drain region 102, and the voltage barrier of the channel can be lowered. This phenomenon is called drain-induced barrier lowering (DIBL).

[0195] Such DIBL may cause abnormal turn-on of the channel region 110c, and may also lead to a punch-through phenomenon in which the depletion layers between the drain region 102 and the source region 112 expand and come into contact with each other.

[0196] However, the power semiconductor device 100-3 described above can reduce the resistance of the drift region 107 and the channel region 110c by using the pillar regions 111 that form a superjunction with the drift region 107, thereby suppressing abnormal current flow and punch-through caused by DIBL and ensuring appropriate breakdown voltage characteristics. Therefore, a high breakdown voltage can be maintained even if the thickness of the drift region 107 that forms the body is reduced. Such breakdown voltage characteristics can be further improved by adjusting the charge amount of the pillar regions 111 and the charge amount of the drift region 107.

[0197] 36 is a graph showing changes in the electric field depending on the depth of a power semiconductor device 100-3 according to one embodiment of the present invention. In FIG. 36, position A indicates the surface of the first well region 110a, position B indicates the bottom surface of the pillar region 111, and position C indicates the bottom surface of the drift region 107.

[0198] 36, when the charge quantity Qp of the pillar region 111 is made larger than the charge quantity Qn of the drift region 107, the breakdown voltage can be increased by generating a maximum electric field in the drift region 107 on the same line as the bottom surface of the pillar region 111 during operation of the power semiconductor device 100-3. In FIG. 36, the gradient of the electric field strength between positions A and B can be controlled by adjusting the charge quantity Qp of the pillar region 111.

[0199] For example, the charge balance can be adjusted by making the doping concentration of the second conductivity type impurity in the pillar region 111 higher than the doping concentration of the first conductivity type impurity in the drift region 107. This adjustment of the charge balance can reduce the field applied to the gate insulating layer 118 and increase the DIBL margin, thereby improving the breakdown voltage characteristics of the power semiconductor element 100-3.

[0200] Therefore, according to the power semiconductor device 100-3 described above, it is possible to increase the channel density and increase the integration level while maintaining the breakdown voltage, thereby reducing the operating loss.

[0201] 29 to 32 are cross-sectional views showing power semiconductor elements 100a-3, 100b-3, 100c-3, and 100d-3 according to other embodiments of the present invention. The power semiconductor elements 100a-3, 100b-3, 100c-3, and 100d-3 are obtained by modifying or adding to part of the configuration of the power semiconductor element 100-3 shown in FIGS. 25 to 28, and therefore the embodiments may refer to each other and redundant explanations will be omitted.

[0202] 29, the power semiconductor device 100a-3 may include at least one trench 138 that penetrates the second source region 112b and exposes the second well region 110b. The trench 138 may expose the surface of the second well region 110b or may be recessed to a predetermined depth in the second well region 110b. A well contact region 114a may be formed on at least the bottom surface of the trench 138 to contact the second well region 110b.

[0203] The source electrode layer 140 may be formed to fill the groove 138 and may be connected to the well contact region 114a, the second well region 110b, and / or the second source region 112b. This structure may increase the contact area between the source electrode layer 140 and the second well region 110b and the second source region 112b, thereby helping to reduce contact resistance therebetween.

[0204] In some embodiments, the well contact region 114a may be formed entirely on the surface of the second well region 110b exposed by the trench 138. Thus, the well contact region 114a may be formed on the second well region 110b exposed from the bottom and sidewalls of the trench 138. This structure of the well contact region 114a may serve to further reduce the contact resistance between the source electrode layer 140 and the second well region 110b.

[0205] 30, in the power semiconductor device 100b-3, the channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. The channel region 107b may have a first conductivity type such that an accumulation channel is formed.

[0206] For example, the channel region 107b may have the same doping type as the source region 112 and the drift region 107. In this case, the source region 112, the channel region 107b, and the drift region 107 are normally electrically connected. However, in the silicon carbide semiconductor layer 105, negative charges generated as carbon clusters form in the gate insulating layer 118 cause the bands in the channel region 107b to bend upward, forming a potential barrier. As a result, when an operating voltage is applied to the gate electrode layer 120, an accumulation channel that allows charge or current flow may be formed in the channel region 107b.

[0207] Therefore, the threshold voltage that must be applied to the gate electrode layer 120 to form an accumulation channel in the channel region 107b may be significantly lower than the threshold voltage that must be applied to the gate electrode layer 120 to form a normal inversion channel.

[0208] In some embodiments, channel region 107b may be part of drift region 107. More specifically, channel region 107b may be part of protruding portion 107a of drift region 107. For example, channel region 107b may be integrally formed with drift region 107.

[0209] The drift region 107 may be connected to the source region 112 via the channel region 107b. More specifically, the protruding portion 107a of the drift region 107 and the first source region 112a may contact each other at the channel region 107b.

[0210] For example, the doping concentration of the first conductivity type impurity in the channel region 107b may be the same as that in the other parts of the drift region 107, or may be different to adjust the threshold voltage.

[0211] In some embodiments, the first well region 110a may be formed below the first source region 112a, protruding further toward the protruding portion 107a of the drift region 107 than the first source region 112a. The channel region 107b may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the protruding portion 107a of the drift region 107 may further extend into a groove portion between the first well region 110a and the gate electrode layer 120, and the channel region 107b may be formed in this portion. This structure may allow the channel region 107b to be limited between the gate electrode layer 120 and the well region 110.

[0212] In some embodiments, the first well region 110a and the first source region 112a may have the same width, in which case the first source region 112a contacts the protruding portion 107a of the drift region 107, and the channel region 107b may be defined in the contact portion of the protruding portion 107a.

[0213] Referring to FIG. 31, in the power semiconductor element 100c-3, the first well region 110a protrudes from the first source region 112a toward the protruding portion 107a of the drift region 107, and can include a tap portion at its end extending toward the gate electrode layer 120.

[0214] The channel region 107b1 may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the channel region 107b1 may be formed in a bent shape on the protruding portion and the tap portion of the first well region 110a. Such a structure may allow the channel region 107b1 to be further confined between the gate electrode layer 120 and the first well region 110a.

[0215] 32, in a power semiconductor device 100d-3, the first well region 110a protrudes from the first source region 112a toward the protruding portion 107a of the drift region 107 and may include a tap portion at its end. Furthermore, the protruding portion 107a of the drift region 107 may further extend between the bottom of the first source region 112a and the first well region 110a.

[0216] The channel region 107b2 may be formed to extend further into the semiconductor layer 105 between the lower portion of the first source region 112a and the first well region 110a. For example, the channel region 107b2 may be formed in a bent shape from above the tap portion of the first well region 110a to the lower portion of the first source region 112a. Such a structure may contribute to increasing the contact area between the channel region 107b2 and the first source region 112a.

[0217] 33 to 35 are schematic perspective views illustrating a method for manufacturing a power semiconductor device 100-3 according to an embodiment of the present invention. Referring to FIG. 33, a drift region 107 having a first conductivity type may be formed in a silicon carbide (SiC) semiconductor layer 105 to provide a vertical transfer path for charges. For example, the drift region 107 may be formed on a drain region 102 having the first conductivity type. In some embodiments, the drain region 102 may be provided as a substrate of the first conductivity type, and the drift region 107 may be formed of one or more epitaxial layers on such a substrate.

[0218] Next, a well region 110 having the second conductivity type can be formed in the semiconductor layer 105 so as to be in contact with at least a portion of the drift region 107. For example, the step of forming the well region 110 can be performed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0219] More specifically, the well region 110 may be formed in the semiconductor layer 105 in contact with the protruding portion 107a so as to define at least one protruding portion 107a of the drift region 107. More specifically, the well region 110 may be formed by doping the drift region 107 or the semiconductor layer 105 with an impurity opposite to that of the drift region 107.

[0220] The well region 110 may be divided into a first well region 110a below the gate electrode layer 120 and a second well region 110b outside the gate electrode layer 120. For example, the first well region 110a defines the protruding portion 107a of the drift region 107, and a well contact region 114 may be subsequently formed in the second well region 110b. The first well region 110a and the second well region 110b may be connected to each other.

[0221] The pillar region 111 may be formed in the semiconductor layer 105 below the well region 110 in contact with the well region 110. The pillar region 111 may have the second conductivity type so as to form a superjunction with the drift region 107. For example, the pillar region 111 may be formed by implanting impurities of the second conductivity type into the semiconductor layer 105 or the drift region 107.

[0222] Furthermore, a source region 112 having the first conductivity type may be formed on or in the well region 110. For example, the step of forming the source region 112 may be performed by implanting impurities of the first conductivity type into the well region 110 or into the semiconductor layer 105.

[0223] For example, the step of forming the source region 112 may include forming a first source region 112a on or in the first well region 110a and forming a second source region 112b on or in the second well region 110b. A portion of the second source region 112b may be assigned to a source contact region 112b1 connected to the source electrode layer 140. The first source region 112a and the second source region 112b may be connected to each other. The source region 112 may be formed at a predetermined depth within or above the well region 110, substantially from the surface of the semiconductor layer 105.

[0224] Simultaneously with the formation of the source region 112, a channel region 110c having the second conductivity type may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107 so that an inversion channel is formed. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. For example, the channel region 110c may not be formed separately as part of the first well region 110a, but may be formed together with the first well region 110a.

[0225] Optionally, a well contact region 114 extending from the second well region 110b through the second source region 112b can be formed in the second source region 112b. For example, the well contact region 114 can be formed by implanting a second conductivity type impurity into a part of the well region 110 at a higher concentration than the well region 110.

[0226] In a variation of this embodiment, the doping order of the impurities in the well region 110, the pillar region 111, the source region 112, the channel region 110c, and the well contact region 114 may be changed appropriately.

[0227] In the above-described manufacturing method, the implantation or doping of impurities can be performed by ion-implanting impurities into the semiconductor layer 105 or by incorporating impurities into the epitaxial layer during formation. However, implantation of impurities into selective regions can be performed using an ion implantation method using a mask pattern. Optionally, the ion implantation can be followed by a heat treatment step to activate or diffuse the impurities.

[0228] 34, a gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c and the protruding portion 107a of the drift region 107.

[0229] For example, the gate insulating layer 118 may be formed as an oxide by oxidizing the semiconductor layer 105, or may be formed by depositing an insulating material such as an oxide or nitride on the semiconductor layer 105.

[0230] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0231] The patterning process can be performed using photolithography and etching processes. The photolithography process includes forming a photoresist pattern as a mask layer using a photolithography process and a development process, and the etching process includes selectively etching the underlying structure using the photoresist pattern.

[0232] 35, an interlayer insulating layer 130 may be formed on the gate electrode layer 120. Optionally, when the interlayer insulating layer 130 is formed entirely on the lower structure, a process of forming contact hole patterns to expose the source contact region 112b1 and the well contact region 114 may follow.

[0233] Then, a source electrode layer 140 may be formed on the semiconductor layer 105 to be connected to the second source region 112b and the well contact region 114. For example, the source electrode layer 140 may be formed by forming a conductive layer, for example, a metal layer, on the interlayer insulating layer 130 and then patterning or planarizing the conductive layer.

[0234] On the other hand, the power semiconductor element 100a-3 of FIG. 29 can be manufactured by adding or modifying some steps in the manufacturing process for the power semiconductor element 100-3 described above.

[0235] The manufacturing of the power semiconductor element 100a-3 of FIG. 29 can include the steps of forming at least one trench 138 in the second source region 112b, penetrating the second source region 112b and exposing the second well region 110b, forming a well contact region 114 at the bottom of the trench 138 so as to contact the well region 110b, and forming a source electrode layer 140 so as to fill the trench 138 and connect to the source region 112b and the well contact region 114.

[0236] 30 to 32, the channel regions 107b, 107b1, and 107b2 may be formed to have the first conductivity type so as to form an accumulation channel. For example, the channel regions 107b, 107b1, and 107b2 may be formed as part of the drift region 107.

[0237] According to the above-described manufacturing method, the semiconductor layer 105 is made of silicon carbide, and the highly integrated power semiconductor element 100-3 can be manufactured economically using the same process as that used for existing silicon substrates.

[0238] Figure 37 is a schematic oblique view showing a power semiconductor element 100-4 according to one embodiment of the present invention, Figure 38 is a plan view showing the power semiconductor element 100-4 cut along line II-II in Figure 37, Figure 39 is a cross-sectional view showing the power semiconductor element 100-4 cut along line III-III in Figure 38, Figure 40 is a cross-sectional view showing the power semiconductor element 100-4 cut along line IV-IV in Figure 38, and Figure 41 is a cross-sectional view showing the power semiconductor element 100-4 cut along line VV in Figure 38.

[0239] 37 to 41, the power semiconductor device 100-4 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-4 may have a power MOSFET structure.

[0240] The semiconductor layer 105 can refer to one or more layers of semiconductor material, such as one or more epitaxial layers, and can also refer to one or more epitaxial layers on a semiconductor substrate.

[0241] For example, the semiconductor layer 105 may be made of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0242] Silicon carbide (SiC) has a wider band gap than silicon, and therefore can maintain stability at higher temperatures than silicon. Furthermore, silicon carbide has a much higher breakdown field than silicon, and therefore can operate stably even at high voltages. Therefore, the power semiconductor element 100-4 using silicon carbide as the semiconductor layer 105 has a higher breakdown voltage than silicon, while also having excellent heat dissipation characteristics, and can exhibit stable operating characteristics even at high temperatures.

[0243] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type into a silicon carbide epitaxial layer.

[0244] The drift region 107 can provide a vertical transfer path for charges. Furthermore, the drift region 107 can include at least one protruding portion 107a disposed under the gate electrode layer 120. The protruding portion 107a can extend substantially above the surface of the semiconductor layer 105.

[0245] The well region 110 may be formed in the semiconductor layer 105 to contact at least a portion of the drift region 107 and may have a second conductivity type. For example, the well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type in the semiconductor layer 105 or the drift region 107.

[0246] For example, the well region 110 may include a first well region 110a formed in the semiconductor layer 105 below the gate electrode layer 120 and in contact with the protruding portion 107a of the drift region 107, and a second well region 110b formed in the semiconductor layer 105 outside the gate electrode layer 120. The first well region 110a and the second well region 110b may be connected to each other. Essentially, the lower portion of the protruding portion 107a of the drift region 107 may be defined by the first well region 110a, and more specifically, may be in contact with a sidewall of the first well region 110a.

[0247] The deep well region 111 may be formed in the semiconductor layer 105 below the well region 110 to have a different conductivity type from the drift region 107. For example, the deep well region 111 may have the same second conductivity type as the well region 110 and may be formed in the semiconductor layer 105 below the well region 110 to be in contact with the well region 110 and the drift region 107. The doping concentration of the second conductivity type impurity in the deep well region 111 may be the same as or smaller than the doping concentration of the second conductivity type impurity in the well region 110.

[0248] For example, the deep well region 111 may be formed in contact with or surrounding the sidewall of the drift region 107 at the bottom of the well region 110. As another example, the deep well region 111 may be divided into a plurality of regions and formed to alternately contact the drift region 107.

[0249] In some embodiments, the deep well region 111 may be narrower than the well region 110 in one direction so as to expose at least a portion of the bottom surface of the well region 110. For example, both ends of the deep well region 111 may be recessed inward from both ends of the well region 110 in one direction and formed below the well region 110. The one direction may indicate the direction of line IV-IV or line VV in FIG. 38. As a result, the well region 110 may be formed to protrude further in the direction of the protruding portion 107a of the drift region 107 than the deep well region 111 in one direction.

[0250] The source region 112 may be formed on or in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping the semiconductor layer 105 or the well region 110 with impurities of the first conductivity type. The source region 112 may be doped with impurities of the first conductivity type at a higher concentration than the drift region 107.

[0251] For example, the source region 112 may include a first source region 112a formed on the first well region 110a and a second source region 112b formed on the second well region 110b. The first source region 112a and the second source region 112b may be connected to each other. The first source region 112a may be disposed under the gate electrode layer 120, and the second source region 112b may be disposed outside the gate electrode layer 120.

[0252] The second source region 112b may include a source contact region 112b1 outside the gate electrode layer 120 and connected to the source electrode layer 140. For example, the source contact region 112b1 may refer to a portion of the second source region 112b to which the source electrode layer 140 is connected.

[0253] The well contact region 114 may be formed in the second source region 112b, more specifically, in the source contact region 112b1. For example, the well contact region 114 may extend from the second well region 110b through the second source region 112b and have the second conductivity type. One or more well contact regions 114 may be formed in the source contact region 112b1.

[0254] The well contact region 114 may be connected to the source electrode layer 140, and may be doped with a second conductivity type impurity at a higher concentration than the well region 110 in order to reduce contact resistance when connected to the source electrode layer 140.

[0255] The channel region 110c may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a.

[0256] For example, the channel region 110c can have the second conductivity type such that an inversion channel is formed. Because the channel region 110c has an opposite doping type to the source region 112 and the drift region 107, the channel region 110c can form a diode junction with the source region 112 and the drift region 107. Thus, although the channel region 110c does not allow charge transfer under normal circumstances, when an operating voltage is applied to the gate electrode layer 120, an inversion channel is formed therein, allowing charge transfer.

[0257] For example, the channel region 110c may be a part of the well region 110. More specifically, the channel region 110c may be a part of the well region 110 adjacent to the bottom of the gate electrode layer 120. In this case, the channel region 110c may be formed integrally or continuously connected to the well region 110. The doping concentration of the second conductive type impurity in the channel region 110c may be the same as that in other parts of the well region 110 or may be different to adjust the threshold voltage.

[0258] In some embodiments, the protruding portion 107a of the drift region 107, the first well region 110a, the channel region 110c, and / or the first source region 112a may extend in one direction. The extension of the first well region 110a in one direction may also allow the deep well region 111 below the first well region 110a to extend in one direction. Here, the extension direction of the channel region 110c does not refer to the direction of charge movement.

[0259] In some embodiments, the first well region 110a, the channel region 110c, and the first source region 112a may be formed symmetrically around the protruding portion 107a of the drift region 107. For example, the first well region 110a, the channel region 110c, and the first source region 112a may be formed in the semiconductor layer 105 on both sides of the protruding portion 107a of the drift region 107, respectively. Furthermore, portions of the deep well regions 111 may also be formed in the lower portions of the first well region 110a on both sides of the protruding portion 107a of the drift region 107.

[0260] In some embodiments, the drift region 107 may include a plurality of protruding portions 107a arranged in one direction. For example, the first well region 110a may be formed in a striped pattern extending in one direction, and the protruding portions 107a may also be formed in a striped pattern. The first source region 112a may be formed in a striped pattern on the first well region 110a. The channel region 110c may be formed between the protruding portions 107a of the drift region 107 and the first source region 112a.

[0261] In some embodiments, the first well region 110a may be formed symmetrically with respect to the second well region 110b, and the first source region 112a may be formed symmetrically with respect to the second source region 112b. In this case, the protruding portion 107a of the drift region 107 may include a plurality of protruding portions 107a formed symmetrically with respect to the second well region 110b or the second source region 112b.

[0262] Furthermore, the first well regions 110a and the second well regions 110b may be alternately and repeatedly formed in one direction, and in this case, the first source regions 112a and the second source regions 112b may also be repeatedly formed.

[0263] Additionally, a drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be more highly doped than the drift region 107.

[0264] In some embodiments, the drain region 102 may be provided as a silicon carbide substrate having the first conductivity type, in which case the drain region 102 may be understood as part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105.

[0265] The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c. More specifically, the gate insulating layer 118 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107.

[0266] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, oxide of silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stacked structure thereof.

[0267] At least one gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed on at least the channel region 110c. More specifically, the gate electrode layer 120 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107. The second well region 110b, the second source region 112b, and the well contact region 114 may be disposed outside the gate electrode layer 120 and may be exposed from the gate electrode layer 120.

[0268] For example, the gate electrode layer 120 may include a suitable conductive material, such as polysilicon, a metal, a metal nitride, a metal silicide, or a stacked structure thereof.

[0269] An interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include an insulator, such as an oxide layer, a nitride layer, or a laminated structure thereof, as appropriate.

[0270] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112, more specifically, the second source region 112b or the source contact region 112b1. Furthermore, the source electrode layer 140 may be commonly connected to the second source region 112b and the well contact region 114. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, etc.

[0271] In the above-described power semiconductor element 100-4, the first conductivity type and the second conductivity type are opposite to each other, but may be either n-type or p-type. For example, if the first conductivity type is n-type, the second conductivity type may be p-type, or vice versa.

[0272] More specifically, if the power semiconductor element 100-4 is an N-type mosfet, the drift region 107 may be an N-region, the source region 112 and the drain region 102 may be N+regions, the well region 110, the channel region 110c, and the deep well region 111 may be P-regions, and the well contact region 114 may be a P+region.

[0273] During operation of the power semiconductor device 100-4, current can flow generally vertically from the drain region 102 along the protruding portion 107a of the drift region 107 and then through the channel region 110c to the source region 112.

[0274] In the above-described power semiconductor device 100-4, the source contact region 112b1 and the well contact region 114 may be separately disposed outside the gate electrode layer 120. Therefore, the first well region 110a and the first source region 112a may be formed so that the protruding portion 107a of the drift region 107 is densely disposed, and thus the channel region 110c may be densely formed below the gate electrode layer 120. Therefore, the power semiconductor device 100-4 may have a high degree of integration.

[0275] In the case of the power semiconductor element 100-4 described above, the deep well region 111 is disposed below the well region 110, thereby reducing the electric field applied to the gate insulating layer 118 on the protruding portion 107a of the drift region 107 between the well regions 110. Furthermore, by reducing the electric field in this manner, the junction resistance of the power semiconductor element 100-4 can be reduced. This increases the electric field margin applied to the gate insulating layer 118 in the power semiconductor element 100-4, thereby improving the operational reliability of the power semiconductor element 100-4.

[0276] 42 to 45 are cross-sectional views showing power semiconductor elements 100a-4, 100b-4, 100c-4, and 100d-4 according to other embodiments of the present invention. The power semiconductor elements 100a-4, 100b-4, 100c-4, and 100d-4 are obtained by modifying or adding to part of the configuration of the power semiconductor element 100-4 shown in FIGS. 37 to 41, and therefore the embodiments may refer to each other, and redundant explanations will be omitted.

[0277] 42, the power semiconductor device 100a-4 may include at least one trench 138 that penetrates the second source region 112b and exposes the second well region 110b. The trench 138 may expose the surface of the second well region 110b or may be recessed to a predetermined depth in the second well region 110b. A well contact region 114a may be formed on at least the bottom surface of the trench 138 to contact the second well region 110b.

[0278] The source electrode layer 140 may be formed to fill the groove 138 and may be connected to the well contact region 114a, the second well region 110b, and / or the second source region 112b. This structure may increase the contact area between the source electrode layer 140 and the second well region 110b and the second source region 112b, thereby helping to reduce contact resistance therebetween.

[0279] In some embodiments, the well contact region 114a may be formed entirely on the surface of the second well region 110b exposed by the trench 138. Thus, the well contact region 114a may be formed on the second well region 110b exposed from the bottom and sidewalls of the trench 138. This structure of the well contact region 114a may serve to further reduce the contact resistance between the source electrode layer 140 and the second well region 110b.

[0280] 43, in the power semiconductor device 100b-4, the channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. The channel region 107b may have a first conductivity type such that an accumulation channel is formed.

[0281] For example, the channel region 107b may have the same doping type as the source region 112 and the drift region 107. In this case, the source region 112, the channel region 107b, and the drift region 107 are normally electrically connected. However, in the silicon carbide semiconductor layer 105, negative charges generated as carbon clusters form in the gate insulating layer 118 cause the bands in the channel region 107b to bend upward, forming a potential barrier. As a result, when an operating voltage is applied to the gate electrode layer 120, an accumulation channel that allows charge or current flow may be formed in the channel region 107b.

[0282] Therefore, the threshold voltage that must be applied to the gate electrode layer 120 to form an accumulation channel in the channel region 107b may be significantly lower than the threshold voltage that must be applied to the gate electrode layer 120 to form a normal inversion channel.

[0283] In some embodiments, channel region 107b may be part of drift region 107. More specifically, channel region 107b may be part of protruding portion 107a of drift region 107. For example, channel region 107b may be integrally formed with drift region 107.

[0284] The drift region 107 may be connected to the source region 112 via the channel region 107b. More specifically, the protruding portion 107a of the drift region 107 and the first source region 112a may contact each other at the channel region 107b.

[0285] For example, the doping concentration of the first conductivity type impurity in the channel region 107b may be the same as that in the other parts of the drift region 107, or may be different to adjust the threshold voltage.

[0286] In some embodiments, the first well region 110a may be formed below the first source region 112a, protruding further toward the protruding portion 107a of the drift region 107 than the first source region 112a. The channel region 107b may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the protruding portion 107a of the drift region 107 may further extend into a groove portion between the first well region 110a and the gate electrode layer 120, and the channel region 107b may be formed in this portion. This structure may allow the channel region 107b to be limited between the gate electrode layer 120 and the well region 110.

[0287] In some embodiments, the first well region 110a and the first source region 112a may have the same width, in which case the first source region 112a contacts the protruding portion 107a of the drift region 107, and the channel region 107b may be defined in the contact portion of the protruding portion 107a.

[0288] Referring to Figure 44, in the power semiconductor element 100c-4, the first well region 110a protrudes from the first source region 112a toward the protruding portion 107a of the drift region 107, and can include a tap portion at its end extending toward the gate electrode layer 120.

[0289] The channel region 107b1 may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the channel region 107b1 may be formed in a bent shape on the protruding portion and the tap portion of the first well region 110a. Such a structure may allow the channel region 107b1 to be further confined between the gate electrode layer 120 and the first well region 110a.

[0290] 45, in a power semiconductor device 100d-4, the first well region 110a protrudes from the first source region 112a toward the protruding portion 107a of the drift region 107 and may include a tap portion at its end. Furthermore, the protruding portion 107a of the drift region 107 may further extend between the bottom of the first source region 112a and the first well region 110a.

[0291] The channel region 107b2 may be formed to extend further into the semiconductor layer 105 between the lower portion of the first source region 112a and the first well region 110a. For example, the channel region 107b2 may be formed in a bent shape from above the tap portion of the first well region 110a to the lower portion of the first source region 112a. Such a structure may contribute to increasing the contact area between the channel region 107b2 and the first source region 112a.

[0292] 46 to 48 are schematic perspective views illustrating a method for manufacturing a power semiconductor device 100-4 according to one embodiment of the present invention. Referring to FIG. 46, a drift region 107 having a first conductivity type may be formed in a silicon carbide (SiC) semiconductor layer 105 to provide a vertical transfer path for charges. For example, the drift region 107 may be formed on a drain region 102 having the first conductivity type. In some embodiments, the drain region 102 may be provided as a substrate of the first conductivity type, and the drift region 107 may be formed of one or more epitaxial layers on such a substrate.

[0293] Next, a well region 110 having the second conductivity type can be formed in the semiconductor layer 105 so as to be in contact with at least a portion of the drift region 107. For example, the step of forming the well region 110 can be performed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0294] More specifically, the well region 110 may be formed in the semiconductor layer 105 in contact with the protruding portion 107a so as to define at least one protruding portion 107a of the drift region 107. More specifically, the well region 110 may be formed by doping the drift region 107 or the semiconductor layer 105 with an impurity opposite to that of the drift region 107.

[0295] The well region 110 may be divided into a first well region 110a below the gate electrode layer 120 and a second well region 110b outside the gate electrode layer 120. For example, the first well region 110a defines the protruding portion 107a of the drift region 107, and a well contact region 114 may be subsequently formed in the second well region 110b. The first well region 110a and the second well region 110b may be connected to each other.

[0296] The deep well region 111 may be formed in the semiconductor layer 105 below the well region 110, in contact with the well region 110 and the drift region. The deep well region 111 may be opposite to the drift region 107 and have the same second conductivity type as the well region 110. For example, the deep well region 111 may be formed by implanting impurities of the second conductivity type into the semiconductor layer 105 or the drift region 107.

[0297] Furthermore, a source region 112 having the first conductivity type may be formed on or in the well region 110. For example, the step of forming the source region 112 may be performed by implanting impurities of the first conductivity type into the well region 110 or into the semiconductor layer 105.

[0298] For example, the step of forming the source region 112 may include forming a first source region 112a on or in the first well region 110a and forming a second source region 112b on or in the second well region 110b. A portion of the second source region 112b may be assigned to a source contact region 112b1 connected to the source electrode layer 140. The first source region 112a and the second source region 112b may be connected to each other. The source region 112 may be formed at a predetermined depth within or above the well region 110, substantially from the surface of the semiconductor layer 105.

[0299] Simultaneously with the formation of the source region 112, a channel region 110c having the second conductivity type may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107 so that an inversion channel is formed. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. For example, the channel region 110c may not be formed separately as part of the first well region 110a, but may be formed together with the first well region 110a.

[0300] Optionally, a well contact region 114 extending from the second well region 110b through the second source region 112b can be formed in the second source region 112b. For example, the well contact region 114 can be formed by implanting a second conductivity type impurity into a part of the well region 110 at a higher concentration than the well region 110.

[0301] In a variation of this embodiment, the doping order of the impurities in the well region 110, the deep well region 111, the source region 112, the channel region 110c, and the well contact region 114 may be changed appropriately.

[0302] In the above-described manufacturing method, the implantation or doping of impurities can be performed by ion-implanting impurities into the semiconductor layer 105 or by incorporating impurities into the epitaxial layer during formation. However, implantation of impurities into selective regions can be performed using an ion implantation method using a mask pattern. Optionally, the ion implantation can be followed by a heat treatment step to activate or diffuse the impurities.

[0303] 47, a gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c and the protruding portion 107a of the drift region 107.

[0304] For example, the gate insulating layer 118 may be formed as an oxide by oxidizing the semiconductor layer 105, or may be formed by depositing an insulating material such as an oxide or nitride on the semiconductor layer 105.

[0305] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0306] The patterning process can be performed using photolithography and etching processes. The photolithography process includes forming a photoresist pattern as a mask layer using a photolithography process and a development process, and the etching process includes selectively etching the underlying structure using the photoresist pattern.

[0307] 48, an interlayer insulating layer 130 may be formed on the gate electrode layer 120. Optionally, if the interlayer insulating layer 130 is formed entirely on the underlying structure, a process of forming contact hole patterns to expose the source contact region 112b1 and the well contact region 114 may follow.

[0308] Then, a source electrode layer 140 may be formed on the semiconductor layer 105 to be connected to the second source region 112b and the well contact region 114. For example, the source electrode layer 140 may be formed by forming a conductive layer, for example, a metal layer, on the interlayer insulating layer 130 and then patterning or planarizing the conductive layer.

[0309] On the other hand, the power semiconductor element 100a-4 of FIG. 42 can be manufactured by adding or modifying some steps in the manufacturing process for the power semiconductor element 100-4 described above.

[0310] The manufacturing of the power semiconductor element 100a-4 of FIG. 42 can include the steps of forming at least one trench 138 in the second source region 112b, penetrating the second source region 112b and exposing the second well region 110b, forming a well contact region 114 at the bottom of the trench 138 so as to contact the well region 110b, and forming a source electrode layer 140 so as to fill the trench 138 and connect to the source region 112b and the well contact region 114.

[0311] 43 to 45, the channel regions 107b, 107b1, and 107b2 may be formed to have the first conductivity type so as to form an accumulation channel. For example, the channel regions 107b, 107b1, and 107b2 may be formed as part of the drift region 107.

[0312] According to the above-described manufacturing method, the semiconductor layer 105 is made of silicon carbide, and the highly integrated power semiconductor element 100-4 can be manufactured economically using the same processes as those used for existing silicon substrates.

[0313] Figure 49 is a schematic oblique view showing a power semiconductor element 100-5 according to one embodiment of the present invention, Figure 50 is a plan view showing the power semiconductor element 100-5 cut along line II-II in Figure 49, Figure 51 is a cross-sectional view showing the power semiconductor element 100-5 cut along line III-III in Figure 50, Figure 52 is a cross-sectional view showing the power semiconductor element 100-5 cut along line IV-IV in Figure 50, and Figure 53 is a cross-sectional view showing the power semiconductor element 100-5 cut along line VV in Figure 50.

[0314] 49 to 53, the power semiconductor device 100-5 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-5 may have a power MOSFET structure.

[0315] The semiconductor layer 105 can refer to one or more layers of semiconductor material, such as one or more epitaxial layers, and can also refer to one or more epitaxial layers on a semiconductor substrate.

[0316] For example, the semiconductor layer 105 may be made of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0317] Silicon carbide (SiC) has a wider band gap than silicon, and therefore can maintain stability at higher temperatures than silicon. Furthermore, silicon carbide has a much higher breakdown field than silicon, and therefore can operate stably even at high voltages. Therefore, the power semiconductor element 100-5 using silicon carbide as the semiconductor layer 105 has a higher breakdown voltage than silicon, while also having excellent heat dissipation characteristics, and can exhibit stable operating characteristics even at high temperatures.

[0318] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type into a silicon carbide epitaxial layer.

[0319] The drift region 107 can provide a vertical transfer path for charges. Furthermore, the drift region 107 can include at least one protruding portion 107a disposed under the gate electrode layer 120. The protruding portion 107a can extend substantially above the surface of the semiconductor layer 105.

[0320] The well region 110 may be formed in the semiconductor layer 105 to contact at least a portion of the drift region 107 and may have a second conductivity type. For example, the well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type in the semiconductor layer 105 or the drift region 107.

[0321] For example, the well region 110 may include a first well region 110a formed in the semiconductor layer 105 below the gate electrode layer 120 and in contact with the protruding portion 107a of the drift region 107, and a second well region 110b formed in the semiconductor layer 105 outside the gate electrode layer 120. The first well region 110a and the second well region 110b may be connected to each other. Essentially, the lower portion of the protruding portion 107a of the drift region 107 may be defined by the first well region 110a, and more specifically, may be in contact with a sidewall of the first well region 110a.

[0322] The source region 112 may be formed on or in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping the semiconductor layer 105 or the well region 110 with impurities of the first conductivity type. The source region 112 may be doped with impurities of the first conductivity type at a higher concentration than the drift region 107.

[0323] For example, the source region 112 may include a first source region 112a formed on the first well region 110a and a second source region 112b formed on the second well region 110b. The first source region 112a and the second source region 112b may be connected to each other. The first source region 112a may be disposed under the gate electrode layer 120, and the second source region 112b may be disposed outside the gate electrode layer 120.

[0324] The second source region 112b may include a source contact region 112b1 outside the gate electrode layer 120 and connected to the source electrode layer 140. For example, the source contact region 112b1 may refer to a portion of the second source region 112b to which the source electrode layer 140 is connected.

[0325] The well contact region 114 may be formed in the second source region 112b, more specifically, in the source contact region 112b1. For example, the well contact region 114 may extend from the second well region 110b through the second source region 112b and have the second conductivity type. One or more well contact regions 114 may be formed in the source contact region 112b1.

[0326] The well contact region 114 may be connected to the source electrode layer 140, and may be doped with a second conductivity type impurity at a higher concentration than the well region 110 in order to reduce contact resistance when connected to the source electrode layer 140.

[0327] The channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. The channel region 107b may have a first conductivity type such that an accumulation channel is formed.

[0328] For example, the channel region 107b may have the same doping type as the source region 112 and the drift region 107. In this case, the source region 112, the channel region 107b, and the drift region 107 are normally electrically connected. However, in the silicon carbide semiconductor layer 105, negative charges generated as carbon clusters form in the gate insulating layer 118 cause the bands in the channel region 107b to bend upward, forming a potential barrier. As a result, when an operating voltage is applied to the gate electrode layer 120, an accumulation channel that allows charge or current flow may be formed in the channel region 107b.

[0329] Therefore, the threshold voltage that must be applied to the gate electrode layer 120 to form an accumulation channel in the channel region 107b may be significantly lower than the threshold voltage that must be applied to the gate electrode layer 120 to form a normal inversion channel.

[0330] In some embodiments, channel region 107b may be part of drift region 107. More specifically, channel region 107b may be part of protruding portion 107a of drift region 107. For example, channel region 107b may be integrally formed with drift region 107.

[0331] The drift region 107 may be connected to the source region 112 via the channel region 107b. More specifically, the protruding portion 107a of the drift region 107 and the first source region 112a may contact each other at the channel region 107b.

[0332] For example, the doping concentration of the first conductivity type impurity in the channel region 107b may be the same as that in the other parts of the drift region 107, or may be different to adjust the threshold voltage.

[0333] In some embodiments, the first well region 110a may be formed below the first source region 112a, protruding further toward the protruding portion 107a of the drift region 107 than the first source region 112a. The channel region 107b may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the protruding portion 107a of the drift region 107 may further extend into a groove portion between the first well region 110a and the gate electrode layer 120, and the channel region 107b may be formed in this portion. This structure may allow the channel region 107b to be limited between the gate electrode layer 120 and the well region 110.

[0334] In some embodiments, the first well region 110a and the first source region 112a may have the same width, in which case the first source region 112a contacts the protruding portion 107a of the drift region 107, and the channel region 107b may be defined in the contact portion of the protruding portion 107a.

[0335] In some embodiments, the protruding portion 107a of the drift region 107, the first well region 110a, the channel region 107b, and / or the first source region 112a may extend in one direction. For example, the direction of line IV-IV or line VV in FIG. 50 may be the one direction. Here, the extension direction of the channel region 107b does not refer to the direction of charge movement.

[0336] In some embodiments, the first well region 110a, the channel region 107b, and the first source region 112a may be formed symmetrically around the protruding portion 107a of the drift region 107. For example, the first well region 110a, the channel region 107b, and the first source region 112a may be formed in the semiconductor layer 105 on both sides of the protruding portion 107a of the drift region 107, respectively.

[0337] In some embodiments, the drift region 107 may include a plurality of protruding portions 107a arranged in one direction. For example, the first well region 110a may be formed in a striped pattern extending in one direction, and the protruding portions 107a may also be formed in a striped pattern.

[0338] The first source region 112a may be formed in a stripe pattern on the first well region 110a, and the channel region 107b may be formed between the protruding portion 107a and the first source region 112a.

[0339] In some embodiments, the first well region 110a may be formed symmetrically with respect to the second well region 110b, and the first source region 112a may be formed symmetrically with respect to the second source region 112b. In this case, the protruding portion 107a and the channel region 107b of the drift region 107 may be formed symmetrically with respect to the second well region 110b or the second source region 112b.

[0340] Furthermore, the first well regions 110a and the second well regions 110b may be alternately and repeatedly formed in one direction, and in this case, the first source regions 112a and the second source regions 112b may also be repeatedly formed.

[0341] Additionally, a drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be more highly doped than the drift region 107.

[0342] In some embodiments, the drain region 102 may be provided as a silicon carbide substrate having the first conductivity type, in which case the drain region 102 may be understood as part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105.

[0343] The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 107b. More specifically, the gate insulating layer 118 may be formed on the first source region 112a, the channel region 107b, and the protruding portion 107a of the drift region 107.

[0344] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, oxide of silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stacked structure thereof.

[0345] At least one gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed on at least the channel region 107b. More specifically, the gate electrode layer 120 may be formed on the first source region 112a, the channel region 107b, and the protruding portion 107a of the drift region 107. Furthermore, the second well region 110b, the second source region 112b, and the well contact region 114 may be disposed outside the gate electrode layer 120 and may be exposed from the gate electrode layer 120.

[0346] For example, the gate electrode layer 120 may include a suitable conductive material, such as polysilicon, a metal, a metal nitride, a metal silicide, or a stacked structure thereof.

[0347] An interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include an insulator, such as an oxide layer, a nitride layer, or a laminated structure thereof, as appropriate.

[0348] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112, more specifically, the second source region 112b or the source contact region 112b1. Furthermore, the source electrode layer 140 may be commonly connected to the second source region 112b and the well contact region 114. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, etc.

[0349] In the above-described power semiconductor element 100-5, the first conductivity type and the second conductivity type are opposite to each other, but may be either n-type or p-type. For example, if the first conductivity type is n-type, the second conductivity type may be p-type, or vice versa.

[0350] More specifically, if the power semiconductor element 100-5 is an N-type mosfet, the drift region 107 and the channel region 107b may be N-regions, the source region 112 and the drain region 102 may be N+regions, the well region 110 may be a P-region, and the well contact region 114 may be a P+region.

[0351] During operation of the power semiconductor device 100-5, current can flow generally vertically from the drain region 102 along the protruding portion 107a of the drift region 107 and then through the channel region 107b to the source region 112.

[0352] In the above-described power semiconductor device 100-5, the source contact region 112b1 and the well contact region 114 may be separately disposed outside the gate electrode layer 120. Therefore, the first well region 110a and the first source region 112a may be formed so that the protruding portions 107a of the drift region 107 are densely arranged, and thus the channel region 107b may be densely formed below the gate electrode layer 120. Therefore, the power semiconductor device 100-5 may have a high degree of integration.

[0353] 54 to 56 are cross-sectional views showing power semiconductor elements 100a-5, 100b-5, and 100c-5 according to other embodiments of the present invention. The power semiconductor elements 100a-5, 100b-5, and 100c-5 are obtained by modifying or adding to part of the configuration of the power semiconductor element 100-5 shown in FIGS. 49 to 53, and therefore the embodiments may refer to each other, and redundant explanations will be omitted.

[0354] 54, the power semiconductor device 100a-5 may include at least one trench 138 formed to penetrate the second source region 112b and recessed to a predetermined depth in the second well region 110b. A well contact region 114a may be formed on at least a bottom surface of the trench 138 so as to contact the second well region 110b.

[0355] The source electrode layer 140 may be formed to fill the groove 138 and may be connected to the well contact region 114a, the second well region 110b, and / or the second source region 112b. This structure may increase the contact area between the source electrode layer 140 and the second well region 110b and the second source region 112b, thereby helping to reduce contact resistance therebetween.

[0356] In some embodiments, the well contact region 114a may be formed entirely on the surface of the second well region 110b exposed by the trench 138. Thus, the well contact region 114a may be formed on the second well region 110b exposed from the bottom and sidewalls of the trench 138. This structure of the well contact region 114a may serve to further reduce the contact resistance between the source electrode layer 140 and the second well region 110b.

[0357] 55, in the power semiconductor device 100b-5, the first well region 110a protrudes from the first source region 112a toward the protruding portion 107a of the drift region 107 and may further include a tap portion at its end extending toward the gate electrode layer 120. The channel region 107b1 may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the channel region 107b1 may be formed in a bent shape on the protruding portion and tap portion of the first well region 110a. This structure may allow the channel region 107b1 to be further confined between the gate electrode layer 120 and the first well region 110a.

[0358] 56, in a power semiconductor device 100c-5, the first well region 110a protrudes from the first source region 112a toward the protruding portion 107a of the drift region 107 and may include a tap portion at its end. Furthermore, the protruding portion 107a of the drift region 107 may extend further between the bottom of the first source region 112a and the first well region 110a.

[0359] The channel region 107b2 may be formed to extend further into the semiconductor layer 105 between the lower portion of the first source region 112a and the first well region 110a. For example, the channel region 107b2 may be formed in a bent shape from above the tap portion of the first well region 110a to the lower portion of the first source region 112a. Such a structure may contribute to increasing the contact area between the channel region 107b2 and the first source region 112a.

[0360] 57 to 59 are schematic perspective views illustrating a method for manufacturing a power semiconductor device 100-5 according to one embodiment of the present invention. Referring to FIG. 57, a drift region 107 having a first conductivity type may be formed in a silicon carbide (SiC) semiconductor layer 105 to provide a vertical transfer path for charges. For example, the drift region 107 may be formed on a drain region 102 having the first conductivity type. In some embodiments, the drain region 102 may be provided as a substrate of the first conductivity type, and the drift region 107 may be formed of one or more epitaxial layers on such a substrate.

[0361] Next, a well region 110 having the second conductivity type can be formed in the semiconductor layer 105 so as to be in contact with at least a portion of the drift region 107. For example, the step of forming the well region 110 can be performed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0362] More specifically, the well region 110 may be formed in the semiconductor layer 105 in contact with the protruding portion 107a so as to define at least one protruding portion 107a of the drift region 107. More specifically, the well region 110 may be formed by doping the drift region 107 or the semiconductor layer 105 with an impurity opposite to that of the drift region 107.

[0363] The well region 110 may be divided into a first well region 110a below the gate electrode layer 120 and a second well region 110b outside the gate electrode layer 120. For example, the first well region 110a defines the protruding portion 107a of the drift region 107, and a well contact region 114 may be subsequently formed in the second well region 110b. The first well region 110a and the second well region 110b may be connected to each other.

[0364] Furthermore, a source region 112 having the first conductivity type may be formed on or in the well region 110. For example, the step of forming the source region 112 may be performed by implanting impurities of the first conductivity type into the well region 110 or into the semiconductor layer 105.

[0365] For example, the step of forming the source region 112 may include forming a first source region 112a on the first well region 110a and a second source region 112b on the second well region 110b. A portion of the second source region 112b may be allocated to a source contact region 112b1 connected to the source electrode layer 140. The first source region 112a and the second source region 112b may be connected to each other. The source region 112 may be formed at a predetermined depth within or on the well region 110 substantially from the surface of the semiconductor layer 105.

[0366] Simultaneously with the formation of the source region 112, a channel region 107b having the first conductivity type may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107 so that an accumulation channel is formed. For example, the channel region 107b may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. For example, the channel region 107b may not be formed separately from the drift region 107, e.g., as part of the protruding portion 107a, but may be formed together with the drift region 107.

[0367] Optionally, a well contact region 114 extending from the second well region 110b through the second source region 112b can be formed in the second source region 112b. For example, the well contact region 114 can be formed by implanting a second conductivity type impurity into a part of the well region 110 at a higher concentration than the well region 110.

[0368] In a variation of this embodiment, the doping order of the well region 110, the source region 112, the channel region 107b, and the well contact region 114 may be changed appropriately.

[0369] In the above-described manufacturing method, the implantation or doping of impurities can be performed by ion-implanting impurities into the semiconductor layer 105 or by incorporating impurities into the epitaxial layer during formation. However, implantation of impurities into selective regions can be performed using an ion implantation method using a mask pattern. Optionally, the ion implantation can be followed by a heat treatment step to activate or diffuse the impurities.

[0370] 58, a gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 107b and the protruding portion 107a of the drift region 107.

[0371] For example, the gate insulating layer 118 may be formed as an oxide by oxidizing the semiconductor layer 105, or may be formed by depositing an insulating material such as an oxide or nitride on the semiconductor layer 105.

[0372] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0373] The patterning process can be performed using photolithography and etching processes. The photolithography process includes forming a photoresist pattern as a mask layer using a photolithography process and a development process, and the etching process includes selectively etching the underlying structure using the photoresist pattern.

[0374] 59, an interlayer insulating layer 130 may be formed on the gate electrode layer 120. Optionally, when the interlayer insulating layer 130 is formed entirely on the lower structure, a process of forming contact hole patterns to expose the source contact region 112b1 and the well contact region 114 may follow.

[0375] Then, a source electrode layer 140 may be formed on the semiconductor layer 105 to be connected to the second source region 112b and the well contact region 114. For example, the source electrode layer 140 may be formed by forming a conductive layer, for example, a metal layer, on the interlayer insulating layer 130 and then patterning or planarizing the conductive layer.

[0376] On the other hand, the power semiconductor element 100a-5 of FIG. 54 can be manufactured by adding or modifying some steps in the manufacturing process for the power semiconductor element 100-5 described above.

[0377] The manufacturing of the power semiconductor element 100a-5 of FIG. 54 can include the additional steps of forming at least one trench 138 in the second source region 112b so as to penetrate the second source region 112b and recess into the second well region 110b, forming a well contact region 114 at the bottom of the trench 138 so as to contact the well region 110b, and forming a source electrode layer 140 so as to fill the trench 138 and connect to the source region 112b and the well contact region 114.

[0378] According to the above-described manufacturing method, the semiconductor layer 105 is made of silicon carbide, and the highly integrated power semiconductor element 100-5 can be manufactured economically using the same processes as those used for existing silicon substrates.

[0379] Figure 60 is a schematic oblique view showing a power semiconductor element 100-6 according to one embodiment of the present invention, Figure 61 is a plan view showing the power semiconductor element 100-6 cut along line II-II in Figure 60, Figure 62 is a cross-sectional view showing the power semiconductor element 100-6 cut along line III-III in Figure 61, Figure 63 is a cross-sectional view showing the power semiconductor element 100-6 cut along line IV-IV in Figure 61, and Figure 64 is a cross-sectional view showing the power semiconductor element 100-6 cut along line VV in Figure 61.

[0380] 60 to 64, the power semiconductor device 100-6 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-6 may have a power MOSFET structure.

[0381] The semiconductor layer 105 can refer to one or more layers of semiconductor material, such as one or more epitaxial layers, and can also refer to one or more epitaxial layers on a semiconductor substrate.

[0382] For example, the semiconductor layer 105 may be made of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0383] Silicon carbide (SiC) has a wider band gap than silicon, and therefore can maintain stability at higher temperatures than silicon. Furthermore, silicon carbide has a much higher breakdown field than silicon, and therefore can operate stably even at high voltages. Therefore, the power semiconductor element 100-6 using silicon carbide as the semiconductor layer 105 has a higher breakdown voltage than silicon, while also having excellent heat dissipation characteristics, and can exhibit stable operating characteristics even at high temperatures.

[0384] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type into a silicon carbide epitaxial layer.

[0385] The drift region 107 can provide a vertical transfer path for charges. Furthermore, the drift region 107 can include at least one protruding portion 107a disposed under the gate electrode layer 120. The protruding portion 107a can extend substantially above the surface of the semiconductor layer 105.

[0386] The well region 110 may be formed in the semiconductor layer 105 to contact at least a portion of the drift region 107 and may have a second conductivity type. For example, the well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type in the semiconductor layer 105 or the drift region 107.

[0387] For example, the well region 110 may include a first well region 110a formed in the semiconductor layer 105 below the gate electrode layer 120 and in contact with the protruding portion 107a of the drift region 107, and a second well region 110b formed in the semiconductor layer 105 outside the gate electrode layer 120. The first well region 110a and the second well region 110b may be connected to each other. Essentially, the lower portion of the protruding portion 107a of the drift region 107 may be defined by the first well region 110a, and more specifically, may be in contact with a sidewall of the first well region 110a.

[0388] The source region 112 may be formed on or in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping the semiconductor layer 105 or the well region 110 with impurities of the first conductivity type. The source region 112 may be doped with impurities of the first conductivity type at a higher concentration than the drift region 107.

[0389] For example, the source region 112 may include a first source region 112a formed on the first well region 110a and a second source region 112b formed on the second well region 110b. The first source region 112a and the second source region 112b may be connected to each other. The first source region 112a may be disposed under the gate electrode layer 120, and the second source region 112b may be disposed outside the gate electrode layer 120.

[0390] The second source region 112b may include a source contact region 112b1 outside the gate electrode layer 120 and connected to the source electrode layer 140. For example, the source contact region 112b1 may refer to a portion of the second source region 112b to which the source electrode layer 140 is connected.

[0391] The well contact region 114 may be formed in the second source region 112b, more specifically, in the source contact region 112b1. For example, the well contact region 114 may extend from the second well region 110b through the second source region 112b and have the second conductivity type. One or more well contact regions 114 may be formed in the source contact region 112b1.

[0392] The well contact region 114 may be connected to the source electrode layer 140, and may be doped with a second conductivity type impurity at a higher concentration than the well region 110 in order to reduce contact resistance when connected to the source electrode layer 140.

[0393] In some embodiments, within the source contact region 112b1, at least a portion of the second well region 110b can be exposed from the second source region 112b. A portion 107c of the drift region 107 can be exposed to the surface of the semiconductor layer 105 through the portion of the second well region 110b exposed from the second source region 112b. This allows the portion 107c of the drift region 107 to be separated from the second source region 112b by the portion of the second well region 110b.

[0394] The channel region 110c may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a.

[0395] For example, the channel region 110c can have the second conductivity type such that an inversion channel is formed. Because the channel region 110c has an opposite doping type to the source region 112 and the drift region 107, the channel region 110c can form a diode junction with the source region 112 and the drift region 107. Thus, although the channel region 110c does not allow charge transfer under normal circumstances, when an operating voltage is applied to the gate electrode layer 120, an inversion channel is formed therein, allowing charge transfer.

[0396] For example, the channel region 110c may be a part of the well region 110. More specifically, the channel region 110c may be a part of the well region 110 adjacent to the bottom of the gate electrode layer 120. In this case, the channel region 110c may be formed integrally or continuously connected to the well region 110. The doping concentration of the second conductive type impurity in the channel region 110c may be the same as that in other parts of the well region 110 or may be different to adjust the threshold voltage.

[0397] In some embodiments, the protruding portion 107a of the drift region 107, the first well region 110a, the channel region 110c, and / or the first source region 112a may extend in one direction, where the extension direction of the channel region 110c does not imply a direction of charge movement.

[0398] In some embodiments, the first well region 110a, the channel region 110c, and the first source region 112a may be formed symmetrically around the protruding portion 107a of the drift region 107. For example, the first well region 110a, the channel region 110c, and the first source region 112a may be formed in the semiconductor layer 105 on both sides of the protruding portion 107a of the drift region 107, respectively.

[0399] In some embodiments, the drift region 107 may include a plurality of protruding portions 107a arranged in one direction. For example, the first well region 110a may be formed in a striped pattern extending in one direction, and the protruding portions 107a may also be formed in a striped pattern. The first source region 112a may be formed in a striped pattern on the first well region 110a. The channel region 110c may be formed between the protruding portions 107a of the drift region 107 and the first source region 112a.

[0400] In some embodiments, the first well region 110a may be formed symmetrically with respect to the second well region 110b, and the first source region 112a may be formed symmetrically with respect to the second source region 112b. In this case, the protruding portion 107a of the drift region 107 may include a plurality of protruding portions 107a formed symmetrically with respect to the second well region 110b or the second source region 112b.

[0401] Furthermore, the first well regions 110a and the second well regions 110b may be alternately and repeatedly formed in one direction, and in this case, the first source regions 112a and the second source regions 112b may also be repeatedly formed.

[0402] Additionally, a drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have the first conductivity type. For example, the drain region 102 may be more highly doped than the drift region 107.

[0403] In some embodiments, the drain region 102 may be provided as a silicon carbide substrate having the first conductivity type, in which case the drain region 102 may be understood as part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105.

[0404] The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c. More specifically, the gate insulating layer 118 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107.

[0405] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, oxide of silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stacked structure thereof.

[0406] At least one gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed on at least the channel region 110c. More specifically, the gate electrode layer 120 may be formed on the first source region 112a, the channel region 110c, and the protruding portion 107a of the drift region 107. The second well region 110b, the second source region 112b, and the well contact region 114 may be disposed outside the gate electrode layer 120 and may be exposed from the gate electrode layer 120.

[0407] For example, the gate electrode layer 120 may include a suitable conductive material, such as polysilicon, a metal, a metal nitride, a metal silicide, or a stacked structure thereof.

[0408] An interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include an insulator, such as an oxide layer, a nitride layer, or a laminated structure thereof, as appropriate.

[0409] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and connected to the source region 112, more specifically, the second source region 112b or the source contact region 112b1. The source electrode layer 140 may also be connected to the well contact region 114.

[0410] Furthermore, the source electrode layer 140 can be in contact with the portion 107c of the drift region 107 to form a Schottky barrier diode (SBD). For example, the source electrode layer 140 can be in contact with the portion 107c of the drift region 107 exposed from the second well region 110bd at the surface of the semiconductor layer 105. The Schottky barrier diode (SBD) can refer to a diode that uses a Schottky barrier created by a junction between a metal and a semiconductor.

[0411] In addition to the Schottky barrier diode (SBD), a body diode may be formed parasitically in the power semiconductor device 100-6. For example, a body diode may be formed between the well region 110 and the drift region 107. Such a body diode may be one of PN diodes formed by joining semiconductors of different polarities.

[0412] As shown in FIG. 73, it can be seen that the Schottky barrier diode (SBD) has a lower forward voltage (VF) and faster switching characteristics than the PN diode.

[0413] Such a Schottky barrier diode (SBD) can reduce switching losses together with the body diode during operation of the power semiconductor device 100-6. For example, the Schottky barrier diode (SBD) and the body diode can function as a freewheeling diode during operation of the power semiconductor device 100-6.

[0414] In some embodiments, the source electrode layer 140 can be in common contact with the second source region 112b, the well contact region 114, and the portion 107c of the drift region 107. For example, the source electrode layer 140 can be formed of a suitable conductive material, such as a metal.

[0415] In the above-described power semiconductor element 100-6, the first conductivity type and the second conductivity type are opposite to each other, but may be either n-type or p-type. For example, if the first conductivity type is n-type, the second conductivity type may be p-type, or vice versa.

[0416] More specifically, if the power semiconductor element 100-6 is an N-type mosfet, the drift region 107 may be an N-region, the source region 112 and the drain region 102 may be N+regions, the well region 110 and the channel region 110c may be P-regions, and the well contact region 114 may be a P+region.

[0417] During operation of the power semiconductor device 100-6, current can flow generally vertically from the drain region 102 along the protruding portion 107a of the drift region 107 and then through the channel region 110c to the source region 112.

[0418] In the above-described power semiconductor device 100-6, the source contact region 112b1 and the well contact region 114 may be separately disposed outside the gate electrode layer 120. Therefore, the first well region 110a and the first source region 112a may be formed so that the protruding portions 107a of the drift region 107 are densely arranged, and thus the channel region 110c may be densely formed below the gate electrode layer 120. Therefore, the power semiconductor device 100-6 may have a high degree of integration.

[0419] Figures 65 and 66 are cross-sectional views showing a power semiconductor device 100a-6 according to another embodiment of the present invention. The power semiconductor device 100a-6 is obtained by modifying or adding to part of the configuration of the power semiconductor device 100-6 of Figures 60 to 64, and therefore the embodiments may refer to each other and redundant explanations will be omitted.

[0420] 65 and 66, the power semiconductor device 100a-6 may include at least one groove 138 formed by partially etching a portion of the second well region 110b exposed from the second source region 112b and a portion 107c of the drift region 107. The groove 138 may expose the surface of the second well region 110b or may be recessed to a predetermined depth in the second well region 110b. A well contact region 114a may be formed on at least a bottom surface of the groove 138 on a portion of the second well region 110b.

[0421] The source electrode layer 140 may be formed to fill the groove 138 and may be connected to the well contact region 114a and the second source region 112b within the groove 138. Furthermore, the source electrode layer 140 may be in contact with the portion 107c of the drift region 107 within the groove 138 to form a Schottky barrier diode. For example, the source electrode layer 140 may be in contact with the portion 107c of the drift region 107 at the bottom of the groove 138. Such a recess structure may increase the contact area between the source electrode layer 140 and the second source region 112b and the well contact region 114a, thereby helping to reduce the contact resistance therebetween.

[0422] In some embodiments, the well contact region 114a may be formed entirely on the surface of the second well region 110b exposed by the trench 138. Thus, the well contact region 114a may be formed on the second well region 110b exposed from the bottom and sidewalls of the trench 138. This structure of the well contact region 114a may serve to further reduce the contact resistance between the source electrode layer 140 and the second well region 110b.

[0423] 67 to 69 are cross-sectional views showing power semiconductor elements 100b-6, 100c-6, and 100d-6 according to other embodiments of the present invention. The power semiconductor elements 100b-6, 100c-6, and 100d-6 are obtained by modifying or adding to part of the configuration of the power semiconductor element 100-6 shown in FIGS. 60 to 64, and therefore the embodiments may refer to each other and redundant explanations will be omitted.

[0424] 67, in the power semiconductor device 100b-6, the channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. The channel region 107b may have a first conductivity type such that an accumulation channel is formed.

[0425] For example, the channel region 107b may have the same doping type as the source region 112 and the drift region 107. In this case, the source region 112, the channel region 107b, and the drift region 107 are normally electrically connected. However, in the silicon carbide semiconductor layer 105, negative charges generated as carbon clusters form in the gate insulating layer 118 cause the bands in the channel region 107b to bend upward, forming a potential barrier. As a result, when an operating voltage is applied to the gate electrode layer 120, an accumulation channel that allows charge or current flow may be formed in the channel region 107b.

[0426] Therefore, the threshold voltage that must be applied to the gate electrode layer 120 to form an accumulation channel in the channel region 107b may be significantly lower than the threshold voltage that must be applied to the gate electrode layer 120 to form a normal inversion channel.

[0427] In some embodiments, channel region 107b may be part of drift region 107. More specifically, channel region 107b may be part of protruding portion 107a of drift region 107. For example, channel region 107b may be integrally formed with drift region 107.

[0428] The drift region 107 may be connected to the source region 112 via the channel region 107b. More specifically, the protruding portion 107a of the drift region 107 and the first source region 112a may contact each other at the channel region 107b.

[0429] For example, the doping concentration of the first conductivity type impurity in the channel region 107b may be the same as that in the other parts of the drift region 107, or may be different to adjust the threshold voltage.

[0430] In some embodiments, the first well region 110a may be formed below the first source region 112a, protruding further toward the protruding portion 107a of the drift region 107 than the first source region 112a. The channel region 107b may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the protruding portion 107a of the drift region 107 may further extend into a groove portion between the first well region 110a and the gate electrode layer 120, and the channel region 107b may be formed in this portion. This structure may allow the channel region 107b to be limited between the gate electrode layer 120 and the well region 110.

[0431] In some embodiments, the first well region 110a and the first source region 112a may have the same width, in which case the first source region 112a contacts the protruding portion 107a of the drift region 107, and the channel region 107b may be defined in the contact portion of the protruding portion 107a.

[0432] Referring to Figure 68, in the power semiconductor element 100c-6, the first well region 110a protrudes from the first source region 112a toward the protruding portion 107a of the drift region 107, and can include a tap portion at its end extending toward the gate electrode layer 120.

[0433] The channel region 107b1 may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the channel region 107b1 may be formed in a bent shape on the protruding portion and the tap portion of the first well region 110a. Such a structure may allow the channel region 107b1 to be further confined between the gate electrode layer 120 and the first well region 110a.

[0434] 69, in a power semiconductor device 100d-6, the first well region 110a protrudes from the first source region 112a toward the protruding portion 107a of the drift region 107 and may include a tap portion at its end. Furthermore, the protruding portion 107a of the drift region 107 may extend further between the lower portion of the first source region 112a and the first well region 110a.

[0435] The channel region 107b2 may be formed to extend further into the semiconductor layer 105 between the lower portion of the first source region 112a and the first well region 110a. For example, the channel region 107b2 may be formed in a bent shape from above the tap portion of the first well region 110a to the lower portion of the first source region 112a. Such a structure may contribute to increasing the contact area between the channel region 107b2 and the first source region 112a.

[0436] 70 to 72 are schematic perspective views illustrating a method for manufacturing a power semiconductor device 100-6 according to one embodiment of the present invention. Referring to FIG. 70, a drift region 107 having a first conductivity type may be formed in a silicon carbide (SiC) semiconductor layer 105 to provide a vertical transfer path for charges. For example, the drift region 107 may be formed on a drain region 102 having the first conductivity type. In some embodiments, the drain region 102 may be provided as a substrate of the first conductivity type, and the drift region 107 may be formed of one or more epitaxial layers on such a substrate.

[0437] Next, a well region 110 having the second conductivity type can be formed in the semiconductor layer 105 so as to be in contact with at least a portion of the drift region 107. For example, the step of forming the well region 110 can be performed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0438] More specifically, the well region 110 may be formed in the semiconductor layer 105 in contact with the protruding portion 107a so as to define at least one protruding portion 107a of the drift region 107. More specifically, the well region 110 may be formed by doping the drift region 107 or the semiconductor layer 105 with an impurity opposite to that of the drift region 107.

[0439] The well region 110 may be divided into a first well region 110a below the gate electrode layer 120 and a second well region 110b outside the gate electrode layer 120. For example, the first well region 110a defines the protruding portion 107a of the drift region 107, and a well contact region 114 may be subsequently formed in the second well region 110b. The first well region 110a and the second well region 110b may be connected to each other.

[0440] Furthermore, a source region 112 having the first conductivity type may be formed on or in the well region 110. For example, the step of forming the source region 112 may be performed by implanting impurities of the first conductivity type into the well region 110 or into the semiconductor layer 105.

[0441] For example, the step of forming the source region 112 may include forming a first source region 112a on or in the first well region 110a and forming a second source region 112b on or in the second well region 110b. A portion of the second source region 112b may be assigned to a source contact region 112b1 connected to the source electrode layer 140. The first source region 112a and the second source region 112b may be connected to each other. The source region 112 may be formed at a predetermined depth within or above the well region 110, substantially from the surface of the semiconductor layer 105.

[0442] Simultaneously with the formation of the source region 112, a channel region 110c having the second conductivity type may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107 so that an inversion channel is formed. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. For example, the channel region 110c may not be formed separately as part of the first well region 110a, but may be formed together with the first well region 110a.

[0443] Optionally, a well contact region 114 extending from the second well region 110b through the second source region 112b can be formed in the second source region 112b. For example, the well contact region 114 can be formed by implanting a second conductivity type impurity into a part of the well region 110 at a higher concentration than the well region 110.

[0444] A portion of the second well region 110b is exposed from the second source region 112b, and a portion 107c of the drift region 107 can be exposed at the surface of the semiconductor layer 105 through the portion of the second well region 110b.

[0445] In a variation of this embodiment, the doping order of the impurities in the well region 110, the source region 112, the channel region 110c, and the well contact region 114 may be changed appropriately.

[0446] In the above-described manufacturing method, the implantation or doping of impurities can be performed by ion-implanting impurities into the semiconductor layer 105 or by incorporating impurities into the epitaxial layer during formation. However, implantation of impurities into selective regions can be performed using an ion implantation method using a mask pattern. Optionally, the ion implantation can be followed by a heat treatment step to activate or diffuse the impurities.

[0447] 71, a gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105. For example, the gate insulating layer 118 may be formed on at least the channel region 110c and the protruding portion 107a of the drift region 107.

[0448] For example, the gate insulating layer 118 may be formed as an oxide by oxidizing the semiconductor layer 105, or may be formed by depositing an insulating material such as an oxide or nitride on the semiconductor layer 105.

[0449] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities into polysilicon, or may be formed to include a conductive metal or metal silicide.

[0450] The patterning process can be performed using photolithography and etching processes. The photolithography process includes forming a photoresist pattern as a mask layer using a photolithography process and a development process, and the etching process includes selectively etching the underlying structure using the photoresist pattern.

[0451] 72, an interlayer insulating layer 130 may be formed on the gate electrode layer 120. Optionally, when the interlayer insulating layer 130 is formed entirely on the lower structure, a process of forming contact hole patterns to expose the source contact region 112b1 and the well contact region 114 may follow.

[0452] Then, a source electrode layer 140 may be formed on the semiconductor layer 105 to be connected to the second source region 112b, the well contact region 114, and the portion 107c of the drift region 107. A contact structure between the source electrode layer 140 and the portion 107c of the drift region 107 may form a Schottky barrier diode (SBD). For example, the source electrode layer 140 may be formed by forming a conductive layer, such as a metal layer, on the interlayer insulating layer 130 and then patterning or planarizing the conductive layer.

[0453] On the other hand, the power semiconductor element 100a-6 of FIGS. 65 and 66 can be manufactured by adding or modifying some steps in the manufacturing process for the power semiconductor element 100-6 described above.

[0454] The manufacturing of the power semiconductor element 100a-6 can include the additional step of partially etching a portion of the second well region 110b exposed from the second source region 112b and a portion 107c of the drift region 107 to form at least one trench 138, forming a well contact region 114 having the second conductivity type on a portion of the second well region 110b in a part of the bottom surface of the trench 138, and forming a source electrode layer 140 to fill the trench 138 and make common contact with the second source region 112b, the well contact region 114, and the portion 107c of the drift region 107.

[0455] 67 to 69, the channel regions 107b, 107b1, and 107b2 may be formed to have the first conductivity type so as to form an accumulation channel. For example, the channel regions 107b, 107b1, and 107b2 may be formed as part of the drift region 107.

[0456] According to the above-described manufacturing method, the semiconductor layer 105 is made of silicon carbide, and the highly integrated power semiconductor element 100-6 can be manufactured economically using the same process as that used for existing silicon substrates.

[0457] Although the present invention has been described with reference to the embodiments shown in the drawings, these are merely illustrative, and those skilled in the art will recognize that various modifications and equivalent embodiments are possible. Therefore, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. a semiconductor layer of silicon carbide (SiC); a gate insulating layer on at least a portion of the semiconductor layer; a gate electrode layer on the gate insulating layer; a drift region having a first conductivity type, the drift region being formed in the semiconductor layer to include at least one protruding portion disposed under the gate electrode layer; a well region having a second conductivity type, the well region including: a first well region formed in the semiconductor layer below the gate electrode layer and in contact with the at least one protruding portion of the drift region; and a second well region formed in the semiconductor layer outside the gate electrode layer and connected to the first well region; a source region having a first conductivity type, the source region including a first source region formed in the first well region and a second source region formed in the second well region and connected to the first source region; a channel region having a first conductivity type, the channel region being disposed below the gate electrode layer and formed in the semiconductor layer between the at least one protruding portion of the drift region and the first source region, the channel region having an inversion channel; a plurality of well contact regions extending from the second well region through the second source region within the second source region; the first source regions are formed symmetrically on both sides of the second source region; the plurality of well contact regions are formed in the same direction as the extension direction of the second source region, spaced apart by a predetermined distance, and are not formed in the first source region; The first source region and the second source region extend in different directions. Power semiconductor element.

2. The power semiconductor device of claim 1 , further comprising a source electrode layer connected to the second source region outside the gate electrode layer.

3. A power semiconductor element as described in claim 2, wherein the plurality of well contact regions are connected to the source electrode layer, have a second conductivity type, and are doped at a higher concentration than the well region.

4. The power semiconductor device according to claim 1 , wherein the at least one protruding portion of the drift region, the first well region, and the first source region extend in one direction.

5. The power semiconductor device according to claim 4 , wherein the first well region, the first source region, and the channel region are respectively formed in the semiconductor layer on both sides of the at least one protruding portion of the drift region.

6. The power semiconductor device according to claim 1 , wherein the channel region is a part of a well region.

7. the at least one protruding portion includes a plurality of protruding portions whose sidewalls are surrounded by the first well region; The power semiconductor device according to claim 1 , wherein the channel region is formed between the plurality of protruding portions and the first source region.

8. The power semiconductor element according to claim 7 , wherein the plurality of protruding portions extend side by side in one direction.

9. the first well region is formed symmetrically with respect to the second well region; The power semiconductor device according to claim 1 , wherein the channel region is formed symmetrically with respect to the second well region or the second source region.

10. the at least one protruding portion includes a plurality of protruding portions arranged symmetrically with respect to the second well region or the second source region; The power semiconductor element according to claim 9 , wherein the plurality of protruding portions extend in one direction.

11. The power semiconductor device according to claim 1 , wherein the gate electrode layer is formed to expose the second source region and to cover the first source region, the channel region, and the at least one protruding portion of the drift region.

12. a drain region having a first conductivity type in the semiconductor layer below the drift region, The power semiconductor device of claim 1 , wherein the drain region is more highly doped than the drift region.

13. forming a drift region having a first conductivity type in a semiconductor layer of silicon carbide (SiC); forming a well region having a second conductivity type in the semiconductor layer, the well region including a first well region defining the at least one protruding portion and a second well region connected to the first well region, such that the drift region includes at least one protruding portion; forming a source region having a first conductivity type, the source region including a first source region formed in the first well region and a second source region formed in the second well region and coupled to the first source region; forming a channel region having a first conductivity type formed in the semiconductor layer between the at least one protruding portion of the drift region and the first source region, the channel region having an inversion channel formed therein; forming a gate insulating layer on at least the channel region and the at least one protruding portion of the drift region; forming at least one gate electrode layer on the gate insulating layer; forming a plurality of well contact regions in the second source region outside the gate electrode layer, the well contact regions extending from the second well region through the second source region; the first source regions are formed symmetrically on both sides of the second source region; the plurality of well contact regions are formed in the same direction as the extension direction of the second source region, spaced apart by a predetermined distance, and are not formed in the first source region; the first source region and the second source region extend in different directions; The method for manufacturing a power semiconductor element, wherein the second well region is formed in the semiconductor layer outside the gate electrode layer.

14. The method of claim 1, further comprising forming a source electrode layer on the semiconductor layer so as to be coupled to the second source region and the well contact region; The method of claim 13 , wherein the plurality of well contact regions are connected to the source electrode layer and are doped at a higher concentration than the well region.

15. the step of forming the well region and the channel region is performed by implanting impurities of a second conductivity type into the semiconductor layer; The method for manufacturing a power semiconductor device according to claim 13 , wherein the step of forming the source region is performed by implanting impurities of the first conductivity type into the well region.

16. the at least one protruding portion includes a plurality of protruding portions whose sidewalls are surrounded by the first well region; The method for manufacturing a power semiconductor element according to claim 13 , wherein the channel region is formed between the plurality of protruding portions and the source region.

17. the first well region is formed symmetrically with respect to the second well region; The method of claim 13 , wherein the channel region is formed symmetrically with respect to the second well region or the second source region.

18. the drift region is formed on a drain region having a first conductivity type; The method for manufacturing a power semiconductor device according to claim 13 , wherein the drift region is formed on the drain region by an epitaxial layer.

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