Semiconductor device, nonvolatile memory device including the same, and electronic system

Abstract

To provide a non-volatile memory device including a semiconductor device with improved reliability and performance by controlling leakage current, and an electronic system including the semiconductor device.SOLUTION: A semiconductor device according to the present invention has a substrate, a device separation film defining a first active region in the substrate, a first gate electrode on the first active region, a first source / drain region located in the first active region between the device separation film and the first gate electrode, and a separation contact extending in the device separation film in a vertical direction intersecting the top surface of the substrate, and a voltage is applied to the separation contact.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a nonvolatile memory device including the same, and an electronic system, and more particularly to a semiconductor device and a nonvolatile memory device including the same that control leakage current to improve reliability and performance, and an electronic system. [Background technology]

[0002] 2. Description of the Related Art As electronic products become lighter, thinner, shorter, and smaller, there is an increasing demand for higher integration of semiconductor devices. As semiconductor devices become more highly integrated, the size of components included in the semiconductor device (eg, transistors) decreases, which causes a problem of leakage current. Therefore, there is a need to control leakage current in semiconductor devices to improve the performance and reliability of the semiconductor devices.

[0003] On the other hand, there is a demand for semiconductor devices capable of storing a large amount of data in electronic systems that require data storage. Therefore, methods for increasing the data storage capacity of semiconductor devices are being studied. For example, as one method for increasing the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally arranged memory cells has been proposed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 10-261725 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned problems in the conventional semiconductor devices, and an object of the present invention is to provide a semiconductor device having improved reliability and performance by controlling leakage current.

[0006] Another object of the present invention is to provide a nonvolatile memory device including a semiconductor device with improved reliability and performance by controlling leakage current, and an electronic system including the semiconductor device. [Means for solving the problem]

[0007] In order to achieve the above object, a semiconductor device according to the present invention includes a substrate, an element isolation film defining a first active region in the substrate, wherein the isolation film includes an insulating liner, an etch stop liner on the insulating liner, and a gap-fill insulating film on the etch stop liner; a first gate electrode on the first active region; a first source / drain region disposed in the first active region between the isolation film and the first gate electrode; and On top , extending in a vertical direction intersecting the upper surface of the substrate , penetrates the gap fill insulating film, and its lower surface contacts the etch stop liner. and an isolation contact, to which a voltage is applied. The side of the isolation contact is spaced from the etch stop liner. It is characterized by:

[0008] In order to achieve the above object, a semiconductor device according to the present invention includes a substrate including an isolation trench defining an active region, an isolation film including an insulating liner extending along a profile of the isolation trench, an etch stop liner on the insulating liner, and a gap fill insulating film filling the isolation trench on the etch stop liner, a gate electrode on the active region, source / drain regions disposed in the active region between the isolation film and the gate electrode, and a gate insulating film formed on the isolation film. Above, The gap-fill insulating film extends in a vertical direction intersecting the upper surface of the substrate. It penetrates and its underside is an isolation contact in contact with the etch stop liner; The sides of the isolation contact are spaced apart from the etch stop liner. It is characterized by:

[0009] To achieve the above object, the nonvolatile memory device according to the present invention comprises: The first substrate is the peripheral circuit area, and the second substrate is the cell area.a first circuit element and a second circuit element disposed on the first substrate; and an element isolation film in the first substrate that separates the first circuit element and the second circuit element; wherein the isolation film includes an insulating liner, an etch stop liner on the insulating liner, and a gap-fill insulating film on the etch stop liner; the element isolation film Above, The first substrate has a top surface extending in a vertical direction. , penetrates the gap fill insulating film, and its lower surface contacts the etch stop liner. The semiconductor memory device includes an isolation contact, a plurality of word lines stacked in sequence on the second substrate, a channel structure on the second substrate intersecting the plurality of word lines, and a bit line connected to the channel structure, and a voltage is applied to the isolation contact. The side of the isolation contact is spaced from the etch stop liner. It is characterized by:

[0010] In order to achieve the above object, the electronic system according to the present invention comprises a main board, A first substrate in the peripheral circuit region and a second substrate in the cell region and a main controller on the main substrate, electrically connected to the nonvolatile memory device, wherein the nonvolatile memory device includes a first circuit element and a second circuit element disposed on the first substrate, an element isolation film in the first substrate that separates the first circuit element and the second circuit element, wherein the isolation film includes an insulating liner, an etch stop liner on the insulating liner, and a gap-fill insulating film on the etch stop liner; the element isolation film Above, The first substrate has a top surface extending in a vertical direction. , penetrates the gap fill insulating film, and its lower surface contacts the etch stop liner. The semiconductor memory device further includes an isolation contact, a plurality of word lines stacked in sequence on the second substrate, a channel structure on the second substrate intersecting the plurality of word lines, and a bit line connected to the channel structure, and a voltage is applied to the isolation contact. The side of the isolation contact is spaced from the etch stop liner. It is characterized by: [Effects of the Invention]

[0011] According to the semiconductor device and the nonvolatile memory device including the same, and the electronic system according to the present invention, a potential barrier can be formed in the isolation region through an isolation contact formed in the element isolation film and to which a voltage is applied, thereby effectively controlling leakage current and improving reliability and performance. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a layout diagram for explaining a semiconductor device according to an embodiment of the present invention; [Figure 2] FIG. 2 is a cross-sectional view showing a schematic configuration taken along line AA' in FIG. [Figure 3a] FIG. 3 is an enlarged cross-sectional view as an example for explaining an R1 region in FIG. 2. [Figure 3b] 3 is an enlarged cross-sectional view illustrating the R1 region in FIG. 2 as another example. FIG. [Figure 4] FIG. 10 is a cross-sectional view showing a schematic configuration of a semiconductor device according to another embodiment of the present invention. [Figure 5] FIG. 10 is a layout diagram illustrating a semiconductor device according to another embodiment of the present invention. [Figure 6] FIG. 6 is a cross-sectional view showing a schematic configuration taken along line BB' in FIG. 5. [Figure 7a] FIG. 7 is an enlarged cross-sectional view as an example for explaining an R2 region in FIG. 6. [Figure 7b] FIG. 7 is an enlarged cross-sectional view illustrating the R2 region in FIG. 6 as another example. [Figure 8] FIG. 10 is a layout diagram illustrating a semiconductor device according to still another embodiment of the present invention. [Figure 9] 1 is a diagram illustrating a schematic configuration of a nonvolatile memory device according to an embodiment of the inventive concept; [Figure 10] 1 is a cross-sectional view illustrating a schematic configuration of a nonvolatile memory device according to an embodiment of the present invention; [Figure 11] FIG. 11 is an enlarged cross-sectional view as an example for explaining an R3 region in FIG. 10. [Figure 12] FIG. 11 is an enlarged cross-sectional view illustrating the R3 region in FIG. 10 as another example. [Figure 13] 10 is a cross-sectional view illustrating a schematic configuration of a nonvolatile memory device according to another embodiment of the present invention; [Figure 14] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 20] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 21] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 23] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 24] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 25] 1 is a diagram showing a schematic configuration for explaining an electronic system according to an embodiment of the present invention; [Figure 26] 1 is a perspective view showing a schematic configuration for explaining an electronic system according to an embodiment of the present invention; [Figure 27] FIG. 27 is a schematic cross-sectional view taken along line II' of FIG. 26 as an example. [Figure 28] FIG. 27 is a schematic cross-sectional view of another example taken along line II' in FIG. 26. DETAILED DESCRIPTION OF THE INVENTION

[0013] Next, specific examples of embodiments for carrying out a semiconductor device, a nonvolatile memory device including the semiconductor device, and an electronic system according to the present invention will be described with reference to the drawings.

[0014] Semiconductor devices according to embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a layout diagram for explaining a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a schematic configuration cut along line A-A' in FIG. 1, and FIGS. 3a and 3b are enlarged cross-sectional views as examples for explaining the R1 region in FIG. 2.

[0015] 1 to 3a, a semiconductor device according to an embodiment of the present invention includes a first substrate 100, an isolation film 110, first to third circuit elements (TR1, TR2, TR3), an interlayer insulating film 150, a gate contact 142, a source / drain contact 144, and an isolation contact 146. For ease of explanation, the gate contact 142 is not shown in FIG. The first substrate 100 may include, but is not limited to, a base substrate and an epitaxial layer grown on the base substrate. For example, the first substrate 100 may include only a base substrate without an epilayer.

[0016] The first substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, a glass substrate for a display, or the like, and may also be an SOI (Semiconductor On Insulator) substrate. In the following description, the first substrate 100 will be exemplarily described as being a silicon substrate. In one embodiment, the first substrate 100 is doped with a first conductivity type. For example, when the first to third circuit elements (TR1, TR2, TR3) described below are n-type transistors, the first substrate 100 contains p-type impurities. Although not shown, the first substrate 100 may also include a well doped with the first conductivity type.

[0017] The isolation layer 110 defines a plurality of active regions (105A, 105B, 105C, 105D) within the first substrate 100. For example, isolation trenches 110t are formed in the first substrate 100 to define a plurality of active regions (105A, 105B, 105C, 105D). The element isolation film 110 fills the element isolation trench 110t. The element isolation film 110 surrounds each of the active regions (105A, 105B, 105C, 105D). In one embodiment, the isolation trench 110t may be formed to a depth of about 3000 Å to about 5000 Å.

[0018] The active regions (105A, 105B, 105C, 105D) are separated from one another by an isolation film 110. For example, the plurality of active regions (105A, 105B, 105C, 105D) includes a first active region 105A and a second active region 105B arranged along a first direction X. The isolation layer 110 between the first active region 105A and the second active region 105B extends in a second direction Y intersecting the first direction X to separate the first active region 105A from the second active region 105B. Or, for example, the plurality of active regions (105A, 105B, 105C, 105D) includes the first active region 105A and a third active region 105C arranged along the second direction Y, and the second active region 105B and a fourth active region 105D arranged along the second direction Y. The isolation layers 110 between the first active region 105A and the third active region 105C and between the second active region 105B and the fourth active region 105D extend in the first direction X to separate the first active region 105A from the third active region 105C and the second active region 105B from the fourth active region 105D.

[0019] The isolation layer 110 defines an isolation region 105I in the first substrate 100 on the lower surface of the isolation layer 110. That is, as shown in FIGS. 2 and 3a, the isolation region 105I is defined below the device isolation film 110 and is a region of the first substrate 100 that overlaps with the device isolation film 110 in the vertical direction. Here, the vertical direction means a direction intersecting with the upper surface of the first substrate 100. For example, an isolation region 105I is defined in the first substrate 100 between the first active region 105A and the second active region 105B. In Figures 2 and 3a, the side of the isolation film 110 is shown to have a slope, but this is merely a characteristic of the process of forming the isolation film 110, and the technical concept of the present invention is not limited thereto.

[0020] In one embodiment, the isolation layer 110 is formed of multiple layers. For example, the isolation layer 110 includes an insulating liner 112, an etch stop liner 114, and a gap-fill insulating layer 116, which are sequentially stacked in the isolation trench 110t. The insulating liner 112 conformally extends along the profile of the side and bottom surfaces of the isolation trench 110t. An etch stop liner 114 is formed on the insulating liner 112 . The etch stop liner 114 conformally extends along the profile of the insulating liner 112 .

[0021] A gap-fill insulating film 116 is formed on the etch stop liner 114 . The gap-fill insulating film 116 fills the area of ​​the isolation trench 110t remaining after the insulating liner 112 and etch stop liner 114 have been formed. The insulating liner 112, the etch stop liner 114, and the gap-fill insulating film 116 may each comprise, for example, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. In one embodiment, the etch stop liner 114 comprises a material that has an etch selectivity with respect to the insulating liner 112 and the gap-fill insulating film 116 . For example, if the insulating liner 112 and the gap-fill insulating film 116 comprise silicon oxide, the etch stop liner 114 may comprise at least one of silicon nitride, silicon carbonitride, silicon oxycarbonitride, and combinations thereof. As an example, the insulating liner 112 and the gap-fill insulating film 116 comprise silicon oxide, and the etch stop liner 114 comprises silicon nitride.

[0022] The first to third circuit elements (TR1, TR2, TR3) are disposed on the active regions (105A, 105B, 105C, 105D). For example, the first circuit element TR1 and the second circuit element TR2 are disposed on the first active region 105A, and the third circuit element TR3 is disposed on the second active region 105B. The first circuit element TR1 includes a first gate dielectric film 132A, a first gate electrode 134A, a first source / drain region 120A, and a second source / drain region 120B. The first gate electrode 134A extends in one direction (eg, the second direction Y) on the first active region 105A. The first gate dielectric film 132A is interposed between the first substrate 100 and the first gate electrode 134A. A first source / drain region 120A is formed in the first active region 105A on one side of the first gate electrode 134A. A second source / drain region 120B is formed in the first active region 105A on the other side of the first gate electrode 134A. The first source / drain region 120A is adjacent to the element isolation film 110. For example, the first source / drain region 120A is formed in the first active region 105A between the first gate electrode 134A and the device isolation layer 110.

[0023] In one embodiment, the first source / drain region 120A is a drain region of the first circuit element TR1, and the second source / drain region 120B is a source region of the first circuit element TR1. For example, if the first circuit element TR1 is an n-type transistor, a voltage relatively higher than that applied to the second source / drain region 120B is applied to the first source / drain region 120A. As an example, a voltage of about 5V is applied to the first source / drain region 120A, and a voltage of 0V is applied to the second source / drain region 120B. Conversely, when the first circuit element TR1 is a p-type transistor, a voltage relatively lower than that applied to the second source / drain region 120B is applied to the first source / drain region 120A.

[0024] The second circuit element TR2 includes a second gate dielectric film 132B, a first gate electrode 134A, a second source / drain region 120B, and a third source / drain region 120C. The second gate electrode 134B extends in one direction (eg, the second direction Y) on the first active region 105A. As an example, the second gate electrode 134B extends alongside the first gate electrode 134A. The second gate dielectric film 132B is interposed between the first substrate 100 and the second gate electrode 134B. A second source / drain region 120B is formed in the first active region 105A on one side of the second gate electrode 134B. A third source / drain region 120C is formed in the first active region 105A on the other side of the second gate electrode 134B.

[0025] In one embodiment, the first circuit element TR1 and the second circuit element TR2 share the second source / drain region 120B. For example, the second source / drain region 120B is formed in the first active region 105A between the first gate electrode 134A and the second gate electrode 134B. The third source / drain region 120C is adjacent to the element isolation film 110. For example, the third source / drain region 120C is formed in the first active region 105A between the second gate electrode 134B and the device isolation film 110.

[0026] In one embodiment, the second source / drain region 120B is a source region of the second circuit element TR2, and the third source / drain region 120C is a drain region of the second circuit element TR2. For example, if the second circuit element TR2 is an n-type transistor, a voltage relatively higher than that applied to the second source / drain region 120B is applied to the third source / drain region 120C. As an example, a voltage of about 5V is applied to the third source / drain region 120C, and a voltage of 0V is applied to the second source / drain region 120B. Conversely, when the second circuit element TR2 is a p-type transistor, a voltage relatively lower than that applied to the second source / drain region 120B is applied to the third source / drain region 120C.

[0027] The third circuit element TR3 includes a third gate dielectric film 132C, a third gate electrode 134C, and a fourth source / drain region 120D. The third gate electrode 134C extends in one direction (for example, the second direction Y) on the second active region 105B. For example, the third gate electrode 134C extends in parallel with the first gate electrode 134A and the second gate electrode 134B. The third gate dielectric film 132C is interposed between the first substrate 100 and the third gate electrode 134C. A fourth source / drain region 120D is formed in the second active region 105B on one side of the third gate electrode 134C. The fourth source / drain region 120D is adjacent to the element isolation film 110. For example, the fourth source / drain region 120D is formed in the second active region 105B between the third gate electrode 134C and the device isolation film 110. In one embodiment, the fourth source / drain region 120D is the drain region of the third circuit element TR3.

[0028] The first to third gate dielectric films 132A, 132B, and 132C may include, but are not limited to, silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a higher dielectric constant than silicon oxide. The high dielectric constant material may include, but is not limited to, at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0029] In one embodiment, the first to third circuit elements (TR1, TR2, TR3) are high-voltage transistors. For example, the first to third circuit elements (TR1, TR2, TR3) may include first to third gate dielectric films (132A, 132B, 132C) having a thickness of about 200 Å or more, respectively, but are not limited thereto. The first to third gate electrodes (134A, 134B, 134C) may include, for example, at least one of polycrystalline silicon (polySi), amorphous silicon (a-Si), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum (Ta), cobalt (Co), ruthenium (Ru), aluminum (Al), tungsten (W), and combinations thereof, but are not limited thereto.

[0030] In one embodiment, the first to third circuit elements (TR1, TR2, TR3) are high-voltage transistors. For example, a high voltage of about 5 V to about 100 V is applied to the first to third gate electrodes (134A, 134B, 134C), but is not limited to this. The first to fourth source / drain regions (120A, 120B, 120C, 120D) are each doped with a second conductivity type different from the first conductivity type. For example, each of the first to fourth source / drain regions (120A, 120B, 120C, 120D) contains an n-type impurity.

[0031] In one embodiment, the first to fourth source / drain regions (120A, 120B, 120C, 120D) each include a lightly doped region (122A, 122B, 122C, 122D) and a heavily doped region (124A, 124B, 124C, 124D). The high concentration impurity regions (124A, 124B, 124C, 124D) are formed within the low concentration impurity regions (122A, 122B, 122C, 122D). The lightly doped regions (122A, 122B, 122C, 122D) surround the heavily doped regions (124A, 124B, 124C, 124D). The lightly doped regions (122A, 122B, 122C, 122D) and the heavily doped regions (124A, 124B, 124C, 124D) are each doped with a second conductivity type. In this case, the doping concentration of the high-concentration impurity regions (124A, 124B, 124C, 124D) is higher than the doping concentration of the low-concentration impurity regions (122A, 122B, 122C, 122D).

[0032] Although not shown in the figure, the first to third circuit elements (TR1, TR2, TR3) may further include gate spacers covering the side surfaces of the first to third gate electrodes (134A, 134B, 134C), respectively. Although not shown in the figure, the first to third circuit elements (TR1, TR2, TR3) may further include gate capping patterns that cover the upper surfaces of the first to third gate electrodes (134A, 134B, 134C), respectively. Although not shown in the figure, the first to third circuit elements (TR1, TR2, TR3) may further include an etching stop layer covering the first to fourth source / drain regions (120A, 120B, 120C, 120D), gate spacers, and gate capping patterns, respectively.

[0033] The interlayer insulating film 150 is formed on the first substrate 100 . The interlayer insulating film 150 covers the first substrate 100, the element isolation film 110, and the first to third circuit elements (TR1, TR2, TR3). The interlayer insulating film 150 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide. The low dielectric constant material may include, but is not limited to, at least one of, for example, FOX (Flowable Oxide), TOSZ (Torene Silazene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped Silicon Oxide), Xerogel, Aerogel, "Amorphous Fluorinated Carbon", OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, "porous polymeric material", and combinations thereof. In one embodiment, the first to third circuit elements TR1, TR2, and TR3 may be formed on the same level. In this specification, "same level" means formed by the same manufacturing process.

[0034] The gate contacts 142 are connected to the first to third gate electrodes (134A, 134B, 134C). For example, the gate contact 142 extends in a vertical direction intersecting the top surface of the first substrate 100 and penetrates the interlayer insulating film 150 . The gate contacts 142 are electrically connected to the first to third gate electrodes (134A, 134B, 134C), respectively, and apply voltages to the first to third gate electrodes (134A, 134B, 134C). The gate contact 142 may include, but is not limited to, a metal such as aluminum (Al), copper (Cu), or tungsten (W).

[0035] The source / drain contacts 144 are connected to the first to fourth source / drain regions (120A, 120B, 120C, 120D), respectively. For example, the source / drain contacts 144 extend vertically through the interlayer insulating film 150 . The source / drain contacts 144 are electrically connected to the first to fourth source / drain regions (120A, 120B, 120C, 120D), respectively, and apply voltages to the first to fourth source / drain regions (120A, 120B, 120C, 120D), respectively. The source / drain contacts 144 may include, but are not limited to, a metal such as aluminum (Al), copper (Cu), or tungsten (W). In one embodiment, the gate contact 142 and the source / drain contacts 144 may be formed at the same level. For example, the gate contact 142 and the source / drain contacts 144 may comprise the same material as each other.

[0036] The isolation contact 146 is disposed on the element isolation film 110 . The isolation contact 146 overlaps the element isolation film 110 in the vertical direction. Furthermore, at least a portion of the isolation contact 146 is disposed within the element isolation film 110 . For example, the isolation contact 146 extends vertically through the interlayer insulating film 150 and into the device isolation film 110 . In one embodiment, the isolation contacts 146 are multiple and are disposed around the periphery of each active area (105A, 105B, 105C, 105D). For example, as shown in FIG. 1, some of the isolation contacts 146 are interposed between the first active region 105A and the second active region 105B. Another part of the plurality of isolation contacts 146 is interposed between the first active region 105A and the third active region 105C. The number and arrangement of the isolation contacts 146 shown in FIG. 1 are merely examples, and the technical idea of ​​the present invention is not limited thereto.

[0037] In one embodiment, the isolation contacts 146 interposed between the first active region 105A and the second active region 105B are arranged along the second direction Y, and the isolation contacts 146 interposed between the first active region 105A and the third active region 105C are arranged along the first direction X. In one embodiment, the isolation contact 146 is spaced apart from the bottom surface of the isolation layer 110 . For example, as shown in FIG. 3a, the bottom surface of the isolation contact 146 is spaced apart from the bottom surface of the device isolation film 110 by DT1. In one embodiment, the distance DT1 by which the isolation contact 146 is spaced from the bottom surface of the device isolation layer 110 may be about 100 Å to about 4000 Å.

[0038] In one embodiment, the isolation contact 146 penetrates the gap-fill insulating film 116 to contact the etch stop liner 114 . For example, the bottom surface of the isolation contact 146 contacts the top surface of the etch stop liner 114 that extends along the bottom surface of the isolation trench 110t. The etch stop liner 114 can be used as an etch stop layer in an etching process for forming a contact hole (eg, the third contact hole 146t in FIG. 20) to form the isolation contact 146. In one embodiment, the isolation contact 146 may not penetrate completely through the etch stop liner 114 . For example, the bottom surface of the isolation contact 146 is separated from the bottom surface of the isolation layer 110 by the insulating liner 112 and the etch stop liner 114 . As an example, the distance DT1 by which the isolation contact 146 is spaced from the bottom surface of the device isolation layer 110 may be the sum of the thickness of the insulating liner 112 and the thickness of the etch stop liner 114.

[0039] In one embodiment, the width W11 of the isolation contact 146 is smaller than the width of the isolation film 110. In this case, the isolation contact 146 is spaced apart from the side of the device isolation film 110 . In one embodiment, the width W11 of the isolation contact 146 is less than the width of the gap-fill insulating film 116. In such a case, the isolation contact 146 is spaced from the side of the etch stop liner 114 . A voltage is applied to the isolation contact 146 . A voltage applied to isolation contact 146 creates an electric field in isolation region 105I, forming a potential barrier. When the isolation contact 146 is spaced from the bottom surface of the device isolation layer 110, the insulating liner 112 and / or the etch stop liner 114 function as a dielectric layer.

[0040] For example, when the first circuit element TR1 is an n-type transistor, the first source / drain region 120A containing n-type impurities functions as the drain region of the first circuit element TR1. At this time, a ground voltage or a negative (−) voltage is applied to the separation contact 146 . As an example, a voltage of 0V to approximately −5V is applied to isolation contact 146. This reduces the leakage current that occurs from the first source / drain region 120A toward the isolation region 105I. Conversely, when the first circuit element TR1 is a p-type transistor, the first source / drain region 120A containing p-type impurities functions as the drain region of the first circuit element TR1. At this time, a ground voltage or a positive (+) voltage is applied to the separation contact 146 . In one embodiment, a distance DT1 by which the isolation contact 146 is spaced from the bottom surface of the device isolation layer 110 is smaller than a distance DT2 by which the isolation contact 146 is spaced from the side surface of the device isolation layer 110. In this case, the electric field formed on the lower surface of the element isolation film 110 (isolation region 105I) is stronger than the electric field formed on the side surface of the element isolation film 110.

[0041] The isolation contact 146 may include, but is not limited to, a metal such as aluminum (Al), copper (Cu), or tungsten (W). In one embodiment, the isolation contact 146 is formed at the same level as the gate contact 142 and the source / drain contacts 144 . For example, the gate contact 142, the source / drain contact 144, and the isolation contact 146 may comprise the same material as each other.

[0042] 1, 2 and 3 b , in a semiconductor device according to an embodiment of the present invention, at least a portion of the isolation contact 146 is disposed within the etch stop liner 114 . For example, the portion of the etch stop liner 114 that extends along the bottom surface of the isolation trench 110t includes a first trench 114t that extends from its top surface. The lower portion of the isolation contact 146 is formed in the first trench 114t. As a result, the lower surface of the isolation contact 146 is formed lower than the upper surface of the etch stop liner 114 that extends along the lower surface of the isolation trench 110t. Unlike what is shown, in some embodiments, the isolation contact 146 can extend completely through the etch stop liner 114 .

[0043] FIG. 4 is a cross-sectional view showing a schematic configuration of a semiconductor device according to another embodiment of the present invention. For convenience of explanation, parts that overlap with the contents described above using FIGS. 1 to 3b will be explained briefly or omitted. Referring to FIG. 4, in the semiconductor device according to the embodiment of the present invention, the isolation layer 110 is formed of a single layer. For example, the isolation layer 110 does not include the insulating liner 112, the etch stop liner 114, and the gap-fill insulating layer 116 of FIG. In one embodiment, the isolation contact 146 is spaced apart from the bottom surface of the isolation layer 110 .

[0044] FIG. 5 is a layout diagram for explaining a semiconductor device according to another embodiment of the present invention, FIG. 6 is a cross-sectional view showing a schematic configuration cut along line B-B' in FIG. 5, and FIGS. 7a and 7b are enlarged cross-sectional views as examples for explaining region R2 in FIG. 6. For convenience of explanation, parts that overlap with the contents described above with reference to FIGS. 1 to 4 will be explained briefly or omitted.

[0045] 5 to 7a, in the semiconductor device according to this embodiment, the isolation contact 146 contacts the isolation region 105I. For example, the isolation contact 146 extends in a vertical direction intersecting the top surface of the first substrate 100 and penetrates the interlayer insulating film 150 and the device isolation film 110 . In one embodiment, contact impurity regions 160 are formed in the isolation region 105I. The contact impurity region 160 is doped with the first conductivity type. For example, the contact impurity region 160 includes p-type impurities.

[0046] The isolation contact 146 is disposed on the contact impurity region 160 . The isolation contact 146 overlaps the contact impurity region 160 in the vertical direction. The isolation contact 146 penetrates the element isolation film 110 and contacts the contact impurity region 160 . The isolation contact 146 contacts the contact impurity region 160 to apply a voltage to the isolation region 105I.

[0047] For example, when the first circuit element TR1 is an n-type transistor, the first source / drain region 120A containing n-type impurities functions as the drain region of the first circuit element TR1. At this time, a ground voltage or a negative (−) voltage is applied to the contact impurity region 160 through the isolation contact 146 . As an example, a voltage of 0V to approximately −5V is applied to isolation contact 146. This reduces the leakage current that occurs from the first source / drain region 120A toward the isolation region 105I. Conversely, when the first circuit element TR1 is a p-type transistor, the first source / drain region 120A containing p-type impurities functions as the drain region of the first circuit element TR1. At this time, a ground voltage or a positive (+) voltage is applied to the contact impurity region 160 through the isolation contact 146 .

[0048] In one embodiment, the contact impurity region 160 forms an ohmic contact with the isolation contact 146 . As long as the contact impurity region 160 forms an ohmic contact with the isolation contact 146, the doping concentration of the contact impurity region 160 may be relatively low. In one embodiment, the contact impurity regions 160 form a plurality of isolated regions spaced apart from one another. For example, each contact impurity region 160 surrounds the isolation contact 146 from a planar perspective. As an example, as shown in FIG. 5, each contact impurity region 160 surrounds one or more isolation contacts 146 . In one embodiment, the width W12 of the contact impurity region 160 is greater than the width W11 of the isolation contact 146, as shown in FIG. 7a. As a result, during the process of forming the isolation contact 146, the isolation contact 146 is in stable contact with the contact impurity region 160.

[0049] 5, 6, and 7b, in the semiconductor device according to this embodiment, at least a portion of the isolation contact 146 is disposed within the contact impurity region 160. In the semiconductor device according to this embodiment, as shown in FIG. For example, the contact impurity region 160 includes a second trench 160t extending from the upper surface thereof. The lower portion of the isolation contact 146 is formed in the second trench 160t. As a result, the bottom surface of the isolation contact 146 is formed lower than the top surface of the contact impurity region 160 .

[0050] FIG. 8 is a layout diagram illustrating a semiconductor device according to still another embodiment of the present invention. For convenience of explanation, parts that overlap with the contents described above using FIGS. 5 to 7b will be briefly explained or omitted. Referring to FIG. 8, in the semiconductor device according to this embodiment, the contact impurity regions 160 surround each of the active regions (105A, 105B, 105C, 105D). For example, a portion of the contact impurity region 160 extends in the second direction Y between the first active region 105A and the second active region 105B. Another part of the contact impurity region 160 extends in the first direction X between the first active region 105A and the third active region 105C.

[0051] As semiconductor devices become more and more highly integrated, the effects of leakage currents become more and more pronounced. For example, as the width of the isolation layer decreases, leakage current (hereinafter, isolation leakage current) generated along the surface of the isolation layer from a transistor adjacent to the isolation layer increases. To prevent this, a potential barrier can be formed by forming a heavily doped region on the underside of the isolation film, but this has the problem of reducing the breakdown voltage of the transistor adjacent to the isolation film. For example, when the first source / drain region 120A contains impurities of a second conductivity type (for example, n-type), the isolation region 105I is heavily doped with impurities of a first conductivity type (for example, p-type) to form a potential barrier. However, the impurities of the first conductivity type (eg, p-type) formed in the isolation region 105I diffuse toward the first source / drain region 120A, lowering the breakdown voltage of the first circuit element TR1.

[0052] In contrast, in the semiconductor device according to the embodiment of the present invention, the isolation leakage current can be controlled by forming no impurity region or only a low concentration impurity region in the isolation region 105I. Specifically, the semiconductor device according to the embodiment of the present invention forms a potential barrier in the isolation region 105I via the isolation contact 146 formed in the device isolation film 110 and to which a voltage is applied. As a result, leakage current can be effectively controlled, thereby providing a semiconductor device with improved reliability and performance.

[0053] Hereinafter, a nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 9 is a diagram showing a schematic configuration of a nonvolatile memory device according to an embodiment of the present invention, FIG. 10 is a cross-sectional view showing a schematic configuration of a nonvolatile memory device according to an embodiment of the present invention, and FIGS. 11 and 12 are enlarged cross-sectional views as examples for explaining the R3 region of FIG. 10. For convenience of explanation, parts that overlap with the contents described above with reference to FIGS. 1 to 8 will be explained briefly or omitted.

[0054] Referring to FIG. 9, a nonvolatile memory device according to an embodiment of the present invention includes a first structure 1100F and a second structure 1100S on the first structure 1100F. In one embodiment, the first structure 1100F is positioned adjacent to the second structure 1100S. The first structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S is a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0055] In the second structure 1100S, each memory cell string CSTR includes a lower transistor (LT1, LT2) adjacent to a common source line CSL, an upper transistor (UT1, UT2) adjacent to a bit line BL, and multiple memory cell transistors MCT arranged between the lower transistor (LT1, LT2) and the upper transistor (UT1, UT2). The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on the embodiment. In one embodiment, the upper transistors (UT1, UT2) comprise string select transistors and the lower transistors (LT1, LT2) comprise ground select transistors. The first and second gate lower lines (LL1, LL2) are the gate electrodes of the lower transistors (LT1, LT2), respectively. The word line WL is the gate electrode of the memory cell transistor MCT, and the first and second gate upper lines (UL1, UL2) are the gate electrodes of the upper transistors (UT1, UT2), respectively.

[0056] In one embodiment, the lower transistors (LT1, LT2) include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors (UT1, UT2) include a series-connected string select transistor UT1 and an upper erase control transistor UT2. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 is used for an erase operation that erases data stored in the memory cell transistor MCT using a gate-induced drain leakage (GIDL) phenomenon.

[0057] The common source line CSL, the first and second gate lower lines (LL1, LL2), the word line WL, and the first and second gate upper lines (UL1, UL2) are electrically connected to the decoder circuit 1110 via first connection wiring 1115 that extends from the first structure 1100F to the second structure 1100S. The bit line BL is electrically connected to the page buffer 1120 via second connection wiring 1125 that extends from the first structure 1100F to the second structure 1100S. In the first structure 1100F, a decoder circuit 1110 and a page buffer 1120 perform a control operation on at least one selected memory cell transistor of the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 are controlled by a logic circuit 1130 .

[0058] Referring to FIG. 10, a nonvolatile memory device according to an embodiment of the present invention includes a peripheral circuit region PERI and a cell region CELL. The peripheral circuit region PERI includes a first substrate 100, an interlayer insulating film 150, a plurality of circuit elements (TR1, TR2, TR3, 220a, 220b) formed on the first substrate 100, first metal layers (144, 146, 230a, 230b) connected to each of the plurality of circuit elements (TR1, TR2, TR3, 220a, 220b), and second metal layers (240, 240a, 240b) formed on the first metal layers (144, 146, 230a, 230b). In one embodiment, the first to third circuit elements (TR1, TR2, TR3) provide a decoder circuit (for example, 1110 in FIG. 9) in the peripheral circuit region PERI. In one embodiment, the fourth circuit element 230a provides a logic circuit (eg, reference numeral 1130 in FIG. 9) in the peripheral circuit region PERI. In one embodiment, the fifth circuit element 230b provides a page buffer (eg, reference numeral 1120 in FIG. 9) in the peripheral circuit region PERI.

[0059] In this specification, only the first metal layers (144, 146, 230a, 230b) and the second metal layers (240, 240a, 240b) are shown and described, but this is not limited thereto, and at least one more metal layer may be formed on the second metal layers (240, 240a, 240b). At least a portion of one or more metal layers formed on the second metal layers (240, 240a, 240b) may be formed of aluminum or the like, which has a lower resistance than copper forming the second metal layers (240, 240a, 240b). In one embodiment, the first metal layers (144, 146, 230a, 230b) are formed of tungsten, which has a relatively high resistance, and the second metal layers (240, 240a, 240b) are formed of copper, which has a relatively low resistance.

[0060] The interlayer insulating film 150 is disposed on the first substrate 100 so as to cover the plurality of circuit elements (TR1, TR2, TR3, 220a, 220b), the first metal layers (144, 146, 230a, 230b), and the second metal layers (240, 240a, 240b). The cell area CELL provides at least one memory block. The cell region CELL includes a second substrate 310 and a common source line 320 . On the second substrate 310, a plurality of word lines (331 to 338, 330) are stacked along the vertical direction Z that intersects with the upper surface of the second substrate 310. String selection lines (e.g., symbols UL1 and UL2 in FIG. 9) and ground selection lines (e.g., symbols LL1 and LL2 in FIG. 9) are arranged above and below the word lines 330, respectively, and multiple word lines 330 are arranged between the string selection lines and the ground selection lines.

[0061] The channel structure CH extends in the vertical direction Z through the word lines 330, the string select lines, and the ground select lines. As shown in FIGS. 11 and 12, the channel structure CH includes a semiconductor pattern 390 and an information storage layer 392 . The semiconductor pattern 390 extends in the third direction Z. Although the semiconductor pattern 390 is shown to be cup-shaped, this is merely an example, and the semiconductor pattern 390 may have various shapes such as a cylindrical shape, a rectangular tube shape, or a filled-in shape. The semiconductor pattern 390 may include semiconductor materials such as, but not limited to, monocrystalline silicon, polycrystalline silicon, organic semiconductor materials, and carbon nanostructures.

[0062] The information storage layer 392 is interposed between the semiconductor pattern 390 and the word line 330 . For example, the information storage film 392 extends along the side of the semiconductor pattern 390 . In one embodiment, the information storage film 392 is formed of multiple films. For example, the information storage layer 392 includes a tunnel insulating layer 392 a, a charge storage layer 392 b, and a blocking insulating layer 392 c, which are sequentially stacked on the semiconductor pattern 390 . The tunnel insulating film 392a includes, for example, silicon oxide or a high-dielectric-constant material having a higher dielectric constant than silicon oxide (for example, aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 )). The charge storage film 392b includes, for example, silicon nitride.

[0063] The blocking insulating film 392c includes, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide. In one embodiment, the information storage layer 392 further includes a gate insulating layer 392 d extending along the surface of each word line 330 . In one embodiment, the channel structure CH further comprises a fill pattern 394 . The filling pattern 394 is formed to fill the inside of the cup-shaped semiconductor pattern 390 . The fill pattern 394 may include an insulating material, such as, but not limited to, silicon dioxide. The common source line 320 is formed to be connected to the semiconductor pattern 390 of the channel structure CH.

[0064] As shown in FIG. 11, in one embodiment, the channel structure CH is embedded in the second substrate 310 through the common source line 320 . The common source line 320 passes through a portion of the information storage layer 392 and is connected to a side of the semiconductor pattern 390 . As shown in FIG. 12, in one embodiment, at least a portion of the common source line 320 is embedded within the second substrate 310 . The common source line 320 is formed from the second substrate 310 by, for example, a selective epitaxial growth (SEG) process. The channel structure CH is connected to the top surface of the common source line 320 through a portion of the information storage film 392 .

[0065] The channel structure CH is electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c is a bit line contact, and the second metal layer 360c is a bit line (for example, symbol BL in FIG. 9). In one embodiment, the bit line 360c extends in one direction parallel to the top surface of the second substrate 310 (eg, the second direction Y). In one embodiment, the bit line 360c is electrically connected to a fifth circuit element 230b that provides a page buffer (eg, reference numeral 1120 in FIG. 9) in the peripheral circuit region PERI. The word lines 330 extend in a direction parallel to the top surface of the second substrate 310 (for example, the first direction X) and are connected to a plurality of cell contact plugs 340 . The word lines 330 and the cell contact plugs 340 are connected to each other through pads provided by extending at least some of the word lines 330 to different lengths. A first metal layer 350b and a second metal layer 360b are sequentially connected to the top of the cell contact plug 340 connected to the word line 330.

[0066] In one embodiment, the cell contact plug 340 is electrically connected to first to third circuit elements (TR1, TR2, TR3) that provide a decoder circuit (eg, reference numeral 1110 in FIG. 9) in the peripheral circuit region PERI. As an example, the first metal layer 350b connected to the cell contact plug 340 is connected to the first metal layer 350d by the second metal layer 360b. The first metal layer 350d is connected to the second metal layer 240 via a connection contact plug 345. As a result, the first to third circuit elements (TR1, TR2, TR3) are electrically connected to the word line 330. For example, the first circuit element TR1 is electrically connected to a portion of the word lines 330, the second circuit element TR2 is electrically connected to another portion of the word lines 330, and the third circuit element TR3 is electrically connected to yet another portion of the word lines 330.

[0067] In one embodiment, the operating voltages of the first to third circuit elements (TR1, TR2, TR3) may be different from the operating voltage of the fifth circuit element 220b that provides the page buffer (eg, reference numeral 1120 in FIG. 9). As an example, the operating voltage of the fifth circuit element 220b is higher than the operating voltages of the first to third circuit elements (TR1, TR2, TR3). The common source line contact plug 380 is electrically connected to the common source line 320 . The common source line contact plug 380 is formed of a conductive material such as metal, metal compound, or polysilicon, and a first metal layer 350 a is formed on the common source line contact plug 380 .

[0068] In one embodiment, a lower insulating film 201 covering the lower surface of the first substrate 100 is formed under the first substrate 100, and a first input / output pad 205 is formed on the lower insulating film 201. The first input / output pad 205 is connected to at least one of a plurality of circuit elements (TR1, TR2, TR3, 220a, 220b) arranged in the peripheral circuit region PERI via the first input / output contact plug 203, and is separated from the first substrate 100 by the lower insulating film 201. In addition, a side insulating film is disposed between the first I / O contact plug 203 and the first substrate 100 to electrically separate the first I / O contact plug 203 from the first substrate 100 . In one embodiment, an upper insulating film 301 is formed on the second substrate 310 to cover the upper surface of the second substrate 310 , and a second input / output pad 305 is disposed on the upper insulating film 301 . The second input / output pad 305 is connected via the second input / output contact plug 303 to at least one of the plurality of circuit elements (TR1, TR2, TR3, 220a, 220b) arranged in the peripheral circuit region PERI.

[0069] In one embodiment, the second substrate 310 and the common source line 320 may not be disposed in the region where the second I / O contact plug 303 is disposed. Also, the second I / O pad 305 does not have to overlap with the word line 330 in the vertical direction Z. The second I / O contact plug 303 is separated from the second substrate 310 in a direction parallel to the upper surface of the second substrate 310 (for example, the first direction X), and is connected to the second I / O pad 305 through the interlayer insulating film 315 in the cell region CELL. In one embodiment, the first I / O pad 205 and the second I / O pad 305 are selectively formed.

[0070] As an example, a nonvolatile memory device according to an embodiment of the present invention may include only a first input / output pad 205 arranged on a first substrate 100, or may include only a second input / output pad 305 arranged on a second substrate 310. Alternatively, the nonvolatile memory device according to the embodiment of the present invention may include both the first I / O pad 205 and the second I / O pad 305 . In one embodiment, the isolation contact 146 is electrically connected to the first I / O pad 205 or the second I / O pad 305 via the first I / O contact plug 203 or the second I / O contact plug 303 . This applies a voltage to the isolation contact 146 .

[0071] FIG. 13 is a cross-sectional view illustrating a schematic configuration of a nonvolatile memory device according to another embodiment of the present invention. For convenience of explanation, parts that overlap with the contents described above with reference to FIGS. 1 to 12 will be explained briefly or omitted. Referring to FIG. 13, the nonvolatile memory device according to this embodiment has a C2C (chip to chip) structure.

[0072] The C2C structure means that an upper chip including a cell region CELL is fabricated on a first wafer, a lower chip including a peripheral circuit region PERI is fabricated on a second wafer different from the first wafer, and then the upper chip and the lower chip are connected to each other by a bonding method. For example, the bonding method refers to a method of electrically connecting a bonding metal formed on the top metal layer of an upper chip and a bonding metal formed on the top metal layer of a lower chip to each other. For example, if the bonding metal is made of copper (Cu), the bonding method is Cu-Cu bonding, and the bonding metal can also be made of aluminum or tungsten.

[0073] In one embodiment, each of the peripheral circuit area PERI and the cell area CELL includes an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. The word line bonding area WLBA is defined as an area where a plurality of cell contact plugs 340 and the like are arranged. Lower bonding metals (271b, 272b) are formed on the second metal layer 240 in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals (271b, 272b) of the peripheral circuit area PERI are electrically connected to the upper bonding metals (371b, 372b) of the cell area CELL by bonding. The lower bonding metals (271b, 272b) and the upper bonding metals (371b, 372b) may be made of aluminum, copper, tungsten, or the like.

[0074] The cell contact plug 340 is connected to the peripheral circuit region PERI in the word line bonding region WLBA via the upper bonding metals (371b, 372b) of the cell region CELL and the lower bonding metals (271b, 272b) of the peripheral circuit region PERI. The bit line bonding area BLBA is defined as an area where the channel structure CH, the bit line 360c, etc. are arranged. The bit line 360c is electrically connected to the fifth circuit element 220b in a bit line bonding area BLBA. As an example, the bit line 360c is connected to upper bonding metals (371c, 372c) in the peripheral circuit region PERI, and the upper bonding metals (371c, 372c) are connected to lower bonding metals (271c, 272c) connected to the fifth circuit element 220b.

[0075] A common source line contact plug 380 is disposed in the external pad bonding area PA. The common source line contact plug 380 is formed of a conductive material such as metal, metal compound, or polysilicon, and is electrically connected to the common source line 320 . A first metal layer 350a and a second metal layer 360a are sequentially stacked on the common source line contact plug 380. As an example, the area where the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a are disposed is defined as an external pad bonding area PA. Furthermore, input / output pads (205, 305) are arranged in the external pad bonding area PA.

[0076] In the external pad bonding area PA and bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, respectively, the metal pattern of the uppermost metal layer exists as a dummy pattern, or the uppermost metal layer is empty. In one embodiment of the nonvolatile memory device, a lower metal pattern 273a having the same shape as the upper metal pattern 372a of the cell region CELL is formed in the uppermost metal layer of the peripheral circuit region PERI in the external pad bonding region PA, corresponding to the upper metal pattern 372a formed in the uppermost metal layer of the cell region CELL.

[0077] The lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit region PERI does not need to be connected to a separate contact in the peripheral circuit region PERI. Similarly, in the external pad bonding area PA, an upper metal pattern having the same shape as the lower metal pattern of the peripheral circuit area PERI can be formed in the upper metal layer of the cell area CELL in response to the lower metal pattern formed in the top metal layer of the peripheral circuit area PERI. In addition, in the bit line bonding region BLBA, an upper metal pattern 372d having the same shape as the lower metal pattern 272d in the peripheral circuit region PERI can be formed in the uppermost metal layer of the cell region CELL corresponding to the lower metal pattern 272d formed in the uppermost metal layer of the peripheral circuit region PERI. It is not necessary to form a contact on the upper metal pattern 372d formed in the uppermost metal layer of the cell region CELL.

[0078] A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS. 14 to 20 are cross-sectional views showing intermediate stages for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. For the sake of convenience, parts that overlap with the contents described above with reference to FIGS. 1 to 13 will be briefly explained or omitted.

[0079] Referring to FIG. 14, a preliminary gate dielectric layer 132L, a gate electrode layer 134L, and a sacrificial layer 170 are sequentially formed on a first substrate 100. The preliminary gate dielectric layer 132L may include, for example, silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a higher dielectric constant than silicon oxide. The gate electrode film 134L may include, but is not limited to, at least one of, for example, polycrystalline silicon (poly Si), amorphous silicon (a-Si), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum (Ta), cobalt (Co), ruthenium (Ru), aluminum (Al), tungsten (W), and combinations thereof. The sacrificial film 170 may include, but is not limited to, silicon oxide, for example. As an example, the sacrificial film 170 includes PEOX (Plasma Enhance Oxide).

[0080] Referring to FIG. 15, an isolation trench 110t is formed in the first substrate 100. The isolation trenches 110t define a plurality of active regions (105A, 105B, 105C, 105D) within the first substrate 100. The isolation trenches 110t also define isolation regions 105I in the first substrate 100 on the lower surfaces of the isolation trenches 110t.

[0081] Referring to FIG. 16, an insulating liner 112, an etch stop liner 114, and a gap-fill insulating film 116 are sequentially formed in the isolation trench 110t. The insulating liner 112 conformally extends along the side and bottom profiles of the isolation trench 110t. The etch stop liner 114 conformally extends along the profile of the insulating liner 112 . The gap-fill insulating film 116 fills the area of ​​the isolation trench 110t remaining after the insulating liner 112 and etch stop liner 114 have been formed. In one embodiment, the etch stop liner 114 comprises a material that has an etch selectivity with respect to the insulating liner 112 and the gap-fill insulating film 116 . As an example, the insulating liner 112 and the gap-fill insulating film 116 comprise silicon oxide, and the etch stop liner 114 comprises silicon nitride.

[0082] Referring to FIG. 17, a portion of the etch stop liner 114 is removed. For example, a recess step for the etch stop liner 114 is performed. In one embodiment, the insulating liner 112 and the gap-fill insulating film 116 comprise materials that have an etch selectivity relative to the etch-stop liner 114, so that the etch-stop liner 114 is selectively removed.

[0083] Referring to FIG. 18, a planarization step is performed. For example, an insulating film is formed to fill the area where the etch stop liner 114 has been removed. Subsequently, a planarization step is performed. The planarization process may include, but is not limited to, a Chemical Mechanical Polishing (CMP) process. As a result, the isolation film 110 filling the isolation trench 110t is formed. In one embodiment, the sacrificial layer 170 is removed by a planarization process. As a result, the upper surface of the gate electrode film 134L, the upper surface of the insulating liner 112, and the upper surface of the gap-fill insulating film 116 are exposed.

[0084] Referring to FIG. 19, first to third circuit elements (TR1, TR2, TR3) and an interlayer insulating film 150 are formed on a first substrate 100. The first to third circuit elements (TR1, TR2, TR3) are formed on the active regions (105A, 105B, 105C, 105D). For example, the first circuit element TR1 and the second circuit element TR2 are disposed on the first active region 105A, and the third circuit element TR3 is disposed on the second active region 105B. Subsequently, an interlayer insulating film 150 is formed on the first substrate 100 to cover the first to third circuit elements (TR1, TR2, TR3).

[0085] Referring to FIG. 20, a first contact hole 142t, a second contact hole 144t, and a third contact hole 146t are formed in the interlayer insulating film 150. The first contact holes 142t penetrate the interlayer insulating film 150 to expose the first to third gate electrodes (134A, 134B, 134C). The second contact holes 144t penetrate the interlayer insulating film 150 to expose the first to fourth source / drain regions (120A, 120B, 120C, 120D). The third contact hole 146t penetrates the interlayer insulating film 150 to expose the element isolation film 110. In one embodiment, the third contact hole 146t penetrates the interlayer insulating layer 150 and the gap-fill insulating layer 116 to expose the etch stop liner 114. The etch stop liner 114 includes a material having an etch selectivity with respect to the gap-fill insulating film 116, and therefore, the etch stop liner 114 can be used as an etch stop layer in the process of forming the third contact hole 146t.

[0086] The third contact hole 146t can be formed simultaneously with the first contact hole 142t and / or the second contact hole 144t, or can be formed before the first contact hole 142t and / or the second contact hole 144t are formed, or after the first contact hole 142t and / or the second contact hole 144t are formed. Continuing with reference to FIG. 2, gate contact 142, source / drain contacts 144, and isolation contacts 146 are formed. The gate contact 142 fills the first contact hole 142t. As a result, the gate contacts 142 are connected to the first to third gate electrodes (134A, 134B, 134C). The source / drain contact 144 fills the second contact hole 144t. As a result, the source / drain contacts 144 are connected to the first to fourth source / drain regions (120A, 120B, 120C, 120D), respectively. The isolation contact 146 fills the third contact hole 146t. As a result, at least a portion of the isolation contact 146 is disposed within the element isolation film 110 .

[0087] 21 to 24 are cross-sectional views showing intermediate stages for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. For convenience of explanation, parts that overlap with the contents described above with reference to FIGS. 1 to 20 will be explained briefly or omitted. For reference, FIG. 21 is a diagram for explaining the steps after FIG.

[0088] Referring to FIG. 21, a contact impurity region 160 is formed in the isolation region 105I. For example, the contact impurity region 160 is formed in the isolation region 105I exposed by the element isolation trench 110t. Forming the contact impurity region 160 may include, but is not limited to, an ion implantation process.

[0089] Referring to FIG. 22, an isolation film 110 is formed in the isolation trench 110t. In FIG. 22, the device isolation film 110 is shown to be formed of a single film, but this is merely an example. For example, the device isolation layer 110 can be formed of multiple layers.

[0090] Referring to FIG. 23, first to third circuit elements (TR1, TR2, TR3) and an interlayer insulating film 150 are formed on a first substrate 100. The formation of the first to third circuit elements (TR1, TR2, TR3) and the interlayer insulating film 150 is the same as that described above with reference to FIG. 19, and therefore a detailed description thereof will be omitted below.

[0091] Referring to FIG. 24, a first contact hole 142t, a second contact hole 144t, and a third contact hole 146t are formed in the interlayer insulating film 150. The formation of the first contact hole 142t and the second contact hole 144t is similar to that described above with reference to FIG. 20, and therefore a detailed description thereof will be omitted below. In one embodiment, the third contact hole 146t penetrates the device isolation layer 110 to expose the contact impurity region 160. The third contact hole 146t can be formed simultaneously with the first contact hole 142t and / or the second contact hole 144t, or can be formed before the first contact hole 142t and / or the second contact hole 144t are formed, or after the first contact hole 142t and / or the second contact hole 144t are formed.

[0092] Continuing with reference to FIG. 6, gate contacts 142, source / drain contacts 144, and isolation contacts 146 are formed. The formation of the gate contact 142, the source / drain contacts 144, and the isolation contact 146 is similar to that described above with reference to FIG. 2, and therefore will not be described in detail below.

[0093] Hereinafter, a nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIGS. Figure 25 is a diagram showing a schematic configuration for explaining an electronic system according to an embodiment of the present invention, Figure 26 is a schematic oblique view for explaining an electronic system according to an embodiment of the present invention, and Figures 27 and 28 are schematic cross-sectional views cut along line II' in Figure 26. For the sake of convenience, parts that overlap with the contents described above with reference to FIGS. 1 to 24 will be explained briefly or omitted.

[0094] Referring to FIG. 25, an electronic system 1000 according to an embodiment of the present invention includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100 . The electronic system 1000 is a storage device that includes one or more semiconductor devices 1100 or an electronic device that includes a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD device), a Universal Serial Bus (USB), a computing system, a medical device, or a communications device that includes one or more semiconductor devices 1100.

[0095] The semiconductor device 1100 may be a non-volatile memory device (eg, a NAND flash memory device), such as the non-volatile memory devices described above with reference to FIGS. The semiconductor device 1100 communicates with the controller 1200 via an input / output pad 1101 electrically connected to a logic circuit 1130 . The input / output pads 1101 are electrically connected to the logic circuit 1130 via input / output connection wiring 1135 that extends within the first structure 1100F to the second structure 1100S. The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. In one embodiment, the electronic system 1000 includes multiple semiconductor devices 1100 , where the controller 1200 controls the multiple semiconductor devices 1100 .

[0096] The processor 1210 controls the overall operation of the electronic system 1000 , including the controller 1200 . The processor 1210 operates according to predetermined firmware and controls the NAND controller 1220 to access the semiconductor device 1100 . The NAND controller 1220 includes a NAND interface 1221 that handles communication with the semiconductor device 1100 . Control commands for controlling the semiconductor device 1100, data to be written to the memory cell transistor MCT of the semiconductor device 1100, data to be read from the memory cell transistor MCT of the semiconductor device 1100, etc. are transmitted via the NAND interface 1221. The host interface 1230 provides communication between the electronic system 1000 and an external host. When a control command is received from an external host via the host interface 1230, the processor 1210 controls the semiconductor device 1100 in response to the control command.

[0097] Referring to FIG. 26, an electronic system according to an embodiment of the present invention includes a main board 2001 , a main controller 2002 mounted on the main board 2001 , one or more semiconductor packages 2003 , and a DRAM 2004 . The semiconductor package 2003 and the DRAM 2004 are connected to the main controller 2002 by a wiring pattern 2005 formed on the main board 2001 . The main board 2001 includes a connector 2006 including a plurality of pins that are coupled to an external host. The number and arrangement of pins in connector 2006 vary depending on the communication interface between electronic system 2000 and an external host.

[0098] In one embodiment, electronic system 2000 may communicate with an external host via any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), or M-Phy for Universal Flash Storage (UFS). In one embodiment, electronic system 2000 operates from power supplied by an external host via connector 2006 . The electronic system 2000 may further include a PMIC (Power Management Integrated Circuit) that distributes power supplied from an external host to the main controller 2002 and the semiconductor package 2003.

[0099] The main controller 2002 can record data to or read data from the semiconductor package 2003, which can improve the operating speed of the electronic system 2000. The DRAM 2004 is a buffer memory for reducing the speed difference between the semiconductor package 2003, which is a data storage space, and the external host. The DRAM 2004 included in the electronic system 2000 can operate as a kind of cache memory and can provide space for temporary data storage during control operations for the semiconductor package 2003 . If the electronic system 2000 includes a DRAM 2004 , the main controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003 .

[0100] The semiconductor package 2003 includes first and second semiconductor packages (2003a, 2003b) spaced apart from each other. The first and second semiconductor packages (2003a, 2003b) are semiconductor packages each including a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages (2003a, 2003b) includes a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0101] Package substrate 2100 is a printed circuit board that includes package top pads 2130 . Each semiconductor chip 2200 includes input / output pads 2210 . The input / output pad 2210 corresponds to the input / output pad 1101 in FIG. Each semiconductor chip 2200 includes a memory block 3210 and a channel structure 3220 . The memory block 3210 corresponds to the memory block in FIG. 10, and the channel structure 3220 corresponds to the channel structure CH in FIG. Each of the semiconductor chips 2200 includes the nonvolatile memory device described above with reference to FIGS.

[0102] In one embodiment, the connection structure 2400 is a bonding wire that electrically connects the I / O pad 2210 and the package top pad 2130 . Therefore, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 are electrically connected to each other by bonding wires and to the upper package pads 2130 of the package substrate 2100. In one embodiment, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of a bonding wire type connection structure 2400.

[0103] In one embodiment, the main controller 2002 and the semiconductor chip 2200 may be included in a single package. In one embodiment, the main controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate other than the main substrate 2001, and the main controller 2002 and the semiconductor chip 2200 may be connected to each other by wiring formed on the interposer substrate.

[0104] Referring to FIG. 27, in a semiconductor package 2003, a package substrate 2100 is a printed circuit board. The package substrate 2100 includes a package substrate body portion 2120, package upper pads (2130 in FIG. 26) arranged on the upper surface of the package substrate body portion 2120, lower pads 2125 arranged on the lower surface of the package substrate body portion 2120 and exposed through the lower surface, and internal wiring 2135 electrically connecting the upper pads 2130 and the lower pads 2125 inside the package substrate body portion 2120. The upper pad 2130 is electrically connected to the connecting structure 2400 . The lower pad 2125 is connected to a wiring pattern 2005 on a main board 2001 of the electronic system 2000 as shown in FIG. 26 via a conductive connection 2800.

[0105] Each semiconductor chip 2200 includes a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010 . The semiconductor substrate 3010 corresponds to the first substrate 100 in FIG. The first structure 3100 corresponds to the peripheral circuit region PERI in FIG. 10, and the second structure 3200 corresponds to the cell region CELL in FIG. For example, the second structure 3200 includes a second substrate 310, a plurality of word lines 330, a channel structure CH, and a plurality of cell contact plugs 340. In one embodiment, as shown, the first structure 3100 includes an isolation layer 110 and an isolation contact 146 . Each of the semiconductor chips 2200 further includes an input / output pad (2210 in FIG. 26) electrically connected to the first structure 3100.

[0106] Referring to FIG. 28, in a semiconductor package 2003A, each semiconductor chip 2200 includes a first structure 3100 and a second structure 3200 bonded by a wafer bonding method. For example, the first structure 3100 corresponds to the peripheral circuit region PERI in FIG. 13, and the second structure 3200 corresponds to the cell region CELL in FIG. The semiconductor chips 2200 in FIGS. 27 and 28 are electrically connected to each other by a connection structure (reference numeral 2400 in FIG. 26) in the form of a bonding wire. However, in one embodiment, semiconductor chips within a single semiconductor package, such as the semiconductor chip 2200 of FIGS. 27 and 28, may be electrically connected to each other by a connection structure including a through-silicon via (TSV).

[0107] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0108] 100 First substrate 105(A~D) Active region 105I Separation area 110 Element isolation film 110t isolation trench 112 Insulation liner 114 Etch-stop liner 114t First Trench 116 Gap fill insulating film 120(A to D) (1st to 4th) source / drain regions 122(A~D) Low concentration impurity region 124(A~D) High concentration impurity region 132(A-C) (1st to 3rd) gate dielectric films 134 (A to C) (first to third) gate electrodes 142 Gate Contact 144 Source / Drain Contacts 146 Separation Contact 150 Interlayer insulating film 160 Contact impurity region 160t Second Trench 201 Lower insulating film 203 First input / output contact plug 205 1st I / O pad 220a, 220b circuit elements 230a, 230b First metal layer 240, 240a, 240b Second metal layer 301 Upper insulating film 303 Second input / output contact plug 305 Second I / O Pad 310 Second board 315 Interlayer insulating film 320 common source line 330, 331-338 Word lines 350(a~d) First metal layer 360a Second metal layer 390 Semiconductor Pattern 392 Information Storage Membrane 392a Tunnel insulating film 392b Charge storage membrane 392c Blocking insulating film 392d Gate insulating film 394 Filling Pattern 1100F 1st structure 1100S 2nd structure 1110 decoder circuit 1115 First connection wiring 1120 page buffers 1125 Second connection wiring 1130 Logic Circuit TR1, TR2, TR3 (1st to 3rd) circuit elements

Claims

1. A substrate; an isolation layer defining a first active region within the substrate; wherein the isolation film includes an insulating liner, an etch stop liner on the insulating liner, and a gap-fill insulating film on the etch stop liner; a first gate electrode on the first active region; a first source / drain region disposed in the first active region between the isolation film and the first gate electrode; an isolation contact on the isolation layer, the isolation contact extending in a vertical direction intersecting with an upper surface of the substrate, penetrating the gap-fill insulating layer, and having a lower surface in contact with the etch stop liner; A voltage is applied to the isolation contact; a side surface of the isolation contact spaced apart from the etch stop liner;

2. the first source / drain region contains n-type impurities; 2. The semiconductor device according to claim 1, wherein a ground (GND) voltage or a negative voltage is applied to the isolation contact.

3. an interlayer insulating film covering the first gate electrode on the substrate and the element isolation film; 2. The semiconductor device according to claim 1, wherein the isolation contact extends in the vertical direction and penetrates the interlayer insulating film.

4. further comprising a source / drain contact that penetrates the interlayer insulating film and is connected to the first source / drain region; 4. The semiconductor device of claim 3, wherein the isolation contact and the source / drain contacts comprise the same material.

5. 2. The semiconductor device according to claim 1, wherein the isolation contact is spaced apart from a lower surface of the element isolation film.

6. the substrate further includes an isolation trench defining the first active region; 2. The semiconductor device of claim 1, wherein the insulating liner extends along a profile of the isolation trench.

7. a second gate electrode extending parallel to and spaced apart from the first gate electrode on the first active region; a second source / drain region disposed in the first active region between the first gate electrode and the second gate electrode; 2. The semiconductor device according to claim 1, wherein the first source / drain region and the second source / drain region contain impurities of the same conductivity type.

8. a second active region in the substrate, the second active region being separated from the first active region by the isolation film; a second gate electrode extending parallel to the first gate electrode on the second active region; a second source / drain region disposed in the second active region between the isolation film and the second gate electrode; 2. The semiconductor device according to claim 1, wherein the first source / drain region and the second source / drain region contain impurities of the same conductivity type.

9. a substrate including isolation trenches defining active areas; an isolation film including an insulating liner extending along a profile of the isolation trench, an etch stop liner on the insulating liner, and a gap fill insulating film filling the isolation trench on the etch stop liner; a gate electrode on the active region; a source / drain region disposed in the active region between the isolation film and the gate electrode; an isolation contact on the isolation layer, extending in a vertical direction intersecting with an upper surface of the substrate, penetrating the gap-fill insulating layer, and having a lower surface in contact with the etch stop liner; a side surface of the isolation contact spaced apart from the etch stop liner;

10. The semiconductor device of claim 9 , wherein the etch stop liner extends along a profile of the insulating liner.

11. If the source / drain regions contain n-type impurities, a ground voltage or a negative voltage is applied to the isolation contact; 10. The semiconductor device of claim 9, wherein when the source / drain regions contain p-type impurities, a ground voltage or a positive voltage is applied to the isolation contact.

12. 10. The semiconductor device of claim 9, wherein a bottom surface of the isolation contact is spaced apart from a bottom surface of the device isolation film.

13. 13. The semiconductor device of claim 12, wherein the insulating liner and the etch stop liner are interposed between a lower surface of the isolation film and a lower surface of the isolation contact.

14. 13. The semiconductor device according to claim 12, wherein the distance that the isolation contact is spaced from the bottom surface of the isolation film is 100 Å to 4000 Å.

15. the etch stop liner comprises silicon nitride; 10. The semiconductor device according to claim 9, wherein the gap-fill insulating film includes at least one of silicon oxide, silicon carbonitride, and silicon oxycarbonitride.

16. 10. The semiconductor device according to claim 9, wherein the source / drain regions include a lightly doped region of a first conductivity type, and a heavily doped region of the first conductivity type within the lightly doped region.

17. A non-volatile memory device comprising: a first substrate in a peripheral circuit region; and a second substrate in a cell region, a first circuit element and a second circuit element disposed on the first substrate; an element isolation film in the first substrate that separates the first circuit element from the second circuit element; wherein the isolation film includes an insulating liner, an etch stop liner on the insulating liner, and a gap-fill insulating film on the etch stop liner; an isolation contact extending on the isolation layer in a vertical direction intersecting with an upper surface of the first substrate, penetrating the gap-fill insulating layer, and having a lower surface in contact with the etch stop liner; a plurality of word lines sequentially stacked on the second substrate; a channel structure on the second substrate that intersects with a plurality of the word lines; a bit line connected to the channel structure; A voltage is applied to the isolation contact; The nonvolatile memory device, wherein a side of the isolation contact is spaced apart from the etch stop liner.

18. a first source / drain region of the first circuit element electrically connected to one of the plurality of word lines; 18. The nonvolatile memory device of claim 17, wherein a first source / drain region of the second circuit element is electrically connected to one of the plurality of word lines.

19. The nonvolatile memory device of claim 17, wherein the second substrate is stacked on an upper surface of the first substrate.

20. The main board and a nonvolatile memory device including a first substrate in a peripheral circuit region and a second substrate in a cell region on the main substrate; a main controller on the main board, electrically connected to the nonvolatile memory device; The nonvolatile memory device includes a first circuit element and a second circuit element disposed on the first substrate; an element isolation film in the first substrate that separates the first circuit element from the second circuit element; wherein the isolation film includes an insulating liner, an etch stop liner on the insulating liner, and a gap-fill insulating film on the etch stop liner; an isolation contact extending on the isolation layer in a vertical direction intersecting with an upper surface of the first substrate, penetrating the gap-fill insulating layer, and having a lower surface in contact with the etch stop liner; a plurality of word lines sequentially stacked on the second substrate; a channel structure on the second substrate that intersects with a plurality of the word lines; a bit line connected to the channel structure; A voltage is applied to the isolation contact; The electronic system is characterized in that a side of the isolation contact is spaced from the etch stop liner.

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