Light receiving element, manufacturing method thereof, and electronic device

Abstract

The present technology relates to a light-receiving element, a method for manufacturing the same, and an electronic apparatus with which it is possible to obtain high quantum efficiency with respect to infrared light and increased sensitivity. The light-receiving element has a pixel array region formed in a first semiconductor substrate and in which pixels each having a photoelectric conversion region are arrayed in a matrix, the photoelectric conversion region of each pixel being formed of an SiGe region or a Ge region. The present technology may be applied to, for example, a ranging module for measuring the distance to a subject.

Description

[Technical Field]

[0001] The present technology relates to a light receiving element, a manufacturing method thereof, and an electronic device, and more particularly to a light receiving element that can increase quantum efficiency for infrared light and improve sensitivity, a manufacturing method thereof, and an electronic device. [Background technology]

[0002] Distance measurement modules using the indirect ToF (Time of Flight) method are known. In an indirect ToF distance measurement module, light is emitted toward an object, and a light receiving element receives the light reflected from the surface of the object. The light receiving element photoelectrically converts the reflected light to generate signal charges, which are then distributed to, for example, two charge accumulation regions, and calculates the distance from the distribution ratio of these signal charges. A back-illuminated light receiving element has been proposed that improves light receiving characteristics (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2018 / 135320 Summary of the Invention [Problem to be solved by the invention]

[0004] The light used for distance measurement modules is generally in the near-infrared region, which has low quantum efficiency (QE) and low sensor sensitivity when a silicon substrate is used as the semiconductor substrate for the light receiving element.

[0005] The present technology has been made in view of such circumstances, and makes it possible to increase the quantum efficiency for infrared light and improve sensitivity. [Means for solving the problem]

[0006] The light receiving element of the first aspect of the present technology has a pixel array region in which pixels each including a photoelectric conversion region are arranged in a matrix, and the photoelectric conversion region of each pixel of a first semiconductor substrate in which the pixel array region is formed is formed in a SiGe region or a Ge region.

[0007] In a method for manufacturing a light-receiving element according to a second aspect of the present technology, at least a photoelectric conversion region of each pixel in a pixel array region of a semiconductor substrate is formed from a SiGe region or a Ge region.

[0008] An electronic device according to a third aspect of the present technology has a pixel array region in which pixels each including a photoelectric conversion region are arranged in a matrix, and includes a light-receiving element in which the photoelectric conversion region of each pixel of a first semiconductor substrate in which the pixel array region is formed is formed in a SiGe region or a Ge region.

[0009] In the first to third aspects of the present technology, at least the photoelectric conversion region of each pixel in the pixel array region of the semiconductor substrate is formed in a SiGe region or a Ge region.

[0010] The light receiving element and the electronic device may be independent devices or may be a module incorporated into another device. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a schematic configuration example of a light receiving element to which the present technology is applied. [Figure 2] FIG. 2 is a cross-sectional view showing a first configuration example of a pixel. [Figure 3] FIG. 2 is a diagram showing a circuit configuration of a pixel. [Figure 4] 4 is a plan view showing an example of the arrangement of the pixel circuits in FIG. 3. FIG. [Figure 5] FIG. 10 is a diagram illustrating another example of a circuit configuration of a pixel. [Figure 6] FIG. 6 is a plan view showing an example of the arrangement of the pixel circuits in FIG. [Figure 7] FIG. 2 is a plan view showing the arrangement of pixels in a pixel array section. [Figure 8]1A to 1C are diagrams illustrating a first method for forming a SiGe region. [Figure 9] 10A to 10C are diagrams illustrating a second method for forming a SiGe region. [Figure 10] 10A and 10B are plan views showing other examples of forming SiGe regions in pixels. [Figure 11] 11A to 11C are diagrams illustrating a method for forming the pixel in FIG. 10. [Figure 12] FIG. 2 is a schematic perspective view showing an example of a substrate configuration of a light receiving element. [Figure 13] FIG. 1 is a cross-sectional view of a pixel configured with a stacked structure of two substrates. [Figure 14] FIG. 1 is a schematic cross-sectional view of a light-receiving element formed by stacking three semiconductor substrates. [Figure 15] FIG. 10 is a plan view of a pixel in the case of a four-tap pixel structure. [Figure 16] 10A and 10B are diagrams illustrating other examples of forming a SiGe region. [Figure 17] 10A and 10B are diagrams illustrating other examples of forming a SiGe region. [Figure 18] FIG. 10 is a cross-sectional view showing an example of Ge concentration. [Figure 19] FIG. 2 is a block diagram showing a detailed configuration example of a pixel having an AD conversion unit for each pixel. [Figure 20] FIG. 2 is a circuit diagram showing detailed configurations of a comparison circuit and a pixel circuit. [Figure 21] FIG. 2 is a circuit diagram showing connections between outputs of each tap of the pixel circuit and a comparison circuit. [Figure 22] FIG. 10 is a cross-sectional view showing a second configuration example of a pixel. [Figure 23] FIG. 23 is an enlarged cross-sectional view of the pixel transistor and its vicinity in FIG. 22. [Figure 24] FIG. 10 is a cross-sectional view showing a third configuration example of a pixel. [Figure 25] FIG. 10 is a diagram showing the circuit configuration of a pixel in the case of an IR imaging sensor. [Figure 26] FIG. 1 is a cross-sectional view of a pixel in the case of an IR imaging sensor. [Figure 27] FIG. 10 is a diagram illustrating an example of a pixel arrangement in the case of an RGBIR imaging sensor. [Figure 28] FIG. 1 is a cross-sectional view illustrating an example of a color filter layer for an RGBIR imaging sensor. [Figure 29] FIG. 2 is a diagram illustrating an example of a circuit configuration of a SPAD pixel. [Figure 30] FIG. 30 is a diagram illustrating the operation of the SPAD pixel of FIG. 29. [Figure 31] FIG. 10 is a cross-sectional view showing a configuration example in the case of a SPAD pixel. [Figure 32] FIG. 10 is a diagram illustrating an example of a circuit configuration in the case of a CAPD pixel. [Figure 33] FIG. 10 is a cross-sectional view showing a configuration example of a CAPD pixel. [Figure 34] FIG. 1 is a block diagram showing an example configuration of a distance measurement module to which the present technology is applied. [Figure 35] FIG. 1 is a block diagram illustrating an example configuration of a smartphone as an electronic device to which the present technology is applied. [Figure 36] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 37] FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, with reference to the accompanying drawings, a description will be given of an embodiment of the present technology. In this specification and the drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted. The description will be given in the following order. 1. Example of photodetector configuration 2. Cross-sectional view of a first configuration example of a pixel 3. Example of pixel circuit configuration 4. Plan view of pixel 5.Other examples of pixel circuit configurations 6. Plan view of pixel 7. Method for forming GeSi region 8. Modification of the First Configuration Example 9. Example of photodetector board configuration 10. Cross-section of a pixel in the case of a stacked structure 11. Three-layer laminate structure 12.4-tap pixel configuration example 13.Other examples of SiGe region formation 14. Detailed configuration example of pixel area ADC 15. Cross-sectional view of a second configuration example of a pixel 16. Cross-sectional view of a third example of a pixel configuration 17. Example of IR imaging sensor configuration 18. Example of RGBIR imaging sensor configuration 19. SPAD pixel configuration example 20. CAPD pixel configuration example 21. Example of a distance measurement module configuration 22.Examples of electronic device configurations 23. Mobile application examples

[0013] In the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, the drawings may include parts whose dimensional relationships and ratios differ from each other.

[0014] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are read inverted.

[0015] <1. Example of photodetector configuration> FIG. 1 is a block diagram showing a schematic configuration example of a light receiving element to which the present technology is applied.

[0016] The light receiving element 1 shown in FIG. 1 is a distance measurement sensor that outputs distance measurement information using an indirect ToF method.

[0017] The light receiving element 1 receives light (reflected light) that is emitted from a predetermined light source and hits an object and is reflected, and outputs a depth image that stores information about the distance to the object as a depth value. The light emitted from the light source is, for example, infrared light with a wavelength of 780 nm or more, and is pulsed light that is repeatedly turned on and off at a predetermined cycle.

[0018] The light receiving element 1 has a pixel array section 21 formed on a semiconductor substrate (not shown) and a peripheral circuit section, which is composed of, for example, a vertical drive section 22, a column processing section 23, a horizontal drive section 24, and a system control section 25.

[0019] The light receiving element 1 is further provided with a signal processing unit 26 and a data storage unit 27. The signal processing unit 26 and the data storage unit 27 may be mounted on the same board as the light receiving element 1, or may be arranged on a board in a module separate from the light receiving element 1.

[0020] The pixel array section 21 has a configuration in which pixels 10, which generate charges according to the amount of light received and output signals according to the charges, are arranged in a matrix in the row and column directions. That is, the pixel array section 21 has a plurality of pixels 10 that perform photoelectric conversion on incident light and output signals according to the resulting charges. Details of the pixels 10 will be described later with reference to FIG. 2 and subsequent figures.

[0021] Here, the row direction refers to the horizontal arrangement direction of the pixels 10, and the column direction refers to the vertical arrangement direction of the pixels 10. The row direction is the horizontal direction in the drawing, and the column direction is the vertical direction in the drawing.

[0022] In the pixel array unit 21, pixel drive lines 28 are wired in the row direction for each pixel row in the matrix-like pixel arrangement, and two vertical signal lines 29 are wired in the column direction for each pixel column. For example, the pixel drive lines 28 transmit drive signals for driving the pixels 10 when reading out signals. Note that although FIG. 1 shows the pixel drive line 28 as a single line, the number of pixel drive lines 28 is not limited to one. One end of the pixel drive line 28 is connected to an output terminal of the vertical drive unit 22 corresponding to each row.

[0023] The vertical drive unit 22 is configured with a shift register, an address decoder, etc., and drives each pixel 10 of the pixel array unit 21 simultaneously for all pixels or in row units, etc. In other words, the vertical drive unit 22, together with a system control unit 25 that controls the vertical drive unit 22, configures a control circuit that controls the operation of each pixel 10 of the pixel array unit 21.

[0024] Pixel signals output from each pixel 10 in a pixel row in response to drive control by the vertical drive unit 22 are input to the column processing unit 23 through vertical signal lines 29. The column processing unit 23 performs predetermined signal processing on the pixel signals output from each pixel 10 through the vertical signal lines 29, and temporarily stores the pixel signals after signal processing. Specifically, the column processing unit 23 performs signal processing such as noise removal processing and AD (Analog to Digital) conversion processing.

[0025] The horizontal driving unit 24 is configured with a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns in the column processing unit 23. By selective scanning by this horizontal driving unit 24, pixel signals that have been signal-processed for each unit circuit in the column processing unit 23 are sequentially output.

[0026] The system control unit 25 is composed of a timing generator that generates various timing signals, and controls the driving of the vertical driving unit 22, column processing unit 23, horizontal driving unit 24, etc. based on the various timing signals generated by the timing generator.

[0027] The signal processing unit 26 has at least an arithmetic processing function and performs various signal processing such as arithmetic processing based on the pixel signals output from the column processing unit 23. The data storage unit 27 temporarily stores data necessary for signal processing in the signal processing unit 26.

[0028] The light receiving element 1 configured as above has a circuit configuration called a column ADC type in which an AD conversion circuit that performs AD conversion processing in the column processing unit 23 is arranged for each pixel column.

[0029] The light receiving element 1 outputs a depth image in which distance information to an object is stored as a depth value in pixel values. The light receiving element 1 is used, for example, in an in-vehicle system that is mounted on a vehicle and measures the distance to an object outside the vehicle, or in a smartphone or the like and is used for gesture recognition processing that measures the distance to an object such as a user's hand and recognizes the user's gesture based on the measurement result.

[0030] <2. Cross-sectional view of the first configuration example of the pixel> FIG. 2 is a cross-sectional view showing a first configuration example of the pixel 10 arranged in the pixel array section 21. As shown in FIG.

[0031] The light receiving element 1 includes a semiconductor substrate 41 and a multi-layer wiring layer 42 formed on the front surface side (lower side in the figure) of the semiconductor substrate 41.

[0032] The semiconductor substrate 41 is made of, for example, silicon (hereinafter referred to as Si) and is formed to have a thickness of, for example, 1 to 10 μm. In the semiconductor substrate 41, for example, an N-type (second conductivity type) semiconductor region 52 is formed in a P-type (first conductivity type) semiconductor region 51 in a pixel unit, thereby forming a photodiode PD in a pixel unit. Here, the P-type semiconductor region 51 is made of a Si region, which is a substrate material, while the N-type semiconductor region 52 is made of a SiGe region in which germanium (hereinafter referred to as Ge) is added to Si. The SiGe region as the N-type semiconductor region 52 can be formed by implanting Ge into a Si region or by epitaxial growth, as will be described later. Note that the N-type semiconductor region 52 may be made of only Ge, rather than a SiGe region.

[0033] 2 is the back surface of the semiconductor substrate 41, which is the light incident surface onto which light is incident. An anti-reflection film 43 is formed on the upper surface of the back surface side of the semiconductor substrate 41.

[0034] The anti-reflection film 43 has a laminated structure in which, for example, a fixed charge film and an oxide film are laminated, and can be, for example, a high-dielectric-constant (High-k) insulating thin film formed by atomic layer deposition (ALD). Specifically, hafnium oxide (HfO), aluminum oxide (AlO), titanium oxide (TiO), STO (Strontium Titan Oxide), etc. can be used. In the example of FIG. 2, the anti-reflection film 43 is configured by laminating a hafnium oxide film 53, an aluminum oxide film 54, and a silicon oxide film 55.

[0035] An inter-pixel light-shielding film 45 that prevents incident light from entering adjacent pixels is formed on the upper surface of the anti-reflection film 43 at a boundary 44 (hereinafter also referred to as a pixel boundary 44) between adjacent pixels 10 of the semiconductor substrate 41. The material of the inter-pixel light-shielding film 45 may be any material that blocks light, and may be, for example, a metal material such as tungsten (W), aluminum (Al), or copper (Cu).

[0036] A planarization film 46 is formed on the upper surface of the anti-reflection film 43 and the upper surface of the inter-pixel light-shielding film 45, and is made of an insulating film such as silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON), or an organic material such as resin.

[0037] An on-chip lens 47 is formed for each pixel on the upper surface of the planarization film 46. The on-chip lens 47 is made of a resin material such as a styrene-based resin, an acrylic-based resin, a styrene-acrylic copolymer resin, or a siloxane-based resin. The light collected by the on-chip lens 47 is efficiently incident on the photodiode PD.

[0038] A moth-eye structure 71 in which minute projections and depressions are periodically formed is formed above the formation region of the photodiode PD on the rear surface of the semiconductor substrate 41. Corresponding to the moth-eye structure 71 of the semiconductor substrate 41, the anti-reflection film 43 formed on the upper surface thereof also has a moth-eye structure.

[0039] The moth-eye structure 71 of the semiconductor substrate 41 is configured such that, for example, a plurality of quadrangular pyramidal regions of approximately the same shape and size are arranged regularly (in a lattice pattern).

[0040] The moth-eye structure 71 is formed, for example, in an inverted pyramid structure in which a plurality of quadrangular pyramidal regions having an apex on the photodiode PD side are regularly arranged.

[0041] Alternatively, the moth-eye structure 71 may have a regular pyramidal structure in which a plurality of quadrangular pyramidal regions having an apex on the on-chip lens 47 side are arranged in a regular pattern. The sizes and arrangement of the plurality of quadrangular pyramids may be random, rather than arranged in a regular pattern. Furthermore, each concave or convex portion of each quadrangular pyramid of the moth-eye structure 71 may have a certain degree of curvature and be rounded. The moth-eye structure 71 may have any shape as long as it has a structure in which a concave-convex structure is repeated periodically or randomly, and the shape of the concave or convex portions is arbitrary.

[0042] In this way, by forming the moth-eye structure 71 as a diffraction structure that diffracts incident light on the light incident surface of the semiconductor substrate 41, it is possible to mitigate the sudden change in refractive index at the substrate interface and reduce the effects of reflected light.

[0043] In the pixel boundary portion 44 on the back surface side of the semiconductor substrate 41, an inter-pixel isolation portion 61 is formed extending from the back surface side (on-chip lens 47 side) of the semiconductor substrate 41 to a predetermined depth in the substrate depth direction, separating adjacent pixels in the depth direction of the semiconductor substrate 41. The depth in the substrate thickness direction at which the inter-pixel isolation portion 61 is formed may be any depth, and may penetrate from the back surface side to the front surface side of the semiconductor substrate 41 to completely isolate pixels. The outer periphery of the inter-pixel isolation portion 61, including the bottom surface and sidewalls, is covered with a hafnium oxide film 53, which is part of the anti-reflection film 43. The inter-pixel isolation portion 61 prevents incident light from penetrating into adjacent pixels 10, confining it within the pixel itself, and also prevents incident light from leaking in from adjacent pixels 10.

[0044] 2, the silicon oxide film 55, which is the uppermost layer of the anti-reflection film 43, is embedded in a trench (groove) dug from the back surface side to simultaneously form the silicon oxide film 55 and the inter-pixel isolation portion 61, so that the silicon oxide film 55, which is part of the laminated film as the anti-reflection film 43, and the inter-pixel isolation portion 61 are made of the same material, but they do not necessarily have to be the same. The material embedded in the trench (groove) dug from the back surface side as the inter-pixel isolation portion 61 may be a metal material such as tungsten (W), aluminum (Al), titanium (Ti), titanium nitride (TiN), or the like.

[0045] Meanwhile, on the surface side of the semiconductor substrate 41 on which the multilayer wiring layer 42 is formed, two transfer transistors TRG1 and TRG2 are formed for one photodiode PD formed in each pixel 10. Also, on the surface side of the semiconductor substrate 41, floating diffusion regions FD1 and FD2 are formed of a high-concentration N-type semiconductor region (N-type diffusion region) as charge retention units that temporarily retain the charges transferred from the photodiode PD.

[0046] The multilayer wiring layer 42 is composed of a plurality of metal films M and interlayer insulating films 62 therebetween. Although Fig. 2 shows an example in which the multilayer wiring layer 42 is composed of three layers, namely, a first metal film M1 to a third metal film M3, the number of layers of the metal films M is not limited to three.

[0047] Of the multiple metal films M of the multilayer wiring layer 42, the first metal film M1 closest to the semiconductor substrate 41 has a region located below the formation region of the photodiode PD, in other words, a region that at least partially overlaps with the formation region of the photodiode PD in a planar view, in which metal wiring such as copper or aluminum is formed as a light-shielding member 63.

[0048] The light-shielding member 63 blocks infrared light that enters the semiconductor substrate 41 from the light incident surface via the on-chip lens 47 and passes through the semiconductor substrate 41 without being photoelectrically converted within the semiconductor substrate 41, using the first metal film M1 that is closest to the semiconductor substrate 41, and prevents it from passing through the second metal film M2 or the third metal film M3 below. This light-shielding function prevents infrared light that passes through the semiconductor substrate 41 without being photoelectrically converted within the semiconductor substrate 41 from being scattered by the metal films M below the first metal film M1 and entering nearby pixels. This makes it possible to prevent nearby pixels from erroneously detecting light.

[0049] The light-shielding member 63 also has the function of reflecting infrared light that enters the semiconductor substrate 41 from the light incident surface via the on-chip lens 47 and passes through the semiconductor substrate 41 without being photoelectrically converted within the semiconductor substrate 41, thereby allowing the light to enter the semiconductor substrate 41 again. Therefore, the light-shielding member 63 can also be said to function as a reflective member. This reflective function increases the amount of infrared light that is photoelectrically converted within the semiconductor substrate 41, thereby improving the quantum efficiency (QE), that is, the sensitivity of the pixel 10 to infrared light.

[0050] The light blocking member 63 may be made of a metal material, or may have a reflecting or light blocking structure made of polysilicon, an oxide film, or the like.

[0051] Furthermore, the light blocking member 63 may not be configured with a single layer of metal film M, but may be configured with a plurality of metal films M, for example, by forming a first metal film M1 and a second metal film M2 in a grid pattern.

[0052] Among the multiple metal films M of the multilayer wiring layer 42, a predetermined metal film M, for example, the second metal film M2, is patterned into a comb-tooth shape in a plan view, thereby forming a wiring capacitance 64. The light-shielding member 63 and the wiring capacitance 64 may be formed in the same layer (metal film M), but when they are formed in different layers, the wiring capacitance 64 is formed in a layer farther from the semiconductor substrate 41 than the light-shielding member 63. In other words, the light-shielding member 63 is formed closer to the semiconductor substrate 41 than the wiring capacitance 64.

[0053] As described above, the light receiving element 1 has a back-illuminated structure in which the semiconductor substrate 41, which is a semiconductor layer, is disposed between the on-chip lens 47 and the multilayer wiring layer 42, and incident light is made incident on the photodiode PD from the back side on which the on-chip lens 47 is formed.

[0054] In addition, the pixel 10 has two transfer transistors TRG1 and TRG2 for the photodiode PD provided in each pixel, and is configured to be able to distribute the charges (electrons) generated by photoelectric conversion in the photodiode PD to the floating diffusion region FD1 or FD2.

[0055] Furthermore, by forming an inter-pixel separation portion 61 at the pixel boundary portion 44, the pixel 10 prevents incident light from penetrating into an adjacent pixel 10, confining the light within the pixel itself and preventing leakage of incident light from an adjacent pixel 10. By providing a light-shielding member 63 on the metal film M below the formation region of the photodiode PD, infrared light that has passed through the semiconductor substrate 41 without being photoelectrically converted within the semiconductor substrate 41 is reflected by the light-shielding member 63 and made to re-enter the semiconductor substrate 41.

[0056] Furthermore, in the pixel 10, the N-type semiconductor region 52, which is a photoelectric conversion region, is formed of a SiGe region or a Ge region. SiGe and Ge have narrower bandgaps than Si, and therefore can increase the quantum efficiency of near-infrared light.

[0057] With the above configuration, the photodetector 1 having the pixel 10 according to the first configuration example can increase the amount of infrared light that is photoelectrically converted within the semiconductor substrate 41, thereby improving the quantum efficiency (QE), i.e., the sensitivity to infrared light.

[0058] <3. Example of pixel circuit configuration> FIG. 3 shows the circuit configuration of each pixel 10 arranged two-dimensionally in the pixel array section 21.

[0059] Each pixel 10 includes a photodiode PD as a photoelectric conversion element. The pixel 10 also includes two transfer transistors TRG, two floating diffusion regions FD, two additional capacitances FDL, two switching transistors FDG, two amplifying transistors AMP, two reset transistors RST, and two selection transistors SEL. The pixel 10 also includes a charge discharging transistor OFG.

[0060] Here, when distinguishing between the transfer transistors TRG, floating diffusion regions FD, additional capacitances FDL, switching transistors FDG, amplification transistors AMP, reset transistors RST, and selection transistors SEL, which are provided in pairs in each pixel 10, they will be referred to as transfer transistors TRG1 and TRG2, floating diffusion regions FD1 and FD2, additional capacitances FDL1 and FDL2, switching transistors FDG1 and FDG2, amplification transistors AMP1 and AMP2, reset transistors RST1 and RST2, and selection transistors SEL1 and SEL2, as shown in Figure 3.

[0061] The transfer transistor TRG, the switching transistor FDG, the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the charge discharging transistor OFG are configured by, for example, N-type MOS transistors.

[0062] When a transfer drive signal TRG1g supplied to its gate electrode becomes active, the transfer transistor TRG1 becomes conductive in response, thereby transferring the charge accumulated in the photodiode PD to the floating diffusion region FD1. When a transfer drive signal TRG2g supplied to its gate electrode becomes active, the transfer transistor TRG2 becomes conductive in response, thereby transferring the charge accumulated in the photodiode PD to the floating diffusion region FD2.

[0063] The floating diffusion regions FD1 and FD2 are charge holding portions that temporarily hold the charges transferred from the photodiode PD.

[0064] When an FD drive signal FDG1g supplied to its gate electrode becomes active, the switching transistor FDG1 becomes conductive in response, thereby connecting the additional capacitance FDL1 to the floating diffusion region FD1. When an FD drive signal FDG2g supplied to its gate electrode becomes active, the switching transistor FDG2 becomes conductive in response, thereby connecting the additional capacitance FDL2 to the floating diffusion region FD2. The additional capacitances FDL1 and FDL2 are formed by the wiring capacitance 64 in FIG. 2.

[0065] The reset transistor RST1 becomes conductive in response to the reset drive signal RSTg supplied to its gate electrode becoming active, thereby resetting the potential of the floating diffusion region FD1. The reset transistor RST2 becomes conductive in response to the reset drive signal RSTg supplied to its gate electrode becoming active, thereby resetting the potential of the floating diffusion region FD2. When the reset transistors RST1 and RST2 are activated, the switching transistors FDG1 and FDG2 are also simultaneously activated, and the additional capacitances FDL1 and FDL2 are also reset.

[0066] For example, when the illuminance is high and the amount of incident light is large, the vertical drive unit 22 activates the switching transistors FDG1 and FDG2 to connect the floating diffusion region FD1 to the additional capacitance FDL1 and also connect the floating diffusion region FD2 to the additional capacitance FDL2, thereby enabling more charge to be stored during times of high illuminance.

[0067] On the other hand, when the illuminance is low and the amount of incident light is small, the vertical drive unit 22 deactivates the switching transistors FDG1 and FDG2 to disconnect the additional capacitances FDL1 and FDL2 from the floating diffusion regions FD1 and FD2, respectively, thereby increasing the conversion efficiency.

[0068] When a discharge drive signal OFG1g supplied to the gate electrode becomes active, the charge discharge transistor OFG becomes conductive in response to this, thereby discharging the charge accumulated in the photodiode PD.

[0069] The amplifier transistor AMP1 has a source electrode connected to a vertical signal line 29A via a selection transistor SEL1, and is therefore connected to a constant current source (not shown) to form a source follower circuit. The amplifier transistor AMP2 has a source electrode connected to a vertical signal line 29B via a selection transistor SEL2, and is therefore connected to a constant current source (not shown) to form a source follower circuit.

[0070] The selection transistor SEL1 is connected between the source electrode of the amplification transistor AMP1 and the vertical signal line 29A. When a selection signal SEL1g supplied to the gate electrode thereof becomes active, the selection transistor SEL1 becomes conductive in response to this, and outputs the pixel signal VSL1 output from the amplification transistor AMP1 to the vertical signal line 29A.

[0071] The selection transistor SEL2 is connected between the source electrode of the amplification transistor AMP2 and the vertical signal line 29B. When a selection signal SEL2g supplied to the gate electrode thereof becomes active, the selection transistor SEL2 becomes conductive in response to this, and outputs the pixel signal VSL2 output from the amplification transistor AMP2 to the vertical signal line 29B.

[0072] The transfer transistors TRG1 and TRG2, the switching transistors FDG1 and FDG2, the amplification transistors AMP1 and AMP2, the selection transistors SEL1 and SEL2, and the charge discharging transistor OFG of the pixel 10 are controlled by a vertical drive unit 22.

[0073] In the pixel circuit of FIG. 3, the additional capacitors FDL1 and FDL2 and the switching transistors FDG1 and FDG2 that control their connection may be omitted, but by providing the additional capacitor FDL and using it depending on the amount of incident light, a high dynamic range can be ensured.

[0074] The operation of pixel 10 in FIG. 3 will now be briefly described.

[0075] First, before light reception begins, a reset operation is performed on all pixels to reset the charges in the pixels 10. That is, the charge drain transistor OFG, reset transistors RST1 and RST2, and switching transistors FDG1 and FDG2 are turned on, and the charges stored in the photodiode PD, floating diffusion regions FD1 and FD2, and additional capacitances FDL1 and FDL2 are drained.

[0076] After the accumulated charge is discharged, light reception begins in all pixels. During the light reception period, the transfer transistors TRG1 and TRG2 are alternately driven. That is, during a first period, the transfer transistor TRG1 is controlled to be on and the transfer transistor TRG2 is controlled to be off. During this first period, the charge generated in the photodiode PD is transferred to the floating diffusion region FD1. During a second period following the first period, the transfer transistor TRG1 is controlled to be off and the transfer transistor TRG2 is controlled to be on. During this second period, the charge generated in the photodiode PD is transferred to the floating diffusion region FD2. As a result, the charge generated in the photodiode PD is alternately distributed and accumulated in the floating diffusion regions FD1 and FD2.

[0077] Then, when the light reception period ends, each pixel 10 in the pixel array unit 21 is selected line-sequentially. In the selected pixel 10, the selection transistors SEL1 and SEL2 are turned on. As a result, the charge accumulated in the floating diffusion region FD1 is output as a pixel signal VSL1 to the column processing unit 23 via the vertical signal line 29A. The charge accumulated in the floating diffusion region FD2 is output as a pixel signal VSL2 to the column processing unit 23 via the vertical signal line 29B.

[0078] This completes one light receiving operation, and the next light receiving operation is executed, starting with a reset operation.

[0079] The reflected light received by pixel 10 is delayed from the time of illumination by the light source according to the distance to the object. The distribution ratio of the charges accumulated in the two floating diffusion regions FD1 and FD2 changes depending on the delay time according to the distance to the object, so the distance to the object can be calculated from the distribution ratio of the charges accumulated in the two floating diffusion regions FD1 and FD2.

[0080] <4. Plan view of pixel> FIG. 4 is a plan view showing an example of the arrangement of the pixel circuits shown in FIG.

[0081] 4 corresponds to the row direction (horizontal direction) in FIG. 1, and the vertical direction corresponds to the column direction (vertical direction) in FIG.

[0082] As shown in FIG. 4, a photodiode PD is formed in an N-type semiconductor region 52 in the central region of a rectangular pixel 10, and this region is a SiGe region.

[0083] Outside the photodiode PD, along a predetermined one of the four sides of the rectangular pixel 10, the transfer transistor TRG1, switching transistor FDG1, reset transistor RST1, amplification transistor AMP1, and selection transistor SEL1 are arranged in a linear line, and along another one of the four sides of the rectangular pixel 10, the transfer transistor TRG2, switching transistor FDG2, reset transistor RST2, amplification transistor AMP2, and selection transistor SEL2 are arranged in a linear line.

[0084] Furthermore, a charge discharging transistor OFG is arranged on a side other than the two sides of the pixel 10 on which the transfer transistor TRG, the switching transistor FDG, the reset transistor RST, the amplifying transistor AMP, and the selection transistor SEL are formed.

[0085] The arrangement of the pixel circuits shown in FIG. 3 is not limited to this example, and other arrangements may also be used.

[0086] <5. Other examples of pixel circuit configurations> FIG. 5 shows another example of the circuit configuration of the pixel 10.

[0087] In FIG. 5, parts corresponding to those in FIG. 3 are given the same reference numerals, and the description of those parts will be omitted as appropriate.

[0088] The pixel 10 includes a photodiode PD as a photoelectric conversion element, and also includes two first transfer transistors TRGa, two second transfer transistors TRGb, a memory MEM, two floating diffusion regions FD, two reset transistors RST, two amplification transistors AMP, and two selection transistors SEL.

[0089] Here, when distinguishing between the first transfer transistor TRGa, the second transfer transistor TRGb, the memory MEM, the floating diffusion region FD, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL, which are provided in pairs in the pixel 10, they will be referred to as the first transfer transistors TRGa1 and TRGa2, the second transfer transistors TRGb1 and TRGb2, the transfer transistors TRG1 and TRG2, the memories MEM1 and MEM2, the floating diffusion regions FD1 and FD2, the amplification transistors AMP1 and AMP2, and the selection transistors SEL1 and SEL2, as shown in Figure 5.

[0090] 3 and 5, the transfer transistor TRG is changed to two types of first transfer transistor TRGa and second transfer transistor TRGb, a memory MEM is added, and the additional capacitance FDL and switching transistor FDG are omitted.

[0091] The first transfer transistor TRGa, the second transfer transistor TRGb, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are configured, for example, by N-type MOS transistors.

[0092] In the pixel circuit shown in Figure 3, the charge generated in the photodiode PD is transferred to and stored in floating diffusion regions FD1 and FD2, but in the pixel circuit of Figure 5, the charge is transferred to and stored in memories MEM1 and MEM2, which are newly provided as charge storage units.

[0093] That is, when a first transfer drive signal TRGa1g supplied to its gate electrode becomes active, the first transfer transistor TRGa1 becomes conductive in response to this, thereby transferring the charge accumulated in the photodiode PD to the memory MEM1. When a first transfer drive signal TRGa2g supplied to its gate electrode becomes active, the first transfer transistor TRGa2 becomes conductive in response to this, thereby transferring the charge accumulated in the photodiode PD to the memory MEM2.

[0094] In addition, when a second transfer drive signal TRGb1g supplied to its gate electrode becomes active, the second transfer transistor TRGb1 becomes conductive in response to this, thereby transferring the charges held in the memory MEM1 to the floating diffusion region FD1. When a second transfer drive signal TRGb2g supplied to its gate electrode becomes active, the second transfer transistor TRGb2 becomes conductive in response to this, thereby transferring the charges held in the memory MEM2 to the floating diffusion region FD2.

[0095] The reset transistor RST1 becomes conductive in response to a reset drive signal RST1g supplied to its gate electrode becoming active, thereby resetting the potential of the floating diffusion region FD1. The reset transistor RST2 becomes conductive in response to a reset drive signal RST2g supplied to its gate electrode becoming active, thereby resetting the potential of the floating diffusion region FD2. When the reset transistors RST1 and RST2 are activated, the second transfer transistors TRGb1 and TRGb2 are also simultaneously activated, and the memories MEM1 and MEM2 are also reset.

[0096] 5, the charge generated in the photodiode PD is divided and stored in the memories MEM1 and MEM2. Then, at the timing of readout, the charge held in the memories MEM1 and MEM2 is transferred to the floating diffusion regions FD1 and FD2, respectively, and output from the pixel 10.

[0097] <6. Plan view of pixel> FIG. 6 is a plan view showing an example of the arrangement of the pixel circuits shown in FIG.

[0098] 6 corresponds to the row direction (horizontal direction) in FIG. 1, and the vertical direction corresponds to the column direction (vertical direction) in FIG.

[0099] As shown in FIG. 6, an N-type semiconductor region 52 serving as a photodiode PD in a rectangular pixel 10 is formed in a SiGe region.

[0100] Outside the photodiode PD, a first transfer transistor TRGa1, a second transfer transistor TRGb1, a reset transistor RST1, an amplifier transistor AMP1, and a select transistor SEL1 are linearly arranged along a predetermined one of the four sides of the rectangular pixel 10, and a first transfer transistor TRGa2, a second transfer transistor TRGb2, a reset transistor RST2, an amplifier transistor AMP2, and a select transistor SEL2 are linearly arranged along another of the four sides of the rectangular pixel 10. The memories MEM1 and MEM2 are formed, for example, by buried N-type diffusion regions.

[0101] The arrangement of the pixel circuits shown in FIG. 5 is not limited to this example, and other arrangements may also be used.

[0102] 7. Method for forming GeSi region FIG. 7 is a plan view showing an example of an arrangement of 3×3 pixels 10 among the plurality of pixels 10 in the pixel array section 21. As shown in FIG.

[0103] When only the N-type semiconductor region 52 of each pixel 10 is formed of a SiGe region, the SiGe regions are arranged in separate pixel units in the entire region of the pixel array section 21, as shown in FIG.

[0104] FIG. 8 is a cross-sectional view of a semiconductor substrate 41 illustrating a first method for forming an N-type semiconductor region 52 in a SiGe region.

[0105] 8, in the first formation method, Ge ions are selectively implanted using a mask into a portion of the semiconductor substrate 41, which is a Si region, that will become the N-type semiconductor region 52, thereby forming the N-type semiconductor region 52 as a SiGe region. The region of the semiconductor substrate 41 other than the N-type semiconductor region 52 becomes the P-type semiconductor region 51, which is a Si region.

[0106] FIG. 9 is a cross-sectional view of a semiconductor substrate 41 illustrating a second method for forming an N-type semiconductor region 52 in a SiGe region.

[0107] In the second formation method, first, as shown in A of Fig. 9, a portion of the Si region of the semiconductor substrate 41 that will become the N-type semiconductor region 52 is removed. Then, as shown in B of Fig. 9, a SiGe layer is epitaxially grown in the removed region, thereby forming the N-type semiconductor region 52 in the SiGe region.

[0108] Note that FIG. 9 shows an example in which the pixel transistors are arranged in a different manner from the arrangement shown in FIG. 4, and the amplification transistor AMP1 is arranged near an N-type semiconductor region 52 formed in a SiGe region.

[0109] As described above, the N-type semiconductor region 52, which is a SiGe region, can be formed by either the first formation method of implanting Ge ions into a Si region or the second formation method of epitaxially growing a SiGe layer. The N-type semiconductor region 52 can also be formed in a Ge region by a similar method.

[0110] 8. Modification of the First Configuration Example In the pixel 10 according to the first configuration example described above, only the N-type semiconductor region 52, which is the photoelectric conversion region in the semiconductor substrate 41, is formed from a SiGe region or a Ge region, but the P-type semiconductor region 51 below the gate of the transfer transistor TRG may also be formed from a P-type SiGe region or a Ge region.

[0111] Figure 10 is a diagram again showing the planar layout of the pixel circuit of Figure 3 shown in Figure 4, in which P-type regions 81 below the gates of transfer transistors TRG1 and TRG2, indicated by dashed lines in Figure 10, are formed of SiGe or Ge regions. By forming the channel regions of transfer transistors TRG1 and TRG2 from SiGe or Ge regions, it is possible to increase the channel mobility in transfer transistors TRG1 and TRG2, which are driven at high speed.

[0112] When epitaxial growth is used to form the channel regions of the transfer transistors TRG1 and TRG2 as SiGe regions, first, a portion of the semiconductor substrate 41 to be formed as an N-type semiconductor region 52 and portions below the gates of the transfer transistors TRG1 and TRG2 are removed, as shown in A of Fig. 11. Then, as shown in B of Fig. 11, a SiGe layer is formed by epitaxial growth in the removed regions, so that the N-type semiconductor region 52 and the regions below the gates of the transfer transistors TRG1 and TRG2 are formed as SiGe regions.

[0113] Here, forming floating diffusion regions FD1 and FD2 in the formed SiGe region causes a problem of increased dark current generated from the floating diffusion region FD. Therefore, when the transfer transistor TRG formation region is made into a SiGe region, a structure is adopted in which an additional Si layer is formed by epitaxial growth on the formed SiGe layer, and a high-concentration N-type semiconductor region (N-type diffusion region) is formed to form the floating diffusion region FD, as shown in B of Figure 11. This makes it possible to suppress the dark current from the floating diffusion region FD.

[0114] Instead of epitaxial growth, the P-type semiconductor region 51 under the gate of the transfer transistor TRG may be made into a SiGe region by selective ion implantation using a mask, and in this case as well, a further Si layer can be formed on the formed SiGe layer by epitaxial growth to form floating diffusion regions FD1 and FD2.

[0115] <9. Example of photodetector board configuration> FIG. 12 is a schematic perspective view showing an example of the substrate configuration of the light receiving element 1. As shown in FIG.

[0116] The light receiving element 1 may be formed on one semiconductor substrate or on multiple semiconductor substrates.

[0117] FIG. 12A shows a schematic configuration example in which the light receiving element 1 is formed on one semiconductor substrate.

[0118] 12A, a pixel array region 111 corresponding to the pixel array section 21 and a logic circuit region 112 corresponding to circuits other than the pixel array section 21, such as control circuits such as the vertical drive section 22 and horizontal drive section 24, and arithmetic circuits of the column processing section 23 and signal processing section 26, are aligned in the planar direction and formed on the single semiconductor substrate 41. The cross-sectional configuration shown in FIG. 2 is the configuration of this single substrate.

[0119] On the other hand, FIG. 12B shows a schematic configuration example in which the light receiving elements 1 are formed on a plurality of semiconductor substrates.

[0120] When the light receiving element 1 is formed on multiple semiconductor substrates, as shown in B of Figure 12, the pixel array region 111 is formed on a semiconductor substrate 41, while the logic circuit region 112 is formed on another semiconductor substrate 141, and is configured by stacking the semiconductor substrate 41 and the semiconductor substrate 141.

[0121] In the following description, for ease of understanding, the semiconductor substrate 41 in the case of a stacked structure will be referred to as the first substrate 41, and the semiconductor substrate 141 will be referred to as the second substrate 141.

[0122] <10. Cross-section of a pixel in the case of a stacked structure> FIG. 13 shows a cross-sectional view of a pixel 10 in the case where the light receiving element 1 has a laminated structure of two substrates.

[0123] In FIG. 13, parts corresponding to those in the first configuration example shown in FIG. 2 are given the same reference numerals, and the description of those parts will be omitted as appropriate.

[0124] The stacked structure of FIG. 13 is configured using two semiconductor substrates, a first substrate 41 and a second substrate 141, as described with reference to FIG.

[0125] 13, an inter-pixel light-shielding film 45, a planarizing film 46, an on-chip lens 47, and a moth-eye structure 71 are formed on the light incident surface side of the first substrate 41, which is similar to the first configuration example of FIG. 2. An inter-pixel isolation portion 61 is also formed in a pixel boundary portion 44 on the back surface side of the first substrate 41, which is similar to the first configuration example of FIG.

[0126] Also, the same applies in that photodiodes PD are formed on the first substrate 41 in pixel units, and two transfer transistors TRG1 and TRG2 and floating diffusion regions FD1 and FD2 as charge storage sections are formed on the front surface side of the first substrate 41.

[0127] 2, an insulating layer 153 that is part of the wiring layer 151 on the front surface side of the first substrate 41 is bonded to an insulating layer 152 of the second substrate 141.

[0128] The wiring layer 151 of the first substrate 41 includes at least one layer of metal film M, and the metal film M is used to form a light blocking member 63 in a region located below the region where the photodiode PD is formed.

[0129] Pixel transistors Tr1 and Tr2 are formed on the interface opposite to the insulating layer 152 side, which is the bonding surface side of the second substrate 141. The pixel transistors Tr1 and Tr2 are, for example, an amplification transistor AMP or a selection transistor SEL.

[0130] That is, in the first configuration example configured using only one semiconductor substrate 41 (first substrate 41), all pixel transistors, namely, the transfer transistor TRG, the switching transistor FDG, the amplification transistor AMP, and the selection transistor SEL, were formed on the semiconductor substrate 41, but in the light receiving element 1 having a stacked structure of two semiconductor substrates, the pixel transistors other than the transfer transistor TRG, namely, the switching transistor FDG, the amplification transistor AMP, and the selection transistor SEL, are formed on the second substrate 141.

[0131] A wiring layer 161 having at least two layers of metal films M is formed on the surface of the second substrate 141 opposite to the first substrate 41 side. The wiring layer 161 includes a first metal film M11, a second metal film M12, and an insulating layer 173.

[0132] A transfer drive signal TRG1g that controls the transfer transistor TRG1 is supplied from a first metal film M11 of the second substrate 141 to the gate electrode of the transfer transistor TRG1 of the first substrate 41 via a TSV (Through Silicon Via) 171-1 that penetrates the second substrate 141. A transfer drive signal TRG2g that controls the transfer transistor TRG2 is supplied from a first metal film M11 of the second substrate 141 to the gate electrode of the transfer transistor TRG2 of the first substrate 41 via a TSV 171-2 that penetrates the second substrate 141.

[0133] Similarly, the charge accumulated in the floating diffusion region FD1 is transferred from the first substrate 41 side to the first metal film M11 of the second substrate 141 by the TSV 172-1 that penetrates the second substrate 141. The charge accumulated in the floating diffusion region FD2 is also transferred from the first substrate 41 side to the first metal film M11 of the second substrate 141 by the TSV 172-2 that penetrates the second substrate 141.

[0134] The wiring capacitance 64 is formed in a region (not shown) of the first metal film M11 or the second metal film M12. The metal film M on which the wiring capacitance 64 is formed is formed with a high wiring density to form capacitance, while the metal film M connected to the gate electrodes of the transfer transistor TRG, switching transistor FDG, etc. is formed with a low wiring density to reduce induced current. The wiring layer (metal film M) connected to the gate electrode may be configured to differ for each pixel transistor.

[0135] As described above, the pixel 10 can be configured by stacking two semiconductor substrates, the first substrate 41 and the second substrate 141, and pixel transistors other than the transfer transistor TRG are formed on the second substrate 141, which is different from the first substrate 41 having the photoelectric conversion unit. In addition, the vertical drive unit 22 that controls the driving of the pixel 10, the pixel drive lines 28, the vertical signal lines 29 that transmit pixel signals, and the like are also formed on the second substrate 141. This allows the pixels to be miniaturized, and also increases the degree of freedom in BEOL (Back End Of Line) design.

[0136] In the pixel 10 of FIG. 13, by adopting a back-illuminated pixel structure, a sufficient aperture ratio can be ensured compared to the front-illuminated pixel structure, and the quantum efficiency (QE) × aperture ratio (FF) can be maximized.

[0137] Furthermore, by providing a light-shielding member (reflecting member) 63 in a region overlapping with the formation region of the photodiode PD of the wiring layer 151 closest to the first substrate 41, infrared light that has passed through the semiconductor substrate 41 without being photoelectrically converted within the semiconductor substrate 41 can be reflected by the light-shielding member 63 and made to re-enter the semiconductor substrate 41. Furthermore, it is possible to prevent infrared light that has passed through the semiconductor substrate 41 without being photoelectrically converted within the semiconductor substrate 41 from entering the second substrate 141 side.

[0138] In the pixel 10 of FIG. 13, the N-type semiconductor region 52 that constitutes the photodiode PD is also formed in a SiGe region or a Ge region, so that the quantum efficiency of near-infrared light can be improved.

[0139] According to the pixel structure described above, the amount of infrared light that is photoelectrically converted within the semiconductor substrate 41 can be increased, the quantum efficiency (QE) can be increased, and the sensitivity of the sensor can be improved.

[0140] <11. Three-layer laminate structure> FIG. 13 shows an example in which the light receiving element 1 is configured with two semiconductor substrates, but it may be configured with three semiconductor substrates.

[0141] FIG. 14 is a schematic cross-sectional view of a light-receiving element 1 formed by stacking three semiconductor substrates.

[0142] In FIG. 14, parts corresponding to those in FIG. 12 are given the same reference numerals, and the description of those parts will be omitted as appropriate.

[0143] The pixel 10 in FIG. 14 is configured by stacking another semiconductor substrate 181 (hereinafter referred to as the third substrate 181) on the first substrate 41 and the second substrate 141.

[0144] At least a photodiode PD and a transfer transistor TRG are formed on the first substrate 41. An N-type semiconductor region 52 that constitutes the photodiode PD is formed in a SiGe region or a Ge region.

[0145] On the second substrate 141, pixel transistors other than the transfer transistor TRG, such as an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL, are formed.

[0146] On the third substrate 181, signal circuits such as the column processing section 23 and the signal processing section 26 that process pixel signals output from the pixels 10 are formed.

[0147] The first substrate 41 has an on-chip lens 47 formed on the back surface opposite to the front surface on which the wiring layer 151 is formed, and is a back-illuminated type in which light is incident from the back surface side of the first substrate 41.

[0148] The wiring layer 151 of the first substrate 41 is bonded to the wiring layer 161 on the front surface side of the second substrate 141 by Cu-Cu bonding.

[0149] Second substrate 141 and third substrate 181 are bonded together by Cu-Cu bonding between a Cu film formed on wiring layer 182 on the front surface side of third substrate 181 and a Cu film formed on insulating layer 152 of second substrate 141. Wiring layer 161 of second substrate 141 and wiring layer 182 of third substrate 181 are electrically connected via through electrodes 163.

[0150] In the example of Figure 14, the wiring layer 161 on the front surface of the second substrate 141 is bonded so as to face the wiring layer 151 of the first substrate 41, but the second substrate 141 may be flipped upside down and bonded so that the wiring layer 161 of the second substrate 141B faces the wiring layer 182 of the third substrate 181.

[0151] <12.4 tap pixel configuration example> The pixel 10 described above has a pixel structure called a two-tap structure, in which two transfer transistors TRG1 and TRG2 are used as transfer gates for one photodiode PD, and two floating diffusion regions FD1 and FD2 are used as charge storage sections, and the charge generated in the photodiode PD is distributed to the two floating diffusion regions FD1 and FD2.

[0152] In contrast, pixel 10 can have a four-tap pixel structure in which four transfer transistors TRG1 to TRG4 and floating diffusion regions FD1 to FD4 are provided for one photodiode PD, and the charge generated in the photodiode PD is distributed to the four floating diffusion regions FD1 to FD4.

[0153] FIG. 15 is a plan view of the memory MEM retention type pixel 10 shown in FIGS. 5 and 6 when it has a four-tap pixel structure.

[0154] The pixel 10 has four first transfer transistors TRGa, four second transfer transistors TRGb, four reset transistors RST, four amplification transistors AMP, and four selection transistors SEL.

[0155] Outside the photodiode PD, along each of the four sides of the rectangular pixel 10, a set of a first transfer transistor TRGa, a second transfer transistor TRGb, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL is arranged in a linear array.

[0156] In Figure 15, each set of a first transfer transistor TRGa, a second transfer transistor TRGb, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL arranged along each of the four sides of a rectangular pixel 10 is distinguished by assigning a number from 1 to 4.

[0157] When pixel 10 has a two-tap structure, the phase (light-receiving timing) of the first tap and the second tap are shifted by 180 degrees, thereby distributing the generated charge to two floating diffusion regions FD. In contrast, when pixel 10 has a four-tap structure, the phase (light-receiving timing) of the first to fourth taps are shifted by 90 degrees, thereby distributing the generated charge to four floating diffusion regions FD. Then, the distance to the object can be calculated based on the distribution ratio of the charges accumulated in the four floating diffusion regions FD.

[0158] As described above, the pixel 10 can be configured to distribute the charge generated by the photodiode PD over two taps or four taps, and can be configured to distribute the charge over three taps or more, rather than just two taps. Note that even if the pixel 10 has a one-tap structure, the distance to the object can be determined by shifting the phase on a frame-by-frame basis.

[0159] <13. Other examples of forming SiGe regions> In the above-described configuration example of the light receiving element 1, a configuration has been described in which a portion of each pixel 10, specifically, only the N-type semiconductor region 52 of the photodiode PD, which is the photoelectric conversion region, or the N-type semiconductor region 52 and the channel region below the gate of the transfer transistor TRG, is made of SiGe. In this case, the SiGe region is provided separately for each pixel, as shown in FIG.

[0160] 16 and 17, a configuration will be described in which the entire pixel array region 111 (pixel array section 21) is an SiGe region.

[0161] FIG. 16 shows a configuration example in which the entire pixel array region 111 is a SiGe region when the light receiving element 1 is formed on one semiconductor substrate as shown in A of FIG.

[0162] 16A is a plan view of a semiconductor substrate 41 in which a pixel array region 111 and a logic circuit region 112 are formed on the same substrate.

[0163] As shown in FIG. 16A, the entire pixel array region 111 can be a SiGe region, and other regions such as a logic circuit region 112 are Si regions.

[0164] As shown in B of Figure 16, the pixel array region 111 formed in the SiGe region can be formed entirely in the SiGe region by ion-implanting Ge into the portion of the semiconductor substrate 41, which is a Si region, that will become the pixel array region 111.

[0165] FIG. 17 shows a configuration example in which the entire pixel array region 111 is a SiGe region when the light receiving element 1 has the stacked structure of two semiconductor substrates shown in FIG. 12B.

[0166] 17A is a plan view of a first substrate 41 (semiconductor substrate 41) of the two semiconductor substrates, and FIG.

[0167] As shown in A of FIG. 17, the entire pixel array region 111 formed on the first substrate 41 is a SiGe region.

[0168] As shown in B of FIG. 17, the pixel array region 111 formed in the SiGe region can be formed entirely in the SiGe region by ion-implanting Ge into the portion of the semiconductor substrate 41, which is a Si region, that will become the pixel array region 111.

[0169] Note that, when the entire pixel array region 111 is made of a SiGe region, the SiGe region may be formed so that the Ge concentration varies in the depth direction of the first substrate 41. Specifically, as shown in Fig. 18, the SiGe region can be formed by providing a gradient in the Ge concentration depending on the substrate depth, such that the Ge concentration is higher on the light incident surface side where the on-chip lenses 47 are formed and becomes thinner toward the pixel transistor formation surface.

[0170] For example, the portion with a higher concentration on the light incident surface side can have a Si:Ge ratio of 2:8 (Si:Ge=2:8) and a substrate concentration of 4E+22 / cm3, while the portion with a lower concentration near the pixel transistor formation surface can have a Si:Ge ratio of 8:2 (Si:Ge=8:2) and a substrate concentration of 1E+22 / cm3, and the concentration in the entire pixel array region 111 can be in the range of 1E+22 to 4E+22 / cm3.

[0171] The concentration can be controlled, for example, by controlling the implantation energy during ion implantation to select the implantation depth, or by using a mask to select the implantation region (region in the planar direction). Naturally, a higher Ge concentration can increase the quantum efficiency of infrared light.

[0172] <14. Detailed configuration example of pixel area ADC> 16 to 18, if not only the photodiode PD (N-type semiconductor region 52) but the entire pixel array region 111 is made of SiGe, there is a concern that the dark current in the floating diffusion region FD may deteriorate. One of the measures to prevent the dark current in the floating diffusion region FD from worsening is to form a Si layer on the SiGe region to serve as the floating diffusion region FD, as shown in FIG.

[0173] As another measure to prevent the dark current from deteriorating in the floating diffusion region FD, a pixel area ADC configuration can be adopted in which an AD conversion unit is provided for each pixel or for each nearby nxn pixel unit (n is an integer greater than or equal to 1), rather than performing AD conversion for each column of pixels 10 as shown in Figure 1. By adopting the pixel area ADC configuration, the time for which charges are held in the floating diffusion region FD can be shortened compared to the column ADC type shown in Figure 1, thereby suppressing the dark current from deteriorating in the floating diffusion region FD.

[0174] 19 and 20, the configuration of the light receiving element 1 in which an AD conversion unit is provided for each pixel will be described.

[0175] FIG. 19 is a block diagram showing a detailed configuration example of a pixel 10 provided with an AD conversion unit for each pixel.

[0176] A pixel 10 is composed of a pixel circuit 201 and an ADC (AD conversion unit) 202. When an AD conversion unit is provided not in units of pixels but in units of nxn pixels, one ADC 202 is provided for nxn pixel circuits 201.

[0177] The pixel circuit 201 outputs a charge signal according to the amount of received light as an analog pixel signal SIG to the ADC 202. The ADC 202 converts the analog pixel signal SIG supplied from the pixel circuit 201 into a digital signal.

[0178] The ADC 202 is composed of a comparison circuit 211 and a data storage unit 212 .

[0179] The comparator circuit 211 compares a reference signal REF supplied from a DAC 241 provided as a peripheral circuit unit with a pixel signal SIG from the pixel circuit 201, and outputs an output signal VCO as a comparison result signal representing the comparison result. When the reference signal REF and the pixel signal SIG become the same (at the same voltage), the comparator circuit 211 inverts the output signal VCO.

[0180] The comparison circuit 211 is configured by a differential input circuit 221, a voltage conversion circuit 222, and a positive feedback circuit (PFB) 223, the details of which will be described later with reference to FIG.

[0181] The data storage unit 212 receives the output signal VCO from the comparison circuit 211, as well as a WR signal indicating a write operation of a pixel signal, an RD signal indicating a read operation of a pixel signal, and a WORD signal that controls the read timing of the pixel 10 during the read operation of a pixel signal, all from the vertical drive unit 22. In addition, a time code generated by a time code generation unit (not shown) in the peripheral circuit unit is supplied via a time code transfer unit 242 provided as part of the peripheral circuit unit.

[0182] The data storage unit 212 is made up of a latch control circuit 231 that controls the write and read operations of the time code based on the WR signal and the RD signal, and a latch storage unit 232 that stores the time code.

[0183] In the time code write operation, the latch control circuit 231 stores the time code, which is supplied from the time code transfer unit 242 and updated every unit time, in the latch storage unit 232 while a Hi (High) output signal VCO is being input from the comparison circuit 211. Then, when the reference signal REF and the pixel signal SIG become the same (at the same voltage) and the output signal VCO supplied from the comparison circuit 211 is inverted to Lo (Low), the latch control circuit 231 stops writing (updating) the supplied time code and causes the latch storage unit 232 to hold the time code finally stored in the latch storage unit 232. The time code stored in the latch storage unit 232 represents the time when the pixel signal SIG and the reference signal REF became equal, and represents a digitized light intensity value.

[0184] After the sweep of the reference signal REF is completed and the time codes are stored in the latch storage units 232 of all the pixels 10 in the pixel array unit 21, the operation of the pixels 10 is changed from a write operation to a read operation.

[0185] In the time code readout operation, when the readout timing of a pixel 10 arrives, the latch control circuit 231 outputs the time code (digital pixel signal SIG) stored in the latch storage unit 232 to the time code transfer unit 242 based on a WORD signal that controls the readout timing. The time code transfer unit 242 sequentially transfers the supplied time code in the column direction (vertical direction) and supplies it to the signal processing unit 26.

[0186] <Example of detailed configuration of comparison circuit> FIG. 20 is a circuit diagram showing a detailed configuration of the differential input circuit 221, the voltage conversion circuit 222, and the positive feedback circuit 223 that constitute the comparison circuit 211, and the pixel circuit 201.

[0187] Due to space limitations, FIG. 20 shows a circuit corresponding to one tap of the pixel 10, which is configured with two taps.

[0188] The differential input circuit 221 compares the pixel signal SIG of one tap output from the pixel circuit 201 in the pixel 10 with the reference signal REF output from the DAC 241, and outputs a predetermined signal (current) when the pixel signal SIG is higher than the reference signal REF.

[0189] The differential input circuit 221 is composed of transistors 281 and 282 forming a differential pair, transistors 283 and 284 forming a current mirror, a transistor 285 as a constant current source for supplying a current IB corresponding to the input bias current Vb, and a transistor 286 for outputting the output signal HVO of the differential input circuit 221.

[0190] The transistors 281, 282, and 285 are composed of NMOS (Negative Channel MOS) transistors, and the transistors 283, 284, and 286 are composed of PMOS (Positive Channel MOS) transistors.

[0191] Among the transistors 281 and 282 forming a differential pair, the reference signal REF output from the DAC 241 is input to the gate of the transistor 281, and the pixel signal SIG output from the pixel circuit 201 in the pixel 10 is input to the gate of the transistor 282. The sources of the transistors 281 and 282 are connected to the drain of the transistor 285, and the source of the transistor 285 is connected to a predetermined voltage VSS (VSS < VDD2 < VDD1).

[0192] The drain of the transistor 281 is connected to the gates of the transistors 283 and 284 forming a current mirror circuit and the drain of the transistor 283, and the drain of the transistor 282 is connected to the drain of the transistor 284 and the gate of the transistor 286. The sources of the transistors 283, 284, and 286 are connected to the first power supply voltage VDD1.

[0193] The voltage conversion circuit 222 is configured, for example, with an NMOS transistor 291. The drain of the transistor 291 is connected to the drain of the transistor 286 of the differential input circuit 221, the source of the transistor 291 is connected to a predetermined connection point within the positive feedback circuit 223, and the gate of the transistor 286 is connected to the bias voltage VBIAS.

[0194] The transistors 281 to 286 that make up the differential input circuit 221 are circuits that operate at high voltages up to a first power supply voltage VDD1, and the positive feedback circuit 223 is a circuit that operates at a second power supply voltage VDD2 that is lower than the first power supply voltage VDD1. The voltage conversion circuit 222 converts the output signal HVO input from the differential input circuit 221 into a low-voltage signal (converted signal) LVI that allows the positive feedback circuit 223 to operate, and supplies the low-voltage signal to the positive feedback circuit 223.

[0195] The bias voltage VBIAS may be any voltage that converts the transistors 301 to 307 of the positive feedback circuit 223, which operates at a low voltage, into a voltage that does not destroy them. For example, the bias voltage VBIAS may be the same voltage as the second power supply voltage VDD2 of the positive feedback circuit 223 (VBIAS=VDD2).

[0196] The positive feedback circuit 223 outputs a comparison result signal that is inverted when the pixel signal SIG is higher than the reference signal REF, based on a converted signal LVI obtained by converting the output signal HVO from the differential input circuit 221 into a signal corresponding to the second power supply voltage VDD2. The positive feedback circuit 223 also increases the transition speed when the output signal VCO output as the comparison result signal is inverted.

[0197] The positive feedback circuit 223 is composed of seven transistors 301 to 307. The transistors 301, 302, 304, and 306 are composed of PMOS transistors, and the transistors 303, 305, and 307 are composed of NMOS transistors.

[0198] The source of transistor 291, which is the output terminal of voltage conversion circuit 222, is connected to the drains of transistors 302 and 303 and the gates of transistors 304 and 305. The source of transistor 301 is connected to a second power supply voltage VDD2, the drain of transistor 301 is connected to the source of transistor 302, and the gate of transistor 302 is connected to the drains of transistors 304 and 305, which are also the output terminal of positive feedback circuit 223. The sources of transistors 303 and 305 are connected to a predetermined voltage VSS. An initialization signal INI is supplied to the gates of transistors 301 and 303.

[0199] The transistors 304 to 307 form a two-input NOR circuit, and the connection point between the drains of the transistors 304 and 305 serves as the output terminal from which the comparator circuit 211 outputs the output signal VCO.

[0200] The gate of the transistor 306 configured as a PMOS transistor and the gate of the transistor 307 configured as an NMOS transistor are supplied with the control signal TERM as the second input, rather than the conversion signal LVI as the first input.

[0201] The source of the transistor 306 is connected to the second power supply voltage VDD2, and the drain of the transistor 306 is connected to the source of the transistor 304. The drain of the transistor 307 is connected to the output terminal of the comparison circuit 211, and the source of the transistor 307 is connected to a predetermined voltage VSS.

[0202] The operation of the comparator circuit 211 configured as above will be described.

[0203] First, the reference signal REF is set to a voltage higher than the pixel signals SIG of all the pixels 10, and the initialization signal INI is set to Hi, thereby initializing the comparison circuit 211.

[0204] More specifically, a reference signal REF is applied to the gate of transistor 281, and a pixel signal SIG is applied to the gate of transistor 282. When the voltage of the reference signal REF is higher than the voltage of the pixel signal SIG, most of the current output by transistor 285, which serves as a current source, flows through transistor 281 to diode-connected transistor 283. The channel resistance of transistor 284, which shares a gate with transistor 283, becomes sufficiently low, keeping the gate of transistor 286 at approximately the level of the first power supply voltage VDD1, and transistor 286 is turned off. Therefore, even if transistor 291 of voltage conversion circuit 222 is turned on, the positive feedback circuit 223, which functions as a charging circuit, does not charge the conversion signal LVI. Meanwhile, because a high signal is supplied as the initialization signal INI, transistor 303 is turned on, and the positive feedback circuit 223 discharges the conversion signal LVI. Furthermore, because transistor 301 is turned off, the positive feedback circuit 223 does not charge the conversion signal LVI via transistor 302. As a result, the conversion signal LVI is discharged to the predetermined voltage VSS level, and the positive feedback circuit 223 outputs the Hi output signal VCO through the transistors 304 and 305 that form the NOR circuit, and the comparison circuit 211 is initialized.

[0205] After the initialization, the initialization signal INI is set to Lo, and the sweep of the reference signal REF begins.

[0206] During the period when the reference signal REF is at a higher voltage than the pixel signal SIG, the transistor 286 is turned off and thus cut off, and the output signal VCO is a high signal, so the transistor 302 is also turned off and cut off. The transistor 303 is also cut off because the initialization signal INI is low. The conversion signal LVI remains in a high impedance state and maintains a predetermined voltage VSS, and a high output signal VCO is output.

[0207] When the reference signal REF becomes lower than the pixel signal SIG, the output current of transistor 285 of the current source stops flowing through transistor 281, the gate potentials of transistors 283 and 284 rise, and the channel resistance of transistor 284 increases. Then, the current flowing through transistor 282 causes a voltage drop, lowering the gate potential of transistor 286, and transistor 291 becomes conductive. The output signal HVO output from transistor 286 is converted into a conversion signal LVI by transistor 291 of the voltage conversion circuit 222 and supplied to the positive feedback circuit 223. The positive feedback circuit 223, which functions as a charging circuit, charges the conversion signal LVI and brings the potential closer to the second power supply voltage VDD2 from the low voltage VSS.

[0208] When the voltage of the conversion signal LVI exceeds the threshold voltage of the inverter formed by transistors 304 and 305, the output signal VCO becomes Lo and transistor 302 becomes conductive. Transistor 301 is also conductive because a Lo initialization signal INI is applied to it, and the positive feedback circuit 223 rapidly charges the conversion signal LVI via transistors 301 and 302, raising the potential up to the second power supply voltage VDD2 in one go.

[0209] Since the bias voltage VBIAS is applied to the gate of the transistor 291 in the voltage conversion circuit 222, the transistor 291 cuts off when the voltage of the conversion signal LVI reaches a voltage value that is lower than the bias voltage VBIAS by the transistor threshold value. Even if the transistor 286 remains conductive, the conversion signal LVI will not be charged any further, and the voltage conversion circuit 222 also functions as a voltage clamp circuit.

[0210] The charging of the conversion signal LVI due to the conduction of transistor 302 is a positive feedback operation that accelerates the conversion signal LVI's rise to the inverter threshold. Because a large number of circuits simultaneously operate in parallel in the light receiving element 1, transistor 285, which serves as the current source for the differential input circuit 221, draws an extremely small current per circuit. Furthermore, the reference signal REF sweeps very slowly because the voltage that changes per unit time when the time code switches corresponds to the LSB step of the AD conversion. Therefore, the gate potential of transistor 286 changes slowly, and the output current of transistor 286 driven by this voltage also changes slowly. However, applying positive feedback from a subsequent stage to the conversion signal LVI, which is charged by the output current, allows the output signal VCO to transition sufficiently quickly. Desirably, the transition time of the output signal VCO is a fraction of the unit time of the time code, typically less than 1 ns. The comparator circuit 211 can achieve this output transition time by simply setting a small current, for example, 0.1 μA, in the current source transistor 285.

[0211] When the control signal TERM, which is the second input of the NOR circuit, is set to Hi, the output signal VCO can be set to Lo regardless of the state of the differential input circuit 221.

[0212] For example, if the voltage of the pixel signal SIG falls below the final voltage of the reference signal REF due to an unexpectedly high luminance, the output signal VCO of the comparator circuit 211 will end the comparison period at a high level, and the data storage unit 212 controlled by the output signal VCO will be unable to fix the value and will lose its AD conversion function. To prevent this from occurring, a high-pulse control signal TERM can be input at the end of the sweep of the reference signal REF to forcibly invert the output signal VCO that has not yet been inverted to low. Since the data storage unit 212 stores (latches) the time code immediately before the forced inversion, when the configuration of Figure 20 is adopted, the ADC 202 will function as an AD converter that clamps the output value for input luminance above a certain level.

[0213] When the bias voltage VBIAS is controlled to a low level to shut off the transistor 291 and set the initialization signal INI to a high level, the output signal VCO goes high regardless of the state of the differential input circuit 221. Therefore, by combining this forced high output of the output signal VCO with the forced low output by the control signal TERM described above, the output signal VCO can be set to any value regardless of the state of the differential input circuit 221 and the pixel circuit 201 and DAC 241 that precede it. This function makes it possible, for example, to test circuits downstream from the pixel 10 using only electrical signal inputs, without relying on optical input to the light receiving element 1.

[0214] FIG. 21 is a circuit diagram showing the connection between the output of each tap of the pixel circuit 201 and the differential input circuit 221 of the comparison circuit 211.

[0215] As shown in FIG. 21, the output destination of each tap of the pixel circuit 201 is connected to the differential input circuit 221 of the comparison circuit 211 shown in FIG.

[0216] The pixel circuit 201 in FIG. 20 is equivalent to the pixel circuit 201 in FIG. 21, and has the same circuit configuration as the pixel 10 shown in FIG.

[0217] When the pixel area ADC configuration is adopted, the number of circuits per pixel or nxn pixel unit (n is an integer equal to or greater than 1) increases, so the light receiving element 1 is configured with the stacked structure shown in FIG. 12B. In this case, for example, as shown in FIG. 21, the pixel circuit 201 and transistors 281, 282, and 285 of the differential input circuit 221 can be arranged on the first substrate 41, and the other circuits can be arranged on the second substrate 141. The first substrate 41 and the second substrate 141 are electrically connected by Cu-Cu bonding. Note that the circuit arrangement on the first substrate 41 and the second substrate 141 is not limited to this example.

[0218] As described above, by adopting the pixel area ADC configuration as a countermeasure to the deterioration of dark current in the floating diffusion region FD when the entire pixel array region 111 is made of a SiGe region, the time required to accumulate charge in the floating diffusion region FD can be made shorter than with the column ADC in Figure 1, and therefore the deterioration of dark current in the floating diffusion region FD can be suppressed.

[0219] <15. Cross-sectional view of second configuration example of pixel> FIG. 22 is a cross-sectional view showing a second configuration example of the pixel 10 arranged in the pixel array section 21. As shown in FIG.

[0220] In FIG. 22, the parts corresponding to those in the first configuration example shown in FIG. 2 are given the same reference numerals, and the description of those parts will be omitted as appropriate.

[0221] FIG. 22 is a cross-sectional view of the pixel structure of the memory MEM retention type pixel 10 shown in FIG. 5, and also shows a cross-sectional view of the case where it is configured with a stacked structure of two substrates shown in FIG. 12B.

[0222] However, in the cross-sectional view of the stacked structure shown in Figure 13, the metal film M of the wiring layer 151 on the first substrate 41 side and the metal film M of the wiring layer 161 on the second substrate 141 are electrically connected by TSV171 and TSV172, whereas in Figure 22 they are electrically connected by Cu-Cu bonding.

[0223] Specifically, the wiring layer 151 of the first substrate 41 includes a first metal film M21, a second metal film M22, and an insulating layer 153, and the wiring layer 161 of the second substrate 141 includes a first metal film M31, a second metal film M32, and an insulating layer 173. The wiring layer 151 of the first substrate 41 and the wiring layer 161 of the second substrate 141 are electrically connected to each other by Cu films formed on parts of the bonding surfaces indicated by dashed lines.

[0224] 22, the entire pixel array region 111 of the first substrate 41, which has been described with reference to Fig. 17, is made of a SiGe region. In other words, the P-type semiconductor region 51 and the N-type semiconductor region 52 are formed of SiGe regions. This improves the quantum efficiency for infrared light.

[0225] With reference to FIG. 23, the surface of the first substrate 41 on which pixel transistors are formed will be described.

[0226] FIG. 23 is an enlarged cross-sectional view of the pixel transistor and its vicinity on the first substrate 41 of FIG.

[0227] At the interface of the first substrate 41 on the wiring layer 151 side, first transfer transistors TRGa1 and TRGa2, second transfer transistors TRGb1 and TRGb2, and memories MEM1 and MEM2 are formed for each pixel 10.

[0228] An oxide film 351 is formed with a thickness of, for example, about 10 to 100 nm on the interface of the first substrate 41 on the wiring layer 151 side. This oxide film 351 is formed by forming a silicon film by epitaxial growth on the surface of the first substrate 41 and then performing a heat treatment. This oxide film 351 also functions as a gate insulating film for each of the first transfer transistor TRGa and the second transfer transistor TRGb.

[0229] Since it is more difficult to form a high-quality oxide film in the SiGe region than in Si, the dark current generated from the transfer transistor TRG and memory MEM increases. In particular, in the indirect ToF photodetector 1, the transfer transistor TRG is repeatedly turned on and off alternately between two or more taps, so the dark current caused by the gate generated when the transfer transistor TRG is turned on cannot be ignored.

[0230] The oxide film 351 having a thickness of about 10 to 100 nm can reduce dark current caused by interface states. Therefore, according to the second configuration example, it is possible to suppress dark current while increasing quantum efficiency. The same effect can be obtained even when a Ge region is formed instead of the SiGe region.

[0231] When the pixel 10 does not have a stacked structure of two substrates, but has all pixel transistors formed on one surface of a single semiconductor substrate 41 as shown in FIG. 2, the formation of the oxide film 351 can also reduce reset noise from the amplifier transistor AMP.

[0232] <16. Cross-sectional view of the third configuration example of the pixel> FIG. 24 is a cross-sectional view showing a third configuration example of the pixel 10 arranged in the pixel array section 21. As shown in FIG.

[0233] The same reference numerals are used to denote parts corresponding to the first configuration example in FIG. 2 and the second configuration example in FIG. 22, and the description of these parts will be omitted as appropriate.

[0234] Fig. 24 is a cross-sectional view of a pixel 10 in which the light receiving element 1 is configured with a stacked structure of two substrates, and is a cross-sectional view in which the substrates are connected by Cu-Cu bonding, similar to the second configuration example shown in Fig. 22. Also, similar to the second configuration example shown in Fig. 22, the entire pixel array region 111 of the first substrate 41 is formed of a SiGe region.

[0235] When the floating diffusion regions FD1 and FD2 are formed in a SiGe region, there is a problem that the dark current generated from the floating diffusion region FD becomes large as described above. Therefore, in order to minimize the influence of the dark current, the volumes of the floating diffusion regions FD1 and FD2 formed in the first substrate 41 are formed small.

[0236] However, simply reducing the volumes of the floating diffusion regions FD1 and FD2 reduces the capacitance of the floating diffusion regions FD1 and FD2, making it impossible to store sufficient charges.

[0237] 24, an MIM (Metal Insulator Metal) capacitance element 371 is formed in the wiring layer 151 of the first substrate 41 and is constantly connected to the floating diffusion region FD, thereby increasing the capacitance of the floating diffusion region FD. Specifically, an MIM capacitance element 371-1 is connected to the floating diffusion region FD1, and an MIM capacitance element 371-2 is connected to the floating diffusion region FD2. The MIM capacitance element 371 has a U-shaped three-dimensional structure, which allows it to be mounted in a small area.

[0238] 24 , the pixel 10 according to the third configuration example can compensate for the lack of capacitance of the floating diffusion region FD, which is formed to have a small volume to suppress the generation of dark current, by using the MIM capacitance element 371. This makes it possible to simultaneously suppress dark current and ensure capacitance when using a SiGe region. In other words, according to the third configuration example, it is possible to suppress dark current while increasing the quantum efficiency for infrared light.

[0239] 24, an example of an MIM capacitance element has been described as the additional capacitance element connected to the floating diffusion region FD, but the additional capacitance element is not limited to an MIM capacitance element. For example, an MOM (Metal Oxide Metal) capacitance element, a poly-poly capacitance element (a capacitance element in which both opposing electrodes are made of polysilicon), or an additional capacitance including a parasitic capacitance formed by wiring may also be used.

[0240] Furthermore, when pixel 10 has a pixel structure including memories MEM1 and MEM2 as in the second configuration example shown in FIG. 22, an additional capacitance element can be connected not only to the floating diffusion region FD but also to the memory MEM.

[0241] Although the additional capacitance element connected to the floating diffusion region FD or the memory MEM is formed in the wiring layer 151 of the first substrate 41 in the example of FIG. 24, it may be formed in the wiring layer 161 of the second substrate .

[0242] In the example of FIG. 24, the light blocking member 63 and the wiring capacitance 64 in the first configuration example of FIG. 2 are omitted, but the light blocking member 63 and the wiring capacitance 64 may be formed.

[0243] 17. Example of IR imaging sensor configuration The structure of the photodetector 1, which improves the quantum efficiency of near-infrared light by making the photodiode PD or pixel array region 111 a SiGe region or a Ge region as described above, can be adopted not only in distance measurement sensors that output distance measurement information using the indirect ToF method, but also in other sensors that receive infrared light.

[0244] Below, we will explain examples of other sensors in which part of the semiconductor substrate is a SiGe region or a Ge region, such as an IR imaging sensor that receives infrared light and generates an IR image, and an RGBIR imaging sensor that receives infrared light and RGB light.

[0245] Further, as other examples of distance measurement sensors that receive infrared light and output distance measurement information, examples of a direct ToF distance measurement sensor using SPAD pixels and a CAPD (Current Assisted Photonic Demodulator) ToF sensor will be described.

[0246] FIG. 25 shows the circuit configuration of the pixel 10 when the light receiving element 1 is configured as an IR imaging sensor that generates and outputs an IR image.

[0247] When the light receiving element 1 is a ToF sensor, the charge generated in the photodiode PD is divided and stored in two floating diffusion regions FD1 and FD2, so the pixel 10 has two each of the transfer transistor TRG, floating diffusion region FD, additional capacitance FDL, switching transistor FDG, amplification transistor AMP, reset transistor RST, and selection transistor SEL.

[0248] When the light receiving element 1 is an IR imaging sensor, only one charge holding section is required to temporarily hold the charge generated in the photodiode PD, and therefore there is only one each of the transfer transistor TRG, floating diffusion region FD, additional capacitance FDL, switching transistor FDG, amplification transistor AMP, reset transistor RST, and selection transistor SEL.

[0249] In other words, when the light receiving element 1 is an IR imaging sensor, the pixel 10 has a configuration equivalent to that shown in Fig. 3 except that the transfer transistor TRG2, switching transistor FDG2, reset transistor RST2, amplifier transistor AMP2, and selection transistor SEL2 are omitted, as shown in Fig. 25. The floating diffusion region FD2 and vertical signal line 29B are also omitted.

[0250] FIG. 26 is a cross-sectional view showing an example of the configuration of the pixel 10 when the light receiving element 1 is configured as an IR imaging sensor.

[0251] The difference between when the light receiving element 1 is configured as an IR imaging sensor and when it is configured as a ToF sensor is the presence or absence of a floating diffusion region FD2 formed on the front surface side of the semiconductor substrate 41 and a pixel transistor, as described in FIG. 25. Therefore, the configuration of the multilayer wiring layer 42 formed on the front surface side of the semiconductor substrate 41 is different from that in FIG. 2. Also, the floating diffusion region FD2 is omitted. The other configurations in FIG. 26 are the same as those in FIG. 2.

[0252] 26, the quantum efficiency of near-infrared light can be improved by making the photodiode PD a SiGe region or a Ge region. The configuration of the pixel area ADC, the second configuration example of FIG. 22, and the third configuration example of FIG. 24 can also be applied to the IR imaging sensor, as well as the first configuration example of FIG. 2 described above. Furthermore, as described with reference to FIGS. 16 to 18, it is also possible to make not only the photodiode PD but also the entire pixel array region 111 a SiGe region or a Ge region.

[0253] <18. RGBIR Image Sensor Configuration Example> The light receiving element 1 having the pixel structure of FIG. 26 is a sensor in which all pixels 10 receive infrared light, but can also be applied to an RGBIR imaging sensor that receives infrared light and RGB light.

[0254] When the light receiving element 1 is configured as an RGBIR imaging sensor that receives infrared light and RGB light, for example, a 2x2 pixel arrangement shown in FIG. 27 is repeatedly arranged in the row and column directions.

[0255] FIG. 27 shows an example of pixel arrangement when the light receiving element 1 is configured as an RGBIR imaging sensor that receives infrared light and RGB light.

[0256] When the light receiving element 1 is configured as an RGBIR imaging sensor, as shown in Figure 27, the four 2x2 pixels are assigned an R pixel that receives R (red) light, a B pixel that receives B (blue) light, a G pixel that receives G (green) light, and an IR pixel that receives IR (infrared) light.

[0257] In an RGBIR imaging sensor, whether each pixel 10 is an R pixel, a B pixel, a G pixel, or an IR pixel is determined by a color filter layer inserted between the planarization film 46 and the on-chip lens 47 in FIG. 26.

[0258] FIG. 28 is a cross-sectional view showing an example of a color filter layer inserted between the planarizing film 46 and the on-chip lens 47 when the light receiving element 1 is configured as an RGBIR imaging sensor.

[0259] In FIG. 28, B pixels, G pixels, R pixels, and IR pixels are arranged in this order from left to right.

[0260] Between the planarization film 46 (not shown in FIG. 28) and the on-chip lens 47, a first color filter layer 381 and a second color filter layer 382 are inserted.

[0261] In the B pixel, a B filter that transmits B light is arranged in the first color filter layer 381, and an IR cut filter that blocks IR light is arranged in the second color filter layer 382. As a result, only B light passes through the first color filter layer 381 and the second color filter layer 382 and enters the photodiode PD.

[0262] In the G pixel, a G filter that transmits G light is arranged in the first color filter layer 381, and an IR cut filter that blocks IR light is arranged in the second color filter layer 382. As a result, only G light passes through the first color filter layer 381 and the second color filter layer 382 and enters the photodiode PD.

[0263] In the R pixel, an R filter that transmits R light is arranged in the first color filter layer 381, and an IR cut filter that blocks IR light is arranged in the second color filter layer 382. As a result, only R light passes through the first color filter layer 381 and the second color filter layer 382 and enters the photodiode PD.

[0264] In the IR pixel, an R filter that transmits R light is arranged in the first color filter layer 381, and a B filter that transmits B light is arranged in the second color filter layer 382. This allows light other than those with wavelengths from B to R to pass through, so that IR light passes through the first color filter layer 381 and the second color filter layer 382 and enters the photodiode PD.

[0265] When the light receiving element 1 is configured as an RGBIR imaging sensor, the photodiode PD of the IR pixel is formed in the above-mentioned SiGe region or Ge region, and the photodiodes PD of the R pixel, G pixel, and R pixel are formed in the Si region.

[0266] Even when the light receiving element 1 is configured as an RGBIR imaging sensor, the quantum efficiency of near-infrared light can be improved by using a SiGe region or a Ge region for the photodiode PD of the IR pixel. Not only the first configuration example of FIG. 2 described above, but also the configuration of the pixel area ADC, the second configuration example of FIG. 22, and the third configuration example of FIG. 24 can be similarly adopted for an RGBIR imaging sensor. Furthermore, as described with reference to FIGS. 16 to 18, it is also possible to use a SiGe region or a Ge region for not only the photodiode PD but also the entire pixel array region 111.

[0267] <19. SPAD pixel configuration example> Next, an example in which the structure of the pixel 10 described above is applied to a direct ToF distance measuring sensor using SPAD pixels will be described.

[0268] There are two types of ToF sensors: indirect ToF sensors and direct ToF sensors. Indirect ToF sensors detect the time of flight from when light is emitted until the reflected light is received as a phase difference to calculate the distance to an object, whereas direct ToF sensors directly measure the time of flight from when light is emitted until the reflected light is received to calculate the distance to an object.

[0269] In the light receiving element 1 that directly measures the time of flight, for example, a SPAD (Single Photon Avalanche Diode) or the like is used as the photoelectric conversion element of each pixel 10.

[0270] FIG. 29 shows an example of the circuit configuration of a SPAD pixel using a SPAD as the photoelectric conversion element of the pixel 10. In FIG.

[0271] 29 includes a SPAD 401 and a readout circuit 402 configured with a transistor 411 and an inverter 412. The pixel 10 also includes a switch 413. The transistor 411 is configured with a P-type MOS transistor.

[0272] The cathode of the SPAD 401 is connected to the drain of the transistor 411, and is also connected to the input terminal of the inverter 412 and one end of the switch 413. The anode of the SPAD 401 is connected to a power supply voltage VA (hereinafter also referred to as an anode voltage VA).

[0273] The SPAD 401 is a photodiode (single-photon avalanche photodiode) that, when incident light is incident, avalanche amplifies the electrons generated and outputs a signal of the cathode voltage VS. The power supply voltage VA supplied to the anode of the SPAD 401 is set to a negative bias (negative potential) of, for example, about −20 V.

[0274] The transistor 411 is a constant current source that operates in the saturation region and performs passive quenching by acting as a quenching resistor. The source of the transistor 411 is connected to the power supply voltage VE, and the drain is connected to the cathode of the SPAD 401, the input terminal of the inverter 412, and one end of the switch 413. This causes the power supply voltage VE to be supplied to the cathode of the SPAD 401 as well. A pull-up resistor can be used instead of the transistor 411 connected in series with the SPAD 401.

[0275] To detect light (photons) with sufficient efficiency, a voltage (excess bias) greater than the breakdown voltage VBD of the SPAD 401 is applied to the SPAD 401. For example, if the breakdown voltage VBD of the SPAD 401 is 20 V and a voltage 3 V greater than that is applied, the power supply voltage VE supplied to the source of the transistor 411 is set to 3 V.

[0276] The breakdown voltage VBD of the SPAD 401 varies significantly depending on the temperature, etc. Therefore, the voltage applied to the SPAD 401 is controlled (adjusted) in accordance with the change in the breakdown voltage VBD. For example, if the power supply voltage VE is a fixed voltage, the anode voltage VA is controlled (adjusted).

[0277] The switch 413 has one end connected to the cathode of the SPAD 401, the input terminal of the inverter 412, and the drain of the transistor 411, and the other end connected to ground (GND). The switch 413 can be configured, for example, by an N-type MOS transistor, and is turned on and off in response to a gating control signal VG supplied from the vertical drive unit 22.

[0278] The vertical drive unit 22 supplies a high or low gating control signal VG to the switch 413 of each pixel 10 to turn the switch 413 on or off, thereby setting each pixel 10 of the pixel array unit 21 as an active pixel or an inactive pixel. An active pixel is a pixel that detects incident photons, and an inactive pixel is a pixel that does not detect incident photons. When the switch 413 is turned on in accordance with the gating control signal VG and the cathode of the SPAD 401 is controlled to ground, the pixel 10 becomes an inactive pixel.

[0279] With reference to FIG. 30, the operation when pixel 10 in FIG. 29 is set as an active pixel will be described.

[0280] FIG. 30 is a graph showing the change in the cathode voltage VS of the SPAD 401 in response to the incidence of photons and the pixel signal PFout.

[0281] First, if pixel 10 is the active pixel, switch 413 is set to off, as described above.

[0282] A power supply voltage VE (e.g., 3 V) is supplied to the cathode of the SPAD 401, and a power supply voltage VA (e.g., −20 V) is supplied to the anode, so that a reverse voltage greater than the breakdown voltage VBD (=20 V) is applied to the SPAD 401, setting the SPAD 401 in Geiger mode. In this state, the cathode voltage VS of the SPAD 401 is the same as the power supply voltage VE, for example, as at time t0 in FIG. 30 .

[0283] When a photon is incident on the SPAD 401 set in Geiger mode, avalanche multiplication occurs and a current flows through the SPAD 401.

[0284] At time t1 in FIG. 30, if avalanche multiplication occurs and a current flows through the SPAD 401, then after time t1, a current flows through the SPAD 401, causing a current to flow through the transistor 411 as well, and a voltage drop occurs due to the resistance component of the transistor 411.

[0285] At time t2, when the cathode voltage Vs of the SPAD 401 falls below 0 V, the anode-cathode voltage of the SPAD 401 falls below the breakdown voltage VBD, and avalanche amplification stops. Here, a current generated by avalanche amplification flows through the transistor 411, causing a voltage drop. As a result of this voltage drop, the cathode voltage Vs falls below the breakdown voltage VBD, and the operation of stopping avalanche amplification is the quench operation.

[0286] When the avalanche amplification stops, the current flowing through the resistor of the transistor 411 gradually decreases, and at time t4, the cathode voltage VS returns to the original power supply voltage VE, making it possible to detect the next new photon (recharge operation).

[0287] The inverter 412 outputs a Lo pixel signal PFout when the cathode voltage VS, which is an input voltage, is equal to or greater than a predetermined threshold voltage Vth, and outputs a Hi pixel signal PFout when the cathode voltage VS is less than the predetermined threshold voltage Vth. Therefore, when a photon is incident on the SPAD 401, avalanche multiplication occurs, causing the cathode voltage VS to decrease and fall below the threshold voltage Vth, the pixel signal PFout is inverted from low to high. On the other hand, when the avalanche multiplication of the SPAD 401 ends, the cathode voltage VS increases, and becomes equal to or greater than the threshold voltage Vth, the pixel signal PFout is inverted from high to low.

[0288] When pixel 10 is designated as an inactive pixel, switch 413 is turned on. When switch 413 is turned on, the cathode voltage VS of SPAD 401 becomes 0 V. As a result, the anode-cathode voltage of SPAD 401 becomes equal to or lower than the breakdown voltage VBD, and the SPAD 401 does not react even if a photon enters it.

[0289] FIG. 31 is a cross-sectional view showing a configuration example in which the pixel 10 is a SPAD pixel.

[0290] In FIG. 31, the same reference numerals are used to designate parts corresponding to the other configuration examples described above, and the description of these parts will be omitted as appropriate.

[0291] In Figure 31, the inter-pixel separation portion 61, which was formed in the pixel boundary portion 44 of Figure 2 from the back side (on-chip lens 47 side) of the semiconductor substrate 41 to a predetermined depth in the substrate depth direction, has been changed to an inter-pixel separation portion 61' that penetrates the semiconductor substrate 41.

[0292] The pixel region inside the inter-pixel isolation portion 61′ of the semiconductor substrate 41 includes an N-well region 441, a P-type diffusion layer 442, an N-type diffusion layer 443, a hole accumulation layer 444, and a high-concentration P-type diffusion layer 445. An avalanche multiplication region 446 is formed by a depletion layer formed in a region where the P-type diffusion layer 442 and the N-type diffusion layer 443 are connected.

[0293] The N-well region 441 is formed by controlling the impurity concentration of the semiconductor substrate 41 to be N-type, and forms an electric field that transfers electrons generated by photoelectric conversion in the pixel 10 to the avalanche multiplication region 446. This N-well region 441 is formed from a SiGe region or a Ge region.

[0294] The P-type diffusion layer 442 is a doped P-type diffusion layer (P+) formed over almost the entire surface of the pixel region in the planar direction. The N-type diffusion layer 443 is a doped N-type diffusion layer (N+) formed near the surface of the semiconductor substrate 41 and, like the P-type diffusion layer 442, over almost the entire surface of the pixel region. The N-type diffusion layer 443 is a contact layer that connects to a contact electrode 451 that serves as a cathode electrode for supplying a negative voltage to form the avalanche multiplication region 446, and has a convex shape such that a portion of it extends to the contact electrode 451 on the surface of the semiconductor substrate 41. A power supply voltage VE is applied to the N-type diffusion layer 443 from the contact electrode 451.

[0295] The hole accumulation layer 444 is a P-type diffusion layer (P) that accumulates holes and is formed so as to surround the side and bottom surfaces of the N-well region 441. The hole accumulation layer 444 is also connected to a high-concentration P-type diffusion layer 445 that is electrically connected to a contact electrode 452 serving as an anode electrode of the SPAD 401.

[0296] The heavily doped P-type diffusion layer 445 is a heavily doped P-type diffusion layer (P++) formed in the vicinity of the surface of the semiconductor substrate 41 so as to surround the outer periphery of the N-well region 441 in the planar direction, and constitutes a contact layer for electrically connecting the hole accumulation layer 444 and the contact electrode 452 of the SPAD 401. A power supply voltage VA is applied to the heavily doped P-type diffusion layer 445 from the contact electrode 452.

[0297] It should be noted that a P-well region in which the impurity concentration of semiconductor substrate 41 is controlled to P-type may be formed instead of N-well region 441. When a P-well region is formed instead of N-well region 441, the voltage applied to N-type diffusion layer 443 becomes power supply voltage VA, and the voltage applied to high-concentration P-type diffusion layer 445 becomes power supply voltage VE.

[0298] In the multi-layer wiring layer 42, contact electrodes 451 and 452, metal wires 453 and 454, contact electrodes 455 and 456, and metal pads 457 and 458 are formed.

[0299] The multilayer wiring layer 42 is bonded to a wiring layer 450 of a logic circuit board on which a logic circuit is formed (hereinafter referred to as the logic wiring layer 450). The logic circuit board is formed with the above-mentioned readout circuit 402, MOS transistors as switches 413, and the like.

[0300] The contact electrode 451 connects the N-type diffusion layer 443 to a metal wiring 453 , and the contact electrode 452 connects the high-concentration P-type diffusion layer 445 to a metal wiring 454 .

[0301] 31 , the metal wiring 453 is formed wider than the avalanche multiplication region 446 in a plan view so as to cover at least the avalanche multiplication region 446. The metal wiring 453 reflects light that has passed through the semiconductor substrate 41 back to the semiconductor substrate 41.

[0302] As shown in FIG. 31, the metal wiring 454 is formed on the outer periphery of the metal wiring 453 and so as to overlap the high concentration P-type diffusion layer 445 in plan view.

[0303] The contact electrode 455 connects the metal wiring 453 to the metal pad 457 , and the contact electrode 456 connects the metal wiring 454 to the metal pad 458 .

[0304] The metal pads 457 and 458 are electrically and mechanically connected to the metal pads 471 and 472 formed on the logic wiring layer 450 by metal bonding between the metals (Cu) forming the respective pads.

[0305] In the logic wiring layer 450, electrode pads 461 and 462, contact electrodes 463 to 466, an insulating layer 469, and metal pads 471 and 472 are formed.

[0306] The electrode pads 461 and 462 are each used for connection to a logic circuit board (not shown), and the insulating layer 469 insulates the electrode pads 461 and 462 from each other.

[0307] Contact electrodes 463 and 464 connect the electrode pad 461 to the metal pad 471 , and contact electrodes 465 and 466 connect the electrode pad 462 to the metal pad 472 .

[0308] Metal pad 471 is bonded to metal pad 457 , and metal pad 472 is bonded to metal pad 458 .

[0309] With this wiring structure, for example, the electrode pad 461 is connected to the N-type diffusion layer 443 via the contact electrodes 463 and 464, the metal pad 471, the metal pad 457, the contact electrode 455, the metal wiring 453, and the contact electrode 451. Therefore, in the pixel 10 of FIG. 31 , the power supply voltage VE applied to the N-type diffusion layer 443 can be supplied from the electrode pad 461 of the logic circuit board.

[0310] 31, the anode voltage VA applied to the hole accumulation layer 444 can be supplied from the electrode pad 462 of the logic circuit board.

[0311] In pixel 10 as a SPAD pixel configured as described above, the quantum efficiency of infrared light can be increased and the sensor sensitivity can be improved by forming at least N-well region 441 from a SiGe region or a Ge region. Not only N-well region 441 but also hole accumulation layer 444 may be formed from a SiGe region or a Ge region.

[0312] <20. CAPD pixel configuration example> Next, an example in which the structure of the light receiving element 1 described above is applied to a CAPD type ToF sensor will be described.

[0313] The pixel 10 described with reference to FIGS. 2 and 3 has a ToF sensor configuration called a gate system in which the charge generated in the photodiode PD is distributed by two gates (transfer transistors TRG).

[0314] In contrast to this, there is a ToF sensor called the CAPD method, in which a voltage is applied directly to the semiconductor substrate 41 of the ToF sensor to generate a current within the substrate, and a wide range of photoelectric conversion areas within the substrate are modulated at high speed to distribute the photoelectrically converted charges.

[0315] FIG. 32 shows an example of a circuit configuration in which the pixel 10 is a CAPD pixel that employs the CAPD method.

[0316] 32 has signal extraction units 765-1 and 765-2 in a semiconductor substrate 41. The signal extraction unit 765-1 includes at least an N+ semiconductor region 771-1, which is an N-type semiconductor region, and a P+ semiconductor region 773-1, which is a P-type semiconductor region. The signal extraction unit 765-2 includes at least an N+ semiconductor region 771-2, which is an N-type semiconductor region, and a P+ semiconductor region 773-2, which is a P-type semiconductor region.

[0317] The pixel 10 has a transfer transistor 721A, an FD 722A, a reset transistor 723A, an amplifier transistor 724A, and a selection transistor 725A for the signal extraction unit 765-1.

[0318] Furthermore, the pixel 10 has a transfer transistor 721B, an FD 722B, a reset transistor 723B, an amplifier transistor 724B, and a selection transistor 725B for the signal extraction unit 765-2.

[0319] The vertical drive unit 22 applies a predetermined voltage MIX0 (first voltage) to the P+ semiconductor region 773-1 and a predetermined voltage MIX1 (second voltage) to the P+ semiconductor region 773-2. For example, one of the voltages MIX0 and MIX1 is 1.5 V and the other is 0 V. The P+ semiconductor regions 773-1 and 773-2 are voltage application units to which the first voltage or the second voltage is applied.

[0320] The N+ semiconductor regions 771-1 and 771-2 are charge detection units that detect and accumulate charges generated by photoelectric conversion of light incident on the semiconductor substrate 41.

[0321] When the transfer drive signal TRG supplied to the gate electrode becomes active, the transfer transistor 721A becomes conductive in response, thereby transferring the charge accumulated in the N+ semiconductor region 771-1 to the FD722A. When the transfer drive signal TRG supplied to the gate electrode becomes active, the transfer transistor 721B becomes conductive in response, thereby transferring the charge accumulated in the N+ semiconductor region 771-2 to the FD722B.

[0322] The FD722A temporarily holds the charge supplied from the N+ semiconductor region 771-1, and the FD722B temporarily holds the charge supplied from the N+ semiconductor region 771-2.

[0323] When the reset drive signal RST supplied to its gate electrode becomes active, the reset transistor 723A becomes conductive in response, thereby resetting the potential of the FD722A to a predetermined level (reset voltage VDD). When the reset drive signal RST supplied to its gate electrode becomes active, the reset transistor 723B becomes conductive in response, thereby resetting the potential of the FD722B to a predetermined level (reset voltage VDD). When the reset transistors 723A and 723B are activated, the transfer transistors 721A and 721B are also simultaneously activated.

[0324] The amplifier transistor 724A has a source electrode connected to the vertical signal line 29A via the selection transistor 725A, and thereby forms a source follower circuit with a load MOS of a constant current source circuit unit 726A connected to one end of the vertical signal line 29A. The amplifier transistor 724B has a source electrode connected to the vertical signal line 29B via the selection transistor 725B, and thereby forms a source follower circuit with a load MOS of a constant current source circuit unit 726B connected to one end of the vertical signal line 29B.

[0325] The selection transistor 725A is connected between the source electrode of the amplification transistor 724A and the vertical signal line 29A. When the selection drive signal SEL supplied to the gate electrode thereof becomes active, the selection transistor 725A becomes conductive in response to this, and outputs the pixel signal output from the amplification transistor 724A to the vertical signal line 29A.

[0326] The selection transistor 725B is connected between the source electrode of the amplification transistor 724B and the vertical signal line 29B. When the selection drive signal SEL supplied to the gate electrode thereof becomes active, the selection transistor 725B becomes conductive in response to this, and outputs the pixel signal output from the amplification transistor 724B to the vertical signal line 29B.

[0327] The transfer transistors 721A and 721B, reset transistors 723A and 723B, amplification transistors 724A and 724B, and selection transistors 725A and 725B of the pixel 10 are controlled by the vertical drive unit 22, for example.

[0328] FIG. 33 is a cross-sectional view of the pixel 10 when it is a CAPD pixel.

[0329] In FIG. 33, parts corresponding to those in the other configuration examples described above are given the same reference numerals, and the description of those parts will be omitted as appropriate.

[0330] In the case of a CAPD pixel 10, the entire semiconductor substrate 41 formed of, for example, P-type is the photoelectric conversion region, which is formed of the above-mentioned SiGe region or Ge region. The surface of the semiconductor substrate 41 on which the on-chip lens 47 is formed is the light incident surface, and the surface opposite to the light incident surface is the circuit forming surface.

[0331] An oxide film 764 is formed in the center of the pixel 10 near the circuit formation surface of the semiconductor substrate 41, and a signal extraction portion 765-1 and a signal extraction portion 765-2 are formed on both ends of the oxide film 764, respectively.

[0332] The signal extraction unit 765-1 has an N-semiconductor region 772-1, which is an N-type semiconductor region, and an N+ semiconductor region 771-1, which has a lower donor impurity concentration than the N+ semiconductor region 771-1, and a P-semiconductor region 773-1, which is a P-type semiconductor region, and a P- semiconductor region 774-1, which has a lower acceptor impurity concentration than the P+ semiconductor region 773-1. Examples of donor impurities include elements belonging to Group 5 of the periodic table of elements, such as phosphorus (P) and arsenic (As) for Si, and examples of acceptor impurities include elements belonging to Group 3 of the periodic table of elements, such as boron (B) for Si. Elements that become donor impurities are called donor elements, and elements that become acceptor impurities are called acceptor elements.

[0333] In the signal extraction unit 765-1, an N+ semiconductor region 771-1 and an N- semiconductor region 772-1 are formed in an annular shape around the P+ semiconductor region 773-1 and the P- semiconductor region 774-1, surrounding the periphery of the P+ semiconductor region 773-1 and the P- semiconductor region 774-1. The P+ semiconductor region 773-1 and the N+ semiconductor region 771-1 are in contact with the multilayer wiring layer 42. The P- semiconductor region 774-1 is disposed above the P+ semiconductor region 773-1 (on the on-chip lens 47 side) so as to cover the P+ semiconductor region 773-1, and the N- semiconductor region 772-1 is disposed above the N+ semiconductor region 771-1 (on the on-chip lens 47 side) so as to cover the N+ semiconductor region 771-1. In other words, the P+ semiconductor region 773-1 and the N+ semiconductor region 771-1 are arranged on the multilayer wiring layer 42 side within the semiconductor substrate 41, and the N- semiconductor region 772-1 and the P- semiconductor region 774-1 are arranged on the on-chip lens 47 side within the semiconductor substrate 41. In addition, between the N+ semiconductor region 771-1 and the P+ semiconductor region 773-1, a separation portion 775-1 is formed of an oxide film or the like to separate these regions.

[0334] Similarly, the signal extraction section 765-2 has an N-type semiconductor region, an N+ semiconductor region 771-2, and an N- semiconductor region 772-2 having a lower donor impurity concentration than the N+ semiconductor region 771-2, and a P-type semiconductor region, a P+ semiconductor region 773-2, and a P- semiconductor region 774-2 having a lower acceptor impurity concentration than the P+ semiconductor region 773-2.

[0335] In the signal extraction unit 765-2, an N+ semiconductor region 771-2 and an N- semiconductor region 772-2 are formed in a ring shape around the P+ semiconductor region 773-2 and the P- semiconductor region 774-2 so as to surround the periphery of the P+ semiconductor region 773-2 and the P- semiconductor region 774-2. The P+ semiconductor region 773-2 and the N+ semiconductor region 771-2 are in contact with the multilayer wiring layer 42. The P- semiconductor region 774-2 is disposed above the P+ semiconductor region 773-2 (on the on-chip lens 47 side) so as to cover the P+ semiconductor region 773-2, and the N- semiconductor region 772-2 is disposed above the N+ semiconductor region 771-2 (on the on-chip lens 47 side) so as to cover the N+ semiconductor region 771-2. In other words, the P+ semiconductor region 773-2 and the N+ semiconductor region 771-2 are arranged on the multilayer wiring layer 42 side within the semiconductor substrate 41, and the N- semiconductor region 772-2 and the P- semiconductor region 774-2 are arranged on the on-chip lens 47 side within the semiconductor substrate 41. In addition, between the N+ semiconductor region 771-2 and the P+ semiconductor region 773-2, a separation portion 775-2 is formed of an oxide film or the like to separate these regions.

[0336] An oxide film 764 is also formed in the boundary region between adjacent pixels 10, between the N+ semiconductor region 771-1 of the signal extraction section 765-1 of a given pixel 10 and the N+ semiconductor region 771-2 of the signal extraction section 765-2 of the adjacent pixel 10.

[0337] At the interface on the light incident surface side of the semiconductor substrate 41, a P+ semiconductor region 701 is formed by stacking a film having a positive fixed charge to cover the entire light incident surface.

[0338] Hereinafter, when there is no need to particularly distinguish between the signal extracting unit 765-1 and the signal extracting unit 765-2, they will also be simply referred to as the signal extracting unit 765.

[0339] Furthermore, hereinafter, when there is no need to particularly distinguish between the N+ semiconductor region 771-1 and the N+ semiconductor region 771-2, they will be simply referred to as the N+ semiconductor region 771, and when there is no need to particularly distinguish between the N- semiconductor region 772-1 and the N- semiconductor region 772-2, they will be simply referred to as the N- semiconductor region 772.

[0340] Furthermore, hereinafter, when there is no need to particularly distinguish between P+ semiconductor region 773-1 and P+ semiconductor region 773-2, they will be simply referred to as P+ semiconductor region 773, and when there is no need to particularly distinguish between P- semiconductor region 774-1 and P- semiconductor region 774-2, they will be simply referred to as P- semiconductor region 774. Furthermore, when there is no need to particularly distinguish between isolation portion 775-1 and isolation portion 775-2, they will be simply referred to as isolation portion 775.

[0341] The N+ semiconductor region 771 provided in the semiconductor substrate 41 functions as a charge detection unit for detecting the amount of light incident on the pixel 10 from the outside, i.e., the amount of signal charge generated by photoelectric conversion by the semiconductor substrate 41. In addition to the N+ semiconductor region 771, the N- semiconductor region 772 having a low donor impurity concentration can also be considered to be part of the charge detection unit. The P+ semiconductor region 773 functions as a voltage application unit for injecting majority carrier current into the semiconductor substrate 41, i.e., for applying a voltage directly to the semiconductor substrate 41 to generate an electric field within the semiconductor substrate 41. In addition to the P+ semiconductor region 773, the P- semiconductor region 774 having a low acceptor impurity concentration can also be considered to be part of the voltage application unit.

[0342] For example, diffusion films 811 regularly arranged at predetermined intervals are formed on the interface on the front surface side of the semiconductor substrate 41, which is the side on which the multilayer wiring layer 42 is formed. Furthermore, although not shown in the figure, an insulating film (gate insulating film) is formed between the diffusion film 811 and the interface of the semiconductor substrate 41.

[0343] The diffusion films 811 are arranged, for example, regularly at predetermined intervals on the interface on the front surface side of the semiconductor substrate 41, which is the side on which the multilayer wiring layer 42 is formed, and prevent light passing from the semiconductor substrate 41 to the multilayer wiring layer 42 and light reflected by a reflecting member 815, which will be described later, from penetrating outside the semiconductor substrate 41 (toward the on-chip lens 47) by being diffused by the diffusion films 811. The material of the diffusion film 811 may also be a material whose main component is polycrystalline silicon such as polysilicon.

[0344] The diffusion film 811 is formed to avoid the positions of the N+ semiconductor region 771-1 and the P+ semiconductor region 773-1 so as not to overlap with the positions of the N+ semiconductor region 771-1 and the P+ semiconductor region 773-1.

[0345] 33, of the four first to fourth metal films M1 to M4 of the multilayer wiring layer 42, the first metal film M1, which is closest to the semiconductor substrate 41, includes a power supply line 813 for supplying a power supply voltage, a voltage application wiring 814 for applying a predetermined voltage to the P+ semiconductor region 773-1 or 773-2, and a reflecting member 815 that is a member that reflects incident light. The voltage application wiring 814 is connected to the P+ semiconductor region 773-1 or 773-2 via a contact electrode 812, and applies a predetermined voltage MIX0 to the P+ semiconductor region 773-1 and a predetermined voltage MIX1 to the P+ semiconductor region 773-2.

[0346] 33, wiring other than the power supply line 813 and the voltage application wiring 814 is a reflective member 815, but some reference numerals have been omitted to avoid complication of the drawing. The reflective member 815 is a dummy wiring provided for the purpose of reflecting incident light. The reflective member 815 is disposed below the N+ semiconductor regions 771-1 and 771-2, which are charge detection units, so as to overlap with the N+ semiconductor regions 771-1 and 771-2 in a plan view. In addition, a contact electrode (not shown) that connects the N+ semiconductor region 771 and the transfer transistor 721 is also formed in the first metal film M1 to transfer the charge accumulated in the N+ semiconductor region 771 to the FD722.

[0347] In this example, the reflecting member 815 is disposed in the same layer as the first metal film M1, but this is not necessarily limited to disposing it in the same layer.

[0348] The second metal film M2, which is the second layer from the semiconductor substrate 41 side, is formed with, for example, a voltage application wiring 816 connected to the voltage application wiring 814 of the first metal film M1, a control line 817 for transmitting a transfer drive signal TRG, a reset drive signal RST, a selection drive signal SEL, an FD drive signal FDG, etc., a ground line, etc. Also formed on the second metal film M2 is an FD722, etc.

[0349] In the third metal film M3, which is the third layer from the semiconductor substrate 41 side, for example, the vertical signal line 29, a shielding wire, etc. are formed.

[0350] In the fourth metal film M4, which is the fourth layer from the semiconductor substrate 41 side, a voltage supply line (not shown) is formed for applying a predetermined voltage MIX0 or MIX1 to, for example, the P+ semiconductor regions 773-1 and 773-2, which are the voltage application portions of the signal extraction portion 65.

[0351] The operation of pixel 10 in FIG. 33, which is a CAPD pixel, will now be described.

[0352] The vertical drive unit 22 drives the pixels 10 and distributes signals corresponding to the charges obtained by photoelectric conversion to FD722A and FD722B (FIG. 32).

[0353] The vertical drive unit 22 applies a voltage to the two P+ semiconductor regions 773 via the contact electrodes 812 etc. For example, the vertical drive unit 22 applies a voltage of 1.5 V to the P+ semiconductor region 773-1 and a voltage of 0 V to the P+ semiconductor region 773-2.

[0354] Application of a voltage generates an electric field between the two P+ semiconductor regions 773 in the semiconductor substrate 41, causing a current to flow from the P+ semiconductor region 773-1 to the P+ semiconductor region 773-2. In this case, holes in the semiconductor substrate 41 move toward the P+ semiconductor region 773-2, and electrons move toward the P+ semiconductor region 773-1.

[0355] Therefore, in this state, when infrared light (reflected light) from outside enters the semiconductor substrate 41 through the on-chip lens 47 and is photoelectrically converted within the semiconductor substrate 41 into pairs of electrons and holes, the resulting electrons are guided toward the P+ semiconductor region 773-1 by the electric field between the P+ semiconductor regions 773 and move into the N+ semiconductor region 771-1.

[0356] In this case, the electrons generated by photoelectric conversion are used as signal charges for detecting the amount of infrared light incident on the pixel 10, that is, a signal corresponding to the amount of received infrared light.

[0357] As a result, an electric charge corresponding to the electrons that have moved into the N+ semiconductor region 771-1 is accumulated in the N+ semiconductor region 771-1, and this electric charge is detected in the column processing unit 23 via the FD722A, the amplifying transistor 724A, the vertical signal line 29A, etc.

[0358] That is, the charges accumulated in the N+ semiconductor region 771-1 are transferred to the FD722A directly connected to the N+ semiconductor region 771-1, and a signal corresponding to the charges transferred to the FD722A is read out by the column processing unit 23 via the amplification transistor 724A and the vertical signal line 29A. The read-out signal is then subjected to processing such as AD conversion in the column processing unit 23, and the resulting pixel signal is supplied to the signal processing unit 26.

[0359] This pixel signal is a signal indicating the amount of charge corresponding to the electrons detected by the N+ semiconductor region 771-1, i.e., the amount of charge accumulated in the FD 722 A. In other words, the pixel signal can be said to be a signal indicating the amount of infrared light received by the pixel 10.

[0360] At this time, a pixel signal corresponding to the electrons detected in the N+ semiconductor region 771-2 may also be used for distance measurement as appropriate, in the same manner as in the case of the N+ semiconductor region 771-1.

[0361] At the next timing, voltages are applied to the two P+ semiconductor regions 73 via contacts or the like by the vertical drive unit 22 so as to generate an electric field in the opposite direction to the electric field that has been generated up until then in the semiconductor substrate 41. Specifically, for example, a voltage of 1.5 V is applied to the P+ semiconductor region 773-2, and a voltage of 0 V is applied to the P+ semiconductor region 773-1.

[0362] As a result, an electric field is generated between the two P+ semiconductor regions 773 in the semiconductor substrate 41, and a current flows from the P+ semiconductor region 773-2 to the P+ semiconductor region 773-1.

[0363] In this state, when infrared light (reflected light) from the outside enters the semiconductor substrate 41 through the on-chip lens 47 and is photoelectrically converted within the semiconductor substrate 41 into pairs of electrons and holes, the resulting electrons are guided toward the P+ semiconductor region 773-2 by the electric field between the P+ semiconductor regions 773 and move into the N+ semiconductor region 771-2.

[0364] As a result, an electric charge corresponding to the electrons that have moved into the N+ semiconductor region 771-2 is accumulated in the N+ semiconductor region 771-2, and this electric charge is detected in the column processing unit 23 via the FD722B, the amplifying transistor 724B, the vertical signal line 29B, etc.

[0365] That is, the charges accumulated in the N+ semiconductor region 771-2 are transferred to the FD722B directly connected to the N+ semiconductor region 771-2, and a signal corresponding to the charges transferred to the FD722B is read out by the column processing unit 23 via the amplification transistor 724B and the vertical signal line 29B. The read-out signal is then subjected to processing such as AD conversion in the column processing unit 23, and the resulting pixel signal is supplied to the signal processing unit 26.

[0366] At this time, similarly to the case of the N+ semiconductor region 771-2, pixel signals corresponding to the electrons detected in the N+ semiconductor region 771-1 may also be used for distance measurement as appropriate.

[0367] In this way, when pixel signals obtained by photoelectric conversion in different periods are obtained in the same pixel 10, the signal processing unit 26 can calculate the distance to the object based on these pixel signals.

[0368] In the pixel 10 as a CAPD pixel configured as described above, by forming the semiconductor substrate 41 in a SiGe region or a Ge region, the quantum efficiency of near-infrared light can be increased, and the sensor sensitivity can be improved.

[0369] <21. Example of distance measurement module configuration> FIG. 34 is a block diagram showing an example of the configuration of a distance measuring module that outputs distance measurement information using the above-described light receiving element 1.

[0370] The distance measurement module 500 includes a light emitting unit 511 , a light emitting control unit 512 , and a light receiving unit 513 .

[0371] The light-emitting unit 511 has a light source that emits light of a predetermined wavelength, and emits irradiation light whose brightness periodically fluctuates to irradiate an object. For example, the light-emitting unit 511 has a light-emitting diode that emits infrared light with a wavelength of 780 nm or more as a light source, and generates the irradiation light in synchronization with a rectangular wave light-emission control signal CLKp supplied from the light-emission control unit 512.

[0372] The light emission control signal CLKp is not limited to a square wave as long as it is a periodic signal. For example, the light emission control signal CLKp may be a sine wave.

[0373] The light emission control unit 512 supplies a light emission control signal CLKp to the light emitter 511 and the light receiver 513 to control the timing of irradiation with light. The frequency of this light emission control signal CLKp is, for example, 20 megahertz (MHz). Note that the frequency of the light emission control signal CLKp is not limited to 20 MHz and may be 5 MHz, 100 MHz, or the like.

[0374] The light receiving unit 513 receives light reflected from an object, calculates distance information for each pixel based on the light receiving results, and generates and outputs a depth image in which depth values ​​corresponding to the distance to the object (subject) are stored as pixel values.

[0375] The light receiving unit 513 uses a light receiving element 1 having the pixel structure of the indirect ToF method (gate method or CAPD method) described above, or a light receiving element 1 having the pixel structure of an SPDAD pixel. For example, the light receiving element 1 serving as the light receiving unit 513 calculates distance information for each pixel from a pixel signal corresponding to the charge distributed to the floating diffusion region FD1 or FD2 of each pixel 10 in the pixel array unit 21, based on the light emission control signal CLKp.

[0376] As described above, the light receiving element 1 having the pixel structure of the indirect ToF method or the direct ToF method can be incorporated as the light receiving unit 513 of the ranging module 500 that determines and outputs information about the distance to the subject. This improves the sensor sensitivity and the ranging characteristics of the ranging module 500.

[0377] <22. Configuration examples of electronic devices> In addition to being applicable to the distance measurement module as described above, the light receiving element 1 can also be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras with distance measurement functions, and smartphones with distance measurement functions.

[0378] FIG. 35 is a block diagram showing an example configuration of a smartphone as an electronic device to which the present technology is applied.

[0379] 35, the smartphone 601 is configured by connecting a distance measurement module 602, an imaging device 603, a display 604, a speaker 605, a microphone 606, a communication module 607, a sensor unit 608, a touch panel 609, and a control unit 610 via a bus 611. In addition, the control unit 610 has functions as an application processing unit 621 and an operation system processing unit 622 by the CPU executing a program.

[0380] 34 is applied to the distance measurement module 602. For example, the distance measurement module 602 is placed on the front of a smartphone 601, and by measuring the distance to the user of the smartphone 601, it is possible to output depth values ​​of the surface shapes of the user's face, hands, fingers, etc. as the distance measurement results.

[0381] The imaging device 603 is arranged on the front side of the smartphone 601, and captures an image of the user of the smartphone 601 by capturing an image of the user as a subject. Although not shown, the smartphone 601 may also have a configuration in which an imaging device 603 is arranged on the back side.

[0382] The display 604 displays an operation screen for performing processing by the application processing unit 621 and the operation system processing unit 622, images captured by the imaging device 603, etc. The speaker 605 and the microphone 606 output the voice of the other party and pick up the voice of the user when making a call using the smartphone 601, for example.

[0383] The communication module 607 performs network communication via communication networks such as the Internet, public telephone network, wide area communication networks for wireless mobile devices such as so-called 4G lines and 5G lines, WAN (Wide Area Network), LAN (Local Area Network), etc., and short-range wireless communication such as Bluetooth (registered trademark) and NFC (Near Field Communication), etc. The sensor unit 608 senses speed, acceleration, proximity, etc., and the touch panel 609 acquires touch operations by the user on the operation screen displayed on the display 604.

[0384] The application processing unit 621 performs processing for providing various services via the smartphone 601. For example, the application processing unit 621 can perform processing for creating a computer graphics face that virtually reproduces the user's facial expression based on the depth value supplied from the distance measurement module 602, and displaying the face on the display 604. Furthermore, the application processing unit 621 can perform processing for creating, for example, three-dimensional shape data of any three-dimensional object based on the depth value supplied from the distance measurement module 602.

[0385] The operation system processing unit 622 performs processing for realizing the basic functions and operations of the smartphone 601. For example, the operation system processing unit 622 can perform processing for authenticating the user's face and unlocking the smartphone 601 based on the depth value supplied from the distance measurement module 602. The operation system processing unit 622 can also perform processing for recognizing the user's gestures based on the depth value supplied from the distance measurement module 602 and inputting various operations in accordance with the gestures.

[0386] In the smartphone 601 configured in this manner, by applying the above-mentioned ranging module 500 as the ranging module 602, it is possible to perform processes such as measuring and displaying the distance to a specified object, and creating and displaying three-dimensional shape data of the specified object.

[0387] <23. Mobile Application Examples> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0388] FIG. 36 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0389] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 36, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0390] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0391] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0392] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0393] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0394] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0395] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0396] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0397] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0398] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 36, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0399] FIG. 37 is a diagram showing an example of the installation position of the imaging unit 12031.

[0400] In FIG. 37, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0401] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0402] 37 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0403] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0404] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0405] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0406] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0407] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the vehicle exterior information detection unit 12030 and the imaging unit 12031 among the above-described configurations. Specifically, the light receiving element 1 or the ranging module 500 can be applied to the distance detection processing block of the vehicle exterior information detection unit 12030 and the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle exterior information detection unit 12030 and the imaging unit 12031, it is possible to measure the distance to an object such as a person, a vehicle, an obstacle, a sign, or text on the road surface with high accuracy, and the obtained distance information can be used to reduce driver fatigue and improve the safety of the driver and the vehicle.

[0408] The embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present technology.

[0409] Furthermore, in the above-described light receiving element 1, an example has been described in which electrons are used as signal carriers, but holes generated by photoelectric conversion may also be used as signal carriers.

[0410] For example, the light receiving element 1 described above may employ a configuration in which all or part of each embodiment is combined.

[0411] The effects described in this specification are merely examples and are not limiting, and there may be effects other than those described in this specification.

[0412] The present technology can have the following configurations. (1) a pixel array region in which pixels each including a photoelectric conversion region are arranged in a matrix; The photoelectric conversion region of each pixel of the first semiconductor substrate on which the pixel array region is formed is formed of a SiGe region or a Ge region. Photodetector. (2) The photoelectric conversion region of each pixel of the first semiconductor substrate is formed of a SiGe region or a Ge region, and the region other than the photoelectric conversion region of each pixel of the first semiconductor substrate is formed of a Si region. The light-receiving element according to (1) above. (3) the pixel has at least a photodiode as the photoelectric conversion region and a transfer transistor that transfers charges generated in the photodiode; The region under the gate of the transfer transistor of each pixel on the first semiconductor substrate is also formed of the SiGe region or the Ge region. The light-receiving element according to (1) or (2) above. (4) The entire pixel array region of the first semiconductor substrate is formed from the SiGe region or the Ge region. The light-receiving element according to any one of (1) to (3) above. (5) the pixel has at least a photodiode as the photoelectric conversion region, a transfer transistor that transfers charges generated in the photodiode, and a charge holding unit that temporarily holds the charges; The charge retention portion is formed of a Si region on the SiGe region or a Ge region. The light-receiving element according to (3) or (4) above. (6) The Ge concentration in the SiGe region or the Ge region varies depending on the depth in the first semiconductor substrate. The light-receiving element according to any one of (1) to (5) above. (7) The Ge concentration on the light incident surface side of the first semiconductor substrate is higher than the Ge concentration on the pixel transistor forming surface of the first semiconductor substrate. The light-receiving element according to (6) above. (8) The first semiconductor substrate includes the pixel array region and a logic circuit region including a control circuit for each pixel. The light-receiving element according to any one of (1) to (7). (9) Further provided is a second semiconductor substrate on which a logic circuit region including a control circuit for each pixel is formed, The first semiconductor substrate and the second semiconductor substrate are stacked together. The light-receiving element according to any one of (1) to (8) above. (10) The light receiving element is a gate-type indirect ToF sensor The light-receiving element according to any one of (1) to (9) above. (11) The light receiving element is a CAPD type indirect ToF sensor The light-receiving element according to any one of (1) to (9) above. (12) The light receiving element is a direct ToF sensor with a SPAD in the pixel The light-receiving element according to any one of (1) to (9) above. (13) The light receiving element is an IR imaging sensor in which all pixels receive infrared light. The light-receiving element according to any one of (1) to (9) above. (14) The light receiving element is an RGBIR imaging sensor having pixels that receive infrared light and pixels that receive RGB light. The light-receiving element according to any one of (1) to (9) above. (15) At least the photoelectric conversion region of each pixel in the pixel array region of the semiconductor substrate is formed from a SiGe region or a Ge region. A method for manufacturing a light-receiving element. (16) The SiGe region or Ge region is formed by ion implanting Ge into the Si region. The method for manufacturing the light-receiving element according to (15) above. (17) The SiGe region or Ge region is formed by epitaxial growth in the region of the semiconductor substrate from which the Si region has been removed. The method for manufacturing the light-receiving element according to (15) above. (18) A Si layer serving as a charge retention portion is formed on the SiGe region or the Ge region of the semiconductor substrate. The method for manufacturing a light-receiving element according to any one of (15) to (17) above. (19) The SiGe region or the Ge region is formed so that the Ge concentration varies depending on the depth of the semiconductor substrate. A method for manufacturing a light-receiving element according to any one of (15) to (18). (20) a predetermined light emitting source; a pixel array region in which pixels each including a photoelectric conversion region are arranged in a matrix; The photoelectric conversion region of each pixel of the first semiconductor substrate on which the pixel array region is formed is formed of a SiGe region or a Ge region. Light receiving element An electronic device comprising: [Explanation of symbols]

[0413] 1 light receiving element, 10 pixel, PD photodiode, TRG transfer transistor, 21 pixel array section, 41 semiconductor substrate (first substrate), 42 multilayer wiring layer, 50 P-type semiconductor region, 52 N-type semiconductor region, 111 pixel array region, 141 semiconductor substrate (second substrate), 201 pixel circuit, 202 ADC (AD converter), 351 oxide film, 371 MIM capacitance element, 381 first color filter layer, 382 second color filter layer, 441 N-well region, 442 P-type diffusion layer, 500 ranging module, 511 light emitting section, 512 light emitting control section, 513 light receiving section, 601 smartphone, 602 ranging module

Claims

1. a pixel array region in which pixels each including a photoelectric conversion region are arranged in a matrix; the photoelectric conversion region of each pixel of the first semiconductor substrate on which the pixel array region is formed is formed of a SiGe region or a Ge region; The Ge concentration on the light incident surface side of the first semiconductor substrate is configured to be higher than the Ge concentration on the pixel transistor forming surface side of the first semiconductor substrate. Photodetector.

2. The photoelectric conversion region of each pixel of the first semiconductor substrate is formed of a SiGe region or a Ge region, and the region other than the photoelectric conversion region of each pixel of the first semiconductor substrate is formed of a Si region. The light-receiving element according to claim 1 .

3. the pixel has at least the photoelectric conversion region and a transfer transistor that transfers charges generated in the photoelectric conversion region; The region under the gate of the transfer transistor of each pixel on the first semiconductor substrate is also formed of the SiGe region or the Ge region. The light-receiving element according to claim 1 .

4. The entire pixel array region of the first semiconductor substrate is formed from the SiGe region or the Ge region. The light-receiving element according to claim 1 .

5. the pixel has at least the photoelectric conversion region, the transfer transistor that transfers charges generated in the photoelectric conversion region, and a charge holding unit that temporarily holds the transferred charges; The charge retention portion is formed of a Si region on the SiGe region or a Ge region. The light-receiving element according to claim 3 .

6. The first semiconductor substrate includes the pixel array region and a logic circuit region including a control circuit for each pixel. The light-receiving element according to claim 1 .

7. a second semiconductor substrate on which a logic circuit region including a control circuit for each pixel is formed; The first semiconductor substrate and the second semiconductor substrate are stacked together. The light-receiving element according to claim 1 .

8. The light receiving element is a gate-type indirect ToF sensor The light-receiving element according to claim 1 .

9. The light receiving element is a CAPD type indirect ToF sensor The light-receiving element according to claim 1 .

10. The light receiving element is a direct ToF sensor with a SPAD in the pixel The light-receiving element according to claim 1 .

11. The light receiving element is an IR imaging sensor in which all pixels receive infrared light. The light-receiving element according to claim 1 .

12. The light receiving element is an RGBIR imaging sensor having pixels that receive infrared light and pixels that receive RGB light. The light-receiving element according to claim 1 .

13. At least a photoelectric conversion region of each pixel in a pixel array region of a semiconductor substrate is formed from a SiGe region or a Ge region; The semiconductor substrate is formed so that the Ge concentration on the light incident surface side is higher than the Ge concentration on the pixel transistor forming surface side of the semiconductor substrate. A method for manufacturing a light-receiving element.

14. The SiGe region or Ge region is formed by ion implanting Ge into the Si region. The method for manufacturing a light-receiving element according to claim 13 .

15. The SiGe region or Ge region is formed by epitaxial growth in the region of the semiconductor substrate from which the Si region has been removed. The method for manufacturing a light-receiving element according to claim 13 .

16. A Si layer serving as a charge retention portion is formed on the SiGe region or the Ge region of the semiconductor substrate. The method for manufacturing a light-receiving element according to claim 13 .

17. a pixel array region in which pixels each including a photoelectric conversion region are arranged in a matrix; the photoelectric conversion region of each pixel of the semiconductor substrate on which the pixel array region is formed is formed in a SiGe region or a Ge region, The Ge concentration on the light incident surface side of the semiconductor substrate is configured to be higher than the Ge concentration on the pixel transistor forming surface side of the semiconductor substrate. Light receiving element An electronic device comprising:

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