Nonvolatile memory device and method of manufacturing the same

Abstract

To provide a nonvolatile memory device with higher product reliability.SOLUTION: A nonvolatile memory device includes a substrate, a first mold structure including a plurality of first gate electrodes on the substrate, a second mold structure including a plurality of second gate electrodes on the first mold structure, and a plurality of channel structures intersecting with the respective first gate electrodes and the respective second gate electrodes penetrating the first mold structure and the second mold structure. The first mold structure includes a first stack and a second stack that are apart from each other. The second mold structure includes a third stack stacked on the first stack, a fourth stack stacked on the second stack, and a first connection part connecting the third stack and the fourth stack.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a non-volatile memory device and a method for manufacturing the same, and more particularly to a non-volatile memory device including a word line cut region and a method for manufacturing the same. [Background technology]

[0002] Semiconductor memory devices can be broadly classified into volatile memory devices and non-volatile memory devices.

[0003] Meanwhile, the integration density of non-volatile memory devices is increasing to meet consumer demands for superior performance and low cost. However, in the case of two-dimensional (2D) or planar memory devices, the integration density is determined by the area occupied by a unit memory cell. Therefore, three-dimensional (3D) memory devices, in which unit memory cells are arranged vertically, have recently been developed. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE INVENTION The present invention provides a nonvolatile memory device with improved product reliability.

[0005] Another technical problem to be solved by the present invention is to provide a method for manufacturing a nonvolatile memory device with improved product reliability.

[0006] The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] In order to achieve the above technical objective, a nonvolatile memory device according to some embodiments includes a substrate, a first mold structure on the substrate, the first mold structure including a plurality of first gate electrodes, a second mold structure on the first mold structure, the second mold structure including a plurality of second gate electrodes, and a plurality of channel structures penetrating the first mold structure and the second mold structure and intersecting with each of the first gate electrodes and each of the second gate electrodes, wherein the first mold structure includes a first stack and a second stack spaced apart from each other, and the second mold structure includes a third stack stacked on the first stack, a fourth stack stacked on the second stack, and a first connecting portion connecting the third stack and the fourth stack.

[0008] In order to achieve the above technical objectives, a nonvolatile memory device according to some embodiments includes: a substrate; a first mold structure on the substrate, the first mold structure including a plurality of first gate electrodes; a second mold structure on the first mold structure, the second mold structure including a plurality of second gate electrodes; a plurality of channel structures penetrating the first mold structure and the second mold structure and intersecting with each of the first gate electrodes and each of the second gate electrodes; and bit lines extending in a first direction and connected to each of the channel structures, wherein the first mold structure includes a first block trench extending in a second direction intersecting with the first direction and completely cutting the first mold structure; and the second mold structure includes a plurality of second block trenches exposing portions of the first block trenches, the plurality of second block trenches being spaced apart from each other and arranged along the second direction.

[0009] A nonvolatile memory device according to some embodiments for achieving the above technical object includes a substrate, a first mold structure on the substrate, the first mold structure including a plurality of first gate electrodes, a second mold structure on the first mold structure, the second mold structure including a plurality of second gate electrodes, a plurality of channel structures passing through the first mold structure and the second mold structure and intersecting with each of the first gate electrodes and each of the second gate electrodes, bit lines extending in a first direction and connected to each of the channel structures, and bit lines extending in a second direction intersecting with the first direction and cutting the plurality of first gate electrodes and the plurality of second gate electrodes. the first mold structure includes a first stack and a second stack separated by the first block trench; the second mold structure includes a third stack stacked on the first stack, a fourth stack stacked on the second stack, and a plurality of first coupling portions coupling the third stack and the fourth stack; and Specific details of other embodiments are included in the detailed description and drawings. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is an exemplary circuit diagram illustrating a nonvolatile memory device according to some embodiments. [Figure 2] 1 is a layout diagram illustrating a nonvolatile memory device according to some embodiments. [Figure 3] FIG. 3 is a cross-sectional view taken along the line AA in FIG. 2. [Figure 4] FIG. 4 is an enlarged view of R1 in FIG. 3. [Figure 5] FIG. 3 is a cross-sectional view taken along line BB in FIG. 2. [Figure 6] FIG. 3 is a cross-sectional view taken along CC in FIG. 2. [Figure 7] FIG. 3 is a cross-sectional view taken along the line DD in FIG. 2. [Figure 8] FIG. 8 is a schematic, partially exploded perspective view for explaining the first mold structure MS1 and the second mold structure MS2 of FIGS. 2 to 7. [Figure 9] 1 is a layout diagram illustrating a nonvolatile memory device according to some embodiments. [Figure 10] FIG. 10 is a cross-sectional view taken along the line EE in FIG. 9. [Figure 11] 11 is a schematic, partially exploded perspective view illustrating the nonvolatile memory device of FIGS. 9 and 10. FIG. [Figure 12] 1 is a schematic, partially exploded perspective view illustrating a nonvolatile memory device according to some embodiments. [Figure 13] 1 is a schematic, partially exploded perspective view illustrating a nonvolatile memory device according to some embodiments. [Figure 14] 1 is a schematic, partially exploded perspective view illustrating a nonvolatile memory device according to some embodiments. [Figure 15] 1 is a cross-sectional view illustrating a nonvolatile memory device according to some embodiments. [Figure 16] 1 is a cross-sectional view illustrating a nonvolatile memory device according to some embodiments. [Figure 17] FIG. 17 is an enlarged view of R2 in FIG. 16. [Figure 18] 18 through 26 are diagrams illustrating intermediate stages in a method for manufacturing a nonvolatile memory device according to some embodiments. [Figure 19] 18 through 26 are diagrams illustrating intermediate stages in a method for manufacturing a nonvolatile memory device according to some embodiments. [Figure 20] 18 through 26 are diagrams illustrating intermediate stages in a method for manufacturing a nonvolatile memory device according to some embodiments. [Figure 21] 18 through 26 are diagrams illustrating intermediate stages in a method for manufacturing a nonvolatile memory device according to some embodiments. [Figure 22]18 through 26 are diagrams illustrating intermediate stages in a method for manufacturing a nonvolatile memory device according to some embodiments. [Figure 23] 18 through 26 are diagrams illustrating intermediate stages in a method for manufacturing a nonvolatile memory device according to some embodiments. [Figure 24] 18 through 26 are diagrams illustrating intermediate stages in a method for manufacturing a nonvolatile memory device according to some embodiments. [Figure 25] 18 through 26 are diagrams illustrating intermediate stages in a method for manufacturing a nonvolatile memory device according to some embodiments. [Figure 26] 18 through 26 are diagrams illustrating intermediate stages in a method for manufacturing a nonvolatile memory device according to some embodiments. [Figure 27] 27 through 30 are diagrams illustrating intermediate stages in a method for manufacturing a nonvolatile memory device according to some embodiments. [Figure 28] 27 through 30 are diagrams illustrating intermediate stages in a method for manufacturing a nonvolatile memory device according to some embodiments. [Figure 29] 27 through 30 are diagrams illustrating intermediate stages in a method for manufacturing a nonvolatile memory device according to some embodiments. [Figure 30] 27 through 30 are diagrams illustrating intermediate stages in a method for manufacturing a nonvolatile memory device according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, nonvolatile memory devices according to some embodiments will be described with reference to FIGS.

[0012] FIG. 1 is an exemplary circuit diagram illustrating a nonvolatile memory device according to some embodiments.

[0013] A memory cell array of a nonvolatile memory device according to some embodiments may include a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR.

[0014] The plurality of bit lines BL are arranged two-dimensionally. For example, the bit lines BL may extend in a first direction X while being spaced apart from one another. A plurality of cell strings CSTR may be connected in parallel to each bit line BL. The cell strings CSTR may be commonly connected to a common source line CSL. That is, a plurality of cell strings CSTR may be arranged between the bit lines BL and the common source line CSL.

[0015] In some embodiments, the common source lines CSL are arranged two-dimensionally. For example, the common source lines CSL may be spaced apart from one another and extend in the second direction Y. The common source lines CSL may be electrically supplied with the same voltage or may be electrically supplied with different voltages and controlled separately.

[0016] Each cell string CSTR may include a ground select transistor GST connected to a common source line CSL, a string select transistor SST connected to a bit line BL, and a plurality of memory cell transistors MCT arranged between the ground select transistor GST and the string select transistor SST. Each memory cell transistor MCT may include a data storage element. The ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.

[0017] A common source line CSL may be commonly connected to the sources of the ground select transistors GST. A ground select line GSL, a plurality of word lines WL11-WL1n, WL21-WL2n, and a string select line SSL may be arranged between the common source line CSL and the bit line BL. The ground select line GSL may be used as a gate electrode of the ground select transistor GST, the word lines WL11-WL1n, WL21-WL2n may be used as gate electrodes of the memory cell transistors MCT, and the string select line SSL may be used as a gate electrode of the string select transistor SST.

[0018] FIG. 2 is a layout diagram illustrating a nonvolatile memory device according to some embodiments. FIG. 3 is a cross-sectional view taken along line AA in FIG. 2. FIG. 4 is an enlarged view of R1 in FIG. 3. FIG. 5 is a cross-sectional view taken along line BB in FIG. 2. FIG. 6 is a cross-sectional view taken along line CC in FIG. 2. FIG. 7 is a cross-sectional view taken along line DD in FIG. 2. For convenience of explanation, bit lines BL are omitted from FIG. 2.

[0019] 2 to 7, a nonvolatile memory device according to some embodiments includes a substrate 100, a first mold structure MS1, a second mold structure MS2, a plurality of channel structures CS, and a plurality of bit lines BL.

[0020] The substrate 100 may include a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate, or may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0021] The substrate 100 may include a cell array region CAR and a contact region CTR.

[0022] A memory cell array including a plurality of memory cells may be formed in the cell array region CAR. The memory cell array may include a plurality of memory cells and a plurality of word lines and a plurality of bit lines electrically connected to the respective memory cells. For example, a first mold structure MS1, a second mold structure MS2, a plurality of channel structures CS, and a plurality of bit lines BL, which will be described later, may be formed in the cell array region CAR.

[0023] The contact region CTR may be arranged around the cell array region CAR. A plurality of gate electrodes GSL, WL11-WL1n, WL21-WL2n, and SSL, which will be described later, may be stacked in a staircase shape in the contact region CTR. Furthermore, memory cell contacts (not shown) connected to the respective gate electrodes GSL, WL11-WL1n, WL21-WL2n, and SSL may be formed in the contact region CTR. For example, the memory cell contacts may be formed to penetrate the first interlayer insulating film 140 and the second interlayer insulating film 165 and be connected to the respective gate electrodes GSL, WL11-WL1n, WL21-WL2n, and SSL.

[0024] The first mold structure MS1 may be formed on the substrate 100. The first mold structure MS1 may include a plurality of first gate electrodes GSL, WL11-WL1n and a plurality of first insulating patterns 110 alternately stacked on the substrate 100. For example, each of the first gate electrodes GSL, WL11-WL1n and each of the first insulating patterns 110 may have a layered structure extending in a first direction X and a second direction Y. The first gate electrodes GSL, WL11-WL1n and the first insulating patterns 110 may be alternately stacked in a third direction Z that intersects (e.g., is perpendicular to) the top surface of the substrate 100.

[0025] In some embodiments, the plurality of first gate electrodes GSL, WL11 to WL1n may include a ground selection line GSL and a plurality of first word lines WL11 to WL1n stacked in sequence on the substrate 100. In some embodiments, the ground selection line GSL may be a gate electrode arranged at the bottom of the plurality of first gate electrodes GSL, WL11 to WL1n.

[0026] The second mold structure MS2 may be formed on the first mold structure MS1. The second mold structure MS2 may include a plurality of second gate electrodes WL21-WL2n, SSL and a plurality of second insulating patterns 112 alternately stacked on the first mold structure MS1. For example, each of the second gate electrodes WL21-WL2n, SSL and each of the second insulating patterns 112 may have a layered structure extending in the first direction X and the second direction Y. The second gate electrodes WL21-WL2n, SSL and the second insulating patterns 112 may be alternately stacked in the third direction Z.

[0027] In some embodiments, the plurality of second gate electrodes WL21-WL2n, SSL may include a plurality of second word lines WL21-WL2n and a string select line SSL stacked in sequence on the first mold structure MS1. In some embodiments, the string select line SSL may be a gate electrode disposed on top of the plurality of second gate electrodes WL21-WL2n, SSL.

[0028] The first gate electrodes GSL, WL11 to WL1n and the second gate electrodes WL21 to WL2n, SSL may include a conductive material, for example, a metal such as tungsten (W), cobalt (Co), or nickel (Ni), or a semiconductor material such as silicon, but are not limited thereto.

[0029] The first insulating pattern 110 and the second insulating pattern 112 may include an insulating material, such as, but not limited to, silicon oxide.

[0030] The plurality of channel structures CS may penetrate the first mold structure MS1 and the second mold structure MS2. The plurality of channel structures CS may extend in a direction intersecting the plurality of gate electrodes GSL, WL11-WL1n, WL21-WL2n, and SSL. For example, each channel structure CS may have a pillar pattern (e.g., a cylindrical shape) extending in the third direction Z. Each channel structure CS may include a semiconductor pattern 130 and an information storage layer 132.

[0031] The semiconductor pattern 130 may penetrate the first mold structure MS1 and the second mold structure MS2. For example, the semiconductor pattern 130 may extend in the third direction Z. Although the semiconductor pattern 130 has a cup shape in the above example, this is merely an example. For example, the semiconductor pattern 130 may have various shapes such as a cylindrical shape, a rectangular tube shape, or a pillar shape with a hollow center.

[0032] The semiconductor pattern 130 may include, but is not limited to, semiconductor materials such as monocrystalline silicon, polycrystalline silicon, organic semiconductor materials, and carbon nanostructures.

[0033] The information storage layer 132 may be interposed between the semiconductor pattern 130 and each of the gate electrodes GSL, WL11 to WL1n, WL21 to WL2n, and SSL. For example, the information storage layer 132 may extend along the side of the semiconductor pattern 130.

[0034] The information storage layer 132 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k (high dielectric constant) material having a higher dielectric constant than silicon oxide. The high-k material may include at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0035] In some embodiments, the information storage layer 132 may include multiple layers. For example, as shown in FIG. 4, the information storage layer 132 may include a tunnel insulating layer 132a, a charge storage layer 132b, and a blocking insulating layer 132c stacked in this order on the semiconductor pattern 130.

[0036] The tunnel insulating film 132a may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)). The charge storage film 132b may include, for example, silicon nitride. The blocking insulating film 132c may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (e.g., aluminum oxide (Al2O3) or hafnium oxide (HfO2)).

[0037] In some embodiments, each channel structure CS may further include a first fill pattern 134. The first fill pattern 134 may be formed to fill the interior of the cup-shaped semiconductor pattern 130. For example, the semiconductor pattern 130 may extend along the side and bottom surfaces of the first fill pattern 134. The first fill pattern 134 may include, for example, but is not limited to, silicon oxide.

[0038] In some embodiments, each channel structure CS may further include a channel pad 136. The channel pad 136 may be formed to be connected to the upper portion of the semiconductor pattern 130. For example, the channel pad 136 may be formed in a first interlayer insulating film 140 formed on the mold structure MS.

[0039] 3, the channel pad 136 is formed on the upper surface of the semiconductor pattern 130, but this is merely an example. For example, the upper portion of the semiconductor pattern 130 may be formed to extend along the side of the channel pad 136. The channel pad 136 may include, for example, impurity-doped polysilicon, but is not limited thereto.

[0040] In some embodiments, the plurality of channel structures CS may be arranged in a zigzag pattern. For example, as shown in FIG. 1, the plurality of channel structures CS may be arranged to cross each other in a first direction X and a second direction Y. The plurality of channel structures CS arranged in a zigzag pattern may further improve the integration density of the nonvolatile memory device.

[0041] In some embodiments, the width of the channel structures CS penetrating the first mold structure MS1 may decrease as they approach the top surface of the substrate 100. Also, the width of the channel structures CS penetrating the second mold structure MS2 may decrease as they approach the top surface of the substrate 100. This is due to the characteristics of the etching process used to form the channel structures CS.

[0042] In some embodiments, the width of the channel structure CS through the top surface of the first mold structure MS1 may be greater than the width of the channel structure CS through the bottom surface of the second mold structure MS2 because the etching steps through the first mold structure MS1 and the etching steps through the second mold structure MS2 are performed separately.

[0043] Unlike the illustrated example, in some embodiments, the width of the channel structure CS may gradually decrease in a direction from the top surface of the second mold structure MS2 to the bottom surface of the first mold structure MS1. For example, the etching through the first mold structure MS1 and the etching through the second mold structure MS2 may be performed simultaneously.

[0044] The multiple bit lines BL may extend side by side and spaced apart from each other. For example, each bit line BL may extend in the first direction X. In some embodiments, the multiple bit lines BL may be formed on the second mold structure MS2.

[0045] Each bit line BL can be connected to multiple channel structures CS. For example, as shown in FIGS. 3 and 5, the bit line BL can be connected to multiple channel structures CS via bit line contacts 170. The bit line contacts 170 can electrically connect the bit lines BL and the channel structures CS through, for example, the second interlayer insulating film 165.

[0046] The first and second mold structures MS1 and MS2 may be separated by first and second word line trenches WLC1 and WLC2. The first and second word line trenches WLC1 and WLC2 may extend in a direction intersecting the bit lines BL. For example, the first word line trench WLC1 may extend in the second direction Y to separate the first and second mold structures MS1 and MS2. The second word line trench WLC2 may be spaced apart from the first word line trench WLC1 in the first direction X and extend in the second direction Y to separate the first and second mold structures MS1 and MS2.

[0047] Therefore, the plurality of first gate electrodes GSL, WL11 to WL1n and the plurality of second gate electrodes WL21 to WL2n, SSL can be cut by the first word line trench WLC1 and the second word line trench WLC2.

[0048] The first mold structure MS1 and the second mold structure MS2 separated by the first word line trench WLC1 and the second word line trench WLC2 may form a block region BLK. For example, as shown in FIG. 2, the block region BLK may be defined between the first word line trench WLC1 and the second word line trench WLC2.

[0049] In some embodiments, the first word line trench WLC1 can completely cut through the first mold structure MS1 and the second mold structure MS2, and the second word line trench WLC2 can completely cut through the first mold structure MS1 and the second mold structure MS2.

[0050] In some embodiments, as shown in FIG. 2, the first word line trench WLC1 and the second word line trench WLC2 may be formed across the cell array region CAR and the contact region CTR.

[0051] 3 and 5, the widths of the first and second word line trenches WLC1 and WLC2 cutting the first mold structure MS1 may decrease as they approach the top surface of the substrate 100. Also, the widths of the first and second word line trenches WLC1 and WLC2 cutting the second mold structure MS2 may decrease as they approach the top surface of the substrate 100. This is due to the characteristics of the etching process that forms the first and second word line trenches WLC1 and WLC2.

[0052] In some embodiments, the widths of the first and second word line trenches WLC1 and WLC2 that cut through the top surface of the first mold structure MS1 may be larger than the widths of the first and second word line trenches WLC1 and WLC2 that cut through the bottom surface of the second mold structure MS2 because the etching steps that cut through the first mold structure MS1 and the etching steps that cut through the second mold structure MS2 are performed separately.

[0053] The first mold structure MS1 may again be cut by a first block trench BC11 and a second block trench BC12, which may be interposed between the first word line trench WLC1 and the second word line trench WLC2. That is, the first block trench BC11 and the second block trench BC12 may cut the first mold structure MS1 within the block region BLK.

[0054] The first block trench BC11 and the second block trench BC12 can define multiple blocks I, II, and III in the block region BLK. For example, as shown in FIG. 2, the first block trench BC11 can define a first block I and a second block II, and the second block trench BC12 can define a second block II and a third block III.

[0055] In some embodiments, the first block trench BC11 and the second block trench BC12 may be formed across the cell array region CAR and the contact region CTR.

[0056] 3 and 5, the widths of first block trench BC11 and second block trench BC12 may decrease as they approach the top surface of substrate 100. This is due to the characteristics of the etching process that forms first block trench BC11 and second block trench BC12.

[0057] In some embodiments, first block trench BC11 and second block trench BC12 may each completely cut through first mold structure MS1, as will be described in more detail below in the discussion of FIG.

[0058] The second mold structure MS2 may again be cut by third and fourth block trenches BC21 and BC22, which may be interposed between the first and second word line trenches WLC1 and WLC2. That is, the third and fourth block trenches BC21 and BC22 may cut the second mold structure MS2 within the block region BLK.

[0059] In some embodiments, as shown in FIG. 2, the third block trench BC21 and the fourth block trench BC22 may be formed across the cell array region CAR and the contact region CTR.

[0060] 3 and 5, the widths of third block trench BC21 and fourth block trench BC22 may decrease as they approach the top surface of substrate 100. This is due to the characteristics of the etching process that forms third block trench BC21 and fourth block trench BC22.

[0061] In some embodiments, the width of the top of the first block trench BC11 and the second block trench BC12 may be greater than the width of the bottom of the third block trench BC21 and the fourth block trench BC22 because the etching step for cutting the first mold structure MS1 and the etching step for cutting the second mold structure MS2 are performed separately.

[0062] In some embodiments, the third block trench BC21 and the fourth block trench BC22 can each cut a portion of the second mold structure MS2, as will be described in more detail below in the description of FIG.

[0063] In some embodiments, spacers 154 and second fill patterns 152 may be formed in the first and second word line trenches WLC1, WLC2 and the first through fourth block trenches BC11, BC12, BC21, BC22.

[0064] The spacers 154 may extend along the profiles of the first and second word line trenches WLC1, WLC2 and the first through fourth block trenches BC11, BC12, BC21, and BC22. The second fill pattern 152 may be formed to fill the regions of the first and second word line trenches WLC1, WLC2 and the first through fourth block trenches BC11, BC12, BC21, and BC22 that remain after the spacers 154 are formed.

[0065] In some embodiments, the second fill pattern 152 filling the first and second word line trenches WLC1, WLC2 may be provided to a common source line (e.g., CSL in FIG. 1) of the non-volatile memory device. For example, the second fill pattern 152 may include a conductive material. The second fill pattern 152 filling the first and second word line trenches WLC1, WLC2 may be connected to the substrate 100 through the first mold structure MS1 and the second mold structure MS2.

[0066] In some embodiments, the second fill pattern 152 may be connected to the impurity regions 105 in the substrate 100. The impurity regions 105 may extend in the second direction Y, for example.

[0067] The spacers 154 may include an insulating material, so that the second filling pattern 152 can be electrically isolated from the plurality of first gate electrodes GSL, WL11 to WL1n and the plurality of second gate electrodes WL21 to WL2n, SSL.

[0068] In some embodiments, the second fill pattern 152 filling the first through fourth block trenches BC11, BC12, BC21, and BC22 may not be connected to the substrate 100. For example, as shown in FIGS. 3 and 5, the spacers 154 may extend along the bottom surfaces of the first and second block trenches BC11 and BC12.

[0069] However, the technical idea of ​​the present invention is not limited thereto, and only insulating material may be formed in the first and second word line trenches WLC1, WLC2 and the first through fourth block trenches BC11, BC12, BC21, BC22.

[0070] In some embodiments, the second mold structure MS2 may further include a first cutting line CL1 and a second cutting line CL2, which may be interposed between the first word line trench WLC1 and the second word line trench WLC2.

[0071] The first cutting line CL1 and the second cutting line CL2 can cut the string selection line SSL. For example, as shown in Fig. 3, the first cutting line CL1 can extend in the second direction Y to cut the string selection line SSL. The second cutting line CL2 can be spaced apart from the first cutting line CL1 in the first direction X and extend in the second direction Y to cut the string selection line SSL.

[0072] 2, a first cutting line CL1 may be interposed between a first block I and a second block II, and a second cutting line CL2 may be interposed between a second block II and a third block III. Therefore, the channel structures CS in the first block I and the channel structures CS in the second block II can be separately selected and controlled via the string select line SSL cut by the first cutting line CL1. Similarly, the channel structures CS in the second block II and the channel structures CS in the third block III can be separately selected and controlled via the string select line SSL cut by the second cutting line CL2.

[0073] Hereinafter, the first mold structure MS1 and the second mold structure MS2 of the nonvolatile memory device according to some embodiments will be described in more detail with reference to FIGS.

[0074] Figure 8 is a schematic, partially exploded perspective view illustrating the first mold structure MS1 and the second mold structure MS2 of Figures 2 to 7. For convenience of explanation, Figure 8 illustrates only the cell array region CAR of Figure 1. Also, in Figure 8, the second filling patterns 152 and the spacers 154 are not shown.

[0075] Referring to FIG. 8, the first mold structure MS1 may include a first block trench BC11 and a second block trench BC12 that cut through the first mold structure MS1.

[0076] In some embodiments, the first block trench BC11 and the second block trench BC12 can each completely cut through the first mold structure MS1. For example, the first block trench BC11 can extend in the second direction Y to completely cut through the first mold structure MS1. The second block trench BC12 can be spaced apart from the first block trench BC11 in the first direction X and extend in the second direction Y to completely cut through the first mold structure MS1.

[0077] Thus, the first mold structure MS1 between the first word line trench WLC1 and the second word line trench WLC2 may include multiple stacks S11, S12, and S13 separated by the first block trench BC11 and the second block trench BC12. For example, the first stack S11 and the second stack S12 may be separated from each other by the first block trench BC11. Furthermore, the second stack S12 and the third stack S13 may be separated from each other by the second block trench BC12.

[0078] The second mold structure MS2 may include a plurality of third block trenches BC21 and a plurality of fourth block trenches BC22 that cut through the second mold structure MS2.

[0079] In some embodiments, the third block trench BC21 and the second block trench BC12 may cut a portion of the second mold structure MS2. For example, the third block trenches BC21 may be spaced apart from one another and arranged along the second direction Y. The fourth block trenches BC22 may be spaced apart from the third block trenches BC21 in the first direction X and arranged along the second direction Y.

[0080] Therefore, the second mold structure MS2 between the first word line trench WLC1 and the second word line trench WLC2 may include a plurality of stacks S21, S22, and S23 that are at least partially connected by a plurality of first connecting portions CP1 and a plurality of second connecting portions CP2. For example, the fourth stack S21 and the fifth stack S22 may be connected to each other by a plurality of first connecting portions CP1. Also, the fifth stack S22 and the sixth stack S23 may be connected to each other by a plurality of second connecting portions CP2.

[0081] The fourth stack S21 may be stacked on the first stack S11, the fifth stack S22 may be stacked on the second stack S12, and the sixth stack S23 may be stacked on the third stack S13.

[0082] The plurality of first connecting parts CP1 may be spaced apart from each other and arranged in the second direction Y. That is, the third isolation trenches BC21 and the first connecting parts CP1 may be alternately arranged in the second direction Y. The plurality of second connecting parts CP2 may be spaced apart from each other and arranged in the second direction Y. That is, the fourth isolation trenches BC22 and the second connecting parts CP2 may be alternately arranged in the second direction Y.

[0083] Therefore, the bottom surfaces of the first and second connecting portions CP1 and CP2 may be spaced apart from the top surface of the substrate 100. In some embodiments, the third block trench BC21 and the first connecting portion CP1 may overlap the first block trench BC11 in the third direction Z, and the fourth block trench BC22 and the second connecting portion CP2 may overlap the second block trench BC12 in the third direction Z.

[0084] Furthermore, each third block trench BC21 may expose a portion of the first block trench BC11, and each fourth block trench BC22 may expose a portion of the second block trench BC12. That is, the third block trench BC21 may be connected to the first block trench BC11, and the fourth block trench BC22 may be connected to the second block trench BC12.

[0085] In some embodiments, the first cutting line CL1 may be formed in the first connecting portion CP1, and the second cutting line CL2 may be formed in the second connecting portion CP2. In some embodiments, the width of the first cutting line CL1 may be smaller than the width of the third block trench BC21, and the width of the second cutting line CL2 may be smaller than the width of the fourth block trench BC22. Here, the width refers to the width in the first direction X. Therefore, a portion of the string select line SSL may be disposed in the first connecting portion CP1 and the second connecting portion CP2.

[0086] As nonvolatile memory devices become more highly integrated, an increasing number of channel structures are disposed within a mold structure cut by word line trenches (e.g., block region BLK in FIG. 2). To individually control the multiple channel structures within a block region BLK, the mold structure cut by the word line trenches can be cut again to form multiple blocks (e.g., first through third blocks I, II, and III).

[0087] However, as the aspect ratio (AR) of a nonvolatile memory device increases, a leaning phenomenon, such as bending or tilting of each block I, II, and III, can occur. To prevent this, connecting portions that support the blocks I, II, and III are formed by patterning the block region BLK into an "H" shape, but these connecting portions can cause poor separation of the lower portion of the mold structure, reducing product reliability. For example, during the process of patterning the block region BLK into an "H" shape, etchant may not be uniformly injected into the lower portion of the mold structure away from the connecting portion and the lower portion of the mold structure adjacent to the connecting portion.

[0088] However, in some embodiments of nonvolatile memory devices, the first mold structure MS1 constituting the lower portion of the mold structure may be completely separated by the first block trench BC11 and the second block trench BC12. That is, because no connection is formed within the first mold structure MS1, separation of the lower portion of the first mold structure MS1 may be improved.

[0089] In addition, the second mold structure MS2 on the first mold structure MS1 may include first and second connecting portions CP1 and CP2 that support the blocks I, II, and III, thereby preventing the leaning phenomenon of the blocks I, II, and III and providing a nonvolatile memory device with improved product reliability.

[0090] Figure 9 is a layout diagram illustrating a nonvolatile memory device according to some embodiments. Figure 10 is a cross-sectional view taken along the line EE in Figure 9. Figure 11 is a schematic, partially exploded perspective view illustrating the nonvolatile memory device of Figures 9 and 10. For convenience of explanation, parts that overlap with those described above using Figures 1 to 8 will be briefly described or omitted.

[0091] 9-11, in nonvolatile memory devices according to some embodiments, the first word line trench WLC1 and the second word line trench WLC2 may cut a portion of the second mold structure MS2.

[0092] Therefore, the second mold structure MS2 may include a seventh stack S24 at least partially connected to the fourth stack S21 by a plurality of third connecting portions CP3. The second mold structure MS2 may also include an eighth stack S25 at least partially connected to the sixth stack S23 by a plurality of fourth connecting portions CP4. For example, the fourth stack S21 and the seventh stack S24 may be connected to each other by a plurality of third connecting portions CP3. The sixth stack S23 and the eighth stack S25 may be connected to each other by a plurality of fourth connecting portions CP4.

[0093] The plurality of third connectors CP3 may be spaced apart from each other and arranged in the second direction Y. That is, the first word line trenches WLC1 and the third connectors CP3 may be alternately arranged in the second direction Y. The plurality of fourth connectors CP4 may be spaced apart from each other and arranged in the second direction Y. That is, the second word line trenches WLC2 and the fourth connectors CP4 may be alternately arranged in the second direction Y.

[0094] In some embodiments, the bottom surface of the third connecting portion CP3 and the bottom surface of the fourth connecting portion CP4 may be spaced apart from the top surface of the substrate 100.

[0095] In some embodiments, the second mold structure MS2 may further include third cutting lines CL3 and fourth cutting lines CL4. The third cutting lines CL3 and fourth cutting lines CL4 can cut the second gate electrodes WL21-WL2n, SSL. For example, as shown in FIG. 10, the third cutting lines CL3 and fourth cutting lines CL4 can extend in the second direction Y to cut the second gate electrodes WL21-WL2n, SSL.

[0096] In some embodiments, the third cutting lines CL3 may be formed in the third connectors CP3, and the fourth cutting lines CL4 may be formed in the fourth connectors CP4. In some embodiments, the width of the third cutting lines CL3 may be smaller than the width of the first word line trenches WLC1, and the width of the fourth cutting lines CL4 may be smaller than the width of the second word line trenches WLC2. Here, "width" refers to the width in the first direction X. Therefore, a portion of each of the second gate electrodes WL21-WL2n, SSL may be disposed within the third connectors CP3 and the fourth connectors CP4.

[0097] 12 is a schematic partially exploded perspective view illustrating a nonvolatile memory device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 8 will be briefly described or omitted.

[0098] Referring to FIG. 12, a nonvolatile memory device according to some embodiments further includes a third mold structure MS3.

[0099] The third mold structure MS3 may be formed on the second mold structure MS2. The third mold structure MS3 may include a plurality of third gate electrodes WL31-WL3n, SSL, and a plurality of third insulating patterns 114 alternately stacked on the second mold structure MS2. A plurality of channel structures CS may penetrate the first mold structure MS1, the second mold structure MS2, and the third mold structure MS3.

[0100] In some embodiments, the plurality of third gate electrodes WL31-WL3n, SSL may include a plurality of third word lines WL31-WL3n and a string select line SSL stacked in sequence on the second mold structure MS2. In some embodiments, the string select line SSL may be a gate electrode disposed on top of the plurality of third gate electrodes WL31-WL3n, SSL.

[0101] In some embodiments, the second mold structure MS2 may not include a string select line SSL. For example, the plurality of second gate electrodes WL21, WL22 to WL2n may include a plurality of second word lines WL21, WL22 to WL2n stacked in sequence on the first mold structure MS1. In some embodiments, the second mold structure MS2 may not include a first cutting line CL1 and a second cutting line CL2.

[0102] In some embodiments, the first word line trench WLC1 and the second word line trench WLC2 can completely cut through the third mold structure MS3.

[0103] The third mold structure MS3 may again be cut by fifth and sixth block trenches BC31 and BC32, which may be interposed between the first and second word line trenches WLC1 and WLC2.

[0104] In some embodiments, the third mold structure MS3 may include a plurality of fifth block trenches BC31 and a plurality of sixth block trenches BC32 that cut through the third mold structure MS3. The fifth block trenches BC31 and the sixth block trenches BC32 may cut through a portion of the third mold structure MS3.

[0105] Therefore, the third mold structure MS3 between the first word line trench WLC1 and the second word line trench WLC2 may include a plurality of stacks S31, S32, and S33 that are at least partially connected by a plurality of fifth connecting portions CP5 and a plurality of sixth connecting portions CP6. For example, the ninth stack S31 and the tenth stack S32 may be connected to each other by a plurality of fifth connecting portions CP5. Also, the tenth stack S32 and the eleventh stack S33 may be connected to each other by a plurality of sixth connecting portions CP6.

[0106] Although the fifth connecting portion CP5 overlaps with the first connecting portion CP1 in the third direction Z and the sixth connecting portion CP6 overlaps with the second connecting portion CP2 in the third direction Z, this is merely an example. For example, the fifth connecting portion CP5 does not have to overlap with the first connecting portion CP1 in the third direction Z, and the sixth connecting portion CP6 does not have to overlap with the second connecting portion CP2 in the third direction Z.

[0107] In some embodiments, the third mold structure MS3 may further include fifth and sixth cut lines CL5 and CL6. The fifth and sixth cut lines CL5 and CL6 may be interposed between the first and second word line trenches WLC1 and WLC2. The fifth and sixth cut lines CL5 and CL6 may extend in the second direction Y to cut the string select lines SSL.

[0108] In some embodiments, the fifth cutting line CL5 may be formed in the fifth connecting portion CP5, and the sixth cutting line CL6 may be formed in the sixth connecting portion CP6.

[0109] 13 is a schematic partially exploded perspective view illustrating a nonvolatile memory device according to some embodiments. For convenience of explanation, parts that overlap with the contents described above using FIGS. 1 to 12 will be briefly described or omitted.

[0110] Referring to FIG. 13, in nonvolatile memory devices according to some embodiments, third block trench BC21 and fourth block trench BC22 each completely cut through second mold structure MS2.

[0111] For example, the third block trench BC21 may extend in the second direction Y to completely cut through the second mold structure MS2. The fourth block trench BC22 may be spaced apart from the third block trench BC21 in the first direction X and extend in the second direction Y to completely cut through the second mold structure MS2.

[0112] Therefore, the fourth stack S21 and the fifth stack S22 may be separated from each other by the third block trench BC21, and the fifth stack S22 and the sixth stack S23 may be separated from each other by the fourth block trench BC22.

[0113] 14 is a schematic partially exploded perspective view illustrating a nonvolatile memory device according to some embodiments. For convenience of explanation, parts that overlap with the contents described above using FIGS. 1 to 12 will be briefly described or omitted.

[0114] Referring to FIG. 14, in nonvolatile memory devices according to some embodiments, fifth block trench BC31 and sixth block trench BC32 each completely cut through third mold structure MS3.

[0115] For example, the fifth block trench BC31 may extend in the second direction Y to completely cut through the third mold structure MS3. The sixth block trench BC32 is spaced apart from the fifth block trench BC31 in the first direction X and extends in the second direction Y to completely cut through the third mold structure MS3.

[0116] Therefore, the ninth stack S31 and the tenth stack S32 may be separated from each other by the fifth block trench BC31, and the tenth stack S32 and the eleventh stack S33 may be separated from each other by the sixth block trench BC32.

[0117] 15 is a cross-sectional view illustrating a nonvolatile memory device according to some embodiments. For convenience of explanation, portions overlapping with those described above using FIGS. 1 to 8 will be briefly described or omitted. For reference, FIG. 15 is a cross-sectional view taken along line AA in FIG. 2.

[0118] Referring to FIG. 15, a nonvolatile memory device according to some embodiments further includes a base substrate 10 and a peripheral circuit structure PS.

[0119] The base substrate 10 may include a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate, or may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0120] A peripheral circuit structure PS may be formed on the base substrate 10. The peripheral circuit structure PS may constitute a peripheral circuit that controls the operation of each memory cell. For example, the peripheral circuit structure PS may include a row decoder, a column decoder, a page buffer, a control circuit, etc. For example, as shown in FIG. 15 , the peripheral circuit structure PS may include a peripheral circuit element PT and a wiring structure PW.

[0121] In some embodiments, the peripheral circuit element PT may include a transistor. For example, the peripheral circuit element PT may include a peripheral circuit gate electrode 12, a peripheral circuit gate insulating film 14, a gate spacer 16, and source / drain regions 18.

[0122] In some embodiments, the peripheral circuit elements PT may be high-voltage transistors. While only the case where the peripheral circuit elements PT are transistors has been described, this is merely an example and the technical concept of the present invention is not limited thereto. For example, the peripheral circuit elements PT may include not only various active elements such as transistors, but also various passive elements such as capacitors, resistors, and inductors.

[0123] In some embodiments, a third interlayer insulating film 20 may be formed on the base substrate 10. The third interlayer insulating film 20 may be formed to cover the peripheral circuit elements PT on the base substrate 10. Although the third interlayer insulating film 20 is illustrated as a single film, this is for convenience of explanation, and the third interlayer insulating film 20 may of course be a multi-film in which multiple insulating films are stacked. The third interlayer insulating film 20 may include, for example, silicon oxide, but is not limited thereto.

[0124] The wiring structure PW may include peripheral circuit wiring 22 and peripheral circuit contacts 24. The peripheral circuit wiring 22 and the peripheral circuit contacts 24 may be formed, for example, in the third interlayer insulating film 20. The peripheral circuit wiring 22 may be coupled to the peripheral circuit elements PT via the peripheral circuit contacts 24.

[0125] The peripheral circuit wiring 22 may include, but is not limited to, a metal (e.g., copper (Cu) or aluminum (Al)). The peripheral circuit contacts 24 may include, but are not limited to, silicon (e.g., polysilicon) or a metal (e.g., tungsten (W) or copper (Cu)).

[0126] Figure 16 is a cross-sectional view illustrating a nonvolatile memory device according to some embodiments. Figure 17 is an enlarged view of R2 in Figure 16. For convenience of explanation, portions that overlap with the contents described above using Figures 1 to 15 will be briefly described or omitted. For reference, Figure 16 is a cross-sectional view taken along line AA in Figure 2.

[0127] 16 and 17, a non-volatile memory device according to some embodiments further includes a source structure 200.

[0128] The source structure 200 may be formed on the substrate 100. In some embodiments, the source structure 200 may be interposed between the substrate 100 and the first mold structure MS1. The source structure 200 may include a conductive material. For example, the source structure 200 may include impurity-doped polysilicon or a metal.

[0129] In some embodiments, each channel structure CS may be connected to the substrate 100 through the source structure 200. For example, as shown in FIG. 17 , the substrate 100 may include a substrate trench ST. The lower portion of each channel structure CS may be formed to fill the substrate trench ST. In some embodiments, the information storage film 132 of each channel structure CS may extend along the side and bottom surfaces of the substrate trench ST.

[0130] In some embodiments, the source structures 200 may be formed to be connected to the semiconductor patterns 130 of the respective channel structures CS. For example, the source structures 200 may be connected to the semiconductor patterns 130 through a portion of the information storage layer 132.

[0131] In some embodiments, a portion of the source structure 200 adjacent to the semiconductor pattern 130 may protrude toward the information storage layer 132. For example, the length of the source structure 200 extending in the third direction Z may be longer in the region adjacent to the semiconductor pattern 130. This is due to the characteristics of the etching process that removes a portion of the information storage layer 132 to form the source structure 200.

[0132] Hereinafter, a method for manufacturing a nonvolatile memory device according to some embodiments will be described with reference to FIGS.

[0133] 18 to 26 are views illustrating intermediate stages for explaining a method for manufacturing a nonvolatile memory device according to some embodiments. For convenience of explanation, portions that overlap with the contents described above using FIGS. 1 to 8 will be briefly explained or omitted. For reference, FIGS. 18 to 26 are schematic, partially exploded perspective views for explaining a method for manufacturing a nonvolatile memory device according to some embodiments.

[0134] Referring to FIG. 18, a plurality of first sacrificial patterns 210 and a plurality of first insulating patterns 110 are formed.

[0135] The first sacrificial patterns 210 and the first insulating patterns 110 may be alternately stacked in the third direction Z. The first sacrificial patterns 210 may include a material having an etching selectivity with respect to the first insulating patterns 110. For example, when the first insulating patterns 110 include silicon oxide, the first sacrificial patterns 210 may include polysilicon.

[0136] Referring to FIG. 19, a plurality of sacrificial channels 220 are formed through the first sacrificial pattern 210 and the first insulating pattern 110 .

[0137] For example, a plurality of first through holes may be formed extending in the third direction Z through the plurality of first sacrificial patterns 210 and the plurality of first insulating patterns 110. Then, a plurality of sacrificial channels 220 may be formed to fill the first through holes, respectively. The sacrificial channels 220 may include a material having an etching selectivity with respect to the first sacrificial patterns 210 and the first insulating patterns 110.

[0138] Referring to FIG. 20, first and second word line trenches WLC1 and WLC2 and first and second block trenches BC11 and BC12 cutting the first sacrificial pattern 210 and the first insulating pattern 110 are formed.

[0139] The first and second word line trenches WLC1, WLC2 and the first and second block trenches BC11, BC12 may cut through the plurality of first sacrificial patterns 210 and the plurality of first insulating patterns 110. In some embodiments, the first and second word line trenches WLC1, WLC2 and the first and second block trenches BC11, BC12 may extend in the second direction Y to completely cut through the plurality of first sacrificial patterns 210 and the plurality of first insulating patterns 110, respectively.

[0140] Therefore, the plurality of first sacrificial patterns 210 and the plurality of first insulating patterns 110 may form first to third stacks S11, S12, and S13 that are separated by the first block trench BC11 and the second block trench BC12.

[0141] Referring to FIG. 21, a plurality of sacrificial fill patterns 230 are formed in the first and second word line trenches WLC1, WLC2 and the first and second block trenches BC11, BC12.

[0142] The sacrificial fill pattern 230 may be formed to fill the first and second word line trenches WLC1 and WLC2 and the first and second block trenches BC11 and BC12. The sacrificial fill pattern 230 may include a material having an etch selectivity with respect to the first sacrificial pattern 210 and the first insulating pattern 110.

[0143] Referring to FIG. 22, a plurality of second sacrificial patterns 212 and a plurality of second insulating patterns 112 are formed on the plurality of first sacrificial patterns 210 and the plurality of first insulating patterns 110.

[0144] The second sacrificial patterns 212 and the second insulating patterns 112 may be alternately stacked in the third direction Z. The second sacrificial patterns 212 may include a material having an etching selectivity with the second insulating patterns 112. For example, when the second insulating patterns 112 include silicon oxide, the second sacrificial patterns 212 may include polysilicon.

[0145] In some embodiments, the second sacrificial pattern 212 may comprise the same material as the first sacrificial pattern 210 and the second insulating pattern 112 may comprise the same material as the first insulating pattern 110 .

[0146] In some embodiments, a first cutting line CL1 and a second cutting line CL2 may further be formed.

[0147] The first cutting line CL1 and the second cutting line CL2 may cut the second sacrificial pattern 212 that is arranged at the top among the plurality of second sacrificial patterns 212. For example, the first cutting line CL1 may extend in the second direction Y to cut the uppermost second sacrificial pattern 212. The second cutting line CL2 may be spaced apart from the first cutting line CL1 in the first direction X and extend in the second direction Y to cut the uppermost second sacrificial pattern 212.

[0148] In some embodiments, the first cutting line CL1 may be formed to overlap the first block trench BC11 in the third direction Z, and the second cutting line CL2 may be formed to overlap the second block trench BC12 in the third direction Z.

[0149] Referring to FIG. 23, a plurality of channel structures CS penetrating the first sacrificial pattern 210, the first insulating pattern 110, the second sacrificial pattern 212 and the second insulating pattern 112 are formed.

[0150] For example, a plurality of second through holes may be formed extending in the third direction Z through the plurality of second sacrificial patterns 212 and the plurality of second insulating patterns 112. The second through holes may be formed to expose sacrificial channels (220 in FIG. 21). The sacrificial channels 220 exposed by the second through holes may then be removed. A plurality of channel structures CS may then be formed to fill the first and second through holes.

[0151] Although the first through hole and the second through hole are formed separately in the above description, the technical concept of the present invention is not limited thereto. In some embodiments, the step of forming the sacrificial channel 220 may be omitted. In that case, a through hole may be formed that penetrates all of the first sacrificial pattern 210, the first insulating pattern 110, the second sacrificial pattern 212, and the second insulating pattern 112.

[0152] Referring to FIG. 24, first and second word line trenches WLC1 and WLC2 cutting the second sacrificial pattern 212 and the second insulating pattern 112, a plurality of third block trenches BC21, and a plurality of fourth block trenches BC22 are formed.

[0153] In some embodiments, the first and second word line trenches WLC1, WLC2 each extend in the second direction Y to completely cut through the plurality of second sacrificial patterns 212 and the plurality of second insulating patterns 112.

[0154] In some embodiments, the third and fourth block trenches BC21 and BC22 may cut a portion of each second sacrificial pattern 212 and a portion of each second insulating pattern 112. For example, the third block trenches BC21 may be spaced apart from one another and arranged along the second direction Y. The fourth block trenches BC22 may be spaced apart from one another in the first direction X and arranged along the second direction Y.

[0155] Therefore, the second sacrificial pattern 212 and the second insulating pattern 112 may form fourth to sixth stacks S21, S22, and S23, at least a portion of which is connected by the first connecting portion CP1 and the second connecting portion CP2.

[0156] In some embodiments, the third block trench BC21 and the first connecting portion CP1 may overlap the first block trench BC11 in the third direction Z, and the fourth block trench BC22 and the second connecting portion CP2 may overlap the second block trench BC12 in the third direction Z. Therefore, the first cutting line CL1 may be formed in the first connecting portion CP1, and the second cutting line CL2 may be formed in the second connecting portion CP2.

[0157] Referring to FIG. 25, the plurality of sacrificial fill patterns 230 are removed.

[0158] Therefore, the first and second word line trenches WLC1, WLC2 and the first and second block trenches BC11, BC12 can expose a portion of each first sacrificial pattern 210.

[0159] Referring to FIG. 26, a plurality of first gate electrodes GSL, WL11 to WL1n and a plurality of second gate electrodes WL21 to WL2n, SSL are formed.

[0160] The plurality of first gate electrodes GSL, WL11 to WL1n can be formed in regions where the plurality of first sacrificial patterns 210 have been removed. That is, the plurality of first sacrificial patterns 210 can be replaced with the plurality of first gate electrodes GSL, WL11 to WL1n.

[0161] The plurality of second gate electrodes WL21 to WL2n, SSL can be formed in the regions from which the plurality of second sacrificial patterns 212 have been removed. That is, the plurality of second sacrificial patterns 212 can be replaced with the plurality of second gate electrodes WL21 to WL2n, SSL.

[0162] Therefore, the first mold structure MS1 and the second mold structure MS2 described above with reference to FIG. 8 can be formed.

[0163] 27 to 30 are views illustrating intermediate steps for describing a method for manufacturing a nonvolatile memory device according to some embodiments. For convenience of description, portions overlapping with those described above using FIGS. 1 to 8 and 18 to 26 will be briefly described or omitted. For reference, FIGS. 27 to 30 are schematic, partially exploded perspective views illustrating a method for manufacturing a nonvolatile memory device according to some embodiments. Also, FIG. 27 is a view illustrating a step subsequent to FIG. 22.

[0164] Referring to FIG. 27, a third cutting line CL3 and a fourth cutting line CL4 are formed.

[0165] The third cutting lines CL3 and the fourth cutting lines CL4 can cut the plurality of second sacrificial patterns 212. For example, the third cutting lines CL3 and the fourth cutting lines CL4 can extend in the second direction Y to cut the plurality of second sacrificial patterns 212.

[0166] In some embodiments, the third cutting line CL3 may be formed to overlap the first word line trench WLC1 in the third direction Z, and the fourth cutting line CL4 may be formed to overlap the second word line trench WLC2 in the third direction Z.

[0167] Referring to FIG. 28, a plurality of channel structures CS penetrating the first sacrificial pattern 210, the first insulating pattern 110, the second sacrificial pattern 212 and the second insulating pattern 112 are formed.

[0168] The formation of the plurality of channel structures CS is similar to that described above with reference to FIG. 23, and therefore a detailed description thereof will be omitted below.

[0169] Next, first and second word line trenches WLC1 and WLC2 cutting the second sacrificial pattern 212 and the second insulating pattern 112, a plurality of third block trenches BC21, and a plurality of fourth block trenches BC22 are formed.

[0170] In some embodiments, the first word line trench WLC1 and the second word line trench WLC2 may cut a portion of the second mold structure MS2. As a result, the second sacrificial pattern 212 and the second insulating pattern 112 may form a seventh stack S24 that is at least partially connected to the fourth stack S21 by the third connector CP3. Additionally, the second sacrificial pattern 212 and the second insulating pattern 112 may form an eighth stack S25 that is at least partially connected to the sixth stack S23 by the fourth connector CP4.

[0171] In some embodiments, the third cutting line CL3 may be formed in the third connecting portion CP3, and the fourth cutting line CL4 may be formed in the fourth connecting portion CP4.

[0172] Referring to FIG. 29, the plurality of sacrificial fill patterns 230 are removed.

[0173] Therefore, the first and second word line trenches WLC1, WLC2 and the first and second block trenches BC11, BC12 can expose a portion of each first sacrificial pattern 210.

[0174] Referring to FIG. 30, a plurality of first gate electrodes GSL, WL11 to WL1n and a plurality of second gate electrodes WL21 to WL2n, SSL are formed.

[0175] The formation of the plurality of first gate electrodes GSL, WL11 to WL1n and the plurality of second gate electrodes WL21 to WL2n, SSL is similar to that described above with reference to FIG. 26, and therefore detailed description thereof will be omitted below.

[0176] Therefore, the first mold structure MS1 and the second mold structure MS2 described above with reference to FIG. 11 can be formed.

[0177] Although the present invention has been described above with reference to the accompanying drawings, it should be understood that the present invention is not limited to the above-described embodiments and may be implemented in various different forms, and that those skilled in the art will appreciate that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, the above-described embodiment is illustrative in all respects and is not limiting. [Explanation of symbols]

[0178] 100: PCB 105: Impurity region 130: Semiconductor pattern 132: Information Storage Membrane 134: First filling pattern 136: Channel Pad 140: First interlayer insulating film 152: Second filling pattern 154: Spacer 165: Second interlayer insulating film 170: Bit line contact BC11, BC12, BC21, BC22: Block trench BL: Bit line CL1, CL2: Cutting line MS1, MS2: Mold structure WLC1, WLC2: word line trench

Claims

1. A substrate; a first mold structure on the substrate, the first mold structure including a plurality of first gate electrodes; a second mold structure on the first mold structure, the second mold structure including a plurality of second gate electrodes; a plurality of channel structures extending through the first mold structure and the second mold structure and intersecting with each of the first gate electrodes and each of the second gate electrodes; the first mold structure includes a first stack and a second stack spaced apart from each other; the second mold structure includes a third stack stacked on the first stack, a fourth stack stacked on the second stack, and a first connecting portion connecting the third stack and the fourth stack, The first connection part keeps all of the second gate electrodes, except for the uppermost second gate electrode, of the plurality of second gate electrodes between the third stack and the fourth stack continuous.

2. the first mold structure includes a block trench separating the first stack and the second stack; The nonvolatile memory device of claim 1 , wherein the first connection portion overlaps the block trench in a direction perpendicular to the top surface of the substrate.

3. The nonvolatile memory device of claim 1 , wherein a bottom surface of the first connection part is spaced apart from an upper surface of the substrate.

4. further comprising a third mold structure between the first mold structure and the second mold structure, the third mold structure including a plurality of third gate electrodes; The nonvolatile memory device of claim 1 , wherein the plurality of channel structures extend through the third mold structure and intersect with the respective third gate electrodes.

5. 5. The nonvolatile memory device of claim 4, wherein the third mold structure includes a fifth stack stacked between the first stack and the third stack, a sixth stack stacked between the second stack and the fourth stack, and a second connecting portion connecting the fifth stack and the sixth stack, wherein the second connecting portion keeps the plurality of third gate electrodes continuous between the fifth stack and the sixth stack.

6. the third mold structure includes a fifth stack stacked between the first stack and the third stack, and a sixth stack stacked between the second stack and the fourth stack; The non-volatile memory device of claim 4 , wherein the fifth stack and the sixth stack are spaced apart from each other.

7. the second mold structure includes a cutting line within the first connecting portion, The nonvolatile memory device according to claim 1 , wherein the cutting line cuts the second gate electrode arranged at the top of the plurality of second gate electrodes.

8. a third mold structure on the second mold structure, the third mold structure including a plurality of third gate electrodes; The nonvolatile memory device of claim 1 , wherein the plurality of channel structures extend through the third mold structure and intersect with the respective third gate electrodes.

9. the third mold structure includes a fifth stack stacked on the third stack, a sixth stack stacked on the fourth stack, and a second connecting portion connecting the fifth stack and the sixth stack, the second connecting portion allowing at least all of the third gate electrodes on the lower layer side, excluding the third gate electrode arranged at the top, among the plurality of third gate electrodes, to remain continuous between the fifth stack and the sixth stack; the third mold structure includes a cutting line in the second connecting portion, The nonvolatile memory device of claim 8 , wherein the cutting line cuts the uppermost third gate electrode among the plurality of third gate electrodes.

10. the third mold structure includes a fifth stack stacked on the third stack and a sixth stack stacked on the fourth stack; The non-volatile memory device of claim 8 , wherein the fifth stack and the sixth stack are spaced apart from each other.

11. A substrate; a first mold structure on the substrate, the first mold structure including a plurality of first gate electrodes; a second mold structure on the first mold structure, the second mold structure including a plurality of second gate electrodes and string select lines on the plurality of second gate electrodes; a plurality of channel structures passing through the first mold structure and the second mold structure and intersecting with each of the first gate electrodes, each of the second gate electrodes, and the string select lines; bit lines extending in a first direction and connected to each of the channel structures; the first mold structure includes a first block trench extending in a second direction intersecting the first direction and completely cutting the first mold structure; the second mold structure includes a plurality of second block trenches exposing portions of the first block trenches; the plurality of second block trenches are arranged alternately with first connection portions along the second direction, and the first connection portions keep the plurality of second gate electrodes continuous; the second mold structure includes a cutting line in the first connection portion that extends in the second direction and cuts the string selection line.

12. the first mold structure further includes a third block trench spaced apart from the first block trench in the first direction and extending in the second direction to completely cut through the first mold structure; the second mold structure includes a plurality of fourth block trenches exposing portions of the third block trenches; 12. The nonvolatile memory device of claim 11, wherein the plurality of fourth block trenches are arranged alternately with second connection portions along the second direction, and the second connection portions maintain the plurality of second gate electrodes continuous.

13. The non-volatile memory device of claim 11 further comprising peripheral circuit structures beneath the substrate.

14. 12. The nonvolatile memory device of claim 11, wherein the channel structure includes a semiconductor pattern penetrating the first mold structure and the second mold structure, and an information storage layer interposed between the semiconductor pattern and each of the plurality of first gate electrodes and each of the plurality of second gate electrodes.

15. further comprising a source structure between the substrate and the first mold structure; the channel structure is connected to the substrate through the source structure; The nonvolatile memory device of claim 14 , wherein the source structure is connected to the semiconductor pattern through the information storage layer.

16. A substrate; a first mold structure on the substrate, the first mold structure including a plurality of first gate electrodes; a second mold structure on the first mold structure, the second mold structure including a plurality of second gate electrodes; a plurality of channel structures extending through the first mold structure and the second mold structure and intersecting each of the first gate electrodes and each of the second gate electrodes; bit lines extending in a first direction and connected to each of the channel structures; a first word line trench extending in a second direction intersecting the first direction and cutting the first gate electrodes and the second gate electrodes; a second word line trench extending in the second direction and cutting through the first gate electrodes and the second gate electrodes; a first block trench extending in the second direction between the first word line trench and the second word line trench and cutting the plurality of first gate electrodes; the first mold structure includes a first stack and a second stack separated by the first block trench; the second mold structure includes a third stack stacked on the first stack, a fourth stack stacked on the second stack, and a plurality of first connecting portions connecting the third stack and the fourth stack; The first connection part keeps all of the second gate electrodes, except for the uppermost second gate electrode, of the plurality of second gate electrodes between the third stack and the fourth stack continuous.

17. the second mold structure includes a plurality of cutting lines extending in the second direction within each of the first connecting portions; The nonvolatile memory device of claim 16 , wherein each of the cutting lines cuts the second gate electrode arranged at the top of the plurality of second gate electrodes.

18. A substrate; a first mold structure on the substrate, the first mold structure including a plurality of first gate electrodes; a second mold structure on the first mold structure, the second mold structure including a plurality of second gate electrodes; a plurality of channel structures extending through the first mold structure and the second mold structure and intersecting each of the first gate electrodes and each of the second gate electrodes; bit lines extending in a first direction and connected to each of the channel structures; a first word line trench extending in a second direction intersecting the first direction, cutting through the plurality of first gate electrodes and cutting through a portion of the plurality of second gate electrodes; a second word line trench extending in the second direction, cutting through the plurality of first gate electrodes and cutting through a portion of the plurality of second gate electrodes; a first block trench extending in the second direction between the first word line trench and the second word line trench and cutting the plurality of first gate electrodes; the first mold structure includes a first stack and a second stack separated by the first block trench; the second mold structure includes a third stack stacked on the first stack, a fourth stack stacked on the second stack, and a plurality of first connecting portions connecting the third stack and the fourth stack; the first connection portion keeps all of the second gate electrodes, except for the second gate electrode arranged at the top, of the plurality of second gate electrodes between the third stack and the fourth stack continuous; the second mold structure further includes a plurality of second connection portions not cut by the first word line trenches, and a fifth stack connected to the third stack by the plurality of second connection portions.

19. 20. The nonvolatile memory device of claim 18, wherein a portion of each of the second gate electrodes is disposed within each of the second coupling portions.

20. The nonvolatile memory device of claim 18 , wherein the second mold structure further comprises, in each of the second connection portions, cutting lines that cut the plurality of second gate electrodes.

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