Solar cell manufacturing method

Abstract

To provide a method for manufacturing a solar cell, capable of improving performance of the solar cell while simplifying a manufacturing process.SOLUTION: A method for manufacturing a solar cell includes, in the following order: a step of forming material films of ground layers 29l and 39l; a step of forming a resist on the material films of the ground layers at a boundary between a first region 7 and a second region 8; a step of forming patterned plating layers 29u, 39u using a plating method in which the resist is used as a mask; an annealing step of heating the plating layers and the material films of the ground layers; a step of removing the resist; and a step of forming patterned ground layers 29I, 39I using an etching method in which the plating layers are used as a mask. In the annealing step, an oxide film is formed on an exposed surface of the plating layers, and in the step of forming the ground layer, the oxide film formed on the exposed surface of the plating layers is removed.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a back electrode type solar cell. [Background technology]

[0002] A known type of solar cell is a back electrode type (also called a back contact type or back junction type) solar cell, in which an electrode is formed only on the back surface. Such a solar cell includes a semiconductor substrate, a first conductivity type semiconductor layer and a first electrode layer stacked in this order on the back surface of the semiconductor substrate, and a second conductivity type semiconductor layer and a second electrode layer stacked in this order on another part of the back surface of the semiconductor substrate. The first electrode layer and the second electrode layer include metal electrode layers and are separated from each other to prevent short circuits.

[0003] Patent Document 1 discloses a manufacturing process for forming a metal electrode layer by a plating method using a resist as a mask. A resist is formed on the electrode layer separation area on the underlayer (seed layer) formed on the entire back surface, Then, a separate plating layer is formed using the resist as a mask. After that, the resist is removed and the underlying layer at the electrode layer separation location is etched. This forms a separate metal electrode layer consisting of an underlayer and a plating layer. In this way, the manufacturing process of forming a metal electrode layer using plating can simplify the manufacturing process of solar cells.

[0004] On the other hand, Patent Document 2 discloses a technique for heating a plating layer in order to promote crystallization of the plating layer. By heating the plating layer in this way, crystallization of the plating layer is promoted, and the resistance of the plating layer can be reduced. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 139020 [Patent Document 2] Japanese Patent Application Publication No. 6-295662 Summary of the Invention [Problem to be solved by the invention]

[0006] It is conceivable that the plating layer crystallization technology described in Patent Document 2 can be applied to the solar cell manufacturing process described in Patent Document 1 to reduce the resistance of the metal electrode layer (plating layer and underlayer) and improve the output of the solar cell, i.e., improve the performance of the solar cell.

[0007] However, for example, if the plating layer crystallization technique described in Patent Document 2 is applied to the final stage of the solar cell manufacturing process described in Patent Document 1, the exposed surface of the metal electrode layer (plating layer and underlayer) is oxidized during the heating step (annealing step), forming an oxide film on the exposed surface of the metal electrode layer. This increases the contact resistance between the metal electrode layer and the wiring member, resulting in a decrease in the output of the solar cell, i.e., a decrease in the performance of the solar cell. This then reduces the effect of improving the solar cell's performance by reducing the resistance of the metal electrode layer, due to the decrease in the performance of the solar cell caused by the increase in contact resistance between the metal electrode layer and the wiring member.

[0008] An object of the present invention is to provide a method for manufacturing a solar cell that can improve the performance of the solar cell while simplifying the manufacturing process. [Means for solving the problem]

[0009] A method for manufacturing a solar cell according to the present invention is a method for manufacturing a back electrode type solar cell including a semiconductor substrate, a first conductivity type semiconductor layer and a first metal electrode layer stacked in this order in a first region that is a part of one main surface side of the semiconductor substrate, and a second conductivity type semiconductor layer and a second metal electrode layer stacked in this order in a second region that is another part of the one main surface side of the semiconductor substrate, wherein each of the first metal electrode layer and the second metal electrode layer has an underlayer and a plating layer, and the method for manufacturing the solar cell includes: an underlayer material film forming step of forming a series of material films for the underlayer across the first region and the second region on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer on the one main surface side of the semiconductor substrate; The method includes, in this order, a resist forming step of forming a resist on the base layer material film at the boundary between the first region and the second region, a plating layer forming step of forming a patterned plating layer on the base layer material film in each of the first region and the second region using a plating method that uses the resist as a mask, an annealing step of heating the plating layer and the base layer material film, a resist removing step of removing the resist, and an base layer forming step of forming the patterned base layer in each of the first region and the second region by etching the base layer material film using an etching method that uses the plating layer as a mask. In the annealing step, an oxide film is formed on the exposed surface of the plating layer, and in the base layer forming step, the oxide film formed on the exposed surface of the plating layer is removed. [Effects of the Invention]

[0010] According to the present invention, it is possible to improve the performance of solar cells while simplifying the manufacturing process. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 2 is a view of the solar cell according to the embodiment as viewed from the back surface side. [Figure 2] 2 is a cross-sectional view taken along line II-II of the solar cell shown in FIG. [Figure 3]3 is an enlarged cross-sectional view of an example of a portion III in the solar cell shown in FIG. 2. FIG. [Figure 4A] 3A to 3C are diagrams illustrating a semiconductor layer forming step in the solar cell manufacturing method according to the present embodiment. [Figure 4B] 1A to 1C are diagrams illustrating a transparent electrode layer material film forming step and a metal electrode layer underlayer material film forming step in the solar cell manufacturing method according to the present embodiment. [Figure 4C] 3A to 3C are diagrams illustrating a resist formation step in the solar cell manufacturing method according to the present embodiment. [Figure 4D] 3A to 3C are diagrams illustrating a step of forming a plating layer of a metal electrode layer in the method for manufacturing a solar cell according to the present embodiment. [Figure 4E] 3A to 3C are diagrams illustrating an annealing step in the method for manufacturing a solar cell according to the present embodiment. [Figure 4F] 1A to 1C are diagrams illustrating a resist removal step in the solar cell manufacturing method according to the present embodiment. [Figure 4G] 3A to 3C are diagrams illustrating a transparent electrode layer forming step and a base layer forming step for a metal electrode layer in the solar cell manufacturing method according to the present embodiment. [Figure 5] 4C and 4D in the step of forming a resist and the step of forming a plating layer of a metal electrode layer. [Figure 6] 2 is a cross-sectional view of an example of an annealing step performed at the end of the manufacturing process of a solar cell according to a comparative example, taken along line II-II in FIG. 1. FIG. [Figure 7A] 4 is a partially enlarged cross-sectional view of the example solar cell according to the present embodiment shown in FIG. 3, and corresponds to a portion III shown in FIG. 2. FIG. [Figure 7B] 3 is a partially enlarged cross-sectional view of an example of a solar cell according to a modified example of the present embodiment, corresponding to a portion III shown in FIG. 2. FIG. [Figure 7C] 3 is a partially enlarged cross-sectional view of an example of a solar cell according to a modified example of the present embodiment, corresponding to a portion III shown in FIG. 2. FIG. [Figure 7D]3 is a partially enlarged cross-sectional view of an example of a solar cell according to a modified example of the present embodiment, corresponding to a portion III shown in FIG. 2. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] An example of an embodiment of the present invention will be described below with reference to the accompanying drawings. The same or equivalent parts in each drawing are designated by the same reference numerals. For convenience, hatching and reference numerals may be omitted. In such cases, reference should be made to other drawings.

[0013] (solar cells) Fig. 1 is a view of the solar cell according to this embodiment as seen from the back surface side, and Fig. 2 is a cross-sectional view of the solar cell shown in Fig. 1 taken along line II-II. The solar cell 1 shown in Figs. 1 and 2 is a back electrode type (also called a back contact type or back junction type) heterojunction solar cell.

[0014] Solar cell 1 includes a semiconductor substrate 11 with two main surfaces, and the main surface of semiconductor substrate 11 has a first region 7 and a second region 8. In the following, the main surface of semiconductor substrate 11 that receives light is referred to as the light-receiving surface, and the main surface of semiconductor substrate 11 opposite the light-receiving surface (one main surface) is referred to as the back surface.

[0015] The first region 7 has a so-called comb shape and includes a plurality of finger portions 7f corresponding to the teeth of the comb and busbar portions 7b corresponding to supports for the teeth of the comb. The busbar portions 7b extend in a first direction (X direction) along one side of the semiconductor substrate 11, and the finger portions 7f extend from the busbar portions 7b in a second direction (Y direction) that intersects with the first direction.

[0016] Similarly, the second region 8 has a so-called comb shape and includes a plurality of finger portions 8f corresponding to the teeth of the comb and busbar portions 8b corresponding to supports for the teeth of the comb. The busbar portions 8b extend in a first direction (X direction) along one side of the semiconductor substrate 11 that faces the other side, and the finger portions 8f extend in a second direction (Y direction) from the busbar portions 8b.

[0017] The finger portions 7f and 8f are strip-shaped and extend in the second direction (Y direction), and are alternately arranged in the first direction (X direction). The first region 7 and the second region 8 may be formed in a stripe pattern.

[0018] 2, solar cell 1 includes a passivation layer 13 and an optical adjustment layer 15 laminated in this order on the light-receiving surface side of semiconductor substrate 11. Solar cell 1 also includes a passivation layer 23, a first conductivity type semiconductor layer 25, and a first electrode layer 27 laminated in this order on a portion (first region 7) of the back surface side of semiconductor substrate 11. Solar cell 1 also includes a passivation layer 33, a second conductivity type semiconductor layer 35, and a second electrode layer 37 laminated in this order on another portion (second region 8) of the back surface side of semiconductor substrate 11.

[0019] The semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate obtained by doping a crystalline silicon material with an n-type dopant. The semiconductor substrate 11 may also be a p-type semiconductor substrate obtained by doping a crystalline silicon material with a p-type dopant. An example of an n-type dopant is phosphorus (P). An example of a p-type dopant is boron (B). The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light-receiving surface side and generates photocarriers (electrons and holes).

[0020] By using crystalline silicon as the material for the semiconductor substrate 11, dark current is relatively small, and a relatively high output (stable output regardless of illuminance) can be obtained even when the intensity of incident light is low.

[0021] The semiconductor substrate 11 may have a pyramidal fine uneven structure called a texture structure on the back side, which increases the recovery efficiency of light that passes through the semiconductor substrate 11 without being absorbed.

[0022] Furthermore, semiconductor substrate 11 may have a pyramidal fine uneven structure called a texture structure on the light-receiving surface side, which reduces the reflection of incident light on the light-receiving surface and improves the light trapping effect in semiconductor substrate 11.

[0023] Passivation layer 13 is formed on the light-receiving surface side of semiconductor substrate 11. Passivation layer 23 is formed in a first region 7 on the back surface side of semiconductor substrate 11. Passivation layer 33 is formed in a second region 8 on the back surface side of semiconductor substrate 11. Passivation layers 13, 23, and 33 are formed of a material containing, for example, an intrinsic (i-type) amorphous silicon material as a main component. Passivation layers 13, 23, and 33 suppress recombination of carriers generated in semiconductor substrate 11 and increase carrier collection efficiency.

[0024] Optical adjustment layer 15 is formed on passivation layer 13 on the light-receiving surface side of semiconductor substrate 11. Optical adjustment layer 15 functions as an anti-reflection layer that prevents reflection of incident light, and also functions as a protective layer that protects the light-receiving surface side of semiconductor substrate 11 and passivation layer 13. Optical adjustment layer 15 is formed of an insulating material, for example, silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).

[0025] The first conductivity type semiconductor layer 25 is formed on the passivation layer 23, i.e., in a first region 7 on the back surface side of the semiconductor substrate 11. On the other hand, the second conductivity type semiconductor layer 35 is formed on the passivation layer 33, i.e., in a second region 8 on the back surface side of the semiconductor substrate 11. That is, the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 have a strip-like shape and extend in the Y direction. The first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 are arranged alternately in the X direction. A portion of the second conductivity type semiconductor layer 35 may overlap a portion of an adjacent first conductivity type semiconductor layer 25 (not shown).

[0026] The first conductivity type semiconductor layer 25 is formed of, for example, an amorphous silicon material. The first conductivity type semiconductor layer 25 is a p-type semiconductor layer obtained by doping an amorphous silicon material with a p-type dopant (for example, the above-mentioned boron (B)).

[0027] The second conductivity type semiconductor layer 35 is formed of, for example, an amorphous silicon material. The second conductivity type semiconductor layer 35 is, for example, an n-type semiconductor layer obtained by doping an n-type dopant (for example, the above-mentioned phosphorus (P)) into an amorphous silicon material. Note that the first conductivity type semiconductor layer 25 may be an n-type semiconductor layer, and the second conductivity type semiconductor layer 35 may be a p-type semiconductor layer.

[0028] The first electrode layer 27 is formed on the first conductivity type semiconductor layer 25, i.e., in a first region 7 on the back surface side of the semiconductor substrate 11. On the other hand, the second electrode layer 37 is formed on the second conductivity type semiconductor layer 35, i.e., in a second region 8 on the back surface side of the semiconductor substrate 11. That is, the first electrode layer 27 and the second electrode layer 37 have a strip-like shape and extend in the Y direction. The first electrode layer 27 and the second electrode layer 37 are provided alternately in the X direction.

[0029] The first electrode layer 27 has a first transparent electrode layer 28 and a first metal electrode layer 29 laminated in this order on the first conductivity-type semiconductor layer 25. On the other hand, the second electrode layer 37 has a second transparent electrode layer 38 and a second metal electrode layer 39 laminated in this order on the second conductivity-type semiconductor layer 35. The first metal electrode layer 29 has a two-layer structure of an underlayer 29l and a plating layer 29u, and the second metal electrode layer 39 has a two-layer structure of an underlayer 39l and a plating layer 39u.

[0030] The first transparent electrode layer 28 and the second transparent electrode layer 38 are formed of a transparent conductive material, such as ITO (Indium Tin Oxide: a composite oxide of indium oxide and tin oxide), ZnO (Zinc Oxide), etc.

[0031] The underlayer 29l in the first metal electrode layer 29 and the underlayer 39l in the second metal electrode layer 39 contain a metal material such as silver, copper, or aluminum, which is formed using a PVD method such as sputtering. On the other hand, the plating layer 29u in the first metal electrode layer 29 and the plating layer 39u in the second metal electrode layer 39 contain a metal material such as silver, copper, or nickel, which is formed using a plating method.

[0032] The first electrode layer 27 and the second electrode layer 37 are strip-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). That is, the first transparent electrode layer 28 and the second transparent electrode layer 38 are strip-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). Furthermore, the first metal electrode layer 29 and the second metal electrode layer 39 are strip-shaped extending in the second direction (Y direction) and are alternately arranged in the first direction (X direction). The first transparent electrode layer 28 and the second transparent electrode layer 38 are separated from each other, and the first metal electrode layer 29 and the second metal electrode layer 39 are also separated from each other.

[0033] Fig. 3 is an enlarged cross-sectional view of an example of portion III in the solar cell shown in Fig. 2. As will be described later, when a pattern printing resist is used as a resist for forming plating layer 29u in first metal electrode layer 29 and plating layer 39u in second metal electrode layer 39, a structure such as that shown in Fig. 3 may be used.

[0034] As shown in FIG. 3, a resin film 41 may be unevenly distributed at least at the end of the first metal electrode layer 29 between the base layer 29l and the plating layer 29u on the boundary side between the first region 7 and the second region 8.

[0035] More specifically, the base layer 29l is relatively thin and has a concave-convex structure corresponding to the concave-convex structure (texture structure) of the semiconductor substrate 11. The resin film 41 is interposed between the plating layer 29u and the valleys of the concave-convex structure at least at the ends of the base layer 29l. The resin film 41 may be formed in a sea-like (i.e., continuous) or island-like (i.e., discontinuous) shape of the sea-island structure. It is preferable that the valleys of the concave-convex structure at least at the ends of the base layer 29l are flattened by the resin film 41.

[0036] Meanwhile, the peaks of the concave-convex structure at least at the ends of the base layer 29l are in contact with the plating layer 29u, and the valleys and peaks of the concave-convex structure other than the ends of the base layer 29l are in contact with the plating layer 29u.

[0037] Similarly, the resin film 41 may be unevenly distributed at least at the end of the second metal electrode layer 39 between the underlayer 39l and the plating layer 39u on the boundary side between the first region 7 and the second region 8.

[0038] More specifically, the base layer 39l is relatively thin and has a concave-convex structure corresponding to the concave-convex structure (texture structure) of the semiconductor substrate 11. The resin film 41 is interposed between the plating layer 39u and valleys of the concave-convex structure at least at the ends of the base layer 39l. The resin film 41 may be formed in a sea-like (i.e., continuous) or island-like (i.e., discontinuous) shape of the sea-island structure. It is preferable that the valleys of the concave-convex structure at least at the ends of the base layer 39l are flattened by the resin film 41.

[0039] Meanwhile, the peaks of the concave-convex structure at least at the ends of the base layer 39l are in contact with the plating layer 39u, and the valleys and peaks of the concave-convex structure other than the ends of the base layer 39l are in contact with the plating layer 39u.

[0040] (Solar Cell Manufacturing Method) Next, a method for manufacturing a solar cell according to this embodiment will be described with reference to FIGS. 4A to 4G. FIG. 4A is a diagram showing a semiconductor layer forming step in the method for manufacturing a solar cell according to this embodiment, and FIG. 4B is a diagram showing a transparent electrode layer material film forming step and a base layer material film forming step for a metal electrode layer in the method for manufacturing a solar cell according to this embodiment. FIG. 4C is a diagram showing a resist forming step in the method for manufacturing a solar cell according to this embodiment, and FIG. 4D is a diagram showing a plating layer forming step for a metal electrode layer in the method for manufacturing a solar cell according to this embodiment. FIG. 4E is a diagram showing an annealing step in the method for manufacturing a solar cell according to this embodiment, and FIG. 4F is a diagram showing a resist removing step in the method for manufacturing a solar cell according to this embodiment. FIG. 4G is a diagram showing a transparent electrode layer forming step and a base layer forming step for a metal electrode layer in the method for manufacturing a solar cell according to this embodiment. FIGS. 4A to 4G show the back side of semiconductor substrate 11, and the front side of semiconductor substrate 11 is omitted.

[0041] 4A, a passivation layer 23 and a first conductivity type semiconductor layer 25 are formed on a portion of the back surface side of semiconductor substrate 11, specifically in first region 7 (semiconductor layer formation step). For example, after a passivation layer material film and a first conductivity type semiconductor layer material film are formed on the entire back surface side of semiconductor substrate 11 using a CVD method or a PVD method, passivation layer 23 and first conductivity type semiconductor layer 25 may be patterned using an etching method that uses a resist or a metal mask generated using a photolithography technique or a printing technique.

[0042] The etching solution for the p-type semiconductor layer material film may be, for example, an acidic solution such as hydrofluoric acid containing ozone or a mixture of nitric acid and hydrofluoric acid, and the etching solution for the n-type semiconductor layer material film may be, for example, an alkaline solution such as an aqueous potassium hydroxide solution.

[0043] Alternatively, when a passivation layer and a first conductivity type semiconductor layer are stacked on the back side of the semiconductor substrate 11 using a CVD method or a PVD method, the passivation layer 23 and the first conductivity type semiconductor layer 25 may be deposited and patterned simultaneously using a mask.

[0044] Next, a passivation layer 33 and a second conductivity type semiconductor layer 35 are formed on another part of the back surface side of the semiconductor substrate 11, specifically in the second region 8 (semiconductor layer formation step). For example, as described above, a passivation layer material film and a second conductivity type semiconductor layer material film may be formed on the entire back surface side of the semiconductor substrate 11 using a CVD method or a PVD method, and then the passivation layer 33 and the second conductivity type semiconductor layer 35 may be patterned using an etching method that uses a resist generated using a photolithography technique or a printing technique, or a metal mask.

[0045] Alternatively, when a passivation layer and a second conductivity type semiconductor layer are stacked on the back side of the semiconductor substrate 11 using a CVD method or a PVD method, the passivation layer 33 and the second conductivity type semiconductor layer 35 may be deposited and patterned simultaneously using a mask.

[0046] In this semiconductor layer forming step, a passivation layer 13 (not shown) may be formed on the entire light-receiving surface side of the semiconductor substrate 11.

[0047] 4B, a continuous transparent electrode layer material film 28Z is formed across the first region 7 and the second region 8 on the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 (transparent electrode layer material film forming step). The transparent electrode layer material film 28Z can be formed by, for example, a CVD method or a PVD method.

[0048] Next, a series of underlayer material films 29lZ is formed on the transparent electrode layer material film 28Z, i.e., on the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35, across the first region 7 and the second region 8 (underlayer material film forming step). The underlayer material film 29lZ is formed by a PVD method such as sputtering, for example.

[0049] Next, as shown in FIG. 4C, a resist 40 is formed on the underlayer material film 291Z at the boundary between the first region 7 and the second region 8 (resist formation step). The method for forming the resist 40 is not particularly limited, but examples thereof include photolithography and printing. Among these, printing is preferred from the viewpoint of simplifying the manufacturing process. In particular, pattern printing methods such as press printing, such as screen printing or gravure printing, or ejection printing, such as inkjet printing, are preferred.

[0050] In the pattern printing method, a printing material containing a resin material and a solvent is printed and baked (cured) to form a patterned resist 40. The temperature during baking (curing) of the resist is, for example, 80°C or higher and 140°C or lower. At this time, as shown in FIG. 5, a resin film 41 formed by exuding the resin material in the printing material is formed in the valleys of the uneven structure (texture structure) of the underlayer material film 291Z.

[0051] The resin film 41 may be formed in the valleys of the uneven structure between the resists 40, i.e., in all of the first region 7 and the second region 8, as shown in Figure 5, or may be formed in the valleys of the uneven structure between the resists 40 at the end of the boundary between the first region 7 and the second region 8, as shown in Figure 3.

[0052] 4D, a plating method using the resist 40 as a mask is used to form a patterned plating layer 29u on the underlayer material film 29lZ in the first region 7, and a patterned plating layer 39u on the underlayer material film 29lZ in the second region 8 (plated metal electrode layer forming step). When the resist 40 is a pattern printing resist, the plating layer 29u is formed on the resin film 41 in the valleys of the concave-convex structure at least at the end of the underlayer material film 29lZ, and on the peaks of the concave-convex structure of the underlayer material film 29lZ, as shown in FIG.

[0053] Next, as shown in FIG. 4E, the semiconductor substrate 11 is heated in an atmospheric environment to heat the plating layers 29u, 39u and the underlayer material film 29lZ (annealing step). This promotes crystallization of the plating layers 29u, 39u and the underlayer material film 29lZ (i.e., the underlayers 29l, 39l). The heating temperature in the annealing step is preferably higher than the temperature used to bake (harden) the resist in the resist formation step described above. For example, the heating temperature is preferably 110°C or higher and 250°C or lower, more preferably 130°C or higher and 200°C or lower, and even more preferably 140°C or higher and 170°C or lower. If the heating temperature is lower than 110°C, the annealing effect is insufficient. On the other hand, if the heating temperature exceeds 250°C, the quality of the amorphous silicon film may be degraded, and the removability of the resist may be reduced in the resist removal step described below. At this time, the exposed surfaces of the plating layers 29u and 39u are oxidized, and an oxide film 29O is formed on the exposed surfaces of the plating layers 29u and 39u.

[0054] Next, as shown in Fig. 4F, the resist 40 is removed (resist removing step). As the resist removing solution, an alkaline aqueous solution such as an aqueous sodium hydroxide solution is used.

[0055] Next, as shown in FIG. 4G, the underlayer material film 29lZ and the transparent electrode layer material film 28Z are etched using an etching method that uses the plating layers 29u and 39u as masks to form a patterned first transparent electrode layer 28 and underlayer 29l in the first region 7, and a patterned second transparent electrode layer 38 and underlayer 39l in the second region 8 (transparent electrode layer forming step and underlayer forming step). At this time, the oxide film 29O formed on the exposed surfaces of the plating layers 29u and 39u is removed. This results in the formation of a first metal electrode layer 29 consisting of the underlayer 29l and the plating layer 29u, and a second metal electrode layer 39 consisting of the underlayer 39l and the plating layer 39u. Furthermore, a first electrode layer 27 consisting of the first transparent electrode layer 28 and the first metal electrode layer 29, and a second electrode layer 37 consisting of the second transparent electrode layer 38 and the second metal electrode layer 39 are formed.

[0056] An example of an etching solution for simultaneous etching of the underlayer material film 29lZ and the transparent electrode layer material film 28Z is a mixed solution of an oxidizing agent such as ammonium persulfate (ammonium persulfate) and an acidic solution such as hydrochloric acid (HCl) when, for example, the transparent electrode layer material film 28Z is ITO and the underlayer material film 29lZ is copper.

[0057] Thereafter, optical adjustment layer 15 (not shown) is formed on the entire light-receiving surface side of semiconductor substrate 11. Through the above steps, back electrode type solar cell 1 of this embodiment shown in FIGS.

[0058] As described above, according to the solar cell manufacturing method of the present embodiment, plating is used to form the plating layers 29u, 39u on the metal electrode layers 29, 39. Furthermore, plating is used using the resist 40 as a mask to directly form the plating layers 29u, 39u on the metal electrode layers 29, 39 (deposition and patterning are performed simultaneously). This makes it possible to simplify the solar cell manufacturing process and reduce costs.

[0059] Furthermore, according to the solar cell manufacturing method of this embodiment, a pattern printing method may be used in the plating method to print a printing material containing a resin material and a solvent and bake (harden) it to directly form a patterned resist 40 (film formation and patterning are performed simultaneously). This allows for simplification and cost reduction of resist formation compared to resist formation using, for example, photolithography techniques. Therefore, the solar cell manufacturing process can be simplified and cost reduced.

[0060] Furthermore, according to the method for manufacturing a solar cell of this embodiment, a relatively inexpensive metal, such as Cu, may be used as the material for the metal electrode layers 29 and 39 instead of the known, relatively expensive Ag paste, thereby reducing the cost of the solar cell.

[0061] Furthermore, according to the manufacturing method of the solar cell of this embodiment, the annealing process promotes crystallization of the metal electrode layers 29, 39 (plated layers 29u, 39u and base layers 29l, 39l), thereby making it possible to reduce the resistance of the electrode layers 27, 37 and improve the output of the solar cell 1, i.e., improve the performance of the solar cell 1.

[0062] If the purpose is to crystallize the metal electrode layers (plating layers and underlayers), the annealing process is generally performed at the end of the manufacturing process, i.e., after the underlayer etching process. However, if the annealing process is performed after the underlayer etching process, as shown in FIG. 6, the exposed surfaces of the metal electrode layers 29, 39 (plating layers 29u, 39u and underlayers 29l, 39l) are oxidized during the annealing process, resulting in the formation of an oxide film 29O on the exposed surfaces of the metal electrode layers 29, 39. This increases the contact resistance between the electrode layers 27, 37 and the wiring member, resulting in a decrease in the output of the solar cell 1, i.e., a decrease in the performance of the solar cell 1. This decrease in performance due to the increase in contact resistance between the electrode layers 27, 37 and the wiring member reduces the effect of improving the performance of the solar cell 1 by reducing the resistance of the electrode layers 27, 37 (Problem 1).

[0063] Furthermore, after the etching step of the base layer, the semiconductor layers 25 (23), 35 (33) are exposed in the boundary region between the first region 7 and the second region 8. Therefore, if the annealing step is performed after the etching step of the base layer, Cu constituting the metal electrode layers 29, 39 will diffuse into the semiconductor layers 25 (23), 35 (33) and the semiconductor substrate 11 during the annealing step, as shown in Figure 6. If Cu diffuses into the semiconductor layers 25 (23), 35 (33) and the semiconductor substrate 11, the photoelectric conversion characteristics of the solar cell 1 will deteriorate, i.e., the reliability of the solar cell 1 will deteriorate (Problem 2).

[0064] Regarding the above-mentioned problem 1, in the solar cell manufacturing method of this embodiment, the annealing step is performed before the underlayer etching step. Therefore, even if the exposed surfaces of the metal electrode layers 29, 39 (plating layers 29u, 39u and underlayers 29l, 39l) are oxidized in the annealing step, forming oxide films 29O on the exposed surfaces of the metal electrode layers 29, 39 (FIG. 4F), the oxide films 29O on the exposed surfaces of the metal electrode layers 29, 39 are removed in the subsequent underlayer etching step (FIG. 4G). Therefore, the oxide films 29O on the exposed surfaces of the metal electrode layers 29, 39 do not increase the contact resistance between the electrode layers 27, 37 and the wiring member, and the output of the solar cell 1, i.e., the performance of the solar cell 1, is not reduced. Therefore, the effect of improving the performance of the solar cell 1 by reducing the resistance of the electrode layers 27, 37 is not reduced.

[0065] Regarding the above-mentioned problem 2, in the manufacturing method of the solar cell of this embodiment, the annealing step is performed before the etching step of the base layer, that is, before the etching step of the base layer where the semiconductor layers 25 (23), 35 (33) are not exposed in the boundary region between the first region 7 and the second region 8 (FIG. 4F), so even if Cu constituting the metal electrode layers 29, 39 diffuses during the annealing step, it does not diffuse into the semiconductor layers 25 (23), 35 (33) and the semiconductor substrate 11. Therefore, the photoelectric conversion characteristics of the solar cell 1, i.e., the reliability of the solar cell 1, do not deteriorate due to the diffusion of Cu.

[0066] Furthermore, according to the solar cell manufacturing method of this embodiment, the crystallization of the plating layers 29u, 39u is promoted in the annealing process, so that the plating layers 29u, 39u are less likely to be etched in the subsequent etching process of the base layer, and thus function favorably as a mask.

[0067] Furthermore, in the solar cell manufacturing method of this embodiment, the annealing step is performed before the resist stripping step, and therefore, the resist 40 present between the plating layers 29u, 39u can prevent the semiconductor substrate from warping (e.g., an upwardly convex arc shape in FIG. 4E) due to accelerated crystallization of the plating layers 29u, 39u during the annealing step. This makes it easier to set the semiconductor substrate in a cassette for chemical treatment in the subsequent base layer etching step.

[0068] Furthermore, in the annealing step, the base layers 29l and 39l are covered with the resist 40 and are not oxidized (FIG. 4E), so that uniform etching can be performed in the subsequent etching step of the base layers.

[0069] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various modifications and variations are possible. For example, the above-described embodiments illustrate a solar cell in which resin film 41 is unevenly distributed in the valleys of the uneven structure between base layer 29l and plating layer 29u in first metal electrode layer 29 and between base layer 39l and plating layer 39u in second metal electrode layer 39, as shown in FIG. 3. However, the present invention is not limited to this, and various solar cells can be conceived depending on the degree of etching in the solar cell manufacturing process. For comparison with the comparative solar cell described below, FIG. 7A shows a partially enlarged cross-sectional view of an example solar cell according to this embodiment shown in FIG. 3, which is an enlarged cross-sectional view of portion III shown in FIG. 2. FIG. 7A collectively shows first conductivity-type semiconductor layer 25 and passivation layer 23 in FIG. 3. FIGS. 7B to 7D are partially enlarged cross-sectional views of an example solar cell according to a modification of this embodiment, corresponding to portion III shown in FIG. 2.

[0070] 7B , in solar cell 1, resin film 41 that is unevenly distributed in the valleys of the uneven structure between base layer 29l and plating layer 29u in first metal electrode layer 29 and between base layer 39l and plating layer 39u in second metal electrode layer 39 may be etched and removed. For example, resin film 41 is etched and removed in the resist removal step described above.

[0071] As a result, in solar cell 1, a space may exist below plating layer 29u in the valleys of the uneven structure at least at the end of first metal electrode layer 29 on the boundary side between first region 7 and second region 8. More specifically, at least at the end of first metal electrode layer 29, base layer 29l may exist below plating layer 29u in the valleys of the uneven structure, and a space may exist between base layer 29l and plating layer 29u in the valleys of the uneven structure without resin film 41 interposed therebetween.

[0072] Similarly, in solar cell 1, a space may exist below plating layer 39u in the valleys of the uneven structure at least at the end of second metal electrode layer 39 on the boundary side between first region 7 and second region 8. More specifically, at least at the end of second metal electrode layer 39, base layer 39l may exist below plating layer 39u in the valleys of the uneven structure, and a space may exist between base layer 39l and plating layer 39u in the valleys of the uneven structure without resin film 41 interposed therebetween.

[0073] 7C , in solar cell 1, base layers 29l and 39l may be further etched and removed, and transparent electrode layers 28 and 38 may be further etched and removed. For example, in the transparent electrode layer forming step and base layer forming step described above, base layers 29l and 39l and transparent electrode layers 28 and 38 are etched and removed.

[0074] As a result, in solar cell 1, resin film 41 and underlayer 29l may not be present and spaces may exist below plating layer 29u in the valleys of the uneven structure at least at the ends of first metal electrode layer 29. Alternatively, in solar cell 1, resin film 41, underlayer 29l and transparent electrode layer 28 may not be present and spaces may exist below plating layer 29u in the valleys of the uneven structure at least at the ends of first metal electrode layer 29.

[0075] Similarly, in the solar cell 1, the resin film 41 and the base layer 39l may not be present and a space may exist below the plating layer 39u in the valleys of the uneven structure at least at the end of the second metal electrode layer 39. Alternatively, in the solar cell 1, the resin film 41, the base layer 39l, and the transparent electrode layer 38 may not be present and a space may exist below the plating layer 39u in the valleys of the uneven structure at least at the end of the second metal electrode layer 39.

[0076] 7D , in solar cell 1, resin film 41 unevenly distributed in the valleys of the concave-convex structure between base layer 29l and plating layer 29u in first metal electrode layer 29 and between base layer 39l and plating layer 39u in second metal electrode layer 39 may remain unetched, and base layers 29l and 39l may be etched and removed, and further transparent electrode layers 28 and 38 may be etched and removed. As described above, for example, in the transparent electrode layer forming step and base layer forming step, base layers 29l and 39l and transparent electrode layers 28 and 38 are etched and removed.

[0077] As a result, in solar cell 1, at least at the end of first metal electrode layer 29, resin film 41 may be present below plating layer 29u in the valleys of the uneven structure, base layer 29l may not be present, and spaces may exist below resin film 41 in the valleys of the uneven structure. Alternatively, in solar cell 1, at least at the end of first metal electrode layer 29, resin film 41 may be present below plating layer 29u in the valleys of the uneven structure, base layer 29l and transparent electrode layer 28 may not be present, and spaces may exist below resin film 41 in the valleys of the uneven structure.

[0078] Similarly, in solar cell 1, at least at the end of second metal electrode layer 39, resin film 41 may be present below plating layer 39u in the valleys of the uneven structure, base layer 39l may not be present, and spaces may exist below resin film 41 in the valleys of the uneven structure. Alternatively, in solar cell 1, at least at the end of second metal electrode layer 39, resin film 41 may be present below plating layer 39u in the valleys of the uneven structure, base layer 39l and transparent electrode layer 38 may not be present, and spaces may exist below resin film 41 in the valleys of the uneven structure.

[0079] In the above-described embodiment, a method for manufacturing a solar cell including an electrode layer including a transparent electrode layer and a metal electrode layer is illustrated. However, the present invention is not limited to this, and can also be applied to a method for manufacturing a solar cell including an electrode layer including only a metal electrode layer.

[0080] Although the above-described embodiment illustrates a method for manufacturing a solar cell using a crystalline silicon material, the present invention is not limited to this and may also be applied to a method for manufacturing a solar cell using various materials such as gallium arsenide (GaAs).

[0081] In the above-described embodiment, a method for manufacturing a heterojunction solar cell is exemplified as shown in Fig. 2. However, the present invention is not limited to this, and can also be applied to methods for manufacturing various solar cells, such as a homojunction solar cell. [Explanation of symbols]

[0082] 1. Solar cells 7 First area 7f Finger section 7b Busbar section 8 Second area 8f Finger section 8b Busbar section 11 Semiconductor substrate 13,23,33 Passivation layer 15 Optical adjustment layer 25 First conductivity type semiconductor layer 27 1st electrode layer 28 First transparent electrode layer 28Z Transparent electrode layer material film 29 First metal electrode layer 29l base layer 29lZ Base layer material film 29u plating layer 29O oxide film 35 Second conductivity type semiconductor layer 37 Second electrode layer 38 Second transparent electrode layer 39 Second metal electrode layer 39l Base layer 39u plating layer 40 Resist 41 Resin film

Claims

1. A method for manufacturing a back electrode type solar cell including a semiconductor substrate, a first conductivity type semiconductor layer and a first metal electrode layer stacked in this order in a first region that is a part of one main surface side of the semiconductor substrate, and a second conductivity type semiconductor layer and a second metal electrode layer stacked in this order in a second region that is another part of the one main surface side of the semiconductor substrate, each of the first metal electrode layer and the second metal electrode layer has an underlayer and a plating layer; The method for manufacturing a solar cell includes: an underlayer material film forming step of forming a series of underlayer material films on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer on the one main surface side of the semiconductor substrate, spanning the first region and the second region; a resist forming step of forming a resist on the material film of the underlayer at the boundary between the first region and the second region; a plating layer forming step of forming a patterned plating layer on the material film of the base layer in each of the first region and the second region by using a plating method using the resist as a mask; an annealing step of heating the material films of the plating layer and the underlayer; a resist removal step of removing the resist; an underlayer forming step of etching a material film of the underlayer using an etching method that uses the plating layer as a mask, thereby forming a patterned underlayer in each of the first region and the second region; in this order, In the annealing step, an oxide film is formed on the exposed surface of the plating layer, In the base layer forming step, the oxide film formed on the exposed surface of the plating layer is removed. How solar cells are manufactured.

2. In the resist forming step, a printing material containing a resin material and a solvent is printed and cured using a pattern printing method to form the patterned resist. The method for producing the solar cell according to claim 1 .

3. The method for manufacturing a solar cell according to claim 2 , wherein the heating temperature in the annealing step is higher than the temperature at which the resist is cured in the resist forming step.

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