Semiconductor Devices

Abstract

To provide a semiconductor device with a large ON-state current.SOLUTION: A semiconductor device includes a transistor. The transistor includes a first insulator, a first oxide on the first insulator, a second oxide on the first oxide, a third oxide, a first conductor and a second conductor on the second oxide, a second insulator, a third conductor, a fourth insulator on the first conductor and the second conductor, and a third insulator on the fourth insulator. The third insulator and the fourth insulator include an opening that reaches the second oxide. The third oxide is disposed to cover an inner wall of the opening. The second insulator is disposed to cover the inner wall of the opening through the third oxide. The third conductor is disposed to embed the opening through the third oxide and the second insulator. In a channel length direction of the transistor, an angle between a bottom surface of the first insulator and a side surface of the first conductor facing the second conductor is less than 90 degrees.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] TECHNICAL FIELD One embodiment of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are also attracting attention as other materials. Oxide semiconductors include not only oxides of single-component metals such as indium oxide and zinc oxide, but also oxides of multi-component metals. Among multi-component metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been particularly active.

[0005] Research on IGZO has revealed that oxide semiconductors have a c-axis aligned crystalline (CAAC) structure and a nanocrystalline (nc) structure, which are neither single crystal nor amorphous (see Non-Patent Documents 1 to 3). Non-Patent Documents 1 and 2 also disclose techniques for fabricating transistors using oxide semiconductors with a CAAC structure. Furthermore, Non-Patent Documents 4 and 5 show that even oxide semiconductors with lower crystallinity than the CAAC structure and the nc structure have minute crystals.

[0006] Furthermore, transistors using IGZO as an active layer have an extremely low off-state current (see Non-Patent Document 6), and LSIs and displays that utilize this property have been reported (see Non-Patent Documents 7 and 8). [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Non-patent document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p.151-154 [Non-patent document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022 [Non-patent document 5] S. Yamazaki, “ECS Transactions”,2014, volume 64, issue 10, p.155-164 [Non-patent document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-patent document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with high frequency characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

[0009] An object of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long period of time.An object of one embodiment of the present invention is to provide a semiconductor device with a high data writing speed.An object of one embodiment of the present invention is to provide a semiconductor device with high design freedom.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including a transistor, the transistor including a first insulator, a first oxide on the first insulator, a second oxide on the first oxide, a third oxide on the second oxide, a first conductor and a second conductor on the second oxide, a second insulator on the third oxide, a third conductor on the second insulator, a fourth insulator on the first conductor and the second conductor, and a third insulator on the fourth insulator. The fourth insulator has an opening that reaches the second oxide, the third oxide is arranged to cover the inner wall of the opening, the second insulator is arranged to cover the inner wall of the opening via the third oxide, the third conductor is arranged to fill the opening via the third oxide and the second insulator, and a first angle formed between a plane parallel to the bottom surface of the first insulator and a side surface of the first conductor facing the second conductor in the channel length direction of the transistor is smaller than 90 degrees.

[0012] In the above semiconductor device, it is preferable that the fourth insulator has a region in contact with a side surface of the first conductor, a side surface of the second oxide, and a side surface of the first oxide, and that a second angle formed in the channel length direction of the transistor between a surface parallel to the bottom surface of the first insulator and a surface parallel to the side end of the fourth insulator in that region facing the second conductor is smaller than 90 degrees.

[0013] In the semiconductor device, the first angle and the second angle are preferably the same angle.

[0014] Another embodiment of the present invention is a semiconductor device including a transistor. The transistor includes a first insulator, a first oxide on the first insulator, a second oxide on the first oxide, a third oxide on the second oxide, a first conductor and a second conductor on the second oxide, a second insulator on the third oxide, a third conductor on the second insulator, a fourth insulator on the first conductor and the second conductor, and a third insulator on the fourth insulator. The third insulator and the fourth insulator have openings that reach the second oxide, and the third oxide is formed so as to cover inner walls of the openings. the second insulator is arranged to cover the inner wall of the opening via the third oxide; the third conductor is arranged to fill the opening via the third oxide and the second insulator; in the channel width direction of the transistor, the height of the bottom surface of the third conductor in the region that does not overlap with the second oxide is lower than the height of the bottom surface of the second oxide, based on the bottom surface of the first insulator; and in the channel length direction of the transistor, the length of the bottom surface of the third conductor in the region that does not overlap with the second oxide is shorter than the length of the bottom surface of the third conductor in the region that overlaps with the second oxide.

[0015] Another embodiment of the present invention is a semiconductor device including a transistor. The transistor includes a first insulator, a first oxide on the first insulator, a second oxide on the first oxide, a third oxide on the second oxide, a first conductor and a second conductor on the second oxide, a second insulator on the third oxide, a third conductor on the second insulator, a fourth insulator on the first conductor and the second conductor, and a third insulator on the fourth insulator. The third insulator and the fourth insulator have openings that reach the second oxide. The third oxide is disposed to cover an inner wall of the opening. The second insulator is disposed to cover the inner wall of the opening with the third oxide interposed therebetween. The third conductor is disposed to fill the opening with the third oxide and the second insulator interposed therebetween. When the transistor is viewed from above, a side edge of the fourth insulator has a curved shape.

[0016] In the above semiconductor device, the fourth insulator preferably contains an oxide of aluminum.

[0017] In the above semiconductor device, the second oxide preferably contains In, an element M (M is Al, Ga, Y, or Sn), and Zn. [Effects of the Invention]

[0018] According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high reliability can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0019] Furthermore, a semiconductor device capable of retaining data for a long period of time can be provided. A semiconductor device with a high data writing speed can be provided. A semiconductor device with a high degree of design freedom can be provided. A semiconductor device with reduced power consumption can be provided. Furthermore, a novel semiconductor device can be provided.

[0020] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0021] [Figure 1] 1A to 1E are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 2] 1A and 1B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 3] FIG. 1 is a schematic top view of a transistor according to one embodiment of the present invention. [Figure 4] 1A, 1B, 1C, and 1D are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 5] 10A, 10B, and 10C are graphs showing electrical characteristics of a transistor according to one embodiment of the present invention and an operating frequency of a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A, 1B, and 1C are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A, 1B, and 1C are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A, 1B, and 1C are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9]1A, 1B, and 1C are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A, 1B, and 1C are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A, 1B, and 1C are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A, 1B, and 1C are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A, 1B, and 1C are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] FIG. 1 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. [Figure 15] FIG. 1 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. [Figure 16] 1A and 1B are a block diagram and a perspective view illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 17] 1A to 1H are circuit diagrams illustrating configuration examples of memory devices according to one embodiment of the present invention. [Figure 18] 1A and 1B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 19] 1A to 1E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 20] 1A to 1F are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 21] (A) and (B) are a cross-sectional STEM image and an EDX map according to an embodiment of the present invention. [Figure 22] (A) and (B) are a planar STEM image and an EDX map according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0023] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers, resist masks, etc. may be unintentionally thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same symbols are used for identical parts or parts having similar functions across different drawings, and repeated explanations may be omitted. When referring to similar functions, the same hatch pattern may be used and no particular symbol may be assigned.

[0024] In order to make the invention easier to understand, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0025] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc. in the description. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification.

[0026] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0027] For example, when it is explicitly stated in this specification that X and Y are connected, it is assumed that the specification discloses cases in which X and Y are electrically connected, cases in which X and Y are functionally connected, and cases in which X and Y are directly connected. Therefore, it is not limited to predetermined connection relationships, for example, connection relationships shown in figures or text, and connection relationships other than those shown in figures or text are also assumed to be disclosed in figures or text.

[0028] Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0029] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. In this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0030] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0031] Note that the channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0032] The channel width refers to, for example, the vertical length of a region where a semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or a channel formation region, based on the channel length direction. Note that the channel width does not necessarily have the same value in all regions of a single transistor. That is, the channel width of a single transistor may not be determined to a single value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0033] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0034] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0035] In this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, when simply referred to as a channel width, it may refer to an effective channel width. Note that values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0036] Note that impurities in semiconductors refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor or reduce its crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor's characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of an oxide semiconductor, water can also function as an impurity. In addition, in the case of an oxide semiconductor, for example, the inclusion of impurities can form oxygen vacancies. In addition, when the semiconductor is silicon, impurities that change the semiconductor's characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements excluding oxygen and hydrogen.

[0037] In this specification and the like, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0038] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0039] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0040] In this specification, a barrier film refers to a film that has the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, and when the barrier film has conductivity, it may be called a conductive barrier film.

[0041] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including an oxide or an oxide semiconductor.

[0042] Furthermore, in this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1 x 10 at 85°C -18 A or less, or 1 x 10 at 125°C-16 This means that it is A or below.

[0043] (Embodiment 1) An example of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described below.

[0044] <Configuration example of semiconductor device> 1A to 1E are a top view and a cross-sectional view of a transistor 200 and the periphery of the transistor 200 according to one embodiment of the present invention.

[0045] FIG. 1A is a top view of a semiconductor device including a transistor 200. FIGS. 1B to 1E are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed-dotted line L1-L2 in FIG. 1A, which is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed-dotted line L3-L4 in FIG. 1A, which is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1D is a cross-sectional view of a portion indicated by a dashed-dotted line W1-W2 in FIG. 1A, which is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1E is a cross-sectional view of a portion indicated by a dashed-dotted line W3-W4 in FIG. 1A, which is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted from the top view in FIG. 1A for clarity. In addition, in FIG. 1C, the conductor 240 and the insulator 241 are omitted.

[0046] A semiconductor device of one embodiment of the present invention includes a transistor 200 and an insulator 214, an insulator 280, an insulator 274, and an insulator 281 which function as interlayer films. The semiconductor device also includes a conductor 240 (conductor 240a and conductor 240b) which is electrically connected to the transistor 200 and functions as a plug. Note that an insulator 241 (insulator 241a and insulator 241b) is provided in contact with a side surface of the conductor 240 which functions as a plug.

[0047] Furthermore, insulator 241 is provided in contact with the side walls of the openings of insulators 254, 280, 274, and 281, and a first conductor of conductor 240 is provided in contact with the side surface of insulator 241, with a second conductor of conductor 240 provided further inward. Here, the height of the top surface of conductor 240 and the height of the top surface of insulator 281 can be approximately the same. Note that, in transistor 200, a configuration in which the first conductor of conductor 240 and the second conductor of conductor 240 are stacked is shown, but the present invention is not limited to this. For example, conductor 240 may be provided as a single layer or a stacked structure of three or more layers. When a structure has a stacked structure, ordinal numbers may be assigned to indicate the order of formation to distinguish them.

[0048] [Transistor 200] As shown in FIG. 1, the transistor 200 includes an insulator 216 disposed on a substrate (not shown), a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and on the conductor 205, an insulator 224 disposed on the insulator 222, an oxide 230 (oxide 230a, oxide 230b, and oxide 230c) disposed on the insulator 224, and an oxide 230 (oxide 230a, oxide 230b, and oxide 230c) disposed on the oxide 230. The oxide 230b includes an insulator 250 arranged on the oxide 230a, a conductor 260 (conductor 260a and conductor 260b) arranged on the insulator 250, conductors 242a and 242b in contact with a portion of the upper surface of the oxide 230b, and an insulator 254 arranged in contact with a portion of the upper surface of the insulator 224, the side of the oxide 230a, the side of the oxide 230b, the side of the conductor 242a, the upper surface of the conductor 242a, the side of the conductor 242b, and the upper surface of the conductor 242b.

[0049] The conductor 260 functions as the gate electrode of the transistor, and the conductors 242a and 242b function as the source and drain electrodes, respectively. In the transistor 200, the conductor 260, which functions as the gate electrode, is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, it is possible to reliably position the conductor 260 in the region between the conductors 242a and 242b without alignment.

[0050] Note that the conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260 is preferably disposed so that the conductor 260a surrounds the bottom and side surfaces of the conductor 260b. As shown in FIG. 1B, the top surface of the conductor 260 is substantially flush with the top surfaces of the insulator 250 and the oxide 230c. Note that although the conductor 260 in the transistor 200 has a two-layer stacked structure, the present invention is not limited thereto. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers.

[0051] It is preferable that the insulators 222, 254, and 274 have the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). It is also preferable that the insulators 222, 254, and 274 have the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, it is preferable that the insulators 222, 254, and 274 each have lower permeability to one or both of hydrogen and oxygen than the insulator 224. It is preferable that the insulators 222, 254, and 274 each have lower permeability to one or both of hydrogen and oxygen than the insulator 250. It is preferable that the insulators 222, 254, and 274 each have lower permeability to one or both of hydrogen and oxygen than the insulator 280.

[0052] 1(B), it is preferable that the insulator 254 be in contact with the top surfaces of the conductors 242a and 242b, the side surfaces of the conductors 242a and 242b other than the side surfaces of the conductors 242a and 242b facing each other, the side surfaces of the oxides 230a and 230b, and a portion of the top surface of the insulator 224. This separates the insulator 280 from the insulators 224, the oxides 230a, and the oxides 230b by the insulator 254. This prevents impurities such as hydrogen contained in the insulator 280 from being mixed into the insulators 224, the oxides 230a, and the oxides 230b.

[0053] Preferably, oxide 230 comprises oxide 230a disposed on insulator 224, oxide 230b disposed on oxide 230a, and oxide 230c disposed on oxide 230b and at least partially in contact with the top surface of oxide 230b.

[0054] Although the transistor 200 has a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c stacked in the channel formation region and its vicinity, the present invention is not limited to this structure. For example, the transistor 200 may have a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers.

[0055] In the transistor 200, it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including the channel formation region.

[0056] The transistor 200 using an oxide semiconductor for a channel formation region has an extremely small leakage current (off-state current) in an off-state, and therefore can provide a semiconductor device with low power consumption. Furthermore, an oxide semiconductor can be deposited by a sputtering method or the like, and therefore can be used for the transistor 200 that constitutes a highly integrated semiconductor device.

[0057] For example, a metal oxide such as In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 230. In particular, element M may be aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn). Alternatively, oxide 230 may be In-Ga oxide or In-Zn oxide.

[0058] Furthermore, if impurities and oxygen vacancies exist in the channel formation region of a transistor using an oxide semiconductor, the electrical characteristics of the transistor may fluctuate, resulting in poor reliability. Furthermore, if oxygen vacancies exist in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics. Therefore, it is preferable to reduce the oxygen vacancies in the channel formation region as much as possible. For example, oxygen may be supplied to the oxide 230 via the insulator 250 or the like to fill the oxygen vacancies. This makes it possible to provide a transistor with reduced fluctuations in electrical characteristics, stable electrical characteristics, and improved reliability.

[0059] Furthermore, when elements contained in the conductor 242 (conductor 242a and conductor 242b) that is provided on and in contact with the oxide 230 and functions as a source electrode or a drain electrode have the function of absorbing oxygen from the oxide 230, a low-resistance region may be partially formed between the oxide 230 and the conductor 242 or near the surface of the oxide 230. In this case, impurities (hydrogen, nitrogen, metal elements, etc.) that have entered the oxygen vacancies may function as donors in the low-resistance region, increasing the carrier density. Note that, hereinafter, defects in which hydrogen has entered the oxygen vacancies are referred to as V. O It may be called H.

[0060] 2A shows an enlarged view of a portion of the transistor 200 shown in FIG. 1B. As shown in FIG. 2A, a conductor 242 is provided on and in contact with the oxide 230b, and a region 243 (region 243a and region 243b) may be formed as a low-resistance region at the interface of the oxide 230b with the conductor 242 and in the vicinity thereof. The oxide 230b includes a region 234 that functions as a channel formation region of the transistor 200 and a region 231 (region 231a and region 231b) that includes at least a part of the region 243 and functions as a source region or drain region. Note that in the following drawings, even when the region 243 is not shown in an enlarged view, a similar region 243 may be formed.

[0061] Although the region 243a and the region 243b are provided so as to diffuse in the depth direction near the conductor 242 of the oxide 230b in this example, the present invention is not limited to this. The region 243a and the region 243b may be formed appropriately according to the desired electrical characteristics of the transistor. Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 230. The concentration of the element detected in each region is not limited to a stepwise change from region to region, but may also change continuously (also called a gradation) within each region.

[0062] The insulator 274 is in contact with the top surfaces of the conductor 260, the oxide 230c, and the insulator 250. The transistor 200 of one embodiment of the present invention has a structure in which the insulator 274 is in contact with the insulator 250, as shown in FIG. 2A. This structure can prevent impurities (such as hydrogen) contained in the insulator 281 and the like from entering the insulator 250. Therefore, adverse effects on the electrical characteristics and reliability of the transistor can be suppressed.

[0063] 2(A), the height of the bottom surface of the conductor 260 in the region overlapping with the region 234 may be lower than the height of the top surfaces of the conductors 242a and 242b, relative to the bottom surface of the insulator 224. For example, the difference between the height of the bottom surface of the conductor 260 in the region overlapping with the region 234 and the height of the top surfaces of the conductors 242a and 242b is set to be 0 nm or more and 30 nm or less, or 0 nm or more and 15 nm or less.

[0064] 1D, in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 is preferably lower than the height of the bottom surface of the oxide 230b, relative to the bottom surface of the insulator 224. When the conductor 260, which functions as a gate electrode, covers the side and top surfaces of the oxide 230b in the channel formation region via the oxide 230c and the insulator 250, the electric field of the conductor 260 can be easily applied to the entire region 234 of the oxide 230b. This increases the on-state current of the transistor 200 and improves its frequency characteristics. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0065] Here, the angle formed between a plane parallel to the bottom surface of the insulator 224 and the side surface of the conductor 242a facing the conductor 242b is defined as angle 244a. If the bottom surfaces of the insulator 224 and the conductor 242a are parallel, as shown in FIG. 2A, angle 244a may be regarded as the angle formed between the bottom surface of the conductor 242a and the side surface of the conductor 242a facing the conductor 242b. If the bottom surfaces of the insulator 224 and the conductor 242b are parallel, as shown in FIG. 2A, angle 244b may be regarded as the angle formed between the bottom surface of the conductor 242b and the side surface of the conductor 242b facing the conductor 242a. In this case, the angles 244a and 244b are preferably smaller than 90 degrees. This structure narrows the width of the region 231 that does not overlap with the conductor 260, a so-called offset region, in the channel length direction of the transistor 200, compared to when the angle 244 (angle 244a and angle 244b) is 90 degrees. This increases the on-state current of the transistor 200 and improves its frequency characteristics. Furthermore, coverage of the oxide 230c, the insulator 250, and the conductor 260, which will be formed in a later process, on the opposing side surfaces of the conductor 242a and the conductor 242b can be improved. Note that the angle 244a or the angle 244b may be appropriately designed depending on the desired transistor characteristics. Changes in the on-state current of the transistor 200 and changes in the operating frequency of a semiconductor device including the transistor 200 when the angle 244 is changed will be described later.

[0066] FIG. 2B shows an enlarged view of a portion of the transistor 200 shown in FIG. 1C. Note that the conductor 240 and the insulator 241 are not shown in FIG. 2B. As shown in FIG. 2B, a region of the insulator 254 that is in contact with the side surfaces of the conductor 242a, the oxide 230b, and the oxide 230a is referred to as a region 256a. A region of the insulator 254 that is in contact with the side surfaces of the conductor 242b, the oxide 230b, and the oxide 230a is referred to as a region 256b. In the channel length direction of the transistor 200, an angle 258a is formed between a plane parallel to the bottom surface of the insulator 224 and a plane parallel to the end of the insulator 254 in the region 256a that faces the conductor 242b. 2B, if the bottom surface of the insulator 224 and the bottom surface of the insulator 254 in the region 256a are parallel, the angle 258a may be regarded as the angle formed between the bottom surface of the insulator 254 in the region 256a and a plane parallel to the side end of the insulator 254 in the region 256a that faces the conductor 242b. The angle formed between the plane parallel to the bottom surface of the insulator 224 and a plane parallel to the side end of the insulator 254 in the region 256b that faces the conductor 242a is defined as angle 258b. In addition, if the bottom surface of insulator 224 and the bottom surface of insulator 254 in region 256b are parallel, as shown in Figure 2(B), angle 258b may be considered to be the angle between the bottom surface of insulator 254 in region 256b and a plane parallel to the side end of insulator 254 in region 256b facing conductor 242a.

[0067] In this case, the angles 258a and 258b are preferably smaller than 90 degrees. A low-resistance region may be formed in the oxide 230 when the oxide 230 is in contact with the insulator 254. Therefore, this structure can reduce the resistance of the region where the regions 256a and 256b of the insulator 254 and the region 234 of the oxide 230b are in contact with each other. This allows the channel length of the transistor 200 to be controlled. An example of an insulator that forms a low-resistance region in the oxide 230 is aluminum oxide. The angles 258a and 258b may be appropriately designed depending on the desired transistor characteristics. The angles 244a and 244b may be the same as or different from the angles 258a and 258b.

[0068] The shape of the side end portions of the insulator 254, where the region 256a and the region 256b face each other, may be evaluated using, for example, an EDX map obtained using energy dispersive X-ray spectroscopy (EDX). For example, when an insulator containing aluminum oxide is used as the insulator 254, the shape can be evaluated by obtaining a cross-sectional EDX map of an Al-K line.

[0069] Furthermore, an opening formed in the insulator 280 or the like that reaches the oxide 230b (an opening that exposes the oxide 230b) preferably has a tapered shape. Here, as shown in FIG. 1C , in the channel length direction of the transistor 200, an angle 248 is defined as an angle formed between a sidewall of the opening formed in the insulator 280 or the like and a surface extending outward from the bottom of the opening, the bottom of a region of the opening that does not overlap with the oxide 230a and the oxide 230b. In this case, for example, the angle 248 is preferably approximately equal to the angle 244 or the angle 258. Such a structure can facilitate processing to make the angle 244 or the angle 258 smaller than 90 degrees. Furthermore, coverage of the oxide 230c, the insulator 250, and the conductor 260 arranged on the inner wall of the opening can be improved.

[0070] Note that by providing the conductor 260 via the oxide 230c and the insulator 250 so as to fill the tapered opening, the length LG2 shown in FIG. 2B can be made shorter than the length LG1 shown in FIG. 2A. Here, the length LG1 is the length of the bottom surface of the conductor 260 in a region that overlaps with the region 234 in the channel length direction of the transistor 200. The length LG2 is the length of the bottom surface of the conductor 260 in a region that does not overlap with the oxide 230a and the oxide 230b in the channel length direction of the transistor 200.

[0071] 3 shows an enlarged view of the region 239 of the transistor 200 shown in FIG. 1A. The region 239 is a region including the side edge of the insulator 254 located near an opening formed in the insulator 280 or the like. FIG. 3 is a schematic top view showing the insulator 254, omitting other elements. As shown in FIG. 3, in a region where the insulator 254 does not overlap with the oxide 230a or the oxide 230b, the shortest distance between the opposing side edges of the insulator 254 is defined as distance LE2. Furthermore, the shortest distance between the side edge of the insulator 254 in a region that contacts the top surface of the conductor 242a and the side edge of the insulator 254 in a region that contacts the top surface of the conductor 242b is defined as distance LE1.

[0072] As shown in FIG. 1E, a curved surface may exist between the side surface of the conductor 242b and the top surface of the conductor 242b. Also, a curved surface may exist between the side surface of the conductor 242a and the top surface of the conductor 242a. When a curved surface exists between the side surface and the top surface of the conductor 242a and / or between the side surface and the top surface of the conductor 242b and an opening formed in the insulator 280 or the like has a tapered shape, as shown in FIG. 3, the side end of the insulator 254 has a shape in which the distance LE2 is shorter than the distance LE1 in the channel length direction of the transistor 200. Also, when the insulator 254 of the transistor 200 is viewed from above, the side end of the insulator 254 has a curved shape.

[0073] The shape of the side edge of the insulator 254 may be evaluated using, for example, an EDX map acquired using EDX. For example, when aluminum oxide is used for the insulator 254, a shape in which the distance LE2 is shorter than the distance LE1 and / or a shape in which the side edge has a curve may be observed in a planar EDX map of Al-K line.

[0074] 1 and 2 show an example in which angle 244, angle 258, and angle 248 are substantially the same, but the present invention is not limited to this. Angle 244, angle 258, and angle 248 may be different. For example, angle 244 can be controlled by processing the insulating layer that will become insulator 280 and insulator 254 to form openings that expose the conductive layer that will become conductor 242a and conductor 242b, and then etching the conductive layer using a gas that can generate an organic substance. This allows angle 244 to be different from angle 258 and angle 248.

[0075] As described above, a semiconductor device including a transistor with a large on-state current can be provided. A semiconductor device including a transistor with high frequency characteristics can be provided. A semiconductor device with stable electrical characteristics and improved reliability, with reduced fluctuations in electrical characteristics, can be provided. A semiconductor device including a transistor with a small off-state current can be provided.

[0076] <<Estimating the operating frequency of a semiconductor device through calculations using a device simulator>> Here, the results of estimating the operating frequency of a semiconductor device including a transistor according to one embodiment of the present invention through calculation using a device simulator will be described with reference to FIGS. 4 and 5. FIG.

[0077] The semiconductor device in this section refers to a DRAM that uses a memory cell with one OS transistor and one capacitor element. A DRAM that uses a memory cell with one OS transistor and one capacitor element is also called DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). Details of DOSRAM will be described in the following embodiments.

[0078] The data retention time of a DOSRAM can be expressed as the time required for the charge stored in the storage capacitance of the DOSRAM to decrease from the "value after data is written" to a "certain value." In this embodiment, the aforementioned "certain value" is defined as the time required for the potential applied to the capacitance element (storage capacitance 3.5 fF) of the DOSRAM to decrease by 0.2 V from the state after data is written. For example, in this embodiment, when DOSRAM data retention is said to be 1 hour, it means that the time required for the potential applied to the capacitance element of the DOSRAM to decrease by 0.2 V from the state after data is written is 1 hour.

[0079] The data retention time of a DOSRAM depends on the magnitude of the off-leak current of the transistors contained in the DOSRAM. Here, the off-leak current of a transistor can be rephrased as the drain current (Id) (i.e., Icut) when the gate voltage (Vg) of the transistor is 0V. For example, if the data retention characteristics of a DOSRAM depend only on the magnitude of Icut of the transistors contained in the DOSRAM, the data retention time of the DOSRAM is inversely proportional to the magnitude of Icut of the transistors contained in the DOSRAM.

[0080] Icut can be estimated by extrapolating the shift value (Vsh) and subthreshold swing value (Svalue) using the following equation (1). Here, Vsh is defined as Vg at the point where the tangent to the maximum slope on the curve of the transistor's Id-Vg characteristics intersects with the line where Id = 1 pA. Furthermore, Svalue refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage. Note that equation (1) holds true when it is assumed that the transistor's off-current monotonically decreases according to the Svalue obtained by Vg-Id measurement until it reaches Vg = 0V.

[0081]

number

[0082] From the above, the data retention time of DOSRAM can be estimated by calculating Vsh and Svalue obtained from the Id-Vg characteristics.

[0083] The DOSRAM operating frequency is defined as the reciprocal of the data write cycle time of the DOSRAM. The data write cycle time of the DOSRAM is a parameter set based on the charging time of the capacitance element of the DOSRAM. In this embodiment, the charging time of the capacitance element of the DOSRAM is set to be 40% of the data write cycle time of the DOSRAM (the reciprocal of the DOSRAM operating frequency).

[0084] As mentioned above, the operating frequency of the DOSRAM depends on the charging time of the capacitance element of the DOSRAM. Therefore, when estimating the operating frequency of the DOSRAM, it is necessary to first know the charging time of the capacitance element of the DOSRAM. In this embodiment, the state in which a potential of 0.55 V or more is applied to the capacitance element (storage capacitance 3.5 fF) of the DOSRAM is defined as the "charged state" of the capacitance element. Therefore, in this embodiment, the time from the start of the data write operation of the DOSRAM until the potential applied to the capacitance element reaches 0.55 V corresponds to the charging time of the capacitance element of the DOSRAM.

[0085] Now, if the charge stored in the capacitance element of the storage capacitance Cs [F] of the DOSRAM is Q [C], the charging time is t [sec], the potential applied to the capacitance element by charging is Vcs (= Vs) [V], and the drain current of the transistor in the DOSRAM is Id [A], then the relationship between each parameter is expressed by the following equation (2).

[0086]

number

[0087] Therefore, by modifying equation (2), the charging time t of the capacitance element of the DOSRAM can be expressed by the following equation (3).

[0088]

number

[0089] As described above, in this embodiment, a state in which the potential applied to a capacitor with a storage capacitance of 3.5 fF is equal to or higher than 0.55 V is defined as the "charged state" of the capacitor. Therefore, by substituting 3.5 fF for Cs, +0.55 V for Vcs, and the measured or calculated value of the transistor according to one embodiment of the present invention for Id in equation (3), the charging time t of the capacitor included in the DOSRAM can be calculated.

[0090] The charging time of the capacitance element in the DOSRAM depends on the magnitude of Id of the transistor in the DOSRAM when writing data to the DOSRAM. In other words, the operating frequency of the DOSRAM can be estimated by obtaining the Id-Vs characteristics.

[0091] Therefore, in this section, a potential that is expected to be applied to a transistor included in a DOSRAM when writing data to the DOSRAM was actually applied to a transistor according to one embodiment of the present invention to reproduce the DOSRAM data write operation, and the Id of the transistor at this time was measured. Specifically, the Id of the transistor was measured by fixing the gate potential of the transistor to +2.97 V, fixing the drain potential to +1.08 V, setting the back gate potential to an arbitrary value, and sweeping the source potential from 0 V to +0.55 V. The measurement temperature was 27°C.

[0092] Furthermore, the data retention time and operating frequency of the DOSRAM were calculated by calculating the Id-Vg and Id-Vs characteristics of the transistor according to one embodiment of the present invention using the above-described conditions with a device simulator. Note that the calculation of the data retention time does not take into account current leakage and degradation of element characteristics due to long-term retention.

[0093] Figures 4A to 4D show a transistor assumed in calculations using a device simulator. Figure 4A is a top view of the transistor. Figures 4B to 4D are cross-sectional views of the transistor. Figure 4B is a cross-sectional view of the portion indicated by the dashed-dotted line L1-L2 in Figure 4A, which is also a cross-sectional view of the transistor in the channel length direction. Figure 4C is a cross-sectional view of the portion indicated by the dashed-dotted line L3-L4 in Figure 4A, which is also a cross-sectional view of the transistor in the channel length direction. Figure 4D is a cross-sectional view of the portion indicated by the dashed-dotted line W1-W2 in Figure 4A, which is also a cross-sectional view of the transistor in the channel width direction. Note that some elements are omitted from the top view of Figure 4A for clarity.

[0094] In FIG. 4, conductor BGE is a back gate electrode and corresponds to conductor 205 in the transistor 200 shown in FIG. 1. Insulators BGI1 and BGI2 are back gate insulators and correspond to insulators 222 and 224, respectively, in the transistor 200 shown in FIG. 1. Semiconductors SEM1, SEM2, and SEM3 are semiconductor layers and correspond to oxides 230a, 230b, and 230c, respectively, in the transistor 200 shown in FIG. 1. Conductor SE is a source electrode and corresponds to one of conductors 242a and 242b in the transistor 200 shown in FIG. 1. Conductor DE is a drain electrode and corresponds to the other of conductors 242a and 242b in the transistor 200 shown in FIG. 1. Insulator CAP is a barrier film and corresponds to insulator 254 in the transistor 200 shown in FIG. 1. Insulator TGI is a top gate insulator and corresponds to insulator 250 in the transistor 200 shown in FIG. 1. The conductor TGE is a top gate electrode and corresponds to the conductor 260 of the transistor 200 shown in Figure 1. In addition, in the transistor structure shown in Figure 4, the angle 248 shown in Figure 1C, the angle 244 shown in Figure 2A, and the angle 258 shown in Figure 2B are all the same angle.

[0095] In this calculation, structures with different sizes (Structure 1A to Structure 3A) were prepared for the transistor shown in Figure 4. Of the parameter values ​​assumed in the calculation using the device simulator, the parameter values ​​that differ between Structures 1A to 3A are shown in Table 1.

[0096] [Table 1]

[0097] The angle θ shown in Table 1 is the angle between a plane parallel to the bottom surface of the conductor SE and the side surface of the conductor SE facing the conductor DE, and is also the angle between a plane parallel to the bottom surface of the conductor DE and the side surface of the conductor DE facing the conductor SE. The angle θ corresponds to the angle 244 shown in FIG. 2A. The length LG2 shown in Table 1 is the length of the bottom surface of the conductor TGE in the region where the semiconductors SEM2 and SEM1 do not overlap with the conductor TGE in the channel length direction of the transistor, as shown in FIG. 4C. The length LG2 is calculated using the angle θ and the parameters shown in Table 2. Table 1 shows that the smaller the angle θ, the shorter the length LG2.

[0098] Calculations were performed using a device simulator for Structures 1A to 3A. The device simulator used was the Atlas3D device simulator manufactured by Silvaco. Among the parameter values ​​assumed in the calculations using the device simulator, the parameter values ​​common to Structures 1A to 3A are shown in Table 2.

[0099] [Table 2]

[0100] IGZO(134) shown in Table 2 is assumed to be an In-Ga-Zn oxide with a composition of In:Ga:Zn=1:3:4. Also, IGZO(423) shown in Table 2 is assumed to be an In-Ga-Zn oxide with a composition of In:Ga:Zn=4:2:3. Also, the parameters listed for the SEMs shown in Table 2 are common to Semiconductor SEM1, Semiconductor SEM2, and Semiconductor SEM3.

[0101] FIG. 5A shows the estimated DOSRAM operating frequencies for a DOSRAM having structure 1A, a DOSRAM having structure 2A, and a DOSRAM having structure 3A at a power supply voltage of 3.3V and a temperature of 27°C. The DOSRAM operating frequencies shown in FIG. 5A are normalized so that the DOSRAM operating frequency of structure 1A is 1. In FIG. 5A, the horizontal axis represents the angle θ [°], and the vertical axis represents the normalized DOSRAM operating frequency. From FIG. 5A, it can be seen that the smaller the angle θ, the higher the DOSRAM frequency.

[0102] <<Evaluation of transistor electrical characteristics through calculations using a device simulator>> Next, the change in the on-current of the transistor 200 when the angle 244 shown in FIG. 2A is changed was evaluated by calculation using a device simulator. Specifically, the S value and on-current of Structures 1A to 3A were calculated. For Structures 1A to 3A, the Id-Vg characteristics at a drain voltage Vd of 1.2 V were calculated, and the S value and on-current Ion were calculated. Here, Ion was the current value when the gate voltage Vg was Vsh+3.0 V. Note that the back-gate voltage Vbg was set to an arbitrary value.

[0103] Figure 5(B) shows Ion calculated for each of Structures 1A to 3A. In Figure 5(B), the horizontal axis represents angle θ [°] and the vertical axis represents Ion [A]. Figure 5(B) shows that the smaller the angle θ, the larger Ion becomes.

[0104] FIG. 5C shows the S value calculated for each of Structures 1A to 3A. In FIG. 5C, the horizontal axis represents angle θ [°], and the vertical axis represents S value [mV / dec.]. From FIG. 5C, it can be seen that the amount of change in S value with respect to a change in angle θ is smaller than the amount of change in Ion. Therefore, it can be seen that angle θ has a large contribution to Ion and a small contribution to S value.

[0105] As a result, it can be seen that the smaller the angle θ, the larger the Ion of the transistor, and thus the higher the operating frequency of the semiconductor device including the transistor. This is presumably because the smaller the angle θ, the narrower the width of the region of the conductor SE or the conductor DE that does not overlap with the conductor TGE, the so-called offset region.

[0106] <<Detailed configuration of semiconductor device>> A detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described below.

[0107] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 216.

[0108] Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. The conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V compared to not applying a negative potential to the conductor 205.

[0109] 1(A), the conductor 205 is preferably larger than the region 234 in the oxide 230. In particular, as shown in FIG. 1(D), it is preferable that the conductor 205 also extends to a region outside the end of the region 234 of the oxide 230b that intersects with the channel width direction. In other words, it is preferable that the conductor 205 and the conductor 260 overlap with each other with an insulator interposed therebetween on the outside of the side surface of the oxide 230 in the channel width direction.

[0110] With the above structure, the channel formation region of the region 234 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

[0111] Furthermore, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component for the conductor 205. Although the conductor 205 is illustrated as a single layer, it may have a multilayer structure, for example, a multilayer structure of titanium, titanium nitride, and the above-mentioned conductive material.

[0112] The insulator 214 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200. Therefore, the insulator 214 is preferably made of an insulating material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, and NO), and copper atoms (i.e., the impurities are less likely to permeate through the material). Alternatively, the insulator 214 is preferably made of an insulating material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) (i.e., the oxygen is less likely to permeate through the material).

[0113] For example, it is preferable to use silicon nitride or the like as the insulator 214. This can prevent impurities such as water and hydrogen from diffusing from the substrate side of the insulator 214 to the transistor 200 side. Alternatively, it can prevent oxygen contained in the insulator 224 or the like from diffusing from the insulator 214 to the substrate side.

[0114] Furthermore, the insulators 216, 280, and 281 preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, the insulators 216, 280, and 281 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0115] The insulator 222 and the insulator 224 function as gate insulators.

[0116] Here, the insulator 224 in contact with the oxide 230 preferably releases oxygen by heating. In this specification, oxygen released by heating is sometimes referred to as excess oxygen. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved.

[0117] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as the insulator 224. The oxide film from which oxygen is released by heating is an oxide film in which the amount of released oxygen converted into oxygen atoms is 1.0×10 in TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0118] 1(D), the thickness of the insulator 224 in a region that does not overlap with the insulator 254 and the oxide 230b may be thinner than the thickness of the other regions. It is preferable that the thickness of the insulator 224 in a region that does not overlap with the insulator 254 and the oxide 230b is a thickness that allows the oxygen to diffuse sufficiently.

[0119] The insulator 222 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side into the transistor 200. For example, the insulator 222 preferably has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the oxide 230, and the like with the insulator 222 and the insulator 254, it is possible to suppress the diffusion of impurities such as water and hydrogen from the outside into the transistor 200.

[0120] Furthermore, it is preferable that the insulator 222 has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). For example, it is preferable that the insulator 222 has lower oxygen permeability than the insulator 224. The insulator 222 is preferable because it has a function of suppressing the diffusion of oxygen and impurities, which can reduce the diffusion of oxygen contained in the oxide 230 toward the insulator 220. Furthermore, it can suppress the reaction of the conductor 205 with the insulator 224 and the oxygen contained in the oxide 230.

[0121] The insulator 222 may be an insulator containing an oxide of one or both of insulating materials, aluminum and hafnium. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing an oxide of one or both of aluminum and hafnium. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230.

[0122] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0123] The insulator 222 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0124] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structures are not limited to those made of the same material, and may be those made of different materials.

[0125] The oxide 230 includes an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. By providing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b. Furthermore, by providing the oxide 230c on the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed above the oxide 230c to the oxide 230b.

[0126] The oxide 230 preferably has a layered structure made up of oxides with different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the main constituent element is preferably greater than the atomic ratio of the element M to the main constituent element in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. In addition, the oxide 230c can be made from the same metal oxide that can be used for the oxide 230a or the oxide 230b.

[0127] Furthermore, the oxide 230b preferably has crystallinity. For example, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) described later. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), a highly crystalline, and a dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 230b. This can reduce the extraction of oxygen from the oxide 230b even during heat treatment, making the transistor 200 stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0128] It is also preferable that the conduction band minimums of the oxides 230a and 230c are closer to the vacuum level than the conduction band minimum of the oxide 230b. In other words, it is preferable that the electron affinity of the oxides 230a and 230c is smaller than that of the oxide 230b.

[0129] Here, the conduction band minimum changes smoothly at the junctions of the oxides 230a, 230b, and 230c. In other words, the conduction band minimum at the junctions of the oxides 230a, 230b, and 230c changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layers formed at the interfaces between the oxides 230a and 230b and between the oxides 230b and 230c.

[0130] Specifically, the oxide 230a may be a metal oxide with an atomic ratio of In:Ga:Zn=1:3:4 or 1:1:0.5. The oxide 230b may be a metal oxide with an atomic ratio of In:Ga:Zn=4:2:3 or 3:1:2. The oxide 230c may be a metal oxide with an atomic ratio of In:Ga:Zn=1:3:4, In:Ga:Zn=4:2:3, Ga:Zn=2:1, or Ga:Zn=2:5. Specific examples of the oxide 230c having a layered structure include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and In:Ga:Zn=1:3:4 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

[0131] In this case, the oxide 230b serves as the main carrier path. The oxide 230a and the oxide 230c are configured as described above, which reduces the defect state density at the interface between the oxide 230a and the oxide 230b and at the interface between the oxide 230b and the oxide 230c. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 200 to achieve a high on-state current and high frequency characteristics. Note that when the oxide 230c has a stacked structure, in addition to the effect of reducing the defect state density at the interface between the oxide 230b and the oxide 230c, it is expected to suppress the diffusion of constituent elements of the oxide 230c toward the insulator 250. More specifically, the oxide 230c has a stacked structure, and an oxide not containing In is positioned above the stacked structure, which suppresses the diffusion of In toward the insulator 250. The insulator 250 functions as a gate insulator, and if In is mixed into the insulator 250, the transistor's characteristics will be impaired. Therefore, by forming the oxide 230c into a stacked structure, it is possible to provide a highly reliable semiconductor device.

[0132] The oxide 230 is preferably a metal oxide that functions as an oxide semiconductor. For example, the metal oxide that forms the region 234 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with such a wide band gap, the off-state current of the transistor can be reduced. By using such a transistor, a semiconductor device with low power consumption can be provided.

[0133] Conductors 242 (conductors 242a and 242b) functioning as a source electrode and a drain electrode are provided on the oxide 230b. The thickness of the conductor 242 is, for example, 1 nm to 50 nm, preferably 2 nm to 25 nm.

[0134] The conductor 242 is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, or an alloy containing the above metal elements or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel are preferred. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are also preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0135] Like the insulator 214, the insulator 254 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from the insulator 280 side to the transistor 200. For example, the insulator 254 preferably has lower hydrogen permeability than the insulator 224. Furthermore, as shown in FIGS. 1B and 1D, the insulator 254 preferably contacts the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the oxide 230a and the oxide 230b, and the top surface of the insulator 224. This structure can suppress diffusion of hydrogen contained in the insulator 280 from the top surfaces or side surfaces of the conductor 242a, the conductor 242b, the oxide 230a, the oxide 230b, and the insulator 224 to the oxide 230.

[0136] In this way, by covering the insulator 224 and the oxide 230 with the insulator 254, which has a barrier property against hydrogen, the insulator 280 is separated from the insulator 224 and the oxide 230 by the insulator 254. This makes it possible to prevent impurities such as hydrogen from diffusing into the transistor 200 from outside the transistor 200, thereby providing the transistor 200 with good electrical characteristics and reliability.

[0137] Furthermore, it is preferable that the insulator 254 has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). For example, it is preferable that the insulator 254 has lower oxygen permeability than the insulator 224.

[0138] The insulator 254 is preferably formed by a sputtering method. By forming the insulator 254 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulator 224 near the region in contact with the insulator 254. This allows oxygen to be supplied from this region into the oxide 230 through the insulator 224. The insulator 254 has a function of suppressing upward oxygen diffusion, thereby preventing oxygen from diffusing from the oxide 230 to the insulator 280. The insulator 222 has a function of suppressing downward oxygen diffusion, thereby preventing oxygen from diffusing from the oxide 230 to the insulator 216. In this way, oxygen is supplied to the region 234, which functions as a channel formation region of the oxide 230. This reduces oxygen vacancies in the oxide 230 and suppresses the transistor from becoming normally on.

[0139] The insulator 254 may be, for example, an insulator containing oxide of one or both of aluminum and hafnium.

[0140] The insulator 254 may have a multilayer structure of two or more layers. For example, the insulator 254 may have a two-layer structure in which a first layer is formed by sputtering in an oxygen-containing atmosphere and then a second layer is formed by ALD. The ALD method provides good coating properties, so it can prevent discontinuities due to the unevenness of the first layer. When the insulator 254 has a multilayer structure of two or more layers, the multilayer structure may be made of different materials. For example, the insulator 254 may have a stacked structure of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride, and an insulator that suppresses the permeation of impurities such as hydrogen and oxygen. As the insulator that suppresses the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing an oxide of one or both of aluminum and hafnium can be used.

[0141] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230c. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0142] Like the insulator 224, the insulator 250 is preferably formed using an insulator that releases oxygen when heated. By providing the insulator that releases oxygen when heated as the insulator 250 in contact with the upper surface of the oxide 230c, oxygen can be effectively supplied to the region 234 of the oxide 230b. Also, like the insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 be reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0143] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0144] Furthermore, the metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By forming the gate insulator into a stacked structure of the insulator 250 and the metal oxide, it is possible to achieve a stacked structure that is thermally stable and has a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0145] Specifically, it is possible to use a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0146] Although the conductor 260 is shown as having a two-layer structure in FIG. 1, it may have a single-layer structure or a laminated structure of three or more layers.

[0147] The conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0148] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0149] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium, titanium nitride, and the above-mentioned conductive material.

[0150] The insulator 280 is provided over the insulator 224, the oxide 230, and the conductor 242 with the insulator 254 interposed therebetween. For example, the insulator 280 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly preferred because they can easily form a region containing oxygen that is released by heating.

[0151] It is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulator 280. The top surface of the insulator 280 may be flattened.

[0152] Similar to the insulator 210, the insulator 274 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 280. As the insulator 274, for example, an insulator that can be used for the insulator 210, the insulator 254, etc. may be used.

[0153] It is also preferable to provide an insulator 281 functioning as an interlayer film over the insulator 274. Like the insulator 224, the insulator 281 preferably has a reduced concentration of impurities such as water and hydrogen.

[0154] Furthermore, the conductor 240a and the conductor 240b are disposed in openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 254. The conductor 240a and the conductor 240b are disposed opposite each other with the conductor 260 interposed therebetween. The height of the upper surfaces of the conductor 240a and the conductor 240b may be flush with the upper surface of the insulator 281.

[0155] Note that insulator 241a is provided in contact with the side walls of the openings of insulators 281, 274, 280, and 254, and a first conductor of conductor 240a is formed in contact with the side surface of insulator 241a. Conductor 242a is located on at least a portion of the bottom of the openings, and conductor 240a is in contact with conductor 242a. Similarly, insulator 241b is provided in contact with the side walls of the openings of insulators 281, 274, 280, and 254, and a first conductor of conductor 240b is formed in contact with the side surface of insulator 241b. Conductor 242b is located on at least a portion of the bottom of the openings, and conductor 240b is in contact with conductor 242b.

[0156] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 240a and 240b may have a layered structure.

[0157] Furthermore, when the conductor 240 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the conductors in contact with the oxide 230a, the oxide 230b, the conductor 242, the insulator 254, the insulator 280, the insulator 274, and the insulator 281. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Using such a conductive material can prevent oxygen added to the insulator 280 from being absorbed by the conductor 240a and the conductor 240b. It can also prevent impurities such as water and hydrogen contained in layers above the insulator 281 from diffusing into the oxide 230 through the conductor 240a and the conductor 240b.

[0158] The insulators 241a and 241b may be, for example, insulators that can be used for the insulator 254. The insulators 241a and 241b are provided in contact with the insulator 254, and therefore can prevent impurities such as water and hydrogen contained in the insulator 280 from diffusing into the oxide 230 through the conductors 240a and 240b. Furthermore, the oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.

[0159] Although not shown, a conductor functioning as wiring may be disposed in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b. The conductor functioning as wiring is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may also have a layered structure, for example, a layered structure of titanium, titanium nitride, and the above-mentioned conductive material. The conductor may also be formed so as to be embedded in an opening provided in an insulator.

[0160] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0161] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates such as silicon and germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride and a metal oxide. Examples of other substrates include an insulating substrate with a conductor or semiconductor provided thereon, a semiconductor substrate with a conductor or insulator provided thereon, and a conductive substrate with a semiconductor or insulator provided thereon. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0162] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0163] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0164] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0165] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0166] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding it with an insulator (such as the insulator 214, the insulator 222, the insulator 254, or the insulator 274) that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, a single-layer or stacked insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide; and metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0167] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0168] <<Conductors>> The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0169] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0170] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0171] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0172] <<Metal oxides>> It is preferable to use a metal oxide that functions as an oxide semiconductor as the oxide 230. Metal oxides that can be used as the oxide 230 according to the present invention will be described below.

[0173] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like.

[0174] Here, we consider a case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M may be aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, there are cases where a combination of the aforementioned elements may be used as element M.

[0175] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0176] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors, such as CAAC-OS, polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0177] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distorted crystal structure refers to the change in the lattice orientation between regions with a uniform lattice arrangement and regions with a different uniform lattice arrangement in the regions where multiple nanocrystals are connected.

[0178] Nanocrystals are basically hexagonal, but not necessarily regular hexagons; they may also have non-regular hexagonal shapes. Furthermore, the lattice arrangement of CAAC-OS may be pentagonal, heptagonal, or other shapes due to distortion. It is difficult to identify clear grain boundaries in CAAC-OS even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the ab-plane direction and the change in interatomic bond distance caused by substitution of metal elements.

[0179] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as an (M,Zn) layer) are stacked. Note that indium and the element M are mutually substituted, and when the element M in an (M,Zn) layer is substituted with indium, it can also be expressed as an (In,M,Zn) layer. When the indium in an In layer is substituted with the element M, it can also be expressed as an (In,M) layer.

[0180] CAAC-OS is a metal oxide with high crystallinity. Because it is difficult to identify clear grain boundaries in CAAC-OS, it is unlikely that the electron mobility will decrease due to grain boundaries. Furthermore, because the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects, CAAC-OS can be considered a metal oxide with few impurities or defects (such as oxygen vacancies). Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0181] The nc-OS has periodic atomic arrangement in a small region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0182] Indium-gallium-zinc oxide (IGZO), a type of metal oxide containing indium, gallium, and zinc, can sometimes have a stable structure when made into the above-mentioned nanocrystals. In particular, because IGZO tends to have difficulty growing crystals in the atmosphere, it may be structurally more stable when made into small crystals (such as the above-mentioned nanocrystals) than large crystals (here, crystals of a few millimeters or a few centimeters).

[0183] The a-like OS is a metal oxide having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0184] Oxide semiconductors (metal oxides) have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0185] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0186] When a metal oxide contains an alkali metal or alkaline earth metal, defect levels may be formed, generating carriers. Therefore, a transistor using a metal oxide containing an alkali metal or alkaline earth metal in a channel formation region is likely to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS (the concentration obtained by secondary ion mass spectrometry (SIMS)) is reduced to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0187] Furthermore, hydrogen contained in metal oxides may react with oxygen bonded to metal atoms to form water, forming oxygen vacancies. Hydrogen entering the oxygen vacancies may generate electrons, which serve as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which serve as carriers. Therefore, transistors using metal oxides containing hydrogen tend to exhibit normally-on characteristics.

[0188] For this reason, it is preferable that the hydrogen content in the metal oxide is reduced as much as possible. Specifically, the hydrogen concentration in the metal oxide obtained by SIMS is reduced to 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide with sufficiently reduced impurities for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0189] It is preferable to use a highly crystalline thin film as the metal oxide semiconductor of a transistor. The use of such a thin film can improve the stability or reliability of the transistor. Examples of such a thin film include a thin film of a single-crystal metal oxide or a thin film of a polycrystalline metal oxide. However, forming a thin film of a single-crystal metal oxide or a thin film of a polycrystalline metal oxide on a substrate requires a high-temperature or laser heating process. This increases the cost of the manufacturing process and also reduces throughput.

[0190] In 2009, the discovery of In-Ga-Zn oxide with a CAAC structure (referred to as CAAC-IGZO) was reported in Non-Patent Documents 1 and 2. It was reported that CAAC-IGZO has a c-axis orientation, no clearly visible grain boundaries, and can be formed on a substrate at low temperatures. Furthermore, it was reported that transistors using CAAC-IGZO have excellent electrical properties and reliability.

[0191] In 2013, an In-Ga-Zn oxide (called nc-IGZO) with an nc structure was discovered (see Non-Patent Document 3). It was reported that nc-IGZO has periodic atomic arrangement in minute regions (for example, regions of 1 nm to 3 nm), and no regularity in the crystal orientation is observed between different regions.

[0192] Non-Patent Documents 4 and 5 show the changes in average crystal size due to electron beam irradiation in thin films of the above-mentioned CAAC-IGZO, nc-IGZO, and low-crystalline IGZO. Crystalline IGZO of approximately 1 nm was observed in the low-crystalline IGZO thin film even before electron beam irradiation. Therefore, it is reported that the presence of a completely amorphous structure could not be confirmed in IGZO. Furthermore, compared with low-crystalline IGZO thin films, CAAC-IGZO thin films and nc-IGZO thin films have been shown to be more stable against electron beam irradiation. Therefore, it is preferable to use CAAC-IGZO thin films or nc-IGZO thin films as semiconductors for transistors.

[0193] A transistor using a metal oxide has an extremely low leakage current in the off-state. Specifically, the off-state current per 1 μm of the channel width of the transistor is yA / μm (10 -24 Non-Patent Document 6 shows that the leakage current is on the order of A / μm. For example, a low-power CPU that utilizes the low leakage current characteristic of transistors using metal oxides has been disclosed (see Non-Patent Document 7).

[0194] Furthermore, the application of metal oxide transistors to display devices has been reported, taking advantage of their low leakage current (see Non-Patent Document 8). Display devices change the displayed image several tens of times per second. The number of image changes per second is called the refresh rate. The refresh rate is also sometimes called the drive frequency. Such high-speed screen changes, which are difficult for the human eye to perceive, are thought to cause eye fatigue. Therefore, it has been proposed to reduce the refresh rate of display devices to reduce the number of image rewrites. Furthermore, driving at a reduced refresh rate can reduce the power consumption of display devices. This driving method is called idling stop (IDS) driving.

[0195] The discovery of the CAAC and nc structures has contributed to improving the electrical characteristics and reliability of transistors using metal oxides with the CAAC or nc structure, as well as reducing the cost and throughput of the manufacturing process. Furthermore, research into the application of these transistors to display devices and LSIs is ongoing, taking advantage of their low leakage current.

[0196] <Method for manufacturing semiconductor device> Next, a manufacturing method of a semiconductor device including the transistor 200 according to the present invention shown in FIG. 1 will be described with reference to FIGS. 6 to 13. In FIGS. 6 to 13, (A) in each figure is a top view. (B) in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line L1-L2 in (A), which is also a cross-sectional view in the channel length direction of the transistor 200. (C) in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line W1-W2 in (A), which is also a cross-sectional view in the channel width direction of the transistor 200. Note that some elements are omitted from the top view (A) in each figure for clarity.

[0197] First, a substrate (not shown) is prepared, and then the insulator 214 is formed on the substrate. The insulator 214 can be formed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), or the like.

[0198] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0199] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0200] Furthermore, ALD utilizes the self-regulating properties of atoms to deposit atoms layer by layer, enabling the formation of ultrathin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films formed at low temperatures. ALD also includes plasma-enhanced ALD (PEALD), which utilizes plasma. Using plasma can sometimes be preferable because it enables film formation at lower temperatures. Note that some precursors used in ALD contain impurities such as carbon. Therefore, films formed by ALD may contain higher amounts of impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0201] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0202] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0203] In this embodiment, a silicon nitride film is formed by a CVD method as the insulator 214. By using an insulator such as silicon nitride, which is difficult for copper to penetrate, as the insulator 214, even if a metal that easily diffuses, such as copper, is used in a conductor below the insulator 214 (not shown), the metal can be prevented from diffusing into layers above the insulator 214.

[0204] Next, a conductive film to become the conductor 205 is formed on the insulator 214. The conductive film to become the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductive film to become the conductor 205 can also be a multilayer film. In this embodiment, a tungsten film is formed as the conductive film to become the conductor 205.

[0205] Next, the conductive film that will become the conductor 205 is processed using lithography to form the conductor 205 .

[0206] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. Then, etching is performed through the resist mask to process conductors, semiconductors, insulators, and the like into desired shapes. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or an ion beam may also be used instead of the light described above. When an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0207] Alternatively, a hard mask made of an insulator or a conductor may be used instead of a resist mask. When using a hard mask, an insulating film or a conductive film that will serve as a hard mask material is formed on the conductive film that will become the conductor 205, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. Etching of the conductive film that will become the conductor 205 may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching of the conductive film that will become the conductor 205. On the other hand, if the material of the hard mask does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0208] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source may be used. For example, an inductively coupled plasma (ICP) etching apparatus may be used as the dry etching apparatus having a high-density plasma source.

[0209] Next, an insulating film that will become the insulator 216 is formed on the insulator 214 and the conductor 205. The insulator that will become the insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed by a CVD method as the insulating film that will become the insulator 216.

[0210] Here, it is preferable that the thickness of the insulating film that becomes the insulator 216 is equal to or greater than the thickness of the conductor 205. For example, if the thickness of the conductor 205 is 1, the thickness of the insulating film that becomes the insulator 216 is equal to or greater than 1 and equal to or less than 3. In this embodiment, the thickness of the conductor 205 is 150 nm, and the thickness of the insulating film that becomes the insulator 216 is 350 nm.

[0211] Next, a CMP (chemical mechanical polishing) process is performed on the insulating film that will become the insulator 216, thereby removing a portion of the insulating film that will become the insulator 216 and exposing the surface of the conductor 205. This makes it possible to form the conductor 205 and the insulator 216 with flat upper surfaces (see FIG. 6).

[0212] Hereinafter, a method for forming the conductor 205 that differs from the above will be described.

[0213] An insulator 216 is deposited on the insulator 214. The insulator 216 can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like.

[0214] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The region where the opening is formed may also be referred to as an opening. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when the insulator 216 is etched to form the groove. For example, if a silicon oxide film is used for the insulator 216 that forms the groove, the insulator 214 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.

[0215] After the openings are formed, a conductive film that will become the conductor 205 is formed. The conductive film preferably contains a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film can be a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film that will become the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0216] In this embodiment, a multilayer structure is used as the conductive film that becomes the conductor 205. First, a tantalum nitride film is formed by sputtering, and then titanium nitride is laminated on the tantalum nitride. By using such a metal nitride as the lower layer of the conductive film that becomes the conductor 205, even if a metal that easily diffuses, such as copper, is used as the upper conductive film of the conductive film that becomes the conductor 205 (described later), the metal can be prevented from diffusing out of the conductor 205.

[0217] Next, a conductive film is formed as an upper layer of the conductive film that will become the conductor 205. The conductive film can be formed by plating, sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as the upper conductive film of the conductive film that will become the conductor 205.

[0218] Next, a CMP process is performed to remove the upper layer of the conductive film that will become the conductor 205 and a portion of the lower layer of the conductive film that will become the conductor 205, thereby exposing the insulator 216. As a result, the conductive film that will become the conductor 205 remains only in the opening. This makes it possible to form a conductor 205 with a flat upper surface. Note that the CMP process may remove a portion of the insulator 216. These are the different methods for forming the conductor 205.

[0219] Next, the insulator 222 is formed over the insulator 216 and the conductor 205. The insulator 222 may be an insulator containing one or both of aluminum and hafnium oxides. Note that aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing one or both of aluminum and hafnium oxides. An insulator containing one or both of aluminum and hafnium oxides has barrier properties against oxygen, hydrogen, and water. The insulator 222 having barrier properties against hydrogen and water prevents hydrogen and water contained in structures provided around the transistor 200 from diffusing into the inside of the transistor 200 through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0220] The insulator 222 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0221] Next, the insulator 224 is deposited on the insulator 222. The insulator 224 can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like.

[0222] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by another heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0223] In this embodiment, treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour, and then treatment is continuously performed in an oxygen atmosphere at 400° C. for 1 hour. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 224.

[0224] Alternatively, the heat treatment may be performed after the formation of the insulator 222. The heat treatment can be performed under the above-described heat treatment conditions.

[0225] Here, to form an excess oxygen region in the insulator 224, a plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use an apparatus having a power source that generates high-density plasma using, for example, microwaves. Alternatively, a power source that applies RF (radio frequency) to the substrate side may be provided. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment containing an inert gas using this apparatus, a plasma treatment containing oxygen may be performed to replenish the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In this case, heat treatment is not required.

[0226] Here, after forming an aluminum oxide film on the insulator 224 by, for example, a sputtering method, CMP processing may be performed until the aluminum oxide reaches the insulator 224. This CMP processing can planarize and smooth the surface of the insulator 224. By placing the aluminum oxide on the insulator 224 and performing the CMP processing, it becomes easier to detect the end point of the CMP processing. Furthermore, the CMP processing may polish a portion of the insulator 224, resulting in a thinner film of the insulator 224. However, the film thickness can be adjusted during the formation of the insulator 224. Planarizing and smoothing the surface of the insulator 224 may prevent a deterioration in the coverage of the oxide film to be formed later and may prevent a decrease in the yield of the semiconductor device. Furthermore, forming an aluminum oxide film on the insulator 224 by a sputtering method is preferable because it allows oxygen to be added to the insulator 224.

[0227] Next, an oxide film 230A that will become oxide 230a and an oxide film 230B that will become oxide 230b are sequentially formed on the insulator 224 (see FIG. 6). Note that it is preferable to form the oxide films in succession without exposing them to the atmospheric environment. By forming the films without exposing them to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide films 230A and 230B, and it is possible to keep the vicinity of the interface between the oxide films 230A and 230B clean.

[0228] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0229] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixture of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, the In-M-Zn oxide target can be used.

[0230] In particular, during the deposition of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230A should be 70% or more, preferably 80% or more, and more preferably 100%.

[0231] When the oxide film 230B is formed by sputtering, an oxygen-deficient oxide semiconductor is formed by setting the ratio of oxygen contained in the sputtering gas to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can achieve relatively high field-effect mobility.

[0232] In this embodiment, the oxide film 230A is formed by sputtering using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn=1:1:0.5 (2:2:1) or 1:3:4. The oxide film 230B is formed by sputtering using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Each oxide film can be formed according to the desired characteristics of the oxide 230 by appropriately selecting the film formation conditions and atomic ratio.

[0233] Next, a heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. The heat treatment can remove impurities such as water and hydrogen from the oxide film 230A and the oxide film 230B. In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 400°C for one hour, followed by another heat treatment in an oxygen atmosphere at 400°C for one hour.

[0234] Next, a conductive film 242A is formed on the oxide film 230B. The conductive film 242A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like (see FIG. 6).

[0235] Next, the oxide film 230A, the oxide film 230B, and the conductive film 242A are processed into islands to form the oxide 230a, the oxide 230b, and the conductive layer 242B. Note that in this process, the thickness of the insulator 224 in the region that does not overlap with the oxide 230a may become thin (see FIG. 7).

[0236] Here, the oxide 230a, the oxide 230b, and the conductive layer 242B are formed so that at least a portion thereof overlaps with the conductor 205. Furthermore, the side surfaces of the oxide 230a, the oxide 230b, and the conductive layer 242B are preferably approximately perpendicular to the top surface of the insulator 222. By making the side surfaces of the oxide 230a, the oxide 230b, and the conductive layer 242B approximately perpendicular to the top surface of the insulator 222, a smaller area and higher density can be achieved when providing multiple transistors 200. Alternatively, the side surfaces of the oxide 230a, the oxide 230b, and the conductive layer 242B may be configured so that the angles formed between the side surfaces and the top surface of the insulator 222 are small. In this case, the angles formed between the side surfaces of the oxide 230a, the oxide 230b, and the conductive layer 242B and the top surface of the insulator 222 are preferably greater than or equal to 60 degrees and less than 70 degrees. By forming the insulating layer 254 in this shape, the covering property of the insulating layer 254 can be improved in the subsequent steps, and defects such as voids can be reduced.

[0237] Furthermore, there is a curved surface between the side surface of the conductive layer 242B and the top surface of the conductive layer 242B. That is, the end of the side surface and the end of the top surface are preferably curved (hereinafter also referred to as rounded). For example, the curved surface has a radius of curvature of 3 nm to 10 nm, preferably 5 nm to 6 nm, at the end of the conductive layer 242B. The lack of corners at the end improves film coverage in the subsequent film formation process.

[0238] The oxide film 230A, the oxide film 230B, and the conductive film 242A may be processed by lithography. The processing may be performed by dry etching or wet etching. Dry etching is suitable for fine processing.

[0239] Next, an insulating film 254A is formed on the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B (see FIG. 8).

[0240] The insulating film 254A is preferably an insulating film that has a function of suppressing oxygen permeation. For example, an aluminum oxide film is preferably formed by sputtering. By forming an aluminum oxide film by sputtering using a gas containing oxygen, oxygen can be injected into the insulator 224. That is, the insulator 224 can have excess oxygen.

[0241] Next, an insulating film that will become the insulator 280 is formed on the insulating film 254A. The insulating film that will become the insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Next, the insulating film that will become the insulator 280 is subjected to a CMP process to form the insulator 280 with a flat upper surface (see FIG. 8).

[0242] Next, a part of the insulator 280, a part of the insulating film 254A, and a part of the conductive layer 242B are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. The conductor 242a, the conductor 242b, and the insulator 254 are formed through the opening (see FIG. 9).

[0243] Furthermore, a portion of the insulator 280, a portion of the insulating film 254A, and a portion of the conductive layer 242B may be processed under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulating film 254A may be processed by wet etching, and a portion of the conductive layer 242B may be processed by dry etching.

[0244] By performing processes such as dry etching, impurities originating from etching gases may adhere to or diffuse into the surface or interior of the oxide 230a, oxide 230b, etc. Examples of impurities include fluorine and chlorine.

[0245] Cleaning is performed to remove the above-mentioned impurities, etc. Cleaning methods include wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate.

[0246] For wet cleaning, cleaning treatment may be performed using an aqueous solution of oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, or ultrasonic cleaning using pure water or carbonated water.

[0247] Next, a heat treatment may be performed. The heat treatment may be performed under reduced pressure, and the oxide film 230C may be formed continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxides 230a and 230b can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is set to 200°C (see FIG. 10).

[0248] The oxide film 230C can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film that becomes the oxide film 230C may be formed by the same film formation method as that for the oxide film 230A or the oxide film 230B, depending on the desired characteristics of the oxide film 230C. In this embodiment, the oxide film 230C is formed by sputtering using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn=1:3:4 or 4:2:4.1.

[0249] In particular, during the deposition of the oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to the oxides 230a and 230b. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230C should be 70% or more, preferably 80% or more, and more preferably 100%.

[0250] Next, a heat treatment may be performed. The heat treatment may be performed under reduced pressure, and insulating film 250A may be formed continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of oxide film 230C can be removed, and the moisture and hydrogen concentrations in oxide 230a, oxide 230b, and oxide film 230C can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower (see FIG. 11).

[0251] The insulating film 250A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. It is preferable to form a silicon oxynitride film as the insulating film 250A by CVD. The film formation temperature for forming the insulating film 250A is preferably 350°C or higher and lower than 450°C, and particularly preferably around 400°C. By forming the insulating film 250A at 400°C, an insulating film with few impurities can be formed.

[0252] Next, the conductive film 260A and the conductive film 260B are formed. The conductive film 260A and the conductive film 260B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to use a CVD method. In this embodiment, the conductive film 260A is formed using an ALD method, and the conductive film 260B is formed using a CVD method (see FIG. 12).

[0253] Next, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (see FIG. 13). As a result, the oxide 230c is arranged to cover the inner wall (side wall and bottom surface) of the opening that reaches the oxide 230b. The insulator 250 is arranged to cover the inner wall of the opening via the oxide 230c. The conductor 260 is arranged to fill the opening via the oxide 230c and the insulator 250.

[0254] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280.

[0255] Next, the insulator 274 may be formed on the insulator 280. The insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 274, for example, an aluminum oxide film is preferably formed by a sputtering method. An aluminum oxide film formed by a sputtering method may extract hydrogen from a structure to be formed. Therefore, forming an aluminum oxide film by a sputtering method may prevent hydrogen from diffusing from the insulator 280 to the insulator 250 and the oxide 230 (see FIG. 13).

[0256] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. By this heat treatment, oxygen added by the formation of the insulator 274 can be injected into the insulators 250 and 280.

[0257] Next, an insulator 281 may be formed on the insulator 274. The insulator 281 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like (see FIG. 13).

[0258] Next, openings reaching the conductor 242a or the conductor 242b are formed in the insulators 254, 280, 274, and 281. The openings may be formed by lithography.

[0259] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241. The insulating film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable to use an insulating film that has the function of suppressing oxygen permeation as the insulating film. For example, it is preferable to form an aluminum oxide film by an ALD method. Furthermore, the anisotropic etching may be performed by, for example, a dry etching method. By configuring the sidewall portion of the opening in this way, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductor 240a and the conductor 240b that will be formed next. It is also possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductor 240a and the conductor 240b.

[0260] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film that will become the conductor 240a and the conductor 240b is preferably a layered structure including a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a layered structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that will become the conductor 240a and the conductor 240b can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0261] Next, CMP processing is performed to remove portions of the conductive film that will become the conductors 240a and 240b, thereby exposing the insulator 281. As a result, the conductive film remains only in the openings, thereby forming the conductors 240a and 240b with flat upper surfaces (see FIG. 1). Note that the CMP processing may remove portions of the insulator 281.

[0262] Through the above steps, a semiconductor device including the transistor 200 illustrated in FIG 1 can be manufactured. As illustrated in FIGS. 6 to 13, the transistor 200 can be manufactured by the method for manufacturing a semiconductor device described in this embodiment.

[0263] According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high reliability can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with low off-state current can be provided. According to another embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to another embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0264] The structures, methods, and the like described in this embodiment can be used in appropriate combination with structures, methods, and the like described in other embodiment modes and examples.

[0265] (Embodiment 2) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0266] [Storage device 1] 14 illustrates an example of a semiconductor device (memory device) including a capacitor according to one embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, a transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistors 300 and 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

[0267] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. The transistor 200 has a low off-state current; therefore, when used in a memory device, the stored data can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the memory device can be sufficiently reduced.

[0268] 14 , a wiring 1001 is electrically connected to the source of a transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of a transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of a capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0269] Moreover, the memory device shown in FIG. 14 can be arranged in a matrix to form a memory cell array.

[0270] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate electrode, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel type or an n-channel type.

[0271] Here, in the transistor 300 shown in FIG. 14, a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. In addition, a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. In addition, although the case where the convex portion is formed by processing a part of the semiconductor substrate has been shown, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0272] Note that the transistor 300 shown in FIG. 14 is just an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration and driving method.

[0273] <Capacitor element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 functioning as a first electrode, a conductor 120 functioning as a second electrode, and an insulator 130 functioning as a dielectric.

[0274] For example, the conductor 112 over the conductor 246 and the conductor 110 can be formed simultaneously. Note that the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

[0275] 14, the conductor 112 and the conductor 110 are shown as having a single layer structure, but are not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0276] The insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be formed as a stacked layer or a single layer.

[0277] For example, it is preferable to use a layered structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitor 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitor 100 can improve its dielectric strength by having an insulator with high dielectric strength, thereby preventing electrostatic breakdown of the capacitor 100.

[0278] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0279] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0280] <Wiring layer> Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductor functioning as a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0281] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and 330 electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings.

[0282] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0283] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 14, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0284] Similarly, a conductor 218 and a conductor (conductor 205) constituting the transistor 200 are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0285] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0286] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0287] For example, it is preferable to use insulators with low dielectric constants for insulators 150, 212, 352, and 354. For example, the insulators preferably include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, vacant silicon oxide, and resin. Alternatively, the insulators preferably have a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or vacant silicon oxide, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a thermally stable layered structure with a low dielectric constant. Examples of suitable resins include polyester, polyolefin, polyamide (e.g., nylon, aramid), polyimide, polycarbonate, and acrylic.

[0288] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, the insulators 210, 350, and the like may be insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0289] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0290] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0291] For example, the conductors 328, 330, 356, conductor 218, conductor 112, etc. can be formed of a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, and metal oxide materials formed from the above materials. High-melting-point materials such as tungsten and molybdenum that have both heat resistance and conductivity are preferably used, and tungsten is preferred. Alternatively, they are preferably formed of low-resistance conductive materials such as aluminum and copper. The use of low-resistance conductive materials can reduce wiring resistance.

[0292] <<Wiring or plug in a layer provided with an oxide semiconductor>> When an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0293] 14, for example, an insulator 276 may be provided between the insulator 224 containing excess oxygen and the conductor 246. By providing the insulator 276 in contact with the insulator 222 and the insulator 274, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties. Furthermore, the insulator 276 is preferably also in contact with a portion of the insulator 280. By extending the insulator 276 to the insulator 280, the diffusion of oxygen and impurities can be further suppressed.

[0294] That is, the insulator 276 can prevent excess oxygen in the insulator 224 from being absorbed by the conductor 246. Furthermore, the insulator 276 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 246.

[0295] The insulator 276 may be made of an insulating material that has the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide or hafnium oxide may be used. Other examples include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0296] The above is a description of the configuration example. By using this configuration, in a semiconductor device using a transistor including an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Furthermore, a transistor including an oxide semiconductor with high on-state current can be provided. Furthermore, a transistor including an oxide semiconductor with low off-state current can be provided. Furthermore, a semiconductor device with reduced power consumption can be provided.

[0297] [Storage device 2] An example of a memory device using a semiconductor device according to one embodiment of the present invention is illustrated in Fig. 15. The memory device illustrated in Fig. 15 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 shown in Fig. 14.

[0298] The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 is connected to the second gate of the transistor 200. In this configuration, when a negative potential is maintained at the second gate of the transistor 200, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source of the transistor 400 are 0 V. Because the drain current of the transistor 400 is very small when the second gate voltage and the first gate voltage are 0 V, the negative potential of the second gate of the transistor 200 can be maintained for a long time without supplying power to the transistors 200 and 400. This allows a memory device including the transistor 200 and 400 to retain stored content for a long time.

[0299] 15 , the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the backgate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and the wiring 1005 is electrically connected to the other electrode of the capacitor 100. The wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the backgate of the transistor 400, and the wiring 1010 is electrically connected to the drain of the transistor 400. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.

[0300] 15 can be arranged in a matrix to form a memory cell array, similar to the memory device shown in FIG. 14. Note that one transistor 400 can control the second gate voltages of multiple transistors 200. Therefore, it is preferable to provide fewer transistors 400 than transistors 200.

[0301] <Transistor 400> The transistor 400 is formed in the same layer as the transistor 200 and can be fabricated in parallel. The transistor 400 includes a conductor 460 (conductor 460a and conductor 460b) functioning as a first gate electrode, a conductor 405 functioning as a second gate electrode, insulators 222, 224, and 450 functioning as gate insulators, an oxide 430c having a region where a channel is formed, a conductor 442a, an oxide 431a, and an oxide 431b functioning as one of a source and a drain, a conductor 442b, an oxide 432a, and an oxide 432b functioning as the other of a source and a drain, and a conductor 440 (conductor 440a and conductor 440b).

[0302] In the transistor 400, the conductor 405 and the conductor 205 are formed in the same layer. The oxide 431a, the oxide 432a, and the oxide 230a are formed in the same layer, and the oxide 431b, the oxide 432b, and the oxide 230b are formed in the same layer. The conductor 442 and the conductor 242 are formed in the same layer. The oxide 430c and the oxide 230c are formed in the same layer. The insulator 450 and the insulator 250 are formed in the same layer. The conductor 460 and the conductor 260 are formed in the same layer.

[0303] Note that structures formed in the same layer can be formed simultaneously. For example, oxide 430c can be formed by processing the oxide film that will become oxide 230c.

[0304] The oxide 430c functioning as an active layer of the transistor 400 has reduced oxygen vacancies and reduced impurities such as water and hydrogen, similar to the oxide 230c, etc. As a result, the threshold voltage of the transistor 400 can be increased, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be made very small.

[0305] <<Dicing line>> The following describes dicing lines (sometimes called scribe lines, dividing lines, or cutting lines) that are provided when dividing a large-area substrate into individual semiconductor elements to extract multiple semiconductor devices in chip form. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (divide) the multiple semiconductor devices.

[0306] 15, for example, it is preferable to design the area where the insulator 254 and the insulator 222 contact each other to be a dicing line. That is, openings are provided in the insulator 224 near areas that will become dicing lines provided on the outer edges of the memory cell having multiple transistors 200 and the transistor 400. Furthermore, the insulator 254 is provided so as to cover the side surfaces of the insulator 224.

[0307] That is, the insulators 222 and 254 are in contact with each other through the openings formed in the insulator 224. For example, the insulators 222 and 254 may be formed using the same material and the same method. By forming the insulators 222 and 254 using the same material and the same method, adhesion can be improved. For example, it is preferable to use aluminum oxide.

[0308] With this structure, the insulator 224, the transistor 200, and the transistor 400 can be enclosed by the insulator 222 and the insulator 254. The insulator 222 and the insulator 254 have a function of suppressing diffusion of oxygen, hydrogen, and water. Therefore, even when the substrate is divided into multiple chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as water and hydrogen can be prevented from entering from the side surface of the divided substrate and diffusing into the transistor 200 and the transistor 400.

[0309] Furthermore, this structure can prevent excess oxygen in the insulator 224 from diffusing to the outside of the insulator 254 and the insulator 222. Therefore, the excess oxygen in the insulator 224 is efficiently supplied to the oxide in which a channel is formed in the transistor 200 or the transistor 400. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200 or the transistor 400. This allows the oxide in which a channel is formed in the transistor 200 or the transistor 400 to be an oxide semiconductor with a low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 or the transistor 400 can be suppressed and reliability can be improved.

[0310] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes and examples.

[0311] (Embodiment 3) In this embodiment, a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a memory device including a capacitor (hereinafter also referred to as an OS memory device) according to one embodiment of the present invention will be described with reference to FIGS. 16 and 17 . The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. The off-state current of the OS transistor is extremely small, so the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0312] <Storage device configuration example> 16A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0313] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is connected to a memory cell in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 also includes, for example, a row decoder, a word line driver circuit, etc., and can select a row to access.

[0314] The memory device 1400 is supplied with a low power supply voltage (VSS) from the outside as power supply voltages, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470. Control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0315] The control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0316] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0317] 16A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but this embodiment is not limited to this. For example, as shown in FIG. 16B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0318] FIG. 17 illustrates an example of the configuration of a memory cell that can be applied to the above-described memory cell MC.

[0319] [DOSRAM] 17A to 17C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be referred to as a DOSRAM. The memory cell 1471 shown in FIG. 17A includes a transistor M1 and a capacitor CA. The transistor M1 includes a gate (sometimes referred to as a top gate) and a back gate.

[0320] The first terminal of the transistor M1 is connected to the first terminal of the capacitance element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, the back gate of the transistor M1 is connected to the wiring BGL, and the second terminal of the capacitance element CA is connected to the wiring CAL.

[0321] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0322] The memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may have a configuration in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 17B. Furthermore, for example, the memory cell MC may be a memory cell including a single-gate transistor, that is, a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 17C.

[0323] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Furthermore, the refresh operation of the memory cell can be made unnecessary. Furthermore, because the leakage current is very small, multilevel data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0324] Furthermore, in the DOSRAM, if the sense amplifier is configured to overlap under the memory cell array 1470 as described above, the bit line can be shortened, which reduces the bit line capacitance and the storage capacitance of the memory cell.

[0325] [NOSRAM] 17D to 17G show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor. The memory cell 1474 shown in FIG. 17D includes a transistor M2, a transistor M3, and a capacitor CB. The transistor M2 has a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and the like, a memory device including a gain cell type memory cell using an OS transistor as the transistor M2 may be referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0326] The first terminal of transistor M2 is connected to the first terminal of capacitor CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitor CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitor CB.

[0327] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0328] Furthermore, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may have a configuration in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 17(E). For example, the memory cell MC may be a memory cell including a single-gate transistor, i.e., a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 17(F). For example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 17(G).

[0329] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor CB can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be significantly reduced. This allows written data to be held by the transistor M2 for a long time, thereby reducing the frequency of refreshing the memory cell. Furthermore, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0330] Note that the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor). The conductivity type of the Si transistor may be either an n-channel type or a p-channel type. The Si transistor may have higher field-effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. Furthermore, by using a Si transistor as the transistor M3, the transistor M2 can be stacked on top of the transistor M3, thereby reducing the area occupied by the memory cell and achieving higher integration of the memory device.

[0331] Furthermore, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0332] FIG. 17H shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1478 shown in FIG. 17H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. The GNDL wiring is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to wirings RBL and WBL instead of wiring BIL.

[0333] The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not necessarily have a back gate.

[0334] Note that the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, or the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured as a circuit using only n-channel transistors.

[0335] When the semiconductor device described in the above embodiment is used in the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors M5 and M6 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made extremely small.

[0336] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.

[0337] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes, examples, and the like.

[0338] (Fourth embodiment) In this embodiment, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown with reference to Fig. 18. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0339] As shown in Figure 18(A), the chip 1200 has a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog calculation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.

[0340] 18(B), the chip 1200 is provided with bumps (not shown), which are connected to a first surface of a printed circuit board (PCB) 1201. In addition, a plurality of bumps 1202 are provided on the backside of the first surface of the PCB 1201, which is connected to a motherboard 1203.

[0341] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM described in the previous embodiment may be used as the DRAM 1221. Also, for example, the NOSRAM described in the previous embodiment may be used as the flash memory 1222.

[0342] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the NOSRAM or DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing and multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0343] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of the calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212.

[0344] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0345] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0346] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0347] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0348] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0349] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204.

[0350] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a small size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0351] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes, examples, and the like.

[0352] (Embodiment 5) In this embodiment, an application example of a storage device using the semiconductor device described in the previous embodiment will be described. The semiconductor device described in the previous embodiment can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), recording / playback devices, navigation systems, etc.). Note that the term "computer" used here includes tablet computers, notebook computers, desktop computers, and large-scale computers such as server systems. Alternatively, the semiconductor device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). FIG. 19 schematically illustrates several configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memories.

[0353] 19A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1105 or the like.

[0354] FIG. 19B is a schematic diagram of the appearance of an SD card, and FIG. 19C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing a memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Furthermore, a wireless chip having a wireless communication function may be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1114 or the like.

[0355] FIG. 19(D) is a schematic diagram of the appearance of an SSD, and FIG. 19(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a board 1153. The board 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the board 1153. The memory chip 1155 is a work memory for the controller chip 1156, and may be, for example, a DOSRAM chip. The capacity of the SSD 1150 can be increased by providing a memory chip 1154 on the back side of the board 1153. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1154 or the like.

[0356] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes, examples, and the like.

[0357] (Embodiment 6) A semiconductor device according to one embodiment of the present invention can be used in a processor such as a CPU or a GPU, or a chip. Figure 20 illustrates a specific example of an electronic device including a processor such as a CPU or a GPU, or a chip according to one embodiment of the present invention.

[0358] <Electronic devices and systems> The GPU or chip according to one embodiment of the present invention can be mounted in various electronic devices. Examples of such electronic devices include electronic devices with relatively large screens, such as televisions, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices. Furthermore, by providing an integrated circuit or chip according to one embodiment of the present invention in an electronic device, it is possible to provide the electronic device with artificial intelligence.

[0359] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0360] An electronic device according to one embodiment of the present invention may have a sensor (including a function for measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0361] An electronic device according to one embodiment of the present invention can have various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, etc. Figure 20 shows an example of an electronic device.

[0362] [mobile phone] 20A illustrates a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 includes a housing 5510 and a display unit 5511. The display unit 5511 is provided with a touch panel and the housing 5510 is provided with buttons as input interfaces.

[0363] By applying the chip of one embodiment of the present invention, the information terminal 5500 can execute applications using artificial intelligence. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5511, an application that recognizes characters, figures, and the like input by a user to a touch panel provided in the display unit 5511 and displays them on the display unit 5511, and an application that performs biometric authentication using fingerprints, voiceprints, etc.

[0364] [Information terminal] 20B shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0365] The desktop information terminal 5300 can execute applications using artificial intelligence by applying a chip of one embodiment of the present invention, similar to the above-described information terminal 5500. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Furthermore, new artificial intelligence can be developed by using the desktop information terminal 5300.

[0366] In the above description, a smartphone and a desktop information terminal are shown as examples of electronic devices in Figures 20(A) and 20(B), but information terminals other than smartphones and desktop information terminals can also be applied. Examples of information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0367] [electric appliances] 20C shows an example of an electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0368] The electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 and their expiration dates, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800, and the like.

[0369] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0370] [Game consoles] 20D shows a portable game machine 5200, which is an example of a game machine. The portable game machine includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0371] A low-power portable game console 5200 can be realized by applying the GPU or chip of one embodiment of the present invention to the portable game console 5200. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0372] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5200, the portable game console 5200 can have artificial intelligence.

[0373] Normally, the progression of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the game's program, but by applying artificial intelligence to the portable game console 5200, it becomes possible to express things that are not limited to the game's program. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of characters appearing in the game.

[0374] Furthermore, when playing a game requiring multiple players on the portable game console 5200, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent a game player based on artificial intelligence.

[0375] 20(D) illustrates a portable game machine as an example of a game machine, but game machines to which the GPU or chip of one embodiment of the present invention is applied are not limited to this. Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include home-use stationary game machines, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), and pitching machines for batting practice installed in sports facilities.

[0376] [Moving object] The GPU or chip according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the area around the driver's seat of an automobile.

[0377] Fig. 20(E1) shows an automobile 5700 as an example of a moving body, and Fig. 20(E2) shows the area around the windshield inside the automobile. Fig. 20(E2) shows display panels 5701, 5702, and 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0378] The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, air conditioning settings, etc. The display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, allowing for improved design. The display panels 5701 to 5703 can also be used as lighting devices.

[0379] The display panel 5704 can complement the view (blind spot) blocked by the pillar by displaying an image from an imaging device (not shown) provided in the automobile 5700. That is, by displaying an image from an imaging device provided outside the automobile 5700, the blind spot can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0380] The GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, and therefore, for example, the chip can be used in an autonomous driving system for an automobile 5700. The chip can also be used in a system that provides road guidance, hazard prediction, etc. The display panels 5701 to 5704 may be configured to display information such as road guidance and hazard prediction.

[0381] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies can include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets), and the chip of one embodiment of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0382] [Broadcasting System] The GPU or chip according to one aspect of the present invention can be applied to a broadcasting system.

[0383] Fig. 20(F) shows a schematic diagram of data transmission in a broadcasting system. Specifically, Fig. 20(F) shows the path that radio waves (broadcast signals) transmitted from a broadcasting station 5680 take to reach a television receiver (TV) 5600 in each home. The TV 5600 includes a receiving device (not shown), and the broadcast signal received by an antenna 5650 is transmitted to the TV 5600 via the receiving device.

[0384] In FIG. 20(F), the antenna 5650 is illustrated as a UHF (Ultra High Frequency) antenna, but the antenna 5650 can also be a BS·110° CS antenna, a CS antenna, or the like.

[0385] Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and radio tower 5670 amplifies received radio waves 5675A and transmits radio waves 5675B. Each home can watch terrestrial TV broadcasting on TV 5600 by receiving radio waves 5675B with antenna 5650. Note that the broadcasting system is not limited to terrestrial broadcasting shown in Fig. 20(F), and may also be satellite broadcasting using an artificial satellite, data broadcasting via optical fiber lines, or the like.

[0386] The above-described broadcasting system may be a broadcasting system using artificial intelligence by applying a chip according to one embodiment of the present invention. When broadcast data is transmitted from a broadcasting station 5680 to a TV 5600 in each home, the broadcast data is compressed by an encoder. When the antenna 5650 receives the broadcast data, the broadcast data is restored by a decoder in a receiving device included in the TV 5600. By using artificial intelligence, for example, it is possible to recognize a display pattern included in a display image in motion compensation prediction, which is one of the compression methods used by the encoder. It is also possible to perform intra-frame prediction using artificial intelligence. Furthermore, for example, when low-resolution broadcast data is received and displayed on a high-resolution TV 5600, image interpolation processing such as upconversion can be performed when the decoder restores the broadcast data.

[0387] The above-described broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting, which involves an increasing amount of broadcast data.

[0388] Furthermore, as an application of artificial intelligence on the TV 5600 side, for example, a recording device with artificial intelligence may be provided in the TV 5600. With such a configuration, the recording device can be made to learn user preferences using artificial intelligence, thereby automatically recording programs that match the user's preferences.

[0389] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof described in this embodiment can be appropriately combined with descriptions of other electronic devices.

[0390] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes, examples, and the like. [Example]

[0391] In this example, a transistor 200 (referred to as Sample 1B) according to one embodiment of the present invention was fabricated, and the shape of Sample 1B was evaluated using a scanning transmission electron microscope (STEM) and energy dispersive X-ray spectroscopy (EDX).

[0392] A method for manufacturing Sample 1B will be described below. Note that for details of the method for manufacturing Sample 1B, the descriptions with reference to FIGS. 6 to 13 can be referred to.

[0393] A tungsten film was used as the conductor 205. A silicon oxynitride film was used as the insulator 216. An aluminum oxide film and a silicon oxynitride film were used as the insulator 222 and the insulator 224, which function as the second gate insulator, respectively.

[0394] An In-Ga-Zn oxide film was formed by sputtering as the first oxide that would become oxide 230a. The first oxide was formed using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn=1:3:4. Subsequently, an In-Ga-Zn oxide film was formed on the first oxide by sputtering as the second oxide that would become oxide 230b. The second oxide was formed using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1.

[0395] Next, a heat treatment was carried out in an atmosphere containing nitrogen at a temperature of 400° C. for 1 hour, and then in an atmosphere containing oxygen at a temperature of 400° C. for 1 hour.

[0396] Next, a tantalum nitride film was formed on the second oxide as a conductor to become the conductor 242. Thereafter, the tantalum nitride film, the second oxide, and the first oxide were processed to form the conductive layer 242B, the oxide 230b, and the oxide 230a.

[0397] Next, an aluminum oxide film was formed over the conductive layer 242B as the insulator 254. Furthermore, a silicon oxynitride film was formed as the insulator 280. After that, the silicon oxynitride film, the aluminum oxide film, and the conductive layer 242B were processed by lithography to form an opening and a conductor 242.

[0398] Next, in the opening, an In-Ga-Zn oxide film was formed as a third oxide layer, which would become the lower layer of oxide 230c, by sputtering using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Subsequently, an In-Ga-Zn oxide film was formed as a fourth oxide layer, which would become the upper layer of oxide 230c, by sputtering using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0399] Next, a silicon oxynitride film was formed as an insulating film to be the insulator 250 .

[0400] Next, a titanium nitride film was formed on the insulating film that would become the insulator 250 as a conductive film that would become the conductor 260a. Subsequently, a tungsten film was formed as a conductive film that would become the conductor 260b. The titanium nitride film and the tungsten film were formed by successive film formation. The tungsten film, the titanium nitride film, the insulating film that would become the insulator 250, the fourth oxide, and the third oxide were then processed to form the conductor 260b, the conductor 260a, the insulator 250, and the oxide 230c.

[0401] Next, an aluminum oxide film was formed as the insulator 274, and a silicon oxynitride film was formed as the insulator 281.

[0402] Through the above steps, Sample 1B was fabricated.

[0403] <Cross-section observation and elemental analysis of sample 1B> The results of cross-sectional observation and elemental analysis of sample 1B are described below. The device used for cross-sectional observation and EDX measurement was a Hitachi High-Technologies HD-2300, and the device used for elemental analysis was an EDX Si(Li) detector manufactured by EDAX. Figure 21(A) is a cross-sectional STEM image of sample 1B at a location between the dashed-dotted line L1-L2 and the dashed-dotted line L3-L4 shown in Figure 1. Figure 21(B) is an EDX map of the Al-K line. The region from which the EDX map was obtained is the same region from which the cross-sectional STEM image shown in Figure 21(A) was obtained.

[0404] 21(A) and 21(B) show that the openings formed in the insulator 280 and the like have a tapered shape. It can also be seen that the surfaces parallel to the side edges of the insulator 254 in the region 256a that contact the side surfaces of the conductor 242a, the oxide 230b, and the oxide 230a are approximately aligned with the side surfaces of the conductor 242a facing each other in the conductor 242b. It can also be seen that the surfaces parallel to the side edges of the insulator 254 in the region 256b that contact the side surfaces of the conductor 242b, the oxide 230b, and the oxide 230a are approximately aligned with the side surfaces of the conductor 242b facing each other in the conductor 242a.

[0405] <Plane observation and elemental analysis of sample 1B> Next, the results of planar observation and elemental analysis of sample 1B will be described. Prior to planar observation and elemental analysis of sample 1B, sample 1B was processed. Specifically, the top surface of sample 1B was planarized until the top surfaces of conductors 242a and 242b were exposed, and the bottom surface of sample 1B was planarized until conductor 205 could be removed.

[0406] Planar observation and elemental analysis were performed on the processed sample 1B. The above-mentioned equipment was used for planar observation and EDX measurement. Figure 22(A) is a planar STEM image of sample 1B. Figure 22(B) is an EDX map of the Al-K line. The area from which the EDX map was obtained is the same area from which the planar STEM image was obtained.

[0407] 22(A) and 22(B) show that the distance corresponding to the distance LE2 shown in Fig. 3 is shorter than the distance corresponding to the distance LE1 shown in Fig. 3. It can also be seen that the side ends of the insulators 254 facing each other have curved shapes.

[0408] This embodiment can be implemented by being appropriately combined with the structures described in other embodiment modes. [Explanation of symbols]

[0409] BGE: conductor, BGI1: insulator, BGI2: insulator, CAP: insulator, DE: conductor, LE1: distance, LE2: distance, LG1: length, LG2: length, SE: conductor, SEM1: semiconductor, SEM2: semiconductor, SEM3: semiconductor, TGE: conductor, TGI: insulator, 100: capacitor, 110: conductor, 112: conductor, 120: conductor, 130: insulator, 150: insulator, 200: transistor, 205: conductor, 210: insulator, 212: insulator, 214: insulator, 216: insulator, 218: conductor, 220: insulator, 222: insulator, 224: insulator , 230: oxide, 230a: oxide, 230A: oxide film, 230b: oxide, 230B: oxide film, 230c: oxide, 230C: oxide film, 231: region, 231a: region, 231b: region, 234: region, 239: region, 240: conductor, 240a: conductor, 240b: conductor, 241: insulator, 241a: insulator, 241b: insulator, 242: conductor, 242a: conductor, 242A: conductive film, 242b: conductor, 242B: conductive layer, 243: region, 243a: region, 243b: region, 244: angle, 244a: angle, 244b: angle, 246: conductor, 248: angle, 250: insulator, 250A: insulating film, 254: insulator, 254A: insulating film, 256a: region, 256b: region, 258: angle, 258a: angle, 258b: angle, 260: conductor, 260a: conductor, 260A: conductive film, 260B: conductive film, 260b: conductor, 274: insulator, 276: insulator, 280: insulator, 281: insulator, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 400: Transistor, 405: Conductor, 430c: Oxide, 431a: Oxide, 431b: Oxide, 432a: Oxide, 432b: Oxide, 440: Conductor, 440a: Conductor, 440b: Conductor, 442: Conductor, 442a: Conductor, 442b: Conductor, 450: Insulator, 460: Conductor, 460a: Conductor, 460b: Conductor, 1001: Wiring, 1002: Wiring, 1003: Wiring, 1004: Wiring, 1005: Wiring, 1006: Wiring,1007: Wiring, 1008: Wiring, 1009: Wiring, 1010: Wiring, 1100: USB memory, 1101: Housing, 1102: Cap, 1103: USB connector, 1104: Board, 1105: Memory chip, 1106: Controller chip, 1110: SD card, 1111: Housing, 1112: Connector, 1113: Board, 1114: Memory chip, 1115: Controller chip, 1150: SSD, 1151: Housing, 1152: Connector, 1153: Board board, 1154: memory chip, 1155: memory chip, 1156: controller chip, 1200: chip, 1201: PCB, 1202: bump, 1203: motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: analog calculation unit, 1214: memory controller, 1215: interface, 1216: network circuit, 1221: DRAM, 1222: flash memory, 1400: storage device, 1411: peripherals Edge circuit, 1420: row circuit, 1430: column circuit, 1440: output circuit, 1460: control logic circuit, 1470: memory cell array, 1471: memory cell, 1472: memory cell, 1473: memory cell, 1474: memory cell, 1475: memory cell, 1476: memory cell, 1477: memory cell, 1478: memory cell, 5200: portable game console, 5201: housing, 5202: display unit, 5203: button, 5300: desktop information terminal, 5301: main body, 5302: display, 5303: keyboard, 5500: information terminal, 5510: housing, 5511: display unit, 5600: TV, 5650: antenna, 5670: radio tower, 5675A: radio waves, 5675B: radio waves, 5680: broadcasting station, 5700: automobile, 5701: display panel, 5702: display panel, 5703: display panel, 5704: display panel, 5800: electric refrigerator-freezer, 5801: housing, 5802: refrigerator door, 5803: freezer door,

Claims

1. A semiconductor device having a transistor, The transistor is a first insulator; and a first oxide on the first insulator; a first conductor and a second conductor on the first oxide; a second insulator on the first oxide; a third conductor on the second insulator; and a fourth conductor on the third conductor; and a third insulator on the first conductor and the second conductor; a fourth insulator on the third insulator; the third insulator and the fourth insulator are provided with first openings that reach the first oxide; the second insulator is disposed so as to cover an inner wall of the first opening; the third conductor is provided in contact with the second insulator, the fourth conductor is provided in contact with the third conductor, a fifth insulator on the third conductor, the fourth conductor, the second insulator, and the fourth insulator; a sixth insulator on the fifth insulator; a second opening reaching the first conductor and a third opening reaching the second conductor are provided in the third insulator, the fourth insulator, the fifth insulator, and the sixth insulator; a seventh insulator in contact with a sidewall of the second opening; an eighth insulator in contact with a sidewall of the third opening; a fifth conductor in contact with the seventh insulator and the first conductor; a sixth conductor in contact with the eighth insulator and the second conductor; a height of a bottom surface of the third conductor in a region not overlapping with the first oxide, with respect to a bottom surface of the first insulator, being lower than a height of a bottom surface of the first oxide in a channel width direction of the transistor; a length of a bottom surface of the third conductor in a region that does not overlap with the first oxide in a channel length direction of the transistor is shorter than a length of a bottom surface of the third conductor in a region that overlaps with the first oxide; When the transistor is viewed from above, a side end of the third insulator on the first conductor and a side end of the third insulator on the second conductor have a curved shape.

2. A semiconductor device having a transistor, The transistor is a first insulator; and a first oxide on the first insulator; a first conductor and a second conductor on the first oxide; a second insulator on the first oxide; a third conductor on the second insulator; and a fourth conductor on the third conductor; and a third insulator on the first conductor and the second conductor; a fourth insulator on the third insulator; the third insulator and the fourth insulator are provided with first openings that reach the first oxide; the second insulator is disposed so as to cover an inner wall of the first opening; the third conductor is provided in contact with the second insulator, the fourth conductor is provided in contact with the third conductor, a fifth insulator on the third conductor, the fourth conductor, the second insulator, and the fourth insulator; a sixth insulator on the fifth insulator; a second opening reaching the first conductor and a third opening reaching the second conductor are provided in the third insulator, the fourth insulator, the fifth insulator, and the sixth insulator; a seventh insulator in contact with a sidewall of the second opening; an eighth insulator in contact with a sidewall of the third opening; a fifth conductor in contact with the seventh insulator and the first conductor; a sixth conductor in contact with the eighth insulator and the second conductor; a length of a bottom surface of the third conductor in a region that does not overlap with the first oxide in a channel length direction of the transistor is shorter than a length of a bottom surface of the third conductor in a region that overlaps with the first oxide; an angle formed by a plane parallel to a bottom surface of the second insulator and a side surface of the first conductor facing the second conductor in the channel length direction of the transistor is smaller than 90 degrees; When the transistor is viewed from above, a side end of the third insulator on the first conductor and a side end of the third insulator on the second conductor have a curved shape.

3. A semiconductor device having a transistor, The transistor is a first insulator; and a first oxide on the first insulator; a first conductor and a second conductor on the first oxide; a second oxide on the first oxide; a second insulator on the second oxide; a third conductor on the second insulator; and a fourth conductor on the third conductor; and a third insulator on the first conductor and the second conductor; a fourth insulator on the third insulator; the third insulator and the fourth insulator are provided with first openings that reach the first oxide; the second oxide is disposed so as to cover an inner wall of the first opening; the second insulator is provided in contact with the second oxide, the third conductor is provided in contact with the second insulator, the fourth conductor is provided in contact with the third conductor, a fifth insulator on the third conductor, the fourth conductor, the second insulator, and the fourth insulator; a sixth insulator on the fifth insulator; a second opening reaching the first conductor and a third opening reaching the second conductor are provided in the third insulator, the fourth insulator, the fifth insulator, and the sixth insulator; a seventh insulator in contact with a sidewall of the second opening; an eighth insulator in contact with a sidewall of the third opening; a fifth conductor in contact with the seventh insulator and the first conductor; a sixth conductor in contact with the eighth insulator and the second conductor; a height of a bottom surface of the third conductor in a region not overlapping with the first oxide, with respect to a bottom surface of the first insulator, being lower than a height of a bottom surface of the first oxide in a channel width direction of the transistor; a length of a bottom surface of the third conductor in a region that does not overlap with the first oxide in a channel length direction of the transistor is shorter than a length of a bottom surface of the third conductor in a region that overlaps with the first oxide; When the transistor is viewed from above, a side end of the third insulator on the first conductor and a side end of the third insulator on the second conductor have a curved shape.

4. A semiconductor device having a transistor, The transistor is a first insulator; and a first oxide on the first insulator; a first conductor and a second conductor on the first oxide; a second oxide on the first oxide; a second insulator on the second oxide; a third conductor on the second insulator; and a fourth conductor on the third conductor; and a third insulator on the first conductor and the second conductor; a fourth insulator on the third insulator; the third insulator and the fourth insulator are provided with first openings that reach the first oxide; the second oxide is disposed so as to cover an inner wall of the first opening; the second insulator is provided in contact with the second oxide, the third conductor is provided in contact with the second insulator, the fourth conductor is provided in contact with the third conductor, a fifth insulator on the third conductor, the fourth conductor, the second insulator, and the fourth insulator; a sixth insulator on the fifth insulator; a second opening reaching the first conductor and a third opening reaching the second conductor are provided in the third insulator, the fourth insulator, the fifth insulator, and the sixth insulator; a seventh insulator in contact with a sidewall of the second opening; an eighth insulator in contact with a sidewall of the third opening; a fifth conductor in contact with the seventh insulator and the first conductor; a sixth conductor in contact with the eighth insulator and the second conductor; a length of a bottom surface of the third conductor in a region that does not overlap with the first oxide in a channel length direction of the transistor is shorter than a length of a bottom surface of the third conductor in a region that overlaps with the first oxide; an angle formed by a plane parallel to a bottom surface of the second insulator and a side surface of the first conductor facing the second conductor in the channel length direction of the transistor is smaller than 90 degrees; When the transistor is viewed from above, a side end of the third insulator on the first conductor and a side end of the third insulator on the second conductor have a curved shape.

5. In any one of claims 1 to 4, The semiconductor device, wherein the fourth insulator includes an oxide of aluminum.

6. In any one of claims 1 to 5, The semiconductor device, wherein the first oxide contains at least indium or zinc.

Images