Timing event detector, microelectronic circuit, and timing event detection method

Abstract

In the microelectronic circuit, a digital value (D) is temporarily stored in a register circuit 101. With respect to an allowable time limit defined by a trigger signal (CKP), the corresponding instantaneous value of the digital value (D) is stored in a differential form including an instantaneous value (A) and its complement (B). During a timing event detection window, either the stored instantaneous value (A) or its complement (B) is toggled such that the stored instantaneous value (A) is toggled only in response to observing a change in the digital value (D) in one direction, and the stored complement (B) is toggled only in response to observing a change in the digital value (D) in the opposite direction. The stored instantaneous value (A) is compared with the stored complement (B), and a timing event observed signal (TEO) is output 105 in response to the comparison indicating that the stored instantaneous value (A) and the stored complement (B) are equal.

Description

[Technical Field]

[0001] The present invention relates to the art of microelectronic circuits that include internal monitors for detecting timing events. In particular, the present invention relates to advantageous circuit element level implementations of timing event detection circuits. [Background technology]

[0002] Time borrowing in microelectronic circuits means that a circuit element can temporarily borrow time from a subsequent stage, i.e., the circuit element changes a digital value slower than expected if subsequent circuit elements in the same processing path could handle the digital value without corrupting the data being processed. Time borrowing may be combined, for example, with Advanced Voltage Scaling (AVS), whereby the occurrence of time borrowing is detected as a timing event, and an increase in the number of detected timing events increases the operating voltage, and vice versa. The number of detected timing events may also trigger other compensatory actions, typically promoting changes in the value of other operating parameters of the circuit, such as the clock frequency, or temporarily changing the clock waveform.

[0003] The processing path of a microelectronic circuit passes through logic units and register circuits, which store the output value of the previous logic unit at the rising or falling edge of a trigger signal (if the register circuit is a flip-flop) or at the high or low level of the trigger signal (if the register circuit is a latch). The trigger edge of the trigger signal or other control event defines an allowable time limit before which the digital value must appear at the data input of the register circuit for proper storage. The allowable time limit is not necessarily the exact instant of the trigger edge, but is defined in some relationship to the allowable time limit due to physical effects such as the finite speed at which voltage levels can change. Logic units may also be called elements of combinatorial logic.

[0004] A monitor circuit is used to detect timing events. It may alternatively be called a timing event detection circuit, but the term monitor circuit is shorter and more practical. A monitor circuit is typically a circuit element or function added to or associated with a register circuit and configured to generate a timing event observation (TEO) signal in response to a change in an input digital value that occurs slower than the allowable time limit. In addition to the actual monitor circuit, a microelectronic circuit must include an OR tree and / or other structure to collect, process, and analyze the TEO signal from the monitor circuit. A monitor circuit may also be used as a standalone device for other applications, such as an edge detector in a digital phase-locked loop.

[0005] The main drawbacks of supervisory circuits are that they consume circuit area and operating power. Many known supervisory circuit implementations also involve performance compromises.

[0006] Testability requirements further complicate the task of designing microelectronic circuits. The concept of DFT (Designed For Testability, or Design-For-Test) has become a de facto industry standard, defining specific procedures for testing microelectronic circuits. As an example, the register circuits contained in a microelectronic circuit could be selectively combined into a long chain that essentially acts as a shift register, into which a series of digital values ​​can be input at one end and read out at the other. Passing a known test pattern through such a chain of register circuits and checking the format of the test pattern at the output determines whether all register circuits in the chain change their state as desired or whether any register circuits are stuck at a particular value (testing for stuck-at faults). At-speed fault testing involves slowly inputting the test pattern at a slow clock speed, then applying one or more clock pulses at the full operating speed to advance the test pattern through the chain at functional logic speed by the same number of steps as the clock pulses, and finally clocking out the test pattern again at the slow clock speed. At-speed testing can provide information about register circuits that are slower than intended. If supervisory circuits and time borrowing capabilities are included, these must also be testable. Summary of the Invention [Problem to be solved by the invention]

[0007] It is an object of the present invention to provide a timing event detector, a microelectronic circuit, and a method of operating the microelectronic circuit that allows monitoring for timing events while requiring only a limited silicon area and consuming only a limited amount of power. It is a further object to enable detection of timing events in a reliable manner even at very low operating voltage levels. It is a further object to make the monitoring of timing events compliant with standard methods of DFT. [Means for solving the problem]

[0008] The objects of the present invention are achieved by using a monitoring device based on parallel one-way latches and equipping the monitoring device with a comparator which compares the outputs of such latches and can selectively freeze the result of such comparison with an external control signal.

[0009] In a first aspect, there is provided a timing event detector circuit for generating a timing event observation signal in response to a change in a digital value at an input of an associated register circuit occurring later than an allowable time limit defined by a trigger signal. The timing event detector circuit includes a data input configured to receive the digital value, a clock signal input configured to receive the trigger signal, and a timing event observation output configured to output the timing event observation signal. The timing event detector circuit is configured to store, with respect to the allowable time limit, a corresponding instantaneous value of the digital value in a differential form including the instantaneous value and its complement. The timing event detector circuit is configured to toggle one of the stored instantaneous values ​​or its complement in response to an observed change in the digital value during a timing event detection window following the allowable time limit, such that each of the stored instantaneous value or its complement is toggled only in response to an observed change in the digital value in one direction. The timing event detection circuit is configured to compare the stored instantaneous value with its stored complement value during the timing event detection window, and output the timing event observation signal in response to the comparison indicating that the stored instantaneous value and its stored complement value are equal.

[0010] In a second aspect, there is provided a timing event detection circuit for generating a timing event observation signal in response to a change in a digital value at an input of an associated register circuit occurring later than an allowable time limit defined by a trigger signal. The timing event detection circuit includes a data input configured to receive the digital value, a clock signal input configured to receive the trigger signal, and a timing event observation output configured to output the timing event observation signal. The timing event detection circuit is configured to store, with respect to the allowable time limit, a corresponding instantaneous value of the digital value in a parallel double form including two copies of the instantaneous value. The timing event detection circuit is configured to toggle one of the stored copies of the instantaneous value in response to an observed change in the digital value during a timing event detection window following the allowable time limit, such that a first copy is toggled only in response to an observed change in the digital value in one direction and a second copy is toggled only in response to an observed change in the digital value in the opposite direction. The timing event detection circuit is configured to compare stored copies of the instantaneous values ​​during the timing event detection window and output the timing event observed signal in response to the comparison indicating that the stored copies of the instantaneous values ​​become unequal.

[0011] In one embodiment, the timing event detection circuit includes a first unidirectional latch circuit and a second unidirectional latch circuit, each having a respective latch data input coupled to the data input, a respective output, and a respective latch clock input coupled to the clock signal input. This type of unidirectional latch circuit is a circuit element configured to store its input data at the start of an enable pulse of the trigger signal and to toggle its output only if the value of its input data changes in a predetermined direction during the enable pulse of the trigger signal. This has the advantage of providing a particularly simple implementation with only a limited number of transistors.

[0012] In one embodiment, both the first one-way latch circuit and the second one-way latch circuit are configured to toggle their outputs only when the value of the corresponding input data changes in the same direction for both of the one-way latch circuits, and the timing event detection circuit includes an inverter between the data input and one of the first one-way latch circuit and the second one-way latch circuit, which stores the corresponding instantaneous value of the digital value in the differential form comprising the instantaneous value in one one-way latch circuit and the complementary value in the other one-way latch circuit, with the advantage that identical circuit elements can be used as both of the two one-way latch circuits, simplifying the design.

[0013] In one embodiment, storing the corresponding instantaneous value of the digital value in a differential form comprising the instantaneous value and its complement is implemented in voltage-mode CMOS logic, with the advantage that floating nodes and other drawbacks of current-mode logic are avoided.

[0014] In one embodiment, each of the first one-way latch circuit and the second one-way latch circuit includes a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, respectively, wherein the first transistor, the fourth transistor, the fifth transistor, and the seventh transistor are PMOS transistors, and the second transistor, the sixth transistor, and the eighth transistor are NMOS transistors; the timing event detection circuit includes an upper voltage rail, a lower voltage rail, and an NMOS type enabler transistor whose source is coupled to the lower voltage rail and whose gate is coupled to the clock signal input; In each of the first one-way latch circuit and the second one-way latch circuit, the source of the first transistor is coupled to the upper voltage rail; the drain of the first transistor is coupled to the source of the fourth transistor; the drain of the fourth transistor is coupled to the drain of the second transistor; the source of the second transistor is coupled to the drain of the enabler transistor; the gate of the first transistor and the gate of the second transistor are coupled to each other and form a latch data input of each of the unidirectional latch circuits; the source of the fifth transistor is coupled to the upper voltage rail; the drain of the fifth transistor is coupled to the drain of the sixth transistor; the source of the sixth transistor is coupled to the drain of the enabler transistor; the gate of the fifth transistor and the gate of the third transistor are coupled to each other and form a latch clock input of each of the unidirectional latch circuits; the gate of the fourth transistor and the gate of the sixth transistor are coupled to each other; the source of the seventh transistor is coupled to the upper voltage rail; the drain of the seventh transistor is coupled to the drain of the eighth transistor; the source of the eighth transistor is coupled to the lower voltage rail; the gate of the seventh transistor and the gate of the eighth transistor are coupled to each other; a point between the drain of the seventh transistor and the drain of the eighth transistor is coupled to the gate of the fourth transistor and to the gate of the sixth transistor; The output terminal of each of the one-way latch circuits is formed by coupling the gate of the seventh transistor and the gate of the eighth transistor, the drain of the fifth transistor and the drain of the fourth transistor, and the drain of the sixth transistor and the drain of the second transistor.

[0015] This has the advantage that the timing event detection circuitry can be implemented with a relatively small number of transistors, saving silicon area and lowering power consumption.

[0016] In one embodiment, the timing event detection circuit includes a control signal input and is configured to respond to a first control signal value at the control signal input by resetting the timing event observation signal at a predetermined instant during each pulse cycle of the trigger signal, and to respond to a second control signal value at the control signal input by maintaining the timing event observation signal for a period during which a second control signal value appears at the control signal input, with the advantage that the timing event detection circuit can be DFT-based.

[0017] In one embodiment, the timing event detection circuit is configured to reset the stored value to a fixed default value at the end of a detection window, the end of the detection window being defined with respect to the trigger signal and occurring after the allowed time limit, with the advantage that a monitoring cycle can be easily restarted at each instant a timing event may occur.

[0018] In a third aspect, there is provided a microelectronic circuit comprising a processing path including a logic unit and a register circuit, the register circuit configured to temporarily store an output value of the logic unit in synchronization with a trigger signal, the microelectronic circuit including at least one timing event detection circuit of the kind described above, the timing event detection circuit being associated with one of the register circuits and configured to generate a timing event observation signal in response to a change in the digital value at the input of the associated register circuit occurring later than an allowed time limit defined by the trigger signal.

[0019] In a fourth aspect, there is provided a method of operating a microelectronic circuit, said method comprising: - temporarily storing the digital value in a register circuit in synchronization with a trigger signal; - storing the corresponding instantaneous value of said digital value in a differential form comprising said instantaneous value and its complement with respect to an allowable time limit defined by said trigger signal; toggling either the stored instantaneous value or its complement such that, during a timing event detection window following the allowable time limit, each of the stored instantaneous value or its complement is toggled only in response to observing a change in one direction of each of the digital values; - comparing said stored instantaneous value with its stored complement value during said timing event detection window; - outputting a timing event observation signal in response to said comparison indicating that said stored instantaneous value and its stored complement value are equal.

[0020] In a fifth aspect, there is provided a method of operating a microelectronic circuit, said method comprising: - temporarily storing the digital value in a register circuit in synchronization with a trigger signal; - storing in two copies the corresponding instantaneous values ​​of said digital values ​​with respect to the allowable time limit defined by said trigger signal; toggling one of the two copies such that, during a timing event detection window following the allowable time limit, each copy is toggled only in response to observing a change in a respective one direction of the digital value; comparing the two copies during the timing event detection window; - outputting a timing event observed signal in response to said comparison indicating that said two copies are different.

[0021] The accompanying drawings, which are included to provide a further understanding of the invention and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 1 shows a monitoring circuit associated with a register circuit. [Figure 2] FIG. 2 shows a monitoring circuit associated with a register circuit. [Figure 3] FIG. 3 shows a logic gate level implementation of an exemplary monitoring circuit. [Figure 4] Figure 4 shows the state diagram of the monitoring circuit. [Figure 5] FIG. 5 shows a timing diagram of the signals in the monitoring circuit. [Figure 6] FIG. 6 shows a timing diagram of the signals in the monitoring circuit. [Figure 7] Figure 7 shows a transistor-level implementation of the monitoring circuit. [Figure 8] FIG. 8 shows a prior art implementation of a monitoring circuit. [Figure 9] FIG. 9 illustrates the method. [Figure 10] FIG. 10 illustrates the method. DETAILED DESCRIPTION OF THE INVENTION

[0023] The following describes microelectronic circuits and methods for their design and operation. A typical microelectronic circuit contains multiple logic units and register circuits arranged in multiple processing paths. A processing path is a series of circuit elements through which digital data passes, where it is processed in the logic units and temporarily stored in register circuits located between successive logic units in the processing path. Software executed by the microelectronic circuit defines which processing path to use at any given time and how.

[0024] FIG. 1 shows a register circuit 101 and an associated monitor circuit 102. The data input of the register circuit 101 is marked with the letter D, and the data output of the register circuit 101 is marked with the letter Q. The register circuit 101 and its associated monitor circuit 102 may be part of a processing path in a microelectronic circuit, whereby a previous element in the processing path generates a digital value that appears at the data input D, and a subsequent element in the processing path receives a digital value that appears at the data output Q. The temporary storage of data in the register circuit 101 is performed synchronously with a clock pulse signal CKP, which may be called a clock signal for short. The clock signal may be called a trigger signal, as it is said to trigger the temporary storage of data. The monitor circuit 102 may alternatively be called a timing event detector circuit.

[0025] To ensure correct operation of the microelectronic circuit, any change in the digital value temporarily stored in register circuit 101 must occur before a respective allowable time limit defined by clock signal CKP (or, more generally, by an appropriate trigger signal). For example, although it is common to think of rising and / or falling edges of clock signal CKP as allowable time limits, the actual allowable time limit may not coincide exactly with such edges, for example, due to the finite time it takes for a semiconductor switch to change from a non-conductive state to a conductive state or vice versa. For the purposes of this discussion, it is sufficient to assume that a known relationship exists between the type of trigger signal and the occurrence of the allowable time limit.

[0026] The purpose of the monitoring circuit 102 is to generate a timing event observation signal TEO in response to a change in the digital value at the input D of the associated register circuit 101 occurring later than the allowed time limit defined by a trigger signal (clock signal) CKP. To this end, the monitoring circuit 102 comprises a data input 103 arranged to receive the digital value D, a clock signal input 104 arranged to receive the trigger signal CKP, and a timing event observation output 105 arranged to output the timing event observation signal TEO.

[0027] The monitoring circuit 102 is configured to store the corresponding instantaneous value of the digital value D in a differential form with respect to an allowable time limit. This means that the monitoring circuit 102 is configured to store both the instantaneous value of the digital value D and its complement. On the side of the monitoring circuit 102, the actual instantaneous value is marked as D and the complement is marked as ~D (signature D). To generate the complement ~D, the monitoring circuit 102 of FIG. 1 is schematically shown to include an inverter 106 coupled to the data input 103.

[0028] The two parallel circuit elements 107 and 108 used to temporarily store a data value D and its complement value ∼D are referred to in FIG. 1 as unidirectional latch circuits. For purposes of this description, a unidirectional latch circuit is a circuit element configured to store its input data at the beginning of an enabling pulse of a trigger signal and to toggle its output only if the value of its input data changes in a predetermined direction during the enabling pulse of the trigger signal. The output signals from the unidirectional latch circuits 107 and 108 are marked A and B, respectively. For simplicity, we may assume here that A and B are directly the digital values ​​last stored in the respective unidirectional latch circuits 107 and 108.

[0029] In the exemplary embodiment of FIG. 1, the clock signal CKP acts as a trigger signal for both the unidirectional latch circuits 107 and 108. As an example, assume that the above-mentioned type of enable pulse is an active pulse of the clock signal CKP (i.e., CKP=1). Further, assume that the unidirectional latch circuits 107 and 108 only respond to a 0->1 transition of their input data (i.e., they are unidirectional in the rising direction). If the digital value D is 0 at the rising edge of the clock signal CKP, the first unidirectional latch circuit 107 stores D=0, and the second unidirectional latch circuit 108 stores D=1. The stored values ​​are visible at their outputs, i.e., A=0 and B=1. Now, when the digital value D changes from 0 to 1 while the clock signal CKP remains high, the upper unidirectional latch circuit 107 toggles its stored value to detect the 0->1 transition of its input data. Conversely, the lower one-way latch circuit 108 does not toggle its stored value because it detects a 1 to 0 transition of its input data, so that after the 0 to 1 transition of the digital value D that occurs during the enable pulse of the clock signal CKP, the outputs of the one-way latch circuits 107 and 108 are A=1 and B=1.

[0030] As another example, all other assumptions above can be maintained except that digital value D is assumed to be 1 at the rising edge of clock signal CKP and to fall to 0 during the active clock pulse. Thus, first one-way latch circuit 107 initially stores D=1, and second one-way latch circuit 108 stores D=0. The stored values ​​are again visible at their outputs, i.e., A=1 and B=0. When digital value D changes from 1 to 0 while clock signal CKP remains high, upper one-way latch circuit 107 does not toggle its stored value because it detects a 1->0 change in its input data. Lower one-way latch circuit 108 detects a 0->1 change in its input data and therefore toggles its stored value. As a result, after the 1->0 change in digital value D that occurs during the enable pulse of clock signal CKP, the outputs of one-way latch circuits 107 and 108 are again A=1 and B=1.

[0031] In summary, it can be said that the monitoring circuit 102 is configured to toggle one of the stored instantaneous values ​​or its stored complements in response to an observed change in the digital value D during a timing event detection window following an allowable time limit. The toggling is conditional, such that during the timing event detection window, each of the stored instantaneous values ​​or its stored complements is toggled only in response to observing a change in the digital value D in one respective direction, i.e., one of the stored values ​​is toggled if the digital value D changes in a first direction and the other of the stored values ​​is toggled if the digital value changes in a second, opposite direction.

[0032] Comparator 109 in the monitoring circuit represents the ability to compare a stored instantaneous value with its stored complement during a timing event detection window. As explained above, one of the instantaneous value and its complement may be toggled during the timing event detection window if there is a corresponding change in digital value D during the timing event detection window. Output TEO is from comparator 109, which generates a timing event observed signal in response to a comparison indicating that the stored instantaneous value and its stored complement are equal.

[0033] The operation of the monitoring circuit 102 follows essentially the same lines in another example in which the one-way latch circuits 107 and 108 respond only to 1->0 transitions in their input data, i.e., they are unidirectional in the falling direction. In this case, if the digital value D is 0 at the rising edge of the clock signal CKP, the first one-way latch circuit 107 again stores D=0, and the second one-way latch circuit 108 stores D=1, so initially A=0 and B=1. Now, if the digital value D changes from 0 to 1 while the clock signal CKP remains high, the upper one-way latch circuit 107 detects a 0->1 transition in its input data and therefore does not toggle its stored value. Conversely, the lower one-way latch circuit 108 detects a 1->0 transition in its input data and therefore toggles its stored value. As a result, after the 0->1 transition of digital value D that occurs during the enable pulse of clock signal CKP, the outputs of one-way latch circuits 107 and 108 are A=0 and B=0. We will now briefly show how to achieve the same result if digital value D is 1 at the rising edge of clock signal CKP and then changes to 0 during the timing event detection window.

[0034] Figure 2 shows another example that shares many features with Figure 1. However, the use of the waveform symbol (~) in the second one-way latch circuit 208 is omitted because the one-way latch circuits 207 and 208 respond to changes in their input data in different directions. There are no inverters between the data input 103 and the inputs of either one-way latch circuit 207 or 208. Thus, the monitoring circuit 202 of Figure 2 is configured to store, with respect to an allowable time limit, the corresponding instantaneous value of the digital value D in a parallel dual format including two copies of the instantaneous value, one copy in the first one-way latch circuit 207 and the other copy in the second one-way latch circuit 208.

[0035] Due to the inverse reaction capabilities of the one-way latch circuits 207 and 208, the monitoring circuit 202 is configured to toggle one of the stored copies of the instantaneous value in response to an observed change in the digital value D during a timing event detection window following an allowable time limit. The first copy stored in the first one-way latch circuit 207 is toggled only in response to an observed change in the digital value D in one direction. The second copy stored in the second one-way latch circuit 208 is toggled only in response to an observed change in the digital value in the opposite direction.

[0036] As an example, assume that the digital value D is D=0 at the rising edge of the clock signal CKP. At the beginning of the timing event detection window, this same value is stored in both one-way latch circuits 207 and 208 and appears at their outputs, i.e., A=B=0. If the first one-way latch circuit 207 responds to a 0->1 transition of its input data and one transition occurs during the timing event detection window, the result will be A=1 and B=0. If the digital value D is D=1 at the rising edge of the clock signal CKP and initially A=B=1, and then a 1->0 transition of the digital value D occurs during the timing event detection window, the result will be A=1 and B=0. Because the arrangement is symmetrical with respect to the input, it is easy to consider further examples in which the response directions of the one-way latch circuits 207 and 208 are switched.

[0037] 2, the monitoring circuit 202 is configured to compare copies of the stored instantaneous values ​​during a timing event detection window using a comparator 209. In response to a comparison indicating that the copies of the stored instantaneous values ​​become unequal, the monitoring circuit 202 is configured to output a timing event observed signal TEO.

[0038] The functionality described above may actually be implemented with circuit elements other than the one-way latch circuits 107, 108, 207 and 208, as is common in digital circuits, and after teaching the required functionality, it would be within the ability of one skilled in the art to suggest several alternative implementations that differ in, for example, the polarity of the signals, the resulting need to use circuit elements such as inverters, appropriately selected logic gates, etc.

[0039] 1 and 2 illustrate the possibility of using a trigger signal (i.e., the clock signal CKP) or some derivative thereof and a portion of the monitoring circuit that performs the comparison. This offers the advantage of, for example, ensuring strict synchronization of the comparison operation with known characteristics of the timing event detection signal. As an example, even if the copying of the digital value and temporary storage of a possible complementary value (and possible toggling depending on the selected reaction direction) in circuit elements such as the one-way latch circuits 107, 108, 207, and 208 occurs over the entire active pulse of the clock signal CKP, it may be advantageous to construct a separate, somewhat shorter clock pulse for the comparison. This allows the actual generation of the timing event observation signal to be concentrated only on a portion of the active pulse of the clock signal CKP. In other words, the actual timing event detection window can be delimited in a different way than the active pulse of the clock signal CKP.

[0040] 1 and 2 also illustrate the possibility of directing other types of control signals to the monitoring circuitry, particularly to the portion of the monitoring circuitry that performs the comparison and generates the timing event observation signal. Control signal input 110 may be used for such other types of control signals. Examples of such other types of control signals and their uses are described in more detail later in this text.

[0041] 3 shows an example of a monitoring circuit, also referred to as a timing event detection circuit, in which both a first one-way latch circuit 107 and a second one-way latch circuit 108 are configured to toggle their outputs only if the value of the corresponding input data changes in the same direction for both one-way latch circuits. The monitoring circuit of FIG. 3 includes an inverter 106 between the data input 103 and one of the first one-way latch circuit 107 and the second one-way latch circuit 108. The monitoring circuit of FIG. 3 thus implements a similar function to that described above with reference to FIG. 1, storing the instantaneous value of a digital value D in a differential form that includes the instantaneous value D itself in the first one-way latch circuit 107 and its complement value ∼D in the second one-way latch circuit 108.

[0042] The detailed structure selected for the first one-way latch circuit 107 and the second one-way latch circuit 108 is such that the input of the one-way latch circuit becomes one input of an OR gate. The output of the OR gate becomes one input of a NAND gate, the other input of which comes from the clock signal CKP. The output of the NAND gate constitutes the output of the one-way latch circuit. The other input of the OR gate is its inverted version. This type of one-way latch circuit only responds to 0->1 transitions of its input. Note that the output of this type of one-way latch circuit is actually the reciprocal of the digital value it reads at the rising edge of the clock signal CKP, but this is irrelevant for the discussion herein, since the following comparison is only sensitive to whether the two compared values ​​are the same in any case.

[0043] 4 illustrates the operation of the monitoring circuit of FIG. 3 in the form of a state diagram. Prior to the rising edge of clock pulse CKP, the circuit is in the leftmost state 401, where A=1, B=1, and TEO=0. The clock pulse (CKP) going active causes a transition to state 402 or state 403, depending on the value of digital signal D; a value D=0 (marked as ∼D) causes a transition to state 402, and a value D=1 (marked as D) causes a transition to state 403. As explained above, the particular structure selected for one-way latch circuits 107 and 108 of FIG. 3 inverts their outputs relative to their inputs, so that in state 402, A=1, B=0, and TEO=0, and in state 403, A=0, B=1, and TEO=0.

[0044] Now, when the digital value D changes while the clock signal CKP is still active, a further transition to state 404 is made. Because the upper intermediate state 402 was a result of the digital signal D=0 at the start of an active clock pulse, a transition from state 402 to the rightmost state 404 occurs when the digital value D changes to 1 while CKP=1. Similarly, the lower intermediate state 403 was a result of the digital signal D=1 at the start of an active clock pulse, so a transition from state 403 to the rightmost state 404 occurs when the digital value D changes to 0 while CKP=1. In any case, in state 404, A=B=0, which results in comparator 109 setting TEO=1.

[0045] The line labeled TMTEOH (Test Mode; Timing Event Observation; High) in FIG. 3 is an example of the kind of control signal whose possible existence was briefly discussed above. It is also a representation of the DFT compliance of the circuit of FIG. 3. When the value of TMTEOH is low, the TEO signal is reset to TEO=0 on the falling edge of each clock pulse. However, when the value of TMTEOH is high, the TEO signal, once set to TEO=1, remains so until the clock signal CKP goes low at the same time that the control signal TMTEOH goes low. Both of these possibilities are represented in FIG. 4 by the transition from state 404 to the initial state 401, which occurs under the condition ∼CKP & ∼TMTEOH (which means that CKP=0 and TMTEOH=0 occur simultaneously).

[0046] The dependence on the value of TMTEOH can be generalized such that the monitoring circuit is configured to respond to a first control signal value at its control signal input 110 by resetting the timing event observation signal at a predetermined instant during each pulse cycle of the trigger signal, and the monitoring circuit is also configured to respond to a second control signal value at the control signal input by maintaining the timing event observation signal for a period during which the second control signal value appears at the control signal input.

[0047] Figures 5 and 6 show examples of signal timing in one case, assuming the monitoring circuit is of the type shown in Figure 3 above.

[0048] In FIG. 5, after the active clock pulses beginning at instants 501 and 502, the timely change in digital value D causes the unequal A and B values ​​to persist for the entire duration of each active clock pulse. Another clock pulse begins at instant 503, but the change in digital signal D occurs a short time later at instant 504. Because digital signal D changes from 0 to 1, the first one-way latch toggles, but the second one-way latch does not, resulting in A=B=0 and the TEO signal then going high. Because the TMTEOH signal is absent in FIG. 5, the TEO signal is reset to TEO=0 with each falling edge of clock signal CKP. A similar cycle of events follows at instants 505 and 506, except because the delayed change in digital value D from 1 to 0 causes the first one-way latch not to toggle, but the second one-way latch does toggle. Of course, the result is again A=B=0 and the TEO signal then going high.

[0049] Because the TMTEOH signal (now present) remains low, the event cycle at instants 601, 602, 603, and 604 of FIG. 6 is similar to the event cycle at instants 503, 504, 505, and 506 of FIG. 5. Before instant 605, the TMTEOH signal goes high. When the slow change in digital value D reaches instant 606, the initial result is A=0, B=0, and TEO=1, similar to instant 602. However, it is not actually important whether a timing event also occurs at instant 608, because any further change in the TEO signal is prevented as long as the high value of TMTEOH remains valid. In the example of FIG. 6, the TMTEOH signal finally goes low before the falling edge of clock signal CKP at instant 609, resulting in the reset of the TEO signal at instant 609.

[0050] Using so-called standard cell implementations, transistor-level implementations of any microelectronic circuit can be constructed by carefully following the presentation of its functionality as a combination of ordinary logic gates. Standard cells are groups of transistors and interconnect structures that provide a Boolean logic function (e.g., AND, OR, XOR, XNOR, inverter) or a memory function (flip-flop or latch). While more complex cells such as various adders and multiplexing flip-flops can be used, the simplest cells are direct representations of the basic NAND, NOR, and XOR Boolean functions.

[0051] FIG. 7 shows an example of how functionality similar to that described above with reference to FIGS. 1 and 3-6 can actually be implemented without a standard cell implementation. For comparison, a widely used standard cell CMOS implementation of a logic gate such as that shown in FIG. 3 may include two transistors for the inverter, four transistors for the NAND gate, and six transistors for the OR gate. Using such a standard cell implementation, the circuit of FIG. 3 would require the use of 40 transistors. The example implementation of FIG. 7 includes only 27 transistors.

[0052] Two transistors M9 and M10 between the upper and lower voltage rails VDD and VSS in Figure 7 constitute an inverter 106 that generates the complement value ~D of the digital value D. As such, this configuration conforms to what would be a standard cell CMOS implementation of an inverter, and requires only two transistors anyway.

[0053] 7, noting that transistor M3 is common to both unidirectional latch circuits 107 and 108. Transistor M3, with its source coupled to the lower voltage rail VSS, may be referred to as an enabler transistor because a high value of the clock signal CKP at its gate enables active operation of unidirectional latch circuits 107 and 108. Similarly, transistor M5 in the first unidirectional latch circuit 107 and transistor M15 in the second unidirectional latch circuit 108 may be referred to as a disabler or reset transistor because a low value of the clock signal CKP at their gates connects their respective outputs (A in the first unidirectional latch circuit 107 and B in the second unidirectional latch circuit 108) directly to the high voltage rail VDD, disabling the respective unidirectional latch circuits by causing transistor M8 or M18, respectively, to conduct. For completeness, an illustrated CMOS implementation of a one-way latch circuit is described below with reference to the first one-way latch circuit 107 of FIG.

[0054] The source of PMOS M1 is coupled to the high voltage rail VDD. The drain of M1 is coupled to the source of PMOS M4, the drain of PMOS M4 is coupled to the drain of NMOS M2, the source of NMOS M2 is coupled to the drain of enabler NMOS M3. The gates of M1 and M2 are coupled together and form the data input of the one-way latch circuit. The source of PMOS M5 is coupled to VDD. The drain of M5 is coupled to the drain of NMOS M6, the source of NMOS M6 is coupled to the drain of enabler NMOS M3. The gates of M5 and M3 are coupled together and form the clock input of the one-way latch circuit. The gates of M4 and M6 are coupled together. The source of PMOS M7 is coupled to VDD. The drain of M7 is coupled to the drain of NMOS M8, the source of NMOS M8 is coupled to VSS. The gates of M7 and M8 are coupled together. The point between the drains of M7 and M8 is coupled to the gates of M4 and M6. The output of the one-way latch is formed by the coupling of the gates of M7 and M8, the drains of M5 and M4, and the drains of M6 and M2.

[0055] For completeness, the illustrated CMOS implementation of comparator 109 is described below. The sources of PMOSs M21, M22, M25, and M28 are coupled to VDD. The sources of NMOSs M24 and M27 are coupled to VSS. The gates of M21 and M24 are coupled together and form the TMTEOH control input of comparator 109. The drains of M21 and M22 are coupled to the gates of M25 and M27, respectively, and to the drain of NMOS M23. The gates of M22 and M23 are coupled together. The source of M23 is coupled to the drain of M24. The drain of M25 is coupled to the drain of NMOS M26. The drain of M28 is coupled to the source of PMOS M29. The drain of M29 is coupled to the drain of NMOS M30. The sources of M26 and M30 are coupled to the drain of M27. The gates of M28 and M26 are coupled together and form a first data input A of comparator 109. The gates of M29 and M30 are coupled together and form a second data input B of comparator 109. The TEO output of comparator 109 is formed by connecting the drains of M29 and M25, the drains of M30 and M26, and the gates of M22 and M23.

[0056] Storing digital value D in a differential form, including an instantaneous value and its complement, is implemented in voltage-mode CMOS logic in FIG. 7 . For comparison, FIG. 8 shows a monitoring circuit of the type known from earlier patent application PCT / FI2017 / 050290, published as WO2018 / 193150, that uses current-mode logic to store digital value D in differential form at the rising edge of clock signal CLK. Also, in the prior art implementation of FIG. 8 , a fundamental difference exists: neither the stored instantaneous value nor its complement can change (“toggle”) during an active pulse of clock signal CLK; they are stored as VC1 and VC2 at the rising edge of the clock signal, and both remain constant until the end of the active pulse of clock signal CLK. The actual detection of a timing event during an active pulse of clock signal CLK is performed by XNOR gate 801, which compares the stored complement value VC2 with the actual digital value D at the input of the monitoring circuit. If they are equal, it means that the actual digital value D has changed since the start of the active clock pulse, indicating a timing event.

[0057] The voltage-mode logic used in Figure 7 is inherently more reliable than the current-mode logic of Figure 8 because the latter includes floating nodes, where when clock signal CLK is low, nodes 802 and 803 float, independent of digital value D. When CLK and D are both high, node 802 floats, and when CLK is high and D is low, node 803 floats. Floating nodes can result in undesirable logic states due to leakage, especially when attempting to operate at very low voltages.

[0058] When a one-way latch circuit is used to store the instantaneous value of D and its complement, the implementation of FIG. 7 requires fewer transistors than when a standard latch circuit is used. For example, consider the first one-way latch circuit 107, which, compared to a standard latch circuit, does not include a pull-up network connection from the output of the inverter formed by transistors M1, M2, and M3 to output A. The one-way function of the latch circuit also reduces the total number of transistors in the circuit tasked with asserting the TEO signal in the event of a detected timing event. For comparison, considering a total of 11 transistors required for a CMOS implementation of an XOR or XNOR gate (e.g., in Texas Instruments' widely used logic circuits CD4070B and CD4077B), 12 transistors required for a CMOS implementation of a two-input AND gate (e.g., in Texas Instruments' circuit CD4081B), and two transistors required for the inverter, the implementation of the circuit of FIG. 8 requires as many as 49 transistors. This is more than the standard cell implementation of the function in Figure 3, which earlier in this text was calculated to have 40 transistors. Naturally, the 27-transistor implementation of Figure 7 is even more efficient in terms of total transistor count.

[0059] FIG. 9 shows an embodiment of a method corresponding to the description given above with reference to FIGS. 1 and 3 to 7. As a starting point of the method, FIG. 9 shows the opening of a detection window in step 901. The detection window relates to the task of monitoring for timing events and then associated with temporarily storing a digital value in a register circuit in synchronization with a trigger signal. The temporary storage of the digital value should be performed before opening the detection window in step 901. A change in the digital value after the detection window is opened, i.e. while the detection window is open, represents a timing event. Strictly speaking, a timing event is a change in the digital value that is slower than the allowed time limit defined by the trigger signal.

[0060] As indicated by steps 902 and 903, the method includes storing, with respect to an allowable time limit defined by the trigger signal, a corresponding instantaneous value of the digital value in a differential form including the instantaneous value (step 902) and its complement (step 903). The checks in steps 904 and 905 include monitoring for a change in a predetermined direction. Only if one is detected is the corresponding stored value correspondingly toggled in either step 906 or step 907. This portion of the method may be characterized by toggling either the stored instantaneous value or its complement such that, during a timing event detection window following the allowable time limit, each of the stored instantaneous value or its complement is toggled only in response to observing a change in the digital value in one respective direction.

[0061] As represented by step 908, while still within the timing event detection window, the stored instantaneous value is compared with the stored complement value. If no timing event has occurred so far during this detection window, but the detection window is still open, transition occurs via step 910 to monitoring steps 904 and 905. If there is an affirmative result at step 908, only one of the stored values ​​is toggled, meaning the values ​​are equal. As represented by step 909, the method includes outputting a timing event observed signal in response to the comparison at step 908 indicating that the stored instantaneous value and its stored complement value are equal.

[0062] The method of Figure 9 terminates any time after enabling the TEO signal in step 909, or when the detection window closes in step 911 due to an affirmative conclusion of step 910 that the end of the detection window has been found. As a possible addition, as shown in Figure 9, step 912 checks whether a control signal (referred to herein as the TMTEOH signal) is active. If the control signal is not active, step 913 resets the TEO signal before returning to step 901 at the start of the next detection window. If the control signal is active, the method returns to step 901 without resetting the TEO signal.

[0063] FIG. 10 illustrates an embodiment of a method corresponding to the description given above with reference to FIG. 2. The method of FIG. 10 is similar in many respects to the method of FIG. 9, with differences regarding the storage and comparison steps. Storage steps 1002 and 1003 involve storing two copies of corresponding instantaneous values ​​of a digital value with respect to an allowable time limit defined by a trigger signal. Monitoring steps 1004 and 1005 complement each other in the sense that one monitors for a change in one direction and the other monitors for a change in the opposite direction. These monitoring steps and their associated toggling steps 906 and 907 can be characterized by toggling one of the two copies so that, during a timing event detection window following the allowable time limit, each copy is toggled only in response to observing a change in the digital value in one direction, respectively. Steps 1008 and 909 involve comparing the two copies during the timing event detection window and outputting a timing event observed signal in response to the comparison indicating that the stored instantaneous value and its stored complement are different.

[0064] It is clear to those skilled in the art that, as technology advances, the basic concept of the present invention can be implemented in a variety of ways. A typical feature of logic circuits is that logical functions can be replaced by structurally different but operationally equivalent functions, taking into account possible inversions and logic transformations that may be required. Therefore, the present invention and its embodiments are not limited to the examples described above, but instead can be modified within the scope of the claims.

Claims

1. a timing event detection circuit (102) for generating a timing event observation signal (TEO) in response to a change in a digital value (D) at an input of an associated register circuit (101) occurring later than an allowable time limit defined by a trigger signal (CKP); a data input (103) adapted to receive said digital value (D); a clock signal input (104) adapted to receive said trigger signal (CKP); a timing event observation output (105) configured to output said timing event observation signal (TEO), the timing event detection circuit (102) is configured to store, with respect to the allowed time limit, a corresponding instantaneous value of the digital value (D) in a differential format comprising the instantaneous value (A) and a complement value (B) of the instantaneous value (A) with voltage-mode CMOS logic without floating nodes; the timing event detection circuit (102) is configured to toggle one of the stored instantaneous value (A) or the stored complement value (B) of the stored instantaneous value (A) in response to an observed change in the digital value (D) such that, during a timing event detection window following the allowed time limit, the stored instantaneous value (A) or the stored complement value (B) of the stored instantaneous value (A) is toggled only in response to an observed change in the digital value (D) in either one direction from 0 to 1 or one direction from 1 to 0; the timing event detection circuit (102) is configured to compare the stored instantaneous value (A) with the stored complement value (B) of the stored instantaneous value (A) during the timing event detection window, and to output the timing event observation signal (TEO) in response to the comparison indicating that the stored instantaneous value (A) and the stored complement value (B) of the stored instantaneous value (A) are equal; A timing event detection circuit (102).

2. a timing event detection circuit (202) that generates a timing event observation signal (TEO) in response to a change in a digital value (D) at an input of an associated register circuit (101) that occurs later than an allowable time limit defined by a trigger signal (CKP); a data input (103) adapted to receive said digital value (D); a clock signal input (104) adapted to receive said trigger signal (CKP); a timing event observation output (105) configured to output said timing event observation signal (TEO), - the timing event detection circuit (202) is configured to store, with respect to the allowed time limit, the corresponding instantaneous value of the digital value (D) in a parallel dual format comprising two copies (A, B) of said instantaneous value with voltage-mode CMOS logic without floating nodes; the timing event detection circuit (202) is configured to toggle one of the stored copies (A, B) of the instantaneous value in response to an observed change in the digital value (D) such that, during a timing event detection window following the allowed time limit, a first copy (A) is toggled only in response to an observation of a change in the digital value (D) in one direction, either from 0 to 1 or from 1 to 0, and a second copy (B) is toggled only in response to an observation of a change in the digital value (D) in a direction opposite to the one direction, the timing event detection circuit (202) is configured to compare the stored copies of the instantaneous values ​​(A, B) during the timing event detection window and to output the timing event observed signal (TEO) in response to the comparison indicating that the stored copies of the instantaneous values ​​(A, B) are no longer equal; A timing event detection circuit (202).

3. The one-way latch circuit includes a first one-way latch circuit (107, 207) and a second one-way latch circuit (108, 208), each of the first one-way latch circuit (107, 207) and the second one-way latch circuit (108, 208) having a respective latch data input terminal coupled to the data input terminal (103), a respective output terminal, and a respective latch clock input terminal coupled to the clock signal input terminal (104), the one-way latch circuit comprising: - storing the input data of said one-way latch circuit at the beginning of an enable pulse of said trigger signal (CKP); - toggling its output only when the value of the input data (D, ∼D) of the one-way latch circuit changes in a predetermined direction, either from 0 to 1 or from 1 to 0, during the enable pulse of the trigger signal (CKP); 3. The timing event detection circuit (102, 202) according to claim 1 or 2, wherein the timing event detection circuit (102, 202) is a circuit element configured as follows:

4. - both the first unidirectional latch circuit (107) and the second unidirectional latch circuit (108) are configured to toggle their outputs only when the value of the corresponding input data (D, ∼D) changes in the same direction for both of the unidirectional latch circuits, either from 0 to 1 or from 1 to 0; the timing event detection circuit (102) includes an inverter (106) between the data input (103) and one of the first one-way latch circuit (107) and the second one-way latch circuit (108), and the timing event detection circuit (102) stores a corresponding instantaneous value of the digital value in the differential format comprising the instantaneous value (A) in one one-way latch circuit (107) and a complementary value (B) in the other one-way latch circuit (108); A timing event detection circuit (102) according to claim 3 when dependent on claim 1.

5. each of the first one-way latch circuit (107) and the second one-way latch circuit (108) includes a first transistor (M1, M11), a second transistor (M2, M12), a fourth transistor (M4, M14), a fifth transistor (M5, M15), a sixth transistor (M6, M16), a seventh transistor (M7, M17), and an eighth transistor (M8, M18), wherein the first transistor (M1, M11), the fourth transistor (M4, M14), the fifth transistor (M5, M15), and the seventh transistor (M7, M17) are PMOS transistors, and the second transistor (M2, M12), the sixth transistor (M6, M16), and the eighth transistor (M8, M18) are NMOS transistors; the timing event detection circuit comprises an upper voltage rail (VDD), a lower voltage rail (VSS), and an enabler transistor (M3) of the NMOS type, the source of which is coupled to the lower voltage rail (VSS) and the gate of which is coupled to the clock signal input; In each of the first one-way latch circuit (107) and the second one-way latch circuit (108), the source of said first transistor (M1, M11) is coupled to said upper voltage rail (VDD); the drain of said first transistor (M1, M11) is coupled to the source of said fourth transistor (M4, M14); the drain of said fourth transistor (M4, M14) is coupled to the drain of said second transistor (M2, M12); the source of said second transistor (M2, M12) is coupled to the drain of said enabler transistor (M3); the gates of the first transistors (M1, M11) and the gates of the second transistors (M2, M12) are coupled to each other and form the latch data inputs of the respective unidirectional latch circuits; the source of said fifth transistor (M5, M15) is coupled to said upper voltage rail (VDD); the drain of said fifth transistor (M5, M15) is coupled to the drain of said sixth transistor (M6, M16); the source of said sixth transistor (M6, M16) is coupled to the drain of said enabler transistor (M3); the gate of the fifth transistor (M5, M15) and the gate of the third transistor (M3, M13) are coupled to each other and constitute the latch clock input of each of the one-way latch circuits; the gate of the fourth transistor (M4, M14) and the gate of the sixth transistor (M6, M16) are coupled to each other; the source of said seventh transistor (M7, M17) is coupled to said upper voltage rail (VDD); the drain of said seventh transistor (M7, M17) is coupled to the drain of said eighth transistor (M8, M18); the source of said eighth transistor (M8, M18) is coupled to said lower voltage rail (VSS); the gate of the seventh transistor (M7, M17) and the gate of the eighth transistor (M8, M18) are coupled to each other; a point between the drain of the seventh transistor (M7, M17) and the drain of the eighth transistor (M8, M18) is coupled to the gate of the fourth transistor (M4, M14) and to the gate of the sixth transistor (M6, M16); - A timing event detection circuit as described in claim 3 or claim 4 that relies on claim 3, wherein the output terminal of each of the one-way latch circuits is formed by coupling the gate of the seventh transistor (M7, M17) and the gate of the eighth transistor (M8, M18), the drain of the fifth transistor (M5, M15) and the drain of the fourth transistor (M4, M14), and the drain of the sixth transistor (M6, M16) and the drain of the second transistor (M2, M12).

6. A control signal input terminal (110) is included; - responding to a first control signal value at said control signal input (110) by resetting said timing event observation signal (TEO) at a predetermined instant during each pulse cycle of said trigger signal (CKP); - responding to said second control signal value at said control signal input (110) by maintaining said timing event observation signal (TEO) for the period when said second control signal value appears at said control signal input (110); 6. The timing event detection circuit according to claim 1, configured as follows:

7. 5. The timing event detection circuit of claim 4, configured to reset the stored instantaneous value (A) and the stored complement value (B) of the stored instantaneous value (A) to fixed default values ​​at the end of a detection window, the end of the detection window being defined with respect to the trigger signal (CKP) and occurring after the allowed time limit.

8. a microelectronic circuit including a processing path comprising a logic unit and a register circuit (101), said register circuit (101) being configured to temporarily store an output value (D) of said logic unit in synchronization with a trigger signal (CKP), The microelectronic circuit comprises at least one timing event detection circuit (102, 202) according to any one of claims 1 to 7, the timing event detection circuit (102, 202) being associated with one of the register circuits (101) and configured to generate a timing event observation signal (TEO) in response to a change in the digital value (D) at the input of the associated register circuit (101) occurring later than an allowed time limit defined by the trigger signal (CKP).

1. A microelectronic circuit comprising:

9. 1. A method of operating a microelectronic circuit, comprising: - temporarily storing a digital value (D) in a register circuit (101) in synchronization with a trigger signal (CKP); - storing (902, 903) the corresponding instantaneous value of said digital value (D) in differential form comprising said instantaneous value (A) and the complement value (B) of said instantaneous value (A) using a voltage mode CMOS logic without floating nodes, with respect to an allowable time limit defined by said trigger signal (CKP); - toggling (906, 907) either the stored instantaneous value (A) or the stored complement value (B) of the stored instantaneous value (A) such that, during a timing event detection window following the allowed time limit, each of the stored instantaneous value (A) or the stored complement value (B) of the stored instantaneous value (A) is toggled only in response to observing (904, 905) a change in the digital value (D) in one direction, either from 0 to 1 or from 1 to 0; - comparing (908) the stored instantaneous value (A) with the stored complement value (B) of the stored instantaneous value (A) during the timing event detection window; - outputting (909) a timing event observed signal (TEO) in response to said comparison indicating that said stored instantaneous value (A) and said stored complement value (B) of said stored instantaneous value (A) are equal; A method comprising:

10. 1. A method of operating a microelectronic circuit, comprising: - temporarily storing a digital value (D) in a register circuit (101) in synchronization with a trigger signal (CKP); - storing (1002, 1003) the corresponding instantaneous value of said digital value in two copies (A, B) using voltage-mode CMOS logic without floating nodes, with respect to the allowed time limit defined by said trigger signal (CKP); - toggling (906, 907) either of said two copies (A, B) such that, during a timing event detection window following said allowed time limit, each copy is toggled only in response to observing (1004, 1005) a change in said digital value in one direction, either from 0 to 1 or from 1 to 0; - comparing (1008) the two copies (A, B) during the timing event detection window; - outputting (909) a timing event observed signal (TEO) in response to said comparison indicating that said stored instantaneous value (A) and a stored complement value (B) of said stored instantaneous value (A) are different; A method comprising:

Images