Pillar Bumps with Noble Metal Seed Layers for Advanced Heterogeneous Integration

Abstract

The pillar bump structure and method for forming the same includes forming a blanket liner on a semiconductor substrate, followed by a seed layer including a noble metal. A first photoresist layer is formed directly over the seed layer, followed by forming a first plurality of openings in the photoresist layer. A first conductive material is deposited within each of the first plurality of openings to form a first pillar bump. The first photoresist layer is removed from the semiconductor structure, followed by removing a portion of the seed layer extending outward from the first pillar bump, leaving a portion of the seed layer below the first pillar bump.

Description

[Technical Field]

[0001] The present invention relates generally to the field of complementary metal oxide semiconductor (CMOS) devices, and more particularly to the fabrication of pillar bumps with a noble metal seed layer to prevent copper loss and copper undercut during advanced heterogeneous integration. [Background technology]

[0002] Copper pillar bump technology is a chip-to-package interconnect technology that offers superior electromigration (EM) performance compared to traditional controlled-disintegration chip-connect (C4) solders common in today's advanced integration schemes.

[0003] In traditional flip-chip packaging, solder bump connections are used to establish electrical connections between the chip's I / O pads and the substrate or lead frame of the package. Instead of using solder bumps, in copper pillar technology, electronic components are connected to the substrate by copper pillar bumps (also called columns, pillar solder bumps, or solder column connections). Copper pillar technology allows for finer pitches by minimizing the possibility of bump bridging, reduces the capacitance loading on the circuit, and enables electronic components to operate at higher frequencies.

[0004] Copper pillar bumps can also include copper alloys and other copper-containing conductors, or pillar bumps can be formed of other conductive materials. The advantage of pillar bumps is that the pillars do not completely deform during reflow. The solder cap forms a spherical tip that melts during thermal reflow, but the columnar copper pillars tend to maintain their shape.

[0005] Furthermore, copper pillars have higher thermal conductivity than previously used solder bumps, resulting in improved heat transfer rates. These thin copper pillars can be used in finer-pitch arrays than previously possible with conventional solder bumps, without bridging shorts and other issues such as uneven bump height. However, certain etching processes utilized during advanced packaging schemes, including 3D heterogeneous integration, can adversely affect the integrity of copper pillar bumps. Summary of the Invention

[0006] Advanced packaging schemes using copper (Cu) pillar bumps or copper pedestals for either Cu-Cu bonding or solder-based Cu bonding utilize a wet copper seed etching process. Wet etching of the copper seed layer causes adverse side effects, such as copper loss from the exposed copper pillar and copper undercutting of the pedestal. Therefore, there is a need for alternative designs and techniques for forming copper pillar bumps that can eliminate copper loss and pedestal undercutting during the wet etching process.

[0007] The shortcomings of the prior art are overcome and further advantages are provided by providing a method for forming a semiconductor structure, the method including: forming a blanket liner on a semiconductor substrate followed by a seed layer comprising a noble metal, forming a first photoresist layer directly over the seed layer, forming a first plurality of openings in the photoresist layer, depositing a first conductive material in each of the first plurality of openings to form first pillar bumps, removing the first photoresist layer from the semiconductor structure, and removing a portion of the seed layer extending outward from the first pillar bumps, wherein a portion of the seed layer remains beneath the first pillar bumps.

[0008] Another embodiment of the present disclosure provides a semiconductor structure including a pillar bump comprising a conductive material above a semiconductor substrate, and a seed layer comprising a noble metal below the pillar bump and above the semiconductor substrate, wherein the width of the seed layer is equal to the width of the pillar bump.

[0009] The following detailed description, given by way of example and not intended to limit the invention thereto, will be best understood in conjunction with the accompanying drawings in which: [Brief explanation of the drawings]

[0010] [Figure 1] 1A-1C are cross-sectional views of simplified semiconductor structures at intermediate steps during a semiconductor manufacturing process in accordance with embodiments of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view of a simplified semiconductor structure after depositing a photoresist layer in accordance with an embodiment of the present disclosure. [Figure 3] 1A-1C are cross-sectional views of simplified semiconductor structures depicting the formation of multiple openings in accordance with embodiments of the present disclosure. [Figure 4] FIG. 2 is a cross-sectional view of a simplified semiconductor structure after filling a plurality of openings in accordance with an embodiment of the present disclosure. [Figure 5] FIG. 2 is a cross-sectional view of a simplified semiconductor structure after removing a photoresist layer in accordance with an embodiment of the present disclosure. [Figure 6] FIG. 2 is a cross-sectional view of a simplified semiconductor structure after removing uncovered portions of a seed layer in accordance with an embodiment of the present disclosure. [Figure 7] 1A-1C are cross-sectional views of simplified semiconductor structures depicting the simplified semiconductor structures at intermediate steps during a semiconductor fabrication process in accordance with another embodiment of the present disclosure. [Figure 8] FIG. 2 is a cross-sectional view of a simplified semiconductor structure after depositing a hard mask layer followed by depositing a photoresist layer in accordance with an embodiment of the present disclosure. [Figure 9] 1 is a cross-sectional view of a simplified semiconductor structure depicting the formation of multiple openings in accordance with another embodiment of the present disclosure. [Figure 10] 1 is a cross-sectional view of a simplified semiconductor structure depicting extension of a plurality of openings and removal of a photoresist layer in accordance with another embodiment of the present disclosure. [Figure 11] 1 is a cross-sectional view of a simplified semiconductor structure depicting the formation of a protective layer in accordance with another embodiment of the present disclosure. [Figure 12] FIG. 2 is a cross-sectional view of a simplified semiconductor structure after filling a plurality of openings in accordance with another embodiment of the present disclosure. [Figure 13] 1 is a cross-sectional view of a simplified semiconductor structure depicting the formation of a metal cap in accordance with another embodiment of the present disclosure. [Figure 14] FIG. 2 is a cross-sectional view of a simplified semiconductor structure after removing a hard mask layer in accordance with another embodiment of the present disclosure. [Figure 15] FIG. 2 is a cross-sectional view of a simplified semiconductor structure after removing the metal cap and uncovered portions of the seed layer from the semiconductor structure in accordance with another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to portray specific parameters of the invention. The drawings are intended to depict merely exemplary embodiments of the invention. Like numbering in the drawings represents like elements.

[0012] Although detailed embodiments of the claimed structures and methods are disclosed herein, it is understood that the disclosed embodiments are merely exemplary of those claimed structures and methods, which may be embodied in various forms. However, the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. The description may omit details of well-known features and techniques so as not to unnecessarily obscure the presented embodiments.

[0013] For purposes of the following description, terms such as "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof, refer to the disclosed structures and methods and their orientation in the drawing figures. The terms "above," "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, e.g., a first structure, is located on a second element, e.g., a second structure, where an intervening element, such as an interface structure, may be located between the first and second elements. The term "direct contact" means that a first element, e.g., a first structure, and a second element, e.g., a second structure, are connected without any intermediate conductive, insulating, or semiconducting layer at the interface between the two elements.

[0014] Although terms such as "first," "second," and the like may be used herein to describe various elements, it will be understood that these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, a first element discussed below could be referred to as a second element without departing from the scope of the present concepts.

[0015] In order to avoid obscuring the presentation of embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be combined together for purposes of presentation and illustration, and in some cases may not be described in detail. In other cases, some process steps or operations known in the art may not be described at all. It should be understood that the following description instead focuses on distinct features or elements of various embodiments of the present invention.

[0016] Copper (Cu) pillar bumps, or simply Cu pillars, offer several advantages over traditional solder bumps for advanced flip-chip packaging. The transition to Cu pillars has been motivated by limitations associated with the size and pitch (i.e., space between features) of traditional controlled-collapse chip connect (C4) bumping. As pitch requirements continue to shrink, Cu pillars may enable higher-density designs while maintaining sufficient bump height.

[0017] However, wet etching of the copper seed layer, which is typically performed in advanced packaging schemes for either Cu-Cu bonding or solder-based Cu bonding, can cause issues such as copper loss from the exposed Cu pillar and copper undercut at the base of the Cu pillar or pedestal, potentially adversely affecting the integrity of the Cu pillar. Therefore, there is a need for alternative designs and techniques for forming Cu pillar bumps that can eliminate copper loss and pedestal undercut during the wet etching process.

[0018] Accordingly, embodiments of the present disclosure provide methods and related structures for fabricating pillar bump structures using a seed layer comprised of a noble metal that enables the use of a directional plasma dry etch process that is selective only to the noble metal seed layer. This prevents copper loss on the top surface and along the sidewalls of the copper pillar, and also prevents undercutting of the pedestal. Another embodiment of the present disclosure provides methods and related structures for fabricating pillar bump structures using a noble metal seed layer in conjunction with a conformal protective layer formed along the sidewalls of the pillar bump to further preserve the structural integrity of the pillar during subsequent etching processes.

[0019] An embodiment in which a pillar bump structure may be formed using a noble metal seed layer to prevent copper loss and pedestal undercutting is described in detail below with reference to the accompanying drawings, Figures 1 through 6. An alternative embodiment in which a pillar bump structure may be formed to prevent copper loss and pedestal undercutting is described in detail below with reference to the accompanying drawings, Figures 7 through 15.

[0020] Referring now to FIG. 1, there is shown a cross-sectional view of a simplified semiconductor structure 100 at an intermediate step in a semiconductor manufacturing process, in accordance with an embodiment of the present disclosure.

[0021] At this step in the fabrication process, semiconductor structure 100 may include semiconductor substrate 102, blanket liner 106, and seed layer 110. For ease of illustration, a simplified version of semiconductor substrate 102 is depicted in the embodiment of FIG.

[0022] As known to those skilled in the art, the semiconductor substrate 102 can be used for bump fabrication during semiconductor integrated circuit fabrication, and integrated circuits can be formed therein and / or on its surface. The semiconductor substrate 102 can include, but is not limited to, a bulk silicon substrate, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon-germanium substrate. Other semiconductor materials containing Group III, IV, and V elements can also be used. The semiconductor substrate 102 can further include multiple isolation features (not shown), such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features. These isolation features can define and isolate various microelectronic elements (not shown).

[0023] Examples of various microelectronic elements that may be formed in the semiconductor substrate 102 include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel field effect transistors or n-channel field effect transistors or both (PFETs / NFETs), etc.), resistors, diodes, capacitors, inductors, fuses, or other suitable elements. Various processes, including deposition, etching, implantation, photolithography, annealing, or other suitable processes, are performed to form the various microelectronic elements. The microelectronic elements are interconnected to form integrated circuit devices, such as logic devices, memory devices (e.g., static random access memories or SRAMs), radio frequency (RF) devices, input / output (I / O) devices, system-on-chip (SoC) devices, combinations thereof, or other suitable types of devices.

[0024] The semiconductor substrate 102 may further include an interlevel dielectric layer (not shown) and a metallization structure (not shown) overlying the integrated circuit. The interlevel dielectric layer in the metallization structure may include a low-k dielectric material, undoped silicate glass (USG), silicon nitride, silicon oxynitride, or other commonly used materials. The low-k dielectric material may have a dielectric constant (k value) less than about 3.9, or less than about 2.8. The metal lines (not shown) in the metallization structure may include copper or a copper alloy. Those skilled in the art will understand the details of forming the metallization structure.

[0025] The blanket liner 106 formed above the semiconductor substrate 102 may function as an adhesion layer to the semiconductor substrate 102 and as a barrier layer to prevent copper from diffusing into the device region of the semiconductor substrate 102. Standard deposition processes may be used to form the blanket liner 106. For example, in some embodiments, the blanket liner 106 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplary materials that may be used to form the blanket liner 106 may include titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof. According to certain embodiments, the blanket liner 106 may have a thickness ranging from about 50 nm to about 500 nm, although thicknesses less than 50 nm and greater than 500 nm may be acceptable.

[0026] In some embodiments, a passivation layer (not shown) comprising any suitable dielectric material may be deposited over the semiconductor substrate 102 prior to forming the blanket liner 106 .

[0027] Continuing with reference to FIG. 1 , seed layer 110 is formed above blanket liner 106 using known deposition processes. For example, seed layer 110 may be formed using sputtering techniques, among other known metal deposition techniques. According to certain embodiments, seed layer 110 is made of a noble metal, including, but not limited to, ruthenium (Ru), rhodium (Rh), iridium (Ir), platinum (Pt), and palladium (Pd). Seed layer 110 may have a thickness ranging from about 20 nm to about 500 nm and therebetween, although thicknesses less than 20 nm and greater than 500 nm may be acceptable.

[0028] The blanket liner 106 and the seed layer 110 together form an under bump metallization (UBM) layer. It should be noted that the use of a noble metal to form the seed layer 110 enables the use of a plasma dry etch process instead of conventional wet chemical etching during subsequent fabrication steps. As will be explained in more detail below, the dry etch process is selective only to the seed layer 110, which prevents damage to the copper pillars during the fabrication process.

[0029] Referring now to FIG. 2, a cross-sectional view of the semiconductor structure 100 after depositing a photoresist layer 210 is shown in accordance with an embodiment of the present disclosure.

[0030] Photoresist layer 210 comprises a photoresist material deposited above seed layer 110 using conventional deposition techniques, such as dry film lamination or liquid resist spin-on. Photoresist layer 210 may have a (vertical) thickness that varies from about 10 μm to about 150 μm and ranges therebetween, although thicknesses less than 10 μm and greater than 150 μm may be acceptable.

[0031] 3, there is shown a cross-sectional view of semiconductor structure 100 depicting the formation of opening 300, in accordance with an embodiment of the present disclosure. At this step in the fabrication process, photoresist layer 210 undergoes conventional lithography and etching processes to form opening 300.

[0032] As shown, openings 300 exposed the top surface of seed layer 110. As known to those skilled in the art, any number of openings 300 may be formed depending on the circuit design and / or requirements.

[0033] Referring now to FIG. 4, a cross-sectional view of the semiconductor structure 100 after filling the opening 300 is shown in accordance with an embodiment of the present disclosure.

[0034] In this embodiment, the opening 300 is partially or completely filled with a solder-wettable conductive material that forms the pillar bump 420. Preferably, the conductive material comprises copper (Cu) or a copper alloy such as CuAl, CuSn, or CuIn. The conductive material that forms the pillar bump 420 is deposited in the opening 300 above and in direct contact with the underlying seed layer 110. Exemplary methods for forming the conductive material include sputtering, printing, electroplating, electroless plating, and CVD. According to one embodiment, the conductive material may be formed by electrochemical plating to form the pillar bump 420.

[0035] In certain embodiments, the height of the pillar bump 420 may vary from about 10 μm to about 150 μm and ranges therebetween, although heights less than 10 μm and greater than 150 μm may be acceptable. Similarly, the width of the pillar bump 420 may vary from about 10 μm to about 100 μm and ranges therebetween, although widths less than 10 μm and greater than 100 μm may be acceptable. It should be noted that although the pillar bump 420 is depicted using a cross-sectional view, the pillar bump 420 is annular in shape.

[0036] 5, a cross-sectional view of the semiconductor structure 100 after removal of the photoresist layer 210 is shown, in accordance with an embodiment of the present disclosure. Any known stripping process can be used to remove the photoresist layer 210. For example, the photoresist layer 210 can be stripped using TMAH, which has a high pH content, along with glycol to aid swelling and NMP to aid dissolution. Alternatively, the photoresist can be stripped using a sodium hydroxide or potassium hydroxide and DMSO solution.

[0037] As depicted in the figure, removal of photoresist layer 210 exposes pillar bumps 420 and uncovered portions of seed layer 110.

[0038] Referring now to FIG. 6 , a cross-sectional view of the semiconductor structure 100 is shown after removal of the uncovered portion of the seed layer 110, in accordance with an embodiment of the present disclosure. During this step of the fabrication process, the portion of the seed layer 110 not covered by the pillar bump 420 can be removed by any suitable directional etching process. For example, the uncovered portion of the seed layer 110 can be removed by using a reactive ion etching (RIE) technique. Specifically, the portion of the seed layer 110 extending outward from the pillar bump 420 is removed, while the portion of the seed layer 110 underlying the pillar bump 420 remains within the conductor structure 100. As depicted in the figure, the width of the remaining portion of the pillar bump 420 below the pillar bump 420 is substantially equal to the width of the pillar bump 420.

[0039] It should be noted that the use of a noble metal to form the seed layer 110 allows dry etching techniques to be used to remove the portions of the seed layer 110 that are not covered by the pillar bump 420. The dry etching techniques are selective only to the noble metal seed layer 110, which allows for the removal of the uncovered portions of the metal seed layer 110 without undercutting the pillar bump 420 or losing the conductive material (i.e., copper). From this step onwards, the manufacturing process continues according to conventional processing steps.

[0040] 7-15, cross-sectional views of a semiconductor structure 700 are shown illustrating an alternative processing sequence for forming a pillar bump according to another embodiment of the present disclosure. Pillar bump 1240 (FIG. 12) is formed similarly to pillar bump 420 described above with reference to FIGS. 1-6. However, in this embodiment, protective layer 1120 is formed prior to depositing the conductive material that forms pillar bump 1240, as depicted in FIG. 11.

[0041] 7, there is shown a cross-sectional view of a semiconductor structure 700, similar to semiconductor structure 100, at an intermediate step in a semiconductor fabrication process in accordance with an embodiment of the present disclosure. At this step, semiconductor structure 700 includes substantially the same elements as semiconductor structure 100 depicted in FIG. 1. Specifically, semiconductor structure 700 includes semiconductor substrate 102, blanket liner 106, and seed layer 110. The process for forming these elements is described in detail above with reference to FIG. 1.

[0042] Referring now to FIG. 8, there is shown a cross-sectional view of the semiconductor structure 700 after depositing a hard mask layer 810 followed by a photoresist layer 820 in accordance with an embodiment of the present disclosure.

[0043] The hard mask layer 810 is formed directly over the seed layer 110 using known deposition techniques. The hard mask layer 810 enables the formation of a protective layer 1120, as described in more detail below with reference to FIG. 11 . Exemplary materials for forming the hard mask layer 810 include titanium nitride (TiN), silane or tetraethylorthosilane (TEOS), silicon nitride (SiN), silicon oxide, an oxide / nitride stack, or similar materials and configurations. The hard mask layer 810 may have a (vertical) thickness ranging from about 10 μm to about 150 μm and therebetween, although thicknesses less than 10 μm and greater than 150 μm may be acceptable.

[0044] Photoresist layer 820 is formed over and in direct contact with hard mask layer 810. Photoresist layer 820 is formed using materials and methods similar to photoresist layer 210 described above with reference to FIG.

[0045] 9, there is shown a cross-sectional view of semiconductor structure 700 depicting the formation of openings 900, in accordance with an embodiment of the present disclosure. In this step of the fabrication process, photoresist layer 820 undergoes conventional lithography and etching processes to form openings 900. As shown, openings 900 expose the top surface of hard mask layer 810 into which openings 900 will extend, as shown in FIG. 10. As known to those skilled in the art, any number of openings 900 may be formed depending on the circuit design and / or requirements.

[0046] 10 , there is shown a cross-sectional view of semiconductor structure 700 after extension of opening 900 and removal of photoresist layer 820, in accordance with an embodiment of the present disclosure. In this embodiment, conventional patterning techniques can be performed to extend opening 900 into hard mask layer 810. As shown, extended opening 900 has exposed the top surface of seed layer 110.

[0047] Similar to photoresist layer 210 (FIG. 2), photoresist layer 820 can be removed using any known stripping process. For example, photoresist layer 820 can be stripped using TMAH, which has a high pH content, along with glycol to aid swelling and NMP to aid dissolution. Alternatively, the photoresist can be stripped using a sodium hydroxide or potassium hydroxide and DMSO solution.

[0048] 11 , there is shown a cross-sectional view of semiconductor structure 700 depicting the formation of protective layer 1120, in accordance with an embodiment of the present disclosure. As its name suggests, protective layer 1120 protects pillar bump 1240 ( FIG. 12 ) during an etching process performed in a subsequent fabrication step. Any suitable deposition technique may be implemented to form protective layer 1120 within opening 900. In one embodiment, a CVD, PVD, or ALD process may be used to form protective layer 1120.

[0049] Any suitable directional etching process may then be performed on the semiconductor structure 700 to remove the portions of the protective layer 1120 that are parallel to the semiconductor substrate 102. As shown, the portions of the protective layer 1120 that are perpendicular to the semiconductor substrate 102 remain along opposing sidewalls of the hard mask layer 810.

[0050] Exemplary materials that may be used to form the protective layer 1120 include tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (WN). The protective layer 1120 may have a (horizontal) thickness that varies from about 20 nm to about 500 nm and ranges therebetween, although thicknesses less than 20 nm and greater than 500 nm may be acceptable.

[0051] Referring now to FIG. 12, a cross-sectional view of the semiconductor structure 700 after filling the opening 900 is shown in accordance with an embodiment of the present disclosure.

[0052] In this embodiment, opening 900 is partially or completely filled with a solder-wettable conductive material to form pillar bump 1240. Preferably, the conductive material comprises copper (Cu) or a copper alloy. Pillar bump 1240 is formed using materials and techniques similar to pillar bump 420, as described above with reference to FIG. 4. In this embodiment, pillar bump 1240 is laterally covered by protective layer 1120, as shown.

[0053] Additionally or alternatively, a metal cap 1310 may be formed over the pillar bump 1240, as depicted in Figure 13. The metal cap 1310 may protect the pillar bump 1240 during removal of the hard mask layer 810. The metal cap 1310 may be made of materials such as ruthenium, nickel, palladium, platinum, and alloys thereof, and may be deposited using standard deposition techniques.

[0054] 14, there is shown a cross-sectional view of semiconductor structure 700 after removing hard mask layer 810, in accordance with an embodiment of the present disclosure. In this embodiment, any suitable etching process may be used to remove hard mask layer 810, such as a dry etch process (e.g., a reactive ion etch) or a wet etch process.

[0055] 15 , there is shown a cross-sectional view of the semiconductor structure 700 after removing the metal cap 1310 and the uncovered portions of the seed layer 110, in accordance with an embodiment of the present disclosure. In this embodiment, the metal cap 1310 and the uncovered portions of the seed layer 110 may be removed by performing a plasma dry etching technique. The metal cap and the seed layer may be removed simultaneously in a single etch step or multiple etch steps.

[0056] As shown in the figure, in this embodiment, the width of the seed layer 110 is equal to the width of the pillar bump 1240 plus the width of the protective layer 1120 positioned along the sidewalls on both sides of the pillar bump 1240.

[0057] It should be noted that the protective layer 1120, together with the remainder of the seed layer 110, protects the pillar bump 1240 during removal of the hard mask layer 810 and during etching of the portions of the seed layer 110 not covered by the pillar bump 1240. As described above, the use of a noble metal to form the seed layer 110 allows dry etching techniques to be performed to remove the portions of the seed layer 110 not covered by the pillar bump 1240. The dry etching techniques are selective only to the noble metal seed layer 110, which allows for removal of the uncovered portions of the metal seed layer 110 without undercutting the pillar bump 1240 or losing the conductive material (i.e., copper).

[0058] Accordingly, embodiments of the present disclosure provide pillar bumps with improved structural features. In one embodiment, the improved pillar bump structure is achieved by forming a noble metal seed layer, which allows for the use of dry etching techniques instead of traditional wet chemical etching, which is associated with copper loss and pedestal undercutting. In another embodiment, a protective layer is formed along the sidewalls of the pillar bump to further protect the pillar bump during hard mask removal and other fabrication steps. The protective layer, together with the noble metal seed layer, can prevent copper loss from the exposed pillar and pedestal undercutting, thereby improving device performance and reliability.

[0059] While the descriptions of various embodiments of the present invention have been presented for illustrative purposes, they are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A method of forming a semiconductor structure, comprising: forming a blanket liner on a semiconductor substrate followed by a seed layer of a material comprising a noble metal; forming a hard mask layer over the seed layer; forming a first photoresist layer over the hard mask layer; forming a first plurality of openings from the first photoresist layer through the hard mask layer to expose the seed layer; depositing a protective layer within the first plurality of openings; depositing a first conductive material different from a material of the seed layer into each of the first plurality of openings to form a first pillar bump, the protection layer being located along opposite sidewalls of the first pillar bump; removing the hard mask layer from the semiconductor structure; removing a portion of the seed layer extending outward from the first pillar bump while protecting the sides of the first pillar bump with the protective layer, wherein a portion of the seed layer remains under the first pillar bump; A method comprising:

2. The method of claim 1 , wherein a width of the portion of the seed layer is equal to a width of the first pillar bump plus a width of the protective layer on either side.

3. 3. The method of claim 1 or claim 2, wherein the noble metal forming the seed layer comprises at least one of ruthenium, rhodium, iridium, platinum, and palladium.

4. 4. The method of claim 1, wherein the seed layer comprising the noble metal enables a directional plasma dry etch process to be used to remove the portion of the seed layer extending outward from the first pillar bump.

5. 5. The method of claim 4, wherein the directional plasma dry etch process is selective only to the seed layer comprising the noble metal.

6. The method according to any one of claims 1 to 5, wherein the first conductive material is copper or a copper alloy.

7. removing the first photoresist layer; The method of any one of claims 1 to 6, further comprising:

8. removing portions of the protective layer parallel to the semiconductor substrate, wherein portions of the protective layer perpendicular to the semiconductor substrate and in direct contact with the hard mask layer remain within the semiconductor structure; The method of any one of claims 1 to 7, further comprising:

9. The method of any one of claims 1 to 7, wherein the protective layer comprises tantalum nitride.

10. The method according to any one of claims 1 to 7, wherein both sidewalls of the first pillar bump are in direct contact with the protective layer.

11. forming a metal cap above the first pillar bump in direct contact with the first pillar bump; The method of claim 10 further comprising:

12. 12. The method of claim 11 , wherein removing the hard mask layer occurs after forming the metal cap, and removing the metal cap occurs during removing the portion of the seed layer.

13. The method of any one of claims 1 to 12, wherein the protective layer protects the first pillar bump during removal of the hard mask layer.

14. 1. A semiconductor structure comprising: a pillar bump comprising a conductive material, the conductive material being copper or a copper alloy, above a semiconductor substrate; a protective layer along the sidewalls of both sides of the pillar bump; a seed layer of a material comprising a noble metal different from the conductive material below the pillar bump and above the semiconductor substrate, the seed layer having a width equal to the width of the pillar bump plus a width of the protective layer along the opposite sidewalls of the pillar bump; 1. A semiconductor structure comprising:

15. 15. The semiconductor structure of claim 14 wherein said noble metal comprises at least one of ruthenium, rhodium, iridium, and palladium.

16. 16. The semiconductor structure of claim 14 or claim 15, wherein said protective layer comprises tantalum nitride, titanium nitride, or tungsten nitride.

17. A semiconductor structure described in any one of claims 14 to 16, wherein the pillar bump is deposited in direct contact with the seed layer.

18. 14. A computer program comprising program code adapted to perform the method steps according to any of claims 1 to 13 when said computer program is run on a computer.

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