Digitally Controlled Regulator

Abstract

[Problem] To provide a digital control regulator that enables an improvement in stability, a reduction in variation of ripple voltage and droop characteristics, and reduction in size with a low voltage. [Solution] The digital control regulator is provided with: a first AD converter that generates a first digital signal according to a difference voltage between an output voltage and a first reference voltage; an output stage circuit that generates the output voltage; a replica circuit that has the same circuit configuration as the output stage circuit and outputs a replica voltage related to the output voltage; a second AD converter that generates a second digital signal according to a difference voltage between the replica voltage and a second reference voltage; and a control circuit that generates a control signal for controlling the gain of the output stage circuit on the basis of the first digital signal and the second digital signal.

Description

[Technical Field]

[0001] The present disclosure relates to digitally controlled regulators. [Background technology]

[0002] Generally, if the output stage circuit of a digital LDO (Low Drop Out) has too low a capacity, the current supply capacity and droop characteristics deteriorate, while if the capacity is too high, it increases ripple voltage and deteriorates stability, so it can be said that there is a trade-off between improving stability and improving transient response characteristics and reducing ripple. This problem can be solved if the capacity of the output stage circuit can be kept constant.

[0003] Various control circuits have been proposed to suppress variations in the performance of output stage circuits (see Patent Document 1). Representative control circuits include (1) a multi-loop controlled digital LDO with a performance correction function, (2) a digitally controlled performance correction circuit, and (3) an analogue controlled performance correction circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2016-519356 Summary of the Invention [Problem to be solved by the invention]

[0005] The digital LDO mentioned above (1) has the problem that it cannot adjust its capacity unless the output changes, and it is difficult to ensure stability due to the multi-loop control.Furthermore, a configuration that implements a loop controlled by an analog voltage requires a large area and leads to an increase in power consumption.

[0006] The digitally controlled performance correction circuit described above in (2) cannot adjust according to the input voltage (or input / output potential difference), take into account transistor skew, or adjust according to temperature, which may result in poor correction accuracy.

[0007] The analog control performance correction circuit described above in (3) increases the area and power consumption, and is not suitable for low-voltage operation.

[0008] Therefore, the present disclosure provides a digitally controlled regulator that can improve stability, reduce variations in ripple voltage and droop characteristics, and can be made small and operate at a low voltage. [Means for solving the problem]

[0009] In order to solve the above problem, according to the present disclosure, there is provided a first AD converter that generates a first digital signal according to a differential voltage between an output voltage and a first reference voltage; an output stage circuit for generating the output voltage; a replica circuit having the same circuit configuration as the output stage circuit and outputting a replica voltage related to the output voltage; a second AD converter that generates a second digital signal according to a differential voltage between the replica voltage and a second reference voltage; and a control circuit that generates a control signal for controlling a gain of the output stage circuit based on the first digital signal and the second digital signal.

[0010] The output stage circuit and the replica circuit may be circuits having the same circuit configuration including transistors of the same conductivity type and the same size.

[0011] The output stage circuit and the replica circuit may be circuits having the same circuit configuration including resistor elements with the same resistance value.

[0012] The second digital signal may include capability information of the replica circuit.

[0013] The control circuit may generate the control signal so that the output voltage is not affected by fluctuations due to performance information of the output stage circuit.

[0014] The capability information may include at least one of information on an input voltage, an output voltage, a manufacturing process, and a temperature of the replica circuit or the output stage circuit.

[0015] The second digital signal may include on-resistance information of the replica circuit.

[0016] The control circuit may generate the control signal based on the second digital signal so that an on-resistance of the output stage circuit matches an on-resistance of the replica circuit.

[0017] the replica circuit outputs the replica voltage before the output stage circuit and the control circuit start feedback control of the output voltage or in synchronization with the start timing of the feedback control; The second AD converter may generate the second digital signal before the output stage circuit and the control circuit start feedback control of the output voltage, or in synchronization with the start timing of the feedback control.

[0018] the replica circuit outputs the replica voltage in synchronization with a timing at which the voltage level of the output voltage is switched while the output stage circuit and the control circuit are performing feedback control of the output voltage; The second AD converter may generate the second digital signal in synchronization with a timing at which the voltage level of the output voltage is switched while the output stage circuit and the control circuit are performing feedback control of the output voltage.

[0019] the replica circuit outputs the replica voltage a predetermined period before a timing at which the voltage level of the output voltage is switched while the output stage circuit and the control circuit are performing feedback control of the output voltage; The second AD converter may generate the second digital signal in accordance with the timing at which the voltage level of the output voltage is switched while the output stage circuit and the control circuit are performing feedback control of the output voltage.

[0020] the replica circuit intermittently outputs the replica voltage while the output stage circuit and the control circuit are performing feedback control of the output voltage; The second AD converter may intermittently generate the second digital signal while the output stage circuit and the control circuit are performing feedback control of the output voltage.

[0021] the replica circuit continuously outputs the replica voltage while the output stage circuit and the control circuit are performing feedback control of the output voltage; The second AD converter may continuously generate the second digital signal while the output stage circuit and the control circuit are performing feedback control of the output voltage.

[0022] The replica circuit may output the replica voltage when an enable signal has a predetermined logic, and may stop outputting the replica voltage when the enable signal has a logic other than the predetermined logic.

[0023] The second reference voltage may be input to the second AD converter in synchronization with the timing at which the enable signal becomes the predetermined logic level.

[0024] The second AD converter a comparator that outputs a signal according to a differential voltage between the replica voltage and the second reference voltage; a variable load circuit that controls a voltage level of the replica voltage by adjusting a current flowing through an output node of the replica circuit; The present invention may also include a control unit that adjusts the current flowing through the output node to the variable load circuit based on the output signal of the comparator, and generates the second digital signal including on-resistance information of the replica circuit for matching the replica voltage to the second reference voltage.

[0025] the replica circuit is capable of adjusting the number of connected stages of transistors or resistor elements; The second AD converter a comparator that outputs a signal according to a differential voltage between the replica voltage and the second reference voltage; and a control unit that adjusts the number of connected stages of transistors or resistor elements in the replica circuit based on the output signal of the comparator, and generates the second digital signal including on-resistance information of the replica circuit for matching the replica voltage with the second reference voltage.

[0026] the output stage circuit is capable of adjusting the number of connected stages of transistors or resistor elements; The control circuit may set the number of connected stages of transistors or resistor elements in the output stage circuit to be the same as the number of connected stages of transistors or resistor elements in the replica circuit, based on the second digital signal.

[0027] the control circuit performs feedback control so that the output voltage is equal to the first reference voltage; The first reference voltage and the second reference voltage may be at the same voltage level.

[0028] the control circuit performs feedback control so that a voltage obtained by dividing the output voltage by 1 / A (A is a real number greater than 1) becomes equal to the first reference voltage; the second reference voltage is set to the same voltage level as the first reference voltage; The second AD converter may compare the replica voltage with a voltage obtained by multiplying the second reference voltage by A. [Brief explanation of the drawings]

[0029] [Figure 1] FIG. 1 is a block diagram of a digitally controlled regulator according to one embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of a circuit configuration in an output stage circuit. [Figure 3A] FIG. 4 is a diagram showing the characteristics of a transistor in an output stage circuit. [Figure 3B] FIG. 4 is a diagram showing the amount of fluctuation in output voltage due to fluctuation in load current. [Figure 4] FIG. 1 is a block diagram showing a first specific example of a digitally controlled regulator. [Figure 5] FIG. 10 is a block diagram showing a second specific example of a digitally controlled regulator. [Figure 6] FIG. 10 is a block diagram showing a third specific example of a digitally controlled regulator. [Figure 7] FIG. 10 is a block diagram showing a fourth specific example of a digitally controlled regulator. [Figure 8] FIG. 10 is a block diagram showing a fifth specific example of a digitally controlled regulator. [Figure 9] FIG. 10 is a block diagram showing a sixth specific example of a digitally controlled regulator. [Figure 10] FIG. 10 is a block diagram showing a seventh specific example of a digitally controlled regulator. [Figure 11] 10 is a flowchart showing an example of a processing procedure for performing digital LDO operation and performance correction of an output stage circuit. [Figure 12] This is a timing diagram when performance correction is performed only at startup. [Figure 13] This is a timing diagram showing the performance correction circuit correcting the performance in response to the start of digital LDO operation. [Figure 14] FIG. 10 is a timing diagram for performing intermittent performance correction. [Figure 15] FIG. 10 is a timing diagram showing the performance correction before switching the voltage level of the output voltage. [Figure 16] This is a timing diagram for when capacity correction is performed continuously before digital LDO operation begins. [Figure 17] This diagram shows an example of continuous performance correction that is timed to coincide with the start of digital LDO operation. [Figure 18]FIG. 1 is a block diagram showing an example of a schematic configuration of a digitally controlled regulator according to an embodiment of the present invention. [Figure 19] FIG. 10 is a block diagram of a digitally controlled regulator according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0030] Hereinafter, an embodiment of a digitally controlled regulator will be described with reference to the drawings. The following description will focus on the main components of the digitally controlled regulator, but the digitally controlled regulator may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0031] Figure 1 is a block diagram of a digitally controlled regulator 1 according to one embodiment. The digitally controlled regulator 1 in Figure 1 is also called a digitally controlled LDO. The digitally controlled regulator 1 in Figure 1 includes a first AD converter (hereinafter referred to as ADC1 or first ADC) 2, an output stage circuit 3, a replica circuit 4, a second AD converter (hereinafter referred to as ADC2 or second ADC) 5, and a control circuit (CTRL) 6.

[0032] The first ADC2 generates a first digital signal D1 corresponding to the differential voltage between the output voltage Vout and the first reference voltage VREF1. The first digital signal D1 is input to the control circuit 6. The first ADC2 performs AD conversion operation when the first reference voltage VREF1 and the output voltage Vout are input.

[0033] The output stage circuit 3 generates an output voltage Vout. A resistor R1 and a capacitor C1 are connected in parallel between the output node of the output stage circuit 3 and a ground node. The output stage circuit 3 is controlled by a control circuit 6. The output stage circuit 3, the first ADC 2, and the control circuit 6 constitute a digital LDO circuit 7. The digital LDO circuit 7 performs feedback control so that the output voltage Vout coincides with the first reference voltage VREF1.

[0034] The replica circuit 4 has the same circuit configuration as the output stage circuit 3, and outputs a replica voltage related to the output voltage Vout. The replica voltage has the same voltage level as the output voltage Vout when there is no load fluctuation. The replica circuit 4 and the second ADC 5 constitute a performance correction circuit 8 that corrects the performance of the output stage circuit 3.

[0035] The replica circuit 4 may be enabled and output a replica voltage when the first enable signal EN1 is at a predetermined logic level. In this case, the replica circuit 4 stops outputting the replica voltage when the first enable signal EN1 is at a logic level other than the predetermined logic level, thereby reducing the power consumption of the replica circuit 4.

[0036] The second ADC5 generates a second digital signal D2 corresponding to the differential voltage between the replica voltage and the second reference voltage VREF2. The second digital signal D2 includes performance information of the replica circuit 4. The performance information of the replica circuit 4 includes, for example, at least one of the input voltage, output voltage Vout, manufacturing process, and temperature of the replica circuit 4. The performance information of the replica circuit 4 is substantially the same as the performance information of the output stage circuit 3. The second digital signal D2 also includes on-resistance information of the replica circuit 4. The second ADC5 performs AD conversion when the replica voltage and the second reference voltage VREF2 are input. The second ADC5 is enabled when the first enable signal EN1 is at a predetermined logic level, and generates the second digital signal D2. The second reference voltage VREF2 is input to the second ADC5 at the timing when the first enable signal EN1 becomes at a predetermined logic level. By limiting the period during which the second reference voltage VREF2 is input to the second ADC 5 and by allowing the second ADC 5 to perform A / D conversion operation only when the first enable signal EN1 is at a predetermined logic level, it is possible to reduce power consumption.

[0037] The control circuit 6 generates a control signal that controls the gain of the output stage circuit 3 based on the first digital signal D1 and the second digital signal D2. The control circuit 6 generates the control signal so that the output voltage Vout is not affected by fluctuations due to performance information of the output stage circuit 3. For example, the control circuit 6 generates the control signal based on the second digital signal D2 so that the on-resistance of the output stage circuit 3 matches the on-resistance of the replica circuit 4.

[0038] The output voltage Vout is fed back to the first ADC 2, which generates a first digital signal D1 corresponding to the differential voltage between the output voltage Vout and the first reference voltage VREF1. The control circuit 6 generates a control signal for controlling the gain of the output stage circuit 3 based on the first digital signal D1 and the second digital signal D2 from the second ADC 5. This feedback loop does not have a double-loop structure, making it easy to design for stability.

[0039] The output stage circuit 3 can adjust its on-resistance using a control signal output from the control circuit 6, and adjusting the on-resistance can control the output voltage Vout. Any specific circuit configuration can be used to adjust the on-resistance of the output stage circuit 3. The output stage circuit 3 may output the output voltage Vout when the second enable signal EN2 is at a predetermined logic level. The second enable signal EN2 may also be input to the first ADC 2 and the control circuit 6. In this case, when the second enable signal EN2 is at a logic level other than the predetermined level, the entire operation of the digital LDO circuit 7, which includes the first ADC 2, the control circuit 6, and the output stage circuit 3, can be stopped, thereby reducing power consumption.

[0040] The output stage circuit 3 and the replica circuit 4 are circuits with the same circuit configuration, including transistors of the same conductivity type and the same size, for example. Alternatively, the output stage circuit 3 and the replica circuit 4 may be circuits with the same circuit configuration, including resistor elements with the same resistance value.

[0041] As will be described later, the replica circuit 4 may output the replica voltage before the output stage circuit 3 and the control circuit 6 start feedback control of the output voltage Vout, or in synchronization with the start timing of the feedback control. In this case, the second ADC 5 generates the second digital signal D2 before the output stage circuit 3 and the control circuit 6 start feedback control of the output voltage Vout, or in synchronization with the start timing of the feedback control. In this way, by correcting the performance of the output stage circuit 3 before the start of digital LDO operation, the digital LDO operation can be performed independently of variations in the performance of the output stage circuit 3.

[0042] Alternatively, the replica circuit 4 may output the replica voltage in synchronization with the timing at which the voltage level of the output voltage Vout is switched while the output stage circuit 3 and the control circuit 6 are performing feedback control of the output voltage Vout. In this case, the second ADC 5 generates the second digital signal D2 in synchronization with the timing at which the voltage level of the output voltage Vout is switched while the output stage circuit 3 and the control circuit 6 are performing feedback control of the output voltage Vout. When the voltage level of the output voltage Vout changes, the droop characteristics and ripple characteristics of the output voltage Vout fluctuate, as will be described later. Therefore, by correcting the performance of the output stage circuit 3 again in synchronization with the timing at which the voltage level of the output voltage Vout changes, the droop characteristics, ripple characteristics, etc. can be improved.

[0043] Alternatively, the replica circuit 4 may output the replica voltage a predetermined period before the timing at which the voltage level of the output voltage Vout is switched while the output stage circuit 3 and the control circuit 6 are performing feedback control of the output voltage Vout. In this case, the second ADC 5 generates the second digital signal D2 in accordance with the timing at which the voltage level of the output voltage Vout is switched while the output stage circuit 3 and the control circuit 6 are performing feedback control of the output voltage Vout. In order to be able to correct the performance of the output stage circuit 3 at the timing at which the output voltage Vout is switched, it is necessary for the second ADC 5 to output the second digital signal D2 including performance information of the replica circuit 4 before the timing at which the output voltage Vout is switched. This allows the performance of the output stage circuit 3 to be corrected from the timing at which the output voltage Vout is switched.

[0044] Alternatively, the replica circuit 4 may intermittently output a replica voltage while the output stage circuit 3 and the control circuit 6 are performing feedback control of the output voltage Vout. In this case, the second ADC 5 intermittently generates the second digital signal D2 while the output stage circuit 3 and the control circuit 6 are performing feedback control of the output voltage Vout. By intermittently correcting the performance of the output stage circuit 3 while the digital LDO is operating, the output voltage Vout can be generated without being affected by fluctuations in the input voltage, output voltage Vout, temperature, etc. of the output stage circuit 3.

[0045] Alternatively, the replica circuit 4 may continuously output the replica voltage while the output stage circuit 3 and the control circuit 6 are performing feedback control of the output voltage Vout. In this case, the second ADC 5 continuously generates the second digital signal D2 while the output stage circuit 3 and the control circuit 6 are performing feedback control of the output voltage Vout. By continuously correcting the performance of the output stage circuit 3 while the digital LDO operation is being performed, the output voltage Vout can be corrected in immediate response to fluctuations in the input voltage of the output stage circuit 3, the output voltage Vout, temperature, etc.

[0046] The replica circuit 4 may output a replica voltage when the first enable signal EN1 is at a predetermined logic level, and may stop outputting the replica voltage when the first enable signal EN1 is at a logic level other than the predetermined logic level. In this way, by operating the replica circuit 4 only when necessary, the power consumption of the replica circuit 4 can be reduced.

[0047] The second ADC 5 performs A / D conversion only when the first enable signal EN1 is at a predetermined logic level. The second reference voltage VREF2 is input to the second ADC 5 at the timing when the first enable signal EN1 becomes at the predetermined logic level. This also reduces power consumption in the second ADC 5.

[0048] 2 is a block diagram showing an example of the circuit configuration within the output stage circuit 3. As shown in FIG. 2, for example, p-type MOS transistors (hereinafter simply referred to as transistors) are provided within the output stage circuit 3. A control circuit 6 outputs a control signal for controlling the number of transistors to be turned on within the output stage circuit 3. The control signal changes the number of transistors to be turned on, and the on-resistance of the output stage circuit 3 changes.

[0049] FIG. 3A is a diagram showing the characteristics of a transistor in output stage circuit 3. The horizontal axis of FIG. 3A is the output voltage Vout, and the vertical axis is the drain current of the transistor in output stage circuit 3. Curves W1 to W3 in FIG. 3A show the relationship between the output voltage Vout and the drain current when the gate-source voltage Vgs of the transistor in output stage circuit 3 is changed in three ways (when the power supply voltage is different). Curve W1 represents the characteristic curve when Vgs=0.6V, curve W2 represents the characteristic curve when Vgs=0.65V, and curve W3 represents the characteristic curve when Vgs=0.7V. As shown in the figure, the higher the gate-source voltage, the larger the drain current and the higher the transistor's performance.

[0050] FIG. 3A shows three drain current lines W4 to W6, each having a different current value. The order of the magnitude of the drain current is W4 <W5<W6である。

[0051] FIG. 3B is a diagram showing the amount of fluctuation in the output voltage Vout due to fluctuations in the load current. Curves W7 to W9 in FIG. 3B correspond to the lines W4 to W6 in FIG. 3A, respectively. As shown in FIG. 3B, when the load current fluctuates, the output voltage Vout changes, but the larger Vgs is, the smaller the amount of fluctuation in the output voltage Vout due to fluctuations in the load current becomes. As shown in FIG. 3B, the degree to which the output voltage Vout temporarily drops when the load current suddenly increases is called the droop characteristic, and the smaller Vgs is, the greater the amount of drop in the output voltage Vout, resulting in a worsening of the droop characteristic.

[0052] As can be seen from FIGS. 3A and 3B, the higher the transistor capability in the output stage circuit 3, the better the droop characteristics will be, but this may result in unstable circuit operation, an increased ripple voltage, and a deterioration in noise characteristics.

[0053] The digitally controlled regulator 1 shown in FIG. 1 includes a replica circuit 4 having the same circuit configuration as the output stage circuit 3, and a second ADC 5 generates a second digital signal D2 corresponding to the differential voltage between the replica voltage output from the replica circuit 4 and a second reference voltage VREF2. This second digital signal D2 is a signal containing performance information about the replica circuit 4. A control circuit 6 controls the gain of the output stage circuit 3 based on the first digital signal D1 corresponding to the differential voltage between the output voltage Vout and the first reference voltage VREF1, and the second digital signal D2. This allows the control circuit 6 to control the gain of the output stage circuit 3 taking into account performance information about the output stage circuit 3, such as the input voltage, output voltage Vout, manufacturing process, and temperature, making it possible to improve stability, transient response, and ripple characteristics, which are normally in a trade-off relationship.

[0054] As described above, the output stage circuit 3 and replica circuit 4 in FIG. 1 have the same circuit configuration, but various modifications are possible for the specific circuit configurations of the output stage circuit 3 and replica circuit 4.

[0055] FIG. 4 is a block diagram showing a first specific example of a digitally controlled regulator 1a. The output stage circuit 3 and replica circuit 4 in the digitally controlled regulator 1a in FIG. 4 have n-type MOS transistors (hereinafter referred to as transistors). The output stage circuit 3 has, for example, multiple transistors connected in parallel between a power supply voltage node and an output node. Although only one transistor may be present in the output stage circuit 3, the following describes an example in which multiple transistors are connected in parallel. A control signal is supplied from a control circuit 6 to the gates of the multiple transistors in the output stage circuit 3. The on-resistance of the output stage circuit 3 is controlled by this control signal.

[0056] The replica circuit 4 has only one transistor that is identical to the transistor connected in parallel in the output stage circuit 3.

[0057] The replica circuit 4 outputs a replica voltage only when the first enable signal EN1 is at a predetermined logic level. Similarly, the output stage circuit 3 outputs the output voltage Vout only when the second enable signal EN2 is at a predetermined logic level. Although the first enable signal EN1 and the second enable signal EN2 are not necessarily required, providing the first enable signal EN1 and the second enable signal EN2 can reduce the power consumption of the performance correction circuit 8, which includes the replica circuit 4 and the second ADC 5, and the digital LDO circuit 7, which includes the first ADC 2, the control circuit 6, and the output stage circuit 3.

[0058] The second ADC 5 has a comparator 11, a variable current source 12, and a control unit 13. The comparator 11 outputs a signal corresponding to the differential voltage between the replica voltage and the second reference voltage VREF2. The variable current source 12 controls the voltage level of the replica voltage by adjusting the current flowing to the output node of the replica circuit 4. The variable current source 12 is connected between the output node and a ground node in the replica circuit 4. More specifically, the variable current source 12 is connected between the source of a transistor in the replica circuit 4 and the ground node.

[0059] The control unit 13 adjusts the current flowing through the variable current source 12 through the output node based on the output signal of the comparator 11, and generates a second digital signal D2 including on-resistance information of the replica circuit 4 for matching the replica voltage to the second reference voltage VREF2. More specifically, the control unit 13 generates an adjustment signal for adjusting the current of the variable current source 12 based on the signal output from the comparator 11. For example, if the replica voltage is lower than the second reference voltage VREF2, the control unit 13 generates the adjustment signal to reduce the current flowing through the variable current source 12.

[0060] The control circuit 6 generates a control signal for controlling the gain of the output stage circuit 3 based on the first digital signal D1 output from the first ADC 2 and the second digital signal D2 including on-resistance information of the replica circuit 4. This control signal controls the on-resistance of the output stage circuit 3. The on-resistance of the output stage circuit 3 varies depending on performance information of the output stage circuit 3, such as the input voltage, output voltage Vout, manufacturing process, and temperature. This change in on-resistance affects the drain current and output voltage Vout. Therefore, in this embodiment, a replica circuit 4 having the same circuit configuration as the output stage circuit 3 is used, and the second ADC 5 detects on-resistance information of the replica circuit 4 and supplies it to the control circuit 6. As a result, the control circuit 6 can control the on-resistance of the output stage circuit 3 taking into account the performance information of the output stage circuit 3.

[0061] FIG. 5 is a block diagram showing a second specific example of a digitally controlled regulator 1b. The output stage circuit 3 and replica circuit 4 in the digitally controlled regulator 1b in FIG. 5 have resistive elements. More specifically, they have resistive elements 4a and switches 4b connected in series between the power supply voltage node and the output node. The switches 4b are used to switch whether or not to use the resistive element 4a. The output stage circuit 3 has multiple sets of resistive elements 3a and switches 3b connected in series connected in parallel. Any of the multiple sets of resistive elements 3a can be selected by the switches 3b. The replica circuit 4 has the same resistive elements 4a and switches 4b as those in the output stage circuit 3.

[0062] 4, the second ADC 5 has a comparator 11, a variable current source 12, and a control unit 13. The variable current source 12 is connected between the output node of the replica circuit 4 and the ground node. The control unit 13 performs the same operation as the control unit 13 in FIG. 4. That is, the control unit 13 adjusts the current flowing through the output node to the variable current source 12 based on the output signal of the comparator 11, and generates a second digital signal D2 including on-resistance information of the replica circuit 4 for matching the replica voltage with the second reference voltage VREF2.

[0063] FIG. 6 is a block diagram showing a third example of a digitally controlled regulator 1c. The output stage circuit 3 and replica circuit 4 in the digitally controlled regulator 1c in FIG. 6 have p-type MOS transistors. As such, the digitally controlled regulator 1c in FIG. 6 has transistors of different conductivity types in the output stage circuit 3 and replica circuit 4 compared to the digitally controlled regulator 1a in FIG. 4. As a result, the logic of the control signal output from the control circuit 6 is reversed, but the circuit operation of the digitally controlled regulators 1a and 1c is the same. Furthermore, the digitally controlled regulator 1c in FIG. 6 includes a variable resistor 12a instead of the variable current source 12. The resistance value of the variable resistor 12a is adjusted by an adjustment signal from the control unit 13, thereby controlling the replica voltage output from the replica circuit 4.

[0064] 4 to 6, the control unit 13 in the second ADC 5 supplies the second digital signal D2 including the on-resistance information of the replica circuit 4 to the control circuit 6. This allows the control circuit 6 to generate a control signal taking the on-resistance information of the replica circuit 4 into consideration.

[0065] 4 to 6 show an example in which a variable current source 12 is provided in the second ADC 5 and the current flowing through the variable current source 12 is controlled by the control unit 13 so that the replica voltage is equal to the second reference voltage VREF2. However, instead of the variable current source 12, a constant current source that flows a constant current may be provided, and the number of connection stages of transistors and resistors in the output stage circuit 3 and the replica circuit 4 may be varied, and information about the number of connection stages may be included in the second digital signal D2 as on-resistance information and supplied to the control circuit 6.

[0066] FIG. 7 is a block diagram showing a fourth specific example of a digitally controlled regulator 1d. The output stage circuit 3 and replica circuit 4 in the digitally controlled regulator 1d in FIG. 7 each have a plurality of p-type MO transistors (hereinafter simply referred to as transistors) whose number of connection stages can be changed. Each transistor is connected between a power supply voltage node and an output node. The more transistors connected in the output stage circuit 3 and replica circuit 4, the smaller the on-resistance of the output stage circuit 3 and replica circuit 4.

[0067] The second ADC 5 includes a comparator 11, a constant current source 12b, and a control unit 13. The comparator 11 outputs a signal corresponding to the differential voltage between the replica voltage and the second reference voltage VREF2. The constant current source 12b is connected between the output node of the replica circuit 4 and the ground node, and supplies a constant current. The control unit 13 adjusts the number of connected transistors in the replica circuit 4 based on the output signal of the comparator 11 and generates a second digital signal D2 containing on-resistance information of the replica circuit 4 for matching the replica voltage to the second reference voltage VREF2. More specifically, the control unit 13 generates an adjustment signal so that the replica voltage matches the second reference voltage VREF2. This adjustment signal is supplied to the replica circuit 4. The replica circuit 4 adjusts the number of connected transistors in the replica circuit 4 based on the adjustment signal. Each transistor in the replica circuit 4 is always on, and the replica circuit 4 adjusts the number of connected transistors in the on-state using the adjustment signal. For example, when the replica voltage is lower than the second reference voltage VREF2, the control unit 13 increases the number of connected transistor stages in the replica circuit 4. This reduces the on-resistance of the replica circuit 4, and increases the replica voltage.

[0068] The on-resistance of the replica circuit 4 varies depending on the number of connected stages of transistors in the replica circuit 4. The control unit 13 supplies a second digital signal D2 including on-resistance information of the replica circuit 4 to the control circuit 6. The control circuit 6 generates a control signal based on the first digital signal D1 and the second digital signal D2, and controls the number of connected stages of transistors in the output stage circuit 3.

[0069] Fig. 8 is a block diagram showing a fifth specific example of a digitally controlled regulator 1e. The output stage circuit 3 and replica circuit 4 in the digitally controlled regulator 1e in Fig. 8 each have a plurality of n-type MOS transistors (hereinafter simply referred to as transistors) whose number of connection stages can be changed. That is, the digitally controlled regulators 1e in Fig. 7 and Fig. 8 have transistors of different conductivity types in the output stage circuit 3 and replica circuit 4, and accordingly, the logic of the control signal output by the control circuit 6 also changes.

[0070] 8, the control unit 13 in the second ADC 5 also supplies a second digital signal D2 including on-resistance information of the replica circuit 4 to the control circuit 6. The control circuit 6 controls the number of connected transistor stages in the output stage circuit 3 based on the first digital signal D1 and the second digital signal D2.

[0071] FIG. 9 is a block diagram illustrating a sixth example of a digitally controlled regulator 1f. The digitally controlled regulator 1f of FIG. 9 includes multiple resistor circuits, the number of which can be changed, in the output stage circuit 3 and replica circuit 4. Each resistor circuit includes resistor elements 3a and 4a and switches 3b and 4b connected in series between the power supply voltage node and the output node. Turning on the switches 3b and 4b selects the resistor elements 3a and 4a connected to the switches 3b and 4b. Turning on or off the switches 3b and 4b for each resistor circuit controls the number of resistor elements 3a and 4a connected in parallel between the power supply voltage node and the output node. Increasing the number of resistor elements connected in parallel in the replica circuit 4 reduces the on-resistance of the replica circuit 4. In the digitally controlled regulator 1f of FIG. 9, the control unit 13 in the second ADC 5 also supplies a second digital signal D2 containing information about the on-resistance of the replica circuit 4 to the control circuit 6.

[0072] Fig. 10 is a block diagram showing a seventh specific example of a digitally controlled regulator 1g. The digitally controlled regulator 1g in Fig. 10 has the same circuit configuration as the digitally controlled regulator 1d in Fig. 7, except that the constant current source in the digitally controlled regulator 1d in Fig. 7 is replaced with a resistive element.

[0073] 7 to 10, similar to the digitally controlled regulators 1a, 1b, and 1c of FIGS. 4 to 6, the second ADC 5 includes on-resistance information of the replica circuit 4 in a second digital signal D2 and supplies the second digital signal D2 to the control circuit 6. The control circuit 6 generates a control signal for controlling the gain of the output stage circuit 3 based on the first digital signal D1 and the second digital signal D2. This makes it possible to control the output voltage Vout taking into account the performance information of the output stage circuit 3.

[0074] The replica circuit 4 and second ADC 5 in the digitally controlled regulators 1, 1a, 1b, 1c, 1d, 1e, 1f, and 1g shown in FIGS. 1, 4, and 10 constitute a performance correction circuit 8 that corrects the performance of the output stage circuit 3. Meanwhile, the output stage circuit 3, first ADC 2, and control circuit 6 constitute a digital LDO circuit. The digital LDO circuit performs feedback control using the first ADC 2 and control circuit 6 so that the output voltage Vout matches the first reference voltage VREF1. The performance correction circuit 8 generates performance information for the replica circuit 4. The control circuit 6 can correct the performance of the output stage circuit 3 by generating a control signal taking into account not only the first digital signal D1 but also the second digital signal D2 output from the second ADC 5.

[0075] There are several possible timings for the capacity correction circuit 8 to perform capacity correction. Fig. 11 is a flowchart showing an example of a processing procedure for correcting the capacity of the digital LDO operation and the output stage circuit 3. Fig. 11 shows the processing procedure performed by any of the digitally controlled regulators 1, 1a, 1b, 1c, 1d, 1e, 1f, and 1g shown in Figs. 1, 4 to 10.

[0076] First, before starting digital LDO operation, capacity correction is performed (step S1). Once capacity correction is complete (step S2), it is determined whether or not capacity correction should be performed only at startup of digital LDO operation (step S3). If it is determined that capacity correction should be performed only at startup, the operation of the capacity correction circuit 8, which includes the replica circuit 4 and the second ADC 5, is stopped (step S4), and digital LDO operation is started (step S5). In step S4, for example, the replica circuit 4 is disabled so that the replica circuit 4 does not output a replica voltage. Alternatively, the supply of power supply voltage to the replica circuit 4 and the second ADC 5 may be cut off. This reduces power consumption in the replica circuit 4 and the second ADC 5.

[0077] Next, if the determination in step S3 is NO, it is determined whether or not to perform intermittent capacity correction (step S6). If it is determined in step S6 that intermittent capacity correction is to be performed, the operation of the capacity correction circuit 8 is stopped (step S7), and digital LDO operation is started (step S8). Thereafter, it is determined again whether or not the timing for intermittent capacity correction has been reached (step S9). If the timing for capacity correction has arrived, the capacity correction circuit 8 is operated (step S10), and the second ADC 5 outputs the second digital signal D2 (step S11). In this way, in step S11, the second digital signal D2 is updated each time intermittent capacity correction is performed. When the processing in step S11 is completed, the processing from step S7 onwards is repeated. If the determination in step S6 is NO, capacity correction is continuously performed during digital LDO operation (steps S12 and S13).

[0078] Fig. 12 is a timing diagram for the case where the answer to step S3 in Fig. 11 is YES, i.e., where performance correction is performed only at startup. Fig. 12 shows the signal waveforms of the first enable signal EN1 of the performance correction circuit 8 having the replica circuit 4 and the second ADC 5, the second enable signal EN2 of the digital LDO circuit 7 having the first ADC 2, the control circuit 13, and the output stage circuit 3, the second digital signal D2, the first reference voltage VREF1, the second reference voltage VREF2, and the output voltage Vout.

[0079] 12, the period from time t1 to time t3 is before the digital LDO operation starts, and the first enable signal EN1 input to the replica circuit 4 becomes high during the period from time t1 to time t2. As a result, the performance correction circuit 8, which includes the replica circuit 4 and the second ADC 5, performs a performance correction process during the period from time t1 to time t2. Specifically, the second reference voltage VREF2 is input to the second ADC 5 during the period from time t1 to time t2. At time t2, the second ADC 5 outputs a second digital signal D2 containing information about the on-resistance of the replica circuit 4. At time t2, the replica circuit 4 is disabled, and the second reference voltage VREF2 is no longer input to the second ADC 5, but the second ADC 5 retains the second digital signal D2 output at time t2.

[0080] After that, from time t3 onwards, the first reference voltage VREF1 is input to the first ADC2, and the digital LDO operates. At this time, the control circuit 6 generates a control signal based on the first digital signal D1 and the second digital signal D2. This control signal is a signal that reflects the digital LDO operation and performance correction of the output stage circuit 3. As a result, the output stage circuit 3 outputs the output voltage Vout that has been subjected to performance correction of the output stage circuit 3.

[0081] The timing at which the performance correction circuit 8 including the replica circuit 4 and the second ADC 5 performs the performance correction may be timed to coincide with the start of the digital LDO operation, rather than before the digital LDO operation.

[0082] FIG. 13 is a timing diagram showing the performance correction circuit 8 performing performance correction in synchronization with the start of digital LDO operation. During the period from time t3 to t4 in FIG. 13, the first enable signal EN1 of the replica circuit 4 goes high, and the second reference voltage VREF2 is input to the second ADC 5. Therefore, after time t3, the output voltage Vout resulting from the digital LDO operation is output. Also, at time t4, the second ADC 5 outputs a second digital signal D2 including on-resistance information of the replica circuit 4. After time t4, a control signal that takes into account the performance correction of the output stage circuit 3 is output from the control unit 13. Therefore, after time t4, the output stage circuit 3 outputs the output voltage Vout resulting from the performance correction of the output stage circuit 3.

[0083] The digitally controlled regulators 1-1g described above may perform intermittent capacity correction using the capacity correction circuit 8. FIG. 14 is a timing diagram showing intermittent capacity correction. The capacity correction circuit 8 performs capacity correction of the output stage circuit 3 during the period from time t1 to t2 before digital LDO operation is started, and during the period from time t4 to t5 after digital LDO operation is started. Although not shown in FIG. 14, the capacity correction circuit 8 also performs intermittent capacity correction during the digital LDO operation period after time t5.

[0084] 14 shows an example in which the output stage circuit 3 switches the voltage level of the output voltage Vout at time t4, and the performance correction circuit 8 performs performance correction in accordance with the timing at which the voltage level of the output voltage Vout switches. This is because when the output voltage Vout of the output stage circuit 3 changes, the droop characteristics, ripple characteristics, etc. change.

[0085] 14, when the voltage level of the output voltage Vout changes, the first enable signal EN1 of the replica circuit 4 goes high and enters an enabled state during the period from time t4 to t5. Also, during the period from time t4 to t5, the second reference voltage VREF2 is input to the second ADC 5. The second ADC 5 outputs a second digital signal D2 including performance information of the replica circuit 4 at time t5, and after time t5, the output stage circuit 3 outputs the output voltage Vout that takes into account the performance correction of the output stage circuit 3.

[0086] When the capacity correction is performed intermittently, the capacity correction may be performed at regular time intervals, or, as at time t4 in Figure 14, after the digital LDO operation has started, the capacity correction may be performed only when the voltage level of the output voltage Vout of the output stage circuit 3 changes.

[0087] In FIG. 14, performance correction is performed when the voltage level of the output voltage Vout is switched. However, as shown in the timing diagram of FIG. 15, performance correction may be performed prior to the timing of switching the voltage level of the output voltage Vout. FIG. 15 illustrates an example in which performance correction is performed during the period from time t1 to t2 before the digital LDO operation begins, and during the period from time t4 to t5 immediately before time t5, when the voltage level of the output voltage Vout is switched after the digital LDO operation begins. Because the digitally controlled regulators 1 to 1g know the timing of switching the voltage level of the output voltage Vout, performance correction can also be performed during the period from time t4 to t5 immediately before switching the voltage level of the output voltage Vout. This allows the second ADC 5 to output a second digital signal D2 containing performance information about the replica circuit 4 at time t5. Therefore, the output voltage Vout with the performance of the output stage circuit 3 corrected can be output after time t5, when the voltage level of the output voltage Vout is switched. That is, when the voltage level of the output voltage Vout is switched, the output voltage Vout whose capacity has been corrected can be output from the point of switching.

[0088] The digitally controlled regulators 1 to 1 g may continuously perform capacity correction using the capacity correction circuit 8. FIGS. 16 and 17 are timing diagrams for continuous capacity correction. FIG. 16 shows a timing diagram for continuous capacity correction, starting before digital LDO operation begins. FIG. 17 shows an example of continuous capacity correction, timed to coincide with the start of digital LDO operation.

[0089] At time t1 in FIG. 16, the first enable signal EN1 input to the replica circuit 4 goes high, entering an enable state. The first enable signal EN1 remains high after time t1. Furthermore, the second reference voltage VREF2 continues to be input to the second ADC 5 after time t1. At time t2, the second ADC 5 outputs a second digital signal D2 containing performance information about the replica circuit 4. Because the second ADC 5 continues to operate after time t2, the second digital signal D2 is updated as needed in accordance with the performance information about the replica circuit 4. At time t3, the second enable signal EN2 input to the output stage circuit 3 goes high, entering an enable state. Furthermore, the first reference voltage VREF1 continues to be input to the first ADC 2 after time t3. The control circuit 6 generates a control signal based on the first digital signal D1 output from the first ADC 2 and the second digital signal D2 output from the second ADC 5. The output stage circuit 3 outputs the output voltage Vout, which takes into account the performance correction of the output stage circuit 3, based on the control signal, from time t3 onwards.

[0090] In FIG. 17, at time t2, the first enable signal EN1 input to the replica circuit 4 and the second enable signal EN2 input to the output stage circuit 3 both go high, and the replica circuit 4 and the output stage circuit 3 remain enabled from time t2 onward. Also at time t2, the first reference voltage VREF1 is input to the first ADC2, and the second reference voltage VREF2 is input to the second ADC5. The first reference voltage VREF1 and the second reference voltage VREF2 are continuously input to the first ADC2 and the second ADC5, respectively, from time t2 onward. From time t3 onward, the second ADC5 outputs a second digital signal D2 containing on-resistance information of the replica circuit 4. From time t3 onward, the second digital signal D2 is continuously updated based on the most recent on-resistance information of the replica circuit 4. From time t3 onward, the output stage circuit 3 continuously outputs the output voltage Vout that takes into account the performance correction of the output stage circuit 3.

[0091] The output voltage Vout output from the output stage circuit 3, the first reference voltage VREF1 input to the first ADC 2, and the second reference voltage VREF2 input to the second ADC 5 all have related voltage levels.

[0092] Fig. 18 is a block diagram showing an example of the schematic configuration of a digitally controlled regulator 1h according to this embodiment. The digitally controlled regulator 1h in Fig. 18 has a more specific configuration than the digitally controlled regulator 1 in Fig. 1. In Fig. 18, components that are common to Fig. 1 are given the same reference numerals, and the following description will focus on the differences.

[0093] The digitally controlled regulator 1h of FIG. 18 includes, in addition to the configuration of FIG. 1, a first reference voltage generating circuit 14 that generates a first reference voltage VREF1, a second reference voltage generating circuit 15 that generates a second reference voltage VREF2, and a variable load circuit 16.

[0094] The first reference voltage generating circuit 14 has a first current source 17 and a first variable resistor 18 connected in series between a power supply voltage node and a ground node. The second reference voltage generating circuit 15 has a second current source 19 and a second variable resistor 20 connected in series between a power supply voltage node and a ground node.

[0095] The variable load circuit 16 is connected between the output node of the replica circuit 4 and the ground node, and its resistance value is variably controlled by an adjustment signal from the second ADC 5. A specific example of the variable load circuit 16 is the variable current source 12 or variable resistor shown in FIGS.

[0096] In the digitally controlled regulator 1h of Fig. 18, the control circuit 6 performs feedback control so that the output voltage Vout coincides with the first reference voltage VREF1. In this case, the second reference voltage VREF2 input to the second ADC 5 is set to the same voltage level as the first reference voltage VREF1. Therefore, in the digitally controlled regulator 1h of Fig. 18, in a stable state, the output voltage Vout = first reference voltage VREF1 = second reference voltage VREF2.

[0097] When the voltage level of the output voltage Vout is high, power consumption increases if the first reference voltage VREF1 and the second reference voltage VREF2 are set to the same voltage level as the output voltage Vout. Therefore, a circuit design may be implemented to lower the voltage levels of the first reference voltage VREF1 and the second reference voltage VREF2 below the output voltage Vout.

[0098] FIG. 19 is a block diagram of a digitally controlled regulator 1i according to a modified example. In addition to the circuit configuration of FIG. 18, FIG. 19 further includes a resistive voltage divider circuit 21 and a voltage amplifier 22. The resistive voltage divider circuit 21 is connected between the output node of the output stage circuit 3 and the ground node, and divides the output voltage Vout. The divided voltage obtained by the resistive voltage divider circuit 21 is input to the first ADC2. The resistive voltage divider circuit 21 generates a divided voltage that is 1 / A times the output voltage Vout. The first ADC2 generates a first digital signal D1 that corresponds to the differential voltage between the divided voltage and the first reference voltage VREF1. Feedback control is performed so that the divided voltage ultimately becomes equal to the first reference voltage VREF1, thereby enabling the voltage level of the first reference voltage VREF1 to be lowered.

[0099] On the other hand, the replica circuit 4 outputs a replica voltage having a voltage level similar to that of the output stage circuit 3. The second reference voltage VREF2 is set to the same voltage level as the first reference voltage VREF1. Therefore, the second reference voltage VREF2 is multiplied by A in the voltage amplifier 22 to make it approximately the same voltage level as the replica voltage.

[0100] In this way, in the configuration of Figure 19, by providing the resistive voltage divider circuit 21 and the voltage amplifier 22, even if the voltage level of the output voltage Vout is high, the voltage levels of the first reference voltage VREF1 and the second reference voltage VREF2 can be kept low, thereby reducing power consumption.

[0101] As described above, in this embodiment, a replica circuit 4 having the same circuit configuration as the output stage circuit 3 is provided, and the second digital signal D2 including performance information of the replica circuit 4 is supplied to the control circuit 6. Therefore, when performing digital LDO operation, the control circuit 6 can output the output voltage Vout taking into account the performance information of the output stage circuit 3. Therefore, it is possible to generate an output voltage Vout that is not dependent on performance information such as the input voltage of the output stage circuit 3, the output voltage Vout, the manufacturing process, and temperature.

[0102] Furthermore, according to this embodiment, even if the load current changes, the fluctuations in the ripple voltage and the fluctuations in the droop characteristics can be suppressed.

[0103] Furthermore, according to this embodiment, the influence of performance variations in the output stage circuit 3 is reduced, so there is no need to complicate the circuit configuration inside the digitally controlled regulators 1 to 1i, and stability can be improved. More specifically, this embodiment does not require a multiple loop configuration for digital LDO operation, making control easier and improving stability.

[0104] Furthermore, according to this embodiment, a circuit can be configured that requires a lower voltage and a smaller area than the analog-controlled current capability correction circuit 8, and integration is also easier, which also reduces manufacturing costs.

[0105] The present technology can be configured as follows: (1) a first AD converter that generates a first digital signal according to a differential voltage between an output voltage and a first reference voltage; an output stage circuit for generating the output voltage; a replica circuit having the same circuit configuration as the output stage circuit and outputting a replica voltage related to the output voltage; a second AD converter that generates a second digital signal according to a differential voltage between the replica voltage and a second reference voltage; a control circuit that generates a control signal that controls a gain of the output stage circuit based on the first digital signal and the second digital signal. (2) The digitally controlled regulator according to (1), wherein the output stage circuit and the replica circuit are circuits of the same circuit configuration including transistors of the same conductivity type and the same size. (3) The digitally controlled regulator according to (1), wherein the output stage circuit and the replica circuit are circuits having the same circuit configuration including resistor elements with the same resistance value. (4) The digitally controlled regulator according to any one of (1) to (3), wherein the second digital signal includes capability information of the replica circuit. (5) The digital control regulator according to (4), wherein the control circuit generates the control signal so that the output voltage is not affected by fluctuations due to performance information of the output stage circuit. (6) The digitally controlled regulator according to (4) or (5), wherein the capability information includes at least one of information on the input voltage, output voltage, manufacturing process, and temperature of the replica circuit or the output stage circuit. (7) The digitally controlled regulator according to any one of (1) to (6), wherein the second digital signal includes on-resistance information of the replica circuit. (8) The digitally controlled regulator according to (7), wherein the control circuit generates the control signal based on the second digital signal so that the on-resistance of the output stage circuit matches the on-resistance of the replica circuit. (9) The replica circuit outputs the replica voltage before the output stage circuit and the control circuit start feedback control of the output voltage or in synchronization with the start timing of the feedback control; The digitally controlled regulator according to any one of (1) to (8), wherein the second AD converter generates the second digital signal before the output stage circuit and the control circuit start feedback control of the output voltage, or in synchronization with the start timing of the feedback control. (10) The replica circuit outputs the replica voltage in synchronization with a timing at which the voltage level of the output voltage is switched while the output stage circuit and the control circuit are performing feedback control of the output voltage; The digitally controlled regulator according to (9), wherein the second AD converter generates the second digital signal in synchronization with the timing at which the voltage level of the output voltage is switched while the output stage circuit and the control circuit are performing feedback control of the output voltage. (11) The replica circuit outputs the replica voltage a predetermined period before a timing at which the voltage level of the output voltage is switched while the output stage circuit and the control circuit are performing feedback control of the output voltage; The digitally controlled regulator according to (9) or (10), wherein the second AD converter generates the second digital signal in accordance with the timing at which the output stage circuit and the control circuit switch the voltage level of the output voltage while performing feedback control of the output voltage. (12) The replica circuit intermittently outputs the replica voltage while the output stage circuit and the control circuit are performing feedback control of the output voltage, The digitally controlled regulator according to any one of (1) to (8), wherein the second AD converter intermittently generates the second digital signal while the output stage circuit and the control circuit are performing feedback control of the output voltage. (13) The replica circuit continuously outputs the replica voltage while the output stage circuit and the control circuit are performing feedback control of the output voltage, The digitally controlled regulator according to any one of (1) to (8), wherein the second AD converter continuously generates the second digital signal while the output stage circuit and the control circuit are performing feedback control of the output voltage. (14) The digitally controlled regulator according to any one of (9) to (13), wherein the replica circuit outputs the replica voltage when an enable signal has a predetermined logic, and stops outputting the replica voltage when the enable signal has a logic other than the predetermined logic. (15) The digitally controlled regulator according to (14), wherein the second reference voltage is input to the second AD converter in synchronization with the timing at which the enable signal becomes the predetermined logic level. (16) The second AD converter a comparator that outputs a signal according to a differential voltage between the replica voltage and the second reference voltage; a variable load circuit that controls a voltage level of the replica voltage by adjusting a current flowing through an output node of the replica circuit; a control unit that adjusts a current flowing through the output node to the variable load circuit based on an output signal of the comparator, and generates the second digital signal including on-resistance information of the replica circuit for matching the replica voltage to the second reference voltage. (17) The replica circuit is capable of adjusting the number of connected stages of transistors or resistor elements; The second AD converter a comparator that outputs a signal according to a differential voltage between the replica voltage and the second reference voltage; a control unit that adjusts the number of connected stages of transistors or resistor elements in the replica circuit based on the output signal of the comparator, and generates the second digital signal including on-resistance information of the replica circuit for matching the replica voltage with the second reference voltage. (18) The output stage circuit is capable of adjusting the number of connected stages of transistors or resistor elements, The digitally controlled regulator according to any one of (1) to (17), wherein the control circuit, based on the second digital signal, makes the number of connected stages of transistors or resistor elements in the output stage circuit the same as the number of connected stages of transistors or resistor elements in the replica circuit. (19) The control circuit performs feedback control so that the output voltage is equal to the first reference voltage, The digitally controlled regulator according to any one of (1) to (18), wherein the first reference voltage and the second reference voltage are at the same voltage level. (20) The control circuit performs feedback control so that a voltage obtained by dividing the output voltage by 1 / A (A is a real number greater than 1) becomes equal to the first reference voltage, the second reference voltage is set to the same voltage level as the first reference voltage; The digitally controlled regulator according to any one of (1) to (18), wherein the second AD converter compares the replica voltage with a voltage obtained by multiplying the second reference voltage by A.

[0106] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0107] 1, 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1i digitally controlled regulator, 2 first ADC, 3 output stage circuit, 4 replica circuit, 5 second ADC, 6 control circuit, 7 digital LDO circuit, 8 capacity correction circuit, 11 comparator, 12 variable current source, 13 control unit, 14 first reference voltage generation circuit, 15 second reference voltage generation circuit, 16 variable load circuit, 17 first current source, 18 first variable resistor, 19 second current source, 20 second variable resistor

Claims

1. a first AD converter that generates a first digital signal corresponding to a differential voltage between the output voltage and a first reference voltage; an output stage circuit for generating the output voltage; a replica circuit having the same circuit configuration as the output stage circuit and outputting a replica voltage related to the output voltage; a second AD converter that generates a second digital signal according to a differential voltage between the replica voltage and a second reference voltage; a control circuit that generates a control signal that controls a gain of the output stage circuit based on the first digital signal and the second digital signal.

2. 2. The digitally controlled regulator according to claim 1, wherein the output stage circuit and the replica circuit are circuits having the same circuit configuration including transistors of the same conductivity type and the same size.

3. 2. The digitally controlled regulator according to claim 1, wherein the output stage circuit and the replica circuit are circuits having the same circuit configuration including resistor elements having the same resistance value.

4. The digitally controlled regulator of claim 1 , wherein the second digital signal includes capability information of the replica circuit.

5. 5. The digitally controlled regulator according to claim 4, wherein the control circuit generates the control signal so that the output voltage is not subject to fluctuations due to performance information of the output stage circuit.

6. 5. The digitally controlled regulator according to claim 4, wherein the capability information includes at least one of information on an input voltage, an output voltage, a manufacturing process, and a temperature of the replica circuit or the output stage circuit.

7. The digitally controlled regulator of claim 1 , wherein the second digital signal includes on-resistance information of the replica circuit.

8. 8. The digitally controlled regulator according to claim 7, wherein the control circuit generates the control signal based on the second digital signal so that an on-resistance of the output stage circuit matches an on-resistance of the replica circuit.

9. the replica circuit outputs the replica voltage before the output stage circuit and the control circuit start feedback control of the output voltage or in synchronization with the start timing of the feedback control; 2. The digitally controlled regulator according to claim 1, wherein the second AD converter generates the second digital signal before the output stage circuit and the control circuit start feedback control of the output voltage or in synchronization with start timing of the feedback control.

10. the replica circuit outputs the replica voltage in synchronization with a timing at which the voltage level of the output voltage is switched while the output stage circuit and the control circuit are performing feedback control of the output voltage; 10. The digitally controlled regulator according to claim 9, wherein the second AD converter generates the second digital signal in synchronization with a timing at which the voltage level of the output voltage is switched while the output stage circuit and the control circuit are performing feedback control of the output voltage.

11. the replica circuit outputs the replica voltage a predetermined period before a timing at which the voltage level of the output voltage is switched while the output stage circuit and the control circuit are performing feedback control of the output voltage; 10. The digitally controlled regulator according to claim 9, wherein the second AD converter generates the second digital signal in accordance with a timing at which the voltage level of the output voltage is switched while the output stage circuit and the control circuit are performing feedback control of the output voltage.

12. the replica circuit intermittently outputs the replica voltage while the output stage circuit and the control circuit are performing feedback control of the output voltage; 2. The digitally controlled regulator according to claim 1, wherein the second AD converter generates the second digital signal intermittently while the output stage circuit and the control circuit are performing feedback control of the output voltage.

13. the replica circuit continuously outputs the replica voltage while the output stage circuit and the control circuit are performing feedback control of the output voltage; 2. The digitally controlled regulator according to claim 1, wherein the second AD converter generates the second digital signal continuously while the output stage circuit and the control circuit are performing feedback control of the output voltage.

14. 10. The digitally controlled regulator according to claim 9, wherein the replica circuit outputs the replica voltage when an enable signal has a predetermined logic level, and stops outputting the replica voltage when the enable signal has a logic level other than the predetermined logic level.

15. 15. The digitally controlled regulator according to claim 14, wherein the second reference voltage is input to the second AD converter in synchronization with the timing at which the enable signal becomes the predetermined logic level.

16. The second AD converter a comparator that outputs a signal corresponding to a differential voltage between the replica voltage and the second reference voltage; a variable load circuit that controls a voltage level of the replica voltage by adjusting a current flowing through an output node of the replica circuit; 2. The digitally controlled regulator according to claim 1, further comprising: a control unit that adjusts a current flowing through the output node to the variable load circuit based on an output signal of the comparator, and generates the second digital signal including on-resistance information of the replica circuit for matching the replica voltage to the second reference voltage.

17. the replica circuit is capable of adjusting the number of connected stages of transistors or resistor elements; The second AD converter a comparator that outputs a signal corresponding to a differential voltage between the replica voltage and the second reference voltage; a control unit that adjusts a number of connected stages of transistors or resistor elements in the replica circuit based on an output signal of the comparator, and generates the second digital signal including on-resistance information of the replica circuit for matching the replica voltage with the second reference voltage.

18. the output stage circuit is capable of adjusting the number of connected stages of transistors or resistor elements; 2. The digitally controlled regulator according to claim 1, wherein the control circuit makes the number of connected stages of transistors or resistor elements in the output stage circuit the same as the number of connected stages of transistors or resistor elements in the replica circuit based on the second digital signal.

19. the control circuit performs feedback control so that the output voltage is equal to the first reference voltage; 2. The digitally controlled regulator of claim 1, wherein the first reference voltage and the second reference voltage are at the same voltage level.

20. the control circuit performs feedback control so that a voltage obtained by dividing the output voltage by 1 / A (A is a real number greater than 1) becomes equal to the first reference voltage; the second reference voltage is set to the same voltage level as the first reference voltage; 2. The digitally controlled regulator according to claim 1, wherein the second AD converter compares the replica voltage with a voltage obtained by multiplying the second reference voltage by A.

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