Analog-to-digital converter and electronic device

Abstract

The present invention reduces the size of a circuit in an SAR ADC in which a circuit for cancelling ripples is provided.　According to the present invention, a digital-analog converter generates at least one of a pair of analog signals in accordance with a predetermined control signal. A comparator compares the pair of analog signals, and generates and outputs a comparison result. A logic circuit generates the control signal on the basis of the comparison result. A plurality of switches, on the basis of the control signal, open or close paths between an output terminal of the comparator and sources or drains of a plurality of positive-side transistors having different sizes and a plurality of negative-side transistors having different sizes. A positive-side common capacitor has one end connected to a node of a predetermined positive-side reference voltage, and has the other end connected to, in a shared manner, the gates of the plurality of positive-side transistors. A negative-side capacitor has one end connected to a node of a negative-side reference voltage which is lower than the positive-side reference voltage, and has the other end connected to, in a shared manner, the gates of the plurality of negative-side transistors.

Description

[Technical Field]

[0001] The present technology relates to an analog-to-digital converter, and more particularly to a successive approximation type analog-to-digital converter and an electronic device. [Background technology]

[0002] Conventionally, Successive Approximation Register Analog-to-Digital Converters (SARADCs) have been widely used in various electronic devices due to their high resolution and low power consumption. Here, a SARADC is a circuit in which a comparator successively compares a sampled analog signal with a reference signal generated by a DAC (Digital-to-Analog Converter), and a logic circuit controls the DAC so that the two signals match. In this SARADC, when the level of the reference signal is changed, fluctuations called ripples may occur in the output signal of the DAC, and these ripples may cause errors in the comparison results of the comparator. To address this issue, a SARADC has been proposed in which a capacitance section including four capacitors and multiple switches is arranged for each bit to generate a signal that is out of phase with the ripples (see, for example, Patent Document 1). [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Xiyuan Tang, et al., A 10-bit 100-MS / s SAR ADC with Always-on Reference Ripple Cancellation, IEEE Symposium on VLSI Circuits, 2020. Summary of the Invention [Problem to be solved by the invention]

[0004] The above-mentioned conventional technology attempts to cancel the ripple by generating a signal with an opposite phase to the ripple. However, the above-mentioned SARADC requires four capacitors per bit, which creates a problem: the circuit size increases as the resolution of the SARADC increases. For example, if the resolution is 5 bits, a total of 20 capacitors must be placed within the five capacitance sections.

[0005] This technology was developed in light of these circumstances, and aims to reduce the circuit size in SARADCs that are equipped with circuits to cancel ripples. [Means for solving the problem]

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an analog-to-digital converter including: a digital-to-analog converter that generates at least one of a pair of analog signals in accordance with a predetermined control signal; a comparator that compares the pair of analog signals to generate and output a comparison result; a logic circuit that generates the control signal based on the comparison result; a plurality of positive-side transistors having different sizes; a plurality of negative-side transistors having different sizes; a plurality of switches that open and close paths between one of the sources and drains of the positive-side transistors and an output terminal of the comparator in accordance with the control signal; a positive-side common capacitor having one end connected to a node of a predetermined positive reference voltage and the other end connected in common to the gates of the positive-side transistors; and a negative-side common capacitor having one end connected to a node of a negative reference voltage lower than the positive reference voltage and the other end connected in common to the gates of the negative-side transistors, thereby achieving an effect of reducing the circuit size.

[0007] In this first aspect, the pair of analog signals may be differential signals, and the digital-to-analog converter may generate the differential signals, thereby providing an effect of reducing the circuit size of the analog-to-digital converter with differential input.

[0008] In addition, in this first aspect, the present invention may further include a sampling switch that opens and closes a path between the other end of each of the positive side common capacitance and the negative side common capacitance and a common voltage between the positive side reference voltage and the negative side reference voltage, thereby providing an effect that the reference voltage is sampled in the positive side common capacitance and the negative side common capacitance.

[0009] In addition, in this first aspect, the sampling switch may transition to a closed state within a predetermined sampling period, thereby providing the effect of sampling within the sampling period.

[0010] In addition, in this first aspect, the sampling switch may transition to a closed state within a period from the end of analog-to-digital conversion to the start of sampling, thereby achieving the effect of sampling within a period from the end of analog-to-digital conversion to the start of sampling.

[0011] In addition, in the first aspect, the circuit may further comprise a latch circuit that holds the comparison result and supplies it to the logic circuit, thereby providing an effect of holding the comparison result.

[0012] In this first aspect, each of the plurality of positive-side transistors and the plurality of negative-side transistors may be an nMOS transistor, thereby providing an effect that a current flows through a differential pair of nMOS transistors.

[0013] In this first aspect, each of the plurality of positive-side transistors and the plurality of negative-side transistors may be a pMOS transistor, thereby providing an effect that a current flows through a differential pair of pMOS transistors.

[0014] In addition, in this first aspect, the power supply may further include a plurality of pairs of common-side transistors having different sizes, and the gates of the plurality of pairs of common-side transistors may be connected to a node of a common voltage between the positive reference voltage and the negative reference voltage, thereby providing an effect that the common voltage is applied to the gates of the common-side transistors.

[0015] In addition, in this first aspect, the power supply may further include a plurality of pairs of first common-side transistors of different sizes and a plurality of pairs of second common-side transistors of different sizes, the positive common capacitance includes a first positive common capacitance and a second positive common capacitance, the negative common capacitance includes a first negative common capacitance and a second negative common capacitance, the positive transistors include a plurality of first positive transistors of different sizes and a plurality of second positive transistors of different sizes, the negative transistors include a plurality of first negative transistors of different sizes and a plurality of second negative transistors of different sizes, wherein gates of the first positive transistors are commonly connected to the first positive common capacitance, gates of the second positive transistors are commonly connected to the second positive common capacitance, gates of the first negative transistors are commonly connected to the first negative common capacitance, and gates of the second negative transistors are commonly connected to the second negative common capacitance. This provides the effect of eliminating the need for a common voltage.

[0016] According to a second aspect of the present technology, there is provided an electronic device including: a digital-to-analog converter that generates at least one of a pair of analog signals in accordance with a predetermined control signal; a comparator that compares the pair of analog signals to generate and output a comparison result; a logic circuit that generates the control signal based on the comparison result and outputs a digital signal; a plurality of positive-side transistors having different sizes; a plurality of negative-side transistors having different sizes; a plurality of switches that open and close paths between one of the sources and drains of the positive-side transistors and an output terminal of the comparator based on the control signal; a positive-side common capacitor having one end connected to a node of a predetermined positive reference voltage and the other end connected in common to the gates of the positive-side transistors; a negative-side common capacitor having one end connected to a node of a negative reference voltage lower than the positive reference voltage and the other end connected in common to the gates of the negative-side transistors; and a digital signal processing circuit that processes the digital signal, thereby achieving an effect of reducing the circuit size of the electronic device. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a block diagram showing an example of the configuration of an electronic device according to a first embodiment of the present technology. [Figure 2] 1 is a block diagram showing an example of the configuration of a SARADC according to a first embodiment of the present technology; [Figure 3] 1 is a circuit diagram showing a configuration example of a CDAC according to a first embodiment of the present technology. [Figure 4] 1 is a circuit diagram showing a configuration example of a comparator according to a first embodiment of the present technology. [Figure 5] 1 is a circuit diagram showing a configuration example of a latch circuit according to a first embodiment of the present technology. [Figure 6] 1 is a circuit diagram showing a configuration example of a ripple canceller according to a first embodiment of the present technology. [Figure 7] 3 is a diagram for explaining a connection state of a CDAC and a ripple canceller according to the first embodiment of the present technology. FIG. [Figure 8] 4A to 4C are diagrams for explaining an example of control of a switch of a ripple canceller according to the first embodiment of the present technology. [Figure 9] FIG. 10 is a circuit diagram showing a configuration example of a ripple canceller in a comparative example. [Figure 10] 4 is a timing chart showing an example of an operation of the SARADC according to the first embodiment of the present technology. [Figure 11] 1 is an example of an overall diagram of a SARADC according to a first embodiment of the present technology; [Figure 12] 10 is an example of an overall diagram of a SARADC according to a second embodiment of the present technology. [Figure 13] 10 is a timing chart showing an example of an operation of the SARADC according to the second embodiment of the present technology. [Figure 14] FIG. 10 is a circuit diagram showing a configuration example of a differential amplifier circuit according to a fourth embodiment of the present technology. [Figure 15] FIG. 13 is a circuit diagram showing a configuration example of a latch circuit according to a fourth embodiment of the present technology. [Figure 16] FIG. 13 is a circuit diagram showing a configuration example of a ripple canceller according to a fourth embodiment of the present technology. [Figure 17] FIG. 13 is a circuit diagram showing a configuration example of a ripple canceller according to a fifth embodiment of the present technology. [Figure 18] FIG. 13 is a circuit diagram showing a configuration example of a comparator unit according to a fifth embodiment of the present technology. [Figure 19] 1 is a block diagram illustrating a schematic configuration example of a vehicle control system. [Figure 20] FIG. 2 is an explanatory diagram showing an example of an installation position of an imaging unit. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described in the following order. 1. First embodiment (example of reducing the number of capacitors) 2. Second embodiment (example in which the number of capacitors is reduced and the sampling timing is changed) 3. Third embodiment (example in which the number of capacitors is reduced and the polarity of the transistors is changed) 4. Fourth embodiment (example in which the number of capacitors is reduced and a common voltage is not required) 5. Mobile Application Examples

[0019] <1. First embodiment> [Example of electronic device configuration] 1 is a block diagram showing an example configuration of an electronic device 100 according to a first embodiment of the present technology. The electronic device 100 converts analog signals into digital signals for processing, and includes an analog signal generation unit 110, an SARADC 200, and a digital signal processing unit 120. The electronic device 100 may be an imaging device, an audio device, a communication device, or the like.

[0020] The analog signal generating unit 110 generates an analog signal AIN and supplies it to the SARADC 200 via a signal line 119. The analog signal AIN may be a pixel signal, an audio signal, or an RF (Radio Frequency) signal.

[0021] The SARADC 200 converts the input analog signal AIN into a digital signal DOUT using a successive approximation method. The SARADC 200 supplies the digital signal DOUT to the digital signal processing unit 120 via a signal line 209.

[0022] The digital signal processing unit 120 performs predetermined signal processing on the digital signal DOUT. The signal processing may include image processing such as demosaic processing, audio compression processing, demodulation processing, and the like.

[0023] The number of SARADCs 200 is not limited to 1, and may be 2 or more. For example, in an imaging device, a SARADC 200 may be arranged for each column.

[0024] [SARADC configuration example] 2 is a block diagram showing an example configuration of the SARADC 200 according to the first embodiment of the present technology. The SARADC 200 includes sampling switches 211 and 212, a CDAC (Capacitor DAC) 300, a latch circuit 430, a comparator 400, and a SAR (Successive Approximation Register) logic circuit 220. The SARADC 200 further includes a ripple canceller 500.

[0025] The sampling switches 211 and 212 receive a differential analog signal from the analog signal generator 110. This differential signal (i.e., analog signal) includes a positive signal AIN_p and a negative signal AIN_n. The sampling switches 211 and 212 open and close a path between the analog signal generator 110 and the CDAC 300 in synchronization with the sampling clock CLK. For example, while the sampling clock CLK is at a high level, the sampling switches 211 and 212 are closed, and the differential signal is sampled.

[0026] The CDAC 300 generates an analog reference signal by DA (Digital to Analog) conversion. The CDAC 300 holds a sampled differential signal (analog signal) and outputs the difference between the analog signal and an internally generated reference signal (analog signal) to the comparator 400.

[0027] The comparator 400 compares the positive and negative sides of the differential signal from the CDAC 300. The comparator 400 supplies the comparison result to the latch circuit 430. The latch circuit 430 holds the comparison result. The latch circuit 430 supplies the held comparison result to the SAR logic circuit 220.

[0028] The SAR logic circuit 220 controls the level of the reference signal based on the comparison result of the comparator 400. This SAR logic circuit 220 updates the level of the reference signal by a successive approximation method so that the positive and negative outputs of the CDAC 300 are balanced. If the resolution of the SAR logic circuit 220 is M bits (M is an integer), the number of successive approximations is M. Furthermore, the SAR logic circuit 220 holds each of the M comparison results and supplies a bit string in which bits indicating these comparison results are arranged to the digital signal processing unit 120 as a digital signal DOUT.

[0029] The ripple canceller 500 cancels the ripple in the output signal of the CDAC 300. The circuit configuration of the ripple canceller 500 will be described later.

[0030] [CDAC configuration example] 3 is a circuit diagram showing an example of a configuration of a CDAC 300 according to the first embodiment of the present technology. The diagram illustrates a circuit with a 5-bit resolution. The CDAC 300 includes positive-side capacitances 311 to 316, negative-side capacitances 317 to 322, a positive-side switching unit 330, and a negative-side switching unit 340. The positive-side switching unit 330 includes positive-side switching circuits 331 to 336, and the negative-side switching unit 340 includes negative-side switching circuits 341 to 346. Note that the positive-side capacitances 314 and 315, the negative-side capacitances 320 and 321, the positive-side switching circuits 334 and 335, and the negative-side switching circuits 344 and 345 are omitted from the diagram.

[0031] Furthermore, a positive signal line 308 and a negative signal line 309 are wired within the CDAC 300. The positive signal line 308 is wired between the positive input terminal and the positive output terminal of the CDAC 300. The negative signal line 309 is wired between the negative input terminal and the negative output terminal of the CDAC 300. The voltage of the positive signal line 308 is a positive voltage V cdac_p The voltage of the negative signal line 309 is output to the comparator 400 as the negative voltage V cdac_n is output to the comparator 400.

[0032] One end of the positive-side capacitors 311 to 316 is commonly connected to the positive-side signal line 308. The other ends of these positive-side capacitors 311 to 316 are connected to positive-side switching circuits 331 to 336. The capacitances of the positive-side capacitors 311 to 315 are different from one another. For example, if a predetermined unit capacitance value is C, the capacitance values ​​of the positive-side capacitors 311, 312, 313, 314, 315, and 316 are set to 16C, 8C, 4C, 2C, C, and C.

[0033] One end of the negative-side capacitors 317 to 322 is commonly connected to the negative-side signal line 309. The other ends of these negative-side capacitors 317 to 322 are connected to the negative-side switching circuits 341 to 346. The capacitances of the negative-side capacitors 317 to 321 are different from one another. For example, the capacitance values ​​of the negative-side capacitors 317, 318, 319, 320, 321, and 322 are set to 16C, 8C, 4C, 2C, C, and C.

[0034] The 16C capacitor and the corresponding switching circuit correspond to the MSB (Most Significant Bit) of the 5 bits. The 8C capacitor and the corresponding switching circuit correspond to the second bit, and the 4C capacitor and the corresponding switching circuit correspond to the third bit. The 2C capacitor and the corresponding switching circuit correspond to the fourth bit, and one of the C capacitors and the corresponding switching circuit correspond to the LSB (Least Significant Bit). The other C capacitor is used as a dummy capacitor.

[0035] The positive-side switching circuits 331 to 335 connect the other end of the corresponding positive-side capacitance to one of the positive-side reference voltage VREFP, the common voltage VCOM, and the negative-side reference voltage VREFN in accordance with control signals Dac_p and Dac_n from the SAR logic circuit 220. The size of each of the control signals Dac_p and Dac_n is 5 bits. The positive-side switching circuit 336 connects the other end of the dummy positive-side capacitance 316 to one of the positive-side reference voltage VREFP, the common voltage VCOM, and the negative-side reference voltage VREFN in accordance with a control signal (not shown) from the SAR logic circuit 220.

[0036] The positive reference voltage VREFP is a constant voltage higher than the common voltage VCOM, and the negative reference voltage VREFN is a constant voltage lower than the common voltage VCOM. The positive reference voltage VREFP can also be expressed as +VREF, and the negative reference voltage VREFN can also be expressed as -VREF.

[0037] The negative-side switching circuits 341 to 345 connect the other end of the corresponding negative-side capacitance to one of the positive-side reference voltage VREFP, the common voltage VCOM, and the negative-side reference voltage VREFN in accordance with control signals Dac_p and Dac_n from the SAR logic circuit 220. The negative-side switching circuit 346 connects the other end of the dummy positive-side capacitance 316 to one of the positive-side reference voltage VREFP, the common voltage VCOM, and the negative-side reference voltage VREFN in accordance with a control signal (not shown) from the SAR logic circuit 220.

[0038] Furthermore, the negative side switching circuit 341 is made up of, for example, switches 351 to 353. The same applies to the positive side switching circuits 331 to 336 and the other negative side switching circuits.

[0039] The SAR logic circuit 220 connects all of the positive-side capacitors 311 to 316 and the negative-side capacitors 317 to 322 to the common voltage VCOM using a control signal while the sampling switches 211 and 212 are in the closed state (i.e., the sampling period), thereby holding the sampled differential signal.

[0040] Then, the SAR logic circuit 220 refers to the comparison result of the comparator 400, and controls the connection destination of the capacitance in the CDAC 300 using a control signal based on the comparison result.

[0041] For example, if the first comparison result shows that the positive side is greater than or equal to the negative side, SAR logic circuit 220 connects negative reference voltage VREFN to positive-side capacitance 311 and connects positive reference voltage VREFP to negative-side capacitance 317. On the other hand, if the first comparison result shows that the positive side is less than the negative side, SAR logic circuit 220 connects positive reference voltage VREFP to positive-side capacitance 311 and connects negative reference voltage VREFN to negative-side capacitance 317. By these controls, -½VREF or +½VREF is added to the positive side, and +½VREF or -½VREF is added to the negative side.

[0042] Furthermore, if the second comparison result shows that the positive side is greater than or equal to the negative side, SAR logic circuit 220 connects negative reference voltage VREFN to positive-side capacitance 312 and connects positive reference voltage VREFP to negative-side capacitance 318. On the other hand, if the second comparison result shows that the positive side is less than the negative side, SAR logic circuit 220 connects positive reference voltage VREFP to positive-side capacitance 312 and connects negative reference voltage VREFN to negative-side capacitance 318. By these controls, -1 / 4 VREF or +1 / 4 VREF is added to the positive side, and +1 / 4 VREF or -1 / 4 VREF is added to the negative side.

[0043] Thereafter, the SAR logic circuit 220 repeats the same control until the number of comparisons reaches five. If the resolution (M bits) is other than five bits, M+1 positive-side capacitors, negative-side capacitors, positive-side switching circuits, and negative-side switching circuits, including dummy ones, are arranged. The capacitance of the m-th bit (m is an integer from 0 to M-1) is set to twice that of the m+1-th bit.

[0044] As described above, the method of controlling the reference voltage based on the results of M successive approximations is called a successive approximation method.

[0045] Instead of a differential signal, a single-ended signal can also be input to the SARADC 200. In this case, no capacitor or switch is required on either the positive or negative side of the CDAC 300. The sampled and held single-ended signal is input to one input terminal of the comparator 400, and the reference voltage generated by the CDAC 300 is input to the other input terminal.

[0046] [Comparator control example] 4 is a circuit diagram showing an example of the configuration of the comparator 400 according to the first embodiment of the present technology. The comparator 400 includes an enable control section 410 and a differential amplifier circuit 420.

[0047] The enable control section 410 generates an enable signal En_Comp from the output of the latch circuit 430 and the sampling clock CLK. The enable control section 410 includes an inverter 411, a NOR (negative OR) gate 412, and an AND (logical product) gate 413.

[0048] The inverter 411 inverts the sampling clock CLK and supplies it to the AND gate 413 .

[0049] The NOR gate 412 is connected to the positive voltage V out_p and the negative voltage V out_n The NOR of this is supplied to the AND gate 413.

[0050] The AND gate 413 supplies the logical product of the signal from the inverter 411 and the signal from the NOR gate 412 as an enable signal En_Comp to the differential amplifier circuit 420 and the ripple canceller 500 .

[0051] The differential amplifier circuit 420 receives the positive voltage V cdac_p and the negative voltage V cdac_nare input to the differential amplifier circuit 420. The differential amplifier circuit 420 compares these voltages. The comparison result is differentially output to the SAR logic circuit 220 latch circuit 430 via a positive signal line 408 and a negative signal line 409. The differential amplifier circuit 420 includes pMOS (p-channel Metal Oxide Semiconductor) transistors 421 and 422, and nMOS (n-channel MOS) transistors 423 to 425.

[0052] The pMOS transistor 421 and the nMOS transistor 423 are connected in series between the power supply node and the drain of the nMOS transistor 425. The pMOS transistor 422 and the nMOS transistor 423 are also connected in series between the power supply node and the drain of the nMOS transistor 425. The source of the nMOS transistor 425 is connected to the ground node.

[0053] An enable signal En_Comp is input to the gates of the pMOS transistors 421 and 422 and the nMOS transistor 425. A negative voltage V cdac_n is input, and the gate of the nMOS transistor 424 is supplied with a positive voltage V cdac_p is entered.

[0054] The voltage at the connection node between the pMOS transistor 421 and the nMOS transistor 423 is the negative voltage V gm_n The voltage at the connection node between the pMOS transistor 422 and the nMOS transistor 424 is output as a positive voltage V gm_p is output as

[0055] [Example of latch circuit configuration] 5 is a circuit diagram showing an example of the configuration of the latch circuit 430 according to the first embodiment of the present technology. The latch circuit 430 includes pMOS transistors 431 to 434 and nMOS transistors 435 to 440.

[0056] The differential amplifier circuit 420 outputs the positive voltage V gm_p is output from the positive output terminal to the latch circuit 430, and the negative voltage V gm_n is output from the negative output terminal to the latch circuit 430.

[0057] In the latch circuit 430, pMOS transistors 431 and 432 are connected in series to a node of the power supply voltage. NMOS transistors 436 and 437 are connected in parallel between the drain of the ground-side pMOS transistor 432 and the node of the ground voltage. An nMOS transistor 435 is inserted between the connection node of the pMOS transistors 431 and 432 and the node of the ground voltage.

[0058] Furthermore, pMOS transistors 433 and 434 are connected in series to a power supply voltage node. nMOS transistors 438 and 439 are connected in parallel between the drain of the ground-side pMOS transistor 434 and the ground voltage node. An nMOS transistor 440 is inserted between the connection node of the pMOS transistors 433 and 434 and the ground voltage node.

[0059] Furthermore, the positive voltage Vgm_p from the differential amplifier circuit 420 is input to the gates of the pMOS transistor 431 and the nMOS transistors 435 and 436. The negative voltage Vgm_n from the differential amplifier circuit 420 is input to the gates of the pMOS transistor 433 and the nMOS transistors 439 and 440.

[0060] The connection node between the pMOS transistor 432 and the nMOS transistor 437 is connected to the gates of the pMOS transistor 434 and the nMOS transistor 438, respectively. The voltage at this connection node is the positive voltage Vout_p to the SAR logic circuit 220 and the comparator 400.

[0061] The connection node between the pMOS transistor 434 and the nMOS transistor 438 is connected to the gates of the pMOS transistor 432 and the nMOS transistor 437, respectively. The voltage at this connection node is the negative voltage V out_n to the SAR logic circuit 220 and the comparator 400.

[0062] The connection configuration shown in the figure provides a positive voltage V gm_p and the negative voltage V gm_n When one of these is at a high level and the other is at a low level, the latch circuit 430 transitions to a through state. gm_p and the negative voltage V gm_n However, as it is, the positive voltage V out_p and the negative voltage V out_n is output as

[0063] Furthermore, when the positive voltage Vgm_p and the negative voltage Vgm_n are in equilibrium, the latch circuit 430 transitions to the holding state, and the previous state is held.

[0064] Moreover, the differential amplifier circuit 420 starts a comparison operation when the enable signal En_Comp changes from low level to high level. gm_p and V gm_n is discharged from the power supply voltage to the ground voltage. V cdac_p and V cdac_n The difference between V gm_p and V gm_n The discharge speed of the latch circuit 430 changes, and the output logic of the latch circuit 430 is determined by the difference in the discharge speed.

[0065] [Ripple canceller configuration example] 6 is a circuit diagram showing a configuration example of a ripple canceller 500 according to the first embodiment of the present technology. The diagram illustrates a circuit with a 5-bit resolution. The ripple canceller 500 includes a capacitance unit 510 and comparator units 521 to 525. The capacitance unit 510 includes sampling switches 511 and 512, a positive-side common capacitance 513, and a negative-side common capacitance 514. Note that the comparator units 524 and 525 are omitted from the diagram.

[0066] The sampling switch 511 opens and closes the path between the common signal line 507 of the common voltage VCOM and the positive signal line 508 in accordance with the sampling clock CLK. The sampling switch 512 opens and closes the path between the common signal line 507 and the negative signal line 509 in accordance with the sampling clock CLK. For example, while the sampling clock CLK is at a high level, the sampling switches 511 and 512 are closed.

[0067] One end of the positive common capacitor 513 is connected to the node of the positive reference voltage VREFP, and the other end is connected to the positive signal line 508. One end of the negative common capacitor 514 is connected to the node of the negative reference voltage VREFN, and the other end is connected to the negative signal line 509. When the charges stored in these capacitors become stable, the sampling switches 511 and 512 transition to the open state.

[0068] Here, it is desirable that the positive reference voltage VREFP and the negative reference voltage VREFN are in a stable state without ripples.

[0069] The comparator section 521 includes switches 531 to 536, common-side transistors 537 and 538, a positive-side transistor 539, a negative-side transistor 540, and a switch transistor 541. These transistors are nMOS transistors.

[0070] The switch 531 opens and closes the path between the drain of the common-side transistor 537 and the positive-side signal line 408 in accordance with a control signal from the SAR logic circuit 220. This positive-side signal line 408 is connected to the positive-side output terminal of the comparator 400 as described above.

[0071] The switch 532 opens and closes the path between the drain of the common-side transistor 538 and the negative-side signal line 409 in accordance with a control signal from the SAR logic circuit 220. This negative-side signal line 409 is connected to the negative-side output terminal of the comparator 400 as described above.

[0072] The switch 533 opens and closes the path between the drain of the positive-side transistor 539 and the negative-side signal line 409 in accordance with a control signal from the SAR logic circuit 220. The switch 534 opens and closes the path between the drain of the positive-side transistor 539 and the positive-side signal line 408 in accordance with a control signal from the SAR logic circuit 220.

[0073] The switch 535 opens and closes the path between the drain of the negative-side transistor 540 and the positive-side signal line 408 in accordance with a control signal from the SAR logic circuit 220. The switch 536 opens and closes the path between the drain of the negative-side transistor 540 and the negative-side signal line 409 in accordance with a control signal from the SAR logic circuit 220.

[0074] The sources of the common-side transistors 537 and 538 are commonly connected to the drain of the switch transistor 541, and the gates thereof are commonly connected to the common signal line 507 of the common voltage VCOM.

[0075] The source of the positive-side transistor 539 is connected to the drain of the switch transistor 541, and the gate thereof is connected to the positive-side common capacitor 513 via the positive-side signal line 508. The source of the negative-side transistor 540 is connected to the drain of the switch transistor 541, and the gate thereof is connected to the negative-side common capacitor 514 via the negative-side signal line 509.

[0076] The source of the switch transistor 541 is connected to a node of the ground voltage, and the enable signal En_Comp is input to the gate.

[0077] The circuit configuration of each of the comparator units 522 to 525 is the same as that of the comparator unit 521. However, the size of the transistors in these comparators is different. Here, the "size" of a transistor refers to the size of the transistor gate (gate width or gate length). For example, when the gate width is constant, the gate length is used as the size.

[0078] If the size of the transistor in the comparator unit 525 is "1", the sizes of the transistors in the comparator units 521, 522, 523 and 524 are set to "16", "8", "4" and "2", respectively.

[0079] Comparator unit 521, whose size is "16", corresponds to the MSB. Comparator unit 522 corresponds to the second bit, comparator unit 523 corresponds to the third bit, comparator unit 524 corresponds to the fourth bit, and comparator unit 525, whose size is "1", corresponds to the LSB.

[0080] Immediately after sampling, only the switches 531 and 532 on the common side of all bits are controlled to be closed, and depending on the comparison result, the switches 533 to 536 on the positive and negative sides of the corresponding bits are opened or closed. The detailed control content will be described later.

[0081] If the resolution (M bits) is other than 5 bits, M comparator sections are arranged. The size of the transistor for the mth bit is twice that of the m+1th bit. Furthermore, the number of resolution bits and the number of comparator sections are the same, but this configuration is not limiting. The number of comparator sections may be slightly less than the number of resolution bits. However, this may reduce the ripple cancellation effect described below.

[0082] 7 is a diagram illustrating a connection state of the CDAC 300 and the ripple canceller 500 according to the first embodiment of the present technology. The m-th bit of the M-bit control signal Dac_p is designated as Dac_p[m]. Similarly, the m-th bit of the control signal Dac_n is designated as Dac_n[m]. The initial value of each bit of the control signals Dac_p and Dac_n is set to, for example, the logical value "0."

[0083] The SAR logic circuit 220 refers to the mth comparison result of the comparator 400, and if the positive side is greater than or equal to the negative side, updates Dac_n[m] to the logical value "1". At this time, Dac_p[m] remains "0". On the other hand, if the positive side is less than the negative side, the SAR logic circuit 220 updates Dac_p[m] to "1". At this time, Dac_n[m] remains "0".

[0084] In the CDAC 300, when Dac_p[m] and Dac_n[m] are both "0", the positive-side capacitance and negative-side capacitance of the mth bit are connected to the common voltage VCOM.

[0085] Also, when Dac_p[m] is "1" and Dac_n[m] is "0", the positive-side capacitance of the mth bit is connected to the positive reference voltage VREFP, and the negative-side capacitance is connected to the negative reference voltage VREFN.

[0086] Also, when Dac_p[m] is "0" and Dac_n[m] is "1", the positive-side capacitance of the mth bit is connected to the negative-side reference voltage VREFN, and the negative-side capacitance is connected to the positive-side reference voltage VREFP.

[0087] Next, in the ripple canceller 500, when Dac_p[m] and Dac_n[m] are both "0," the m-th bit switches 531 and 532 transition to a closed state. This connects the drains of the m-th bit common-side transistors 537 and 538 to the positive output terminal and negative output terminal of the comparator 400, respectively. At this time, all switches other than switches 531 and 532 transition to an open state.

[0088] Furthermore, when Dac_p[m] is "1" and Dac_n[m] is "0", switches 533 and 535 for the mth bit transition to a closed state. As a result, the drain of positive-side transistor 539 is connected to the negative output terminal of comparator 400, and the drain of negative-side transistor 540 is connected to the positive output terminal of comparator 400. At this time, all switches other than switches 533 and 535 transition to an open state.

[0089] Furthermore, when Dac_p[m] is "0" and Dac_n[m] is "1", switches 534 and 536 for the mth bit transition to a closed state. As a result, the drain of positive-side transistor 539 is connected to the positive output terminal of comparator 400, and the drain of negative-side transistor 540 is connected to the negative output terminal of comparator 400. At this time, all switches other than switches 534 and 536 transition to an open state.

[0090] 8 is a diagram for explaining an example of control of the switches of the ripple canceller according to the first embodiment of the present technology. In the diagram, it is assumed that control up to the third bit has been completed. Also, in the diagram, the comparator 400 is omitted.

[0091] Based on the result of the first comparison, the SAR logic circuit 220 connects the positive side capacitance 311 of 16C to the positive side reference voltage VREFP and the negative side capacitance 317 of 16C to the negative side reference voltage VREFN using a control signal.

[0092] Based on the result of the second comparison, the SAR logic circuit 220 uses a control signal to connect the positive-side capacitance 312 of 8C to the negative-side reference voltage VREFN and connect the negative-side capacitance 318 of 8C to the positive-side reference voltage VREFP.

[0093] Based on the result of the third comparison, the SAR logic circuit 220 uses a control signal to connect the positive-side capacitance 313 of 4C to the positive-side reference voltage VREFP and connect the negative-side capacitance 319 of 4C to the negative-side reference voltage VREFN.

[0094] If a ripple component of Δ occurs in the positive reference voltage VREFP, the ripple component V that occurs in the differential output of the CDAC300 is dac is expressed by the following formula: V dac ={(16-8+4)C / 32C}·Δ···Equation 1

[0095] On the other hand, the positive-side transistor of the first-bit comparator section 521 is connected to the negative-side output terminal of the comparator 400 via the negative-side signal line 409, and the negative-side transistor is connected to the positive-side output terminal of the comparator 400 via the positive-side signal line 408. In the figure, white triangles indicate positive-side transistors, black triangles indicate common-side transistors, and gray triangles indicate negative-side transistors.

[0096] The positive-side transistor of the second-bit comparator section 522 is connected to the positive output terminal, and the negative-side transistor is connected to the negative output terminal. The positive-side transistor of the third-bit comparator section 523 is connected to the negative output terminal, and the negative-side transistor is connected to the positive output terminal.

[0097] With the above-mentioned connection, the ripple component V generated in the ripple canceller 500 cancel is expressed by the following formula: V cancel =-(16C / 32)Δ'+(8C / 32)Δ'-(4C / 32)Δ' =-{(16-8+4) / 32}·Δ' ···Equation 2

[0098] The value of Δ′ depends on the size of the smallest transistor in the ripple canceller 500. The size of the smallest transistor is adjusted to a value such that Δ in Equation 1 and Δ′ in Equation 2 approximately match.

[0099] When Δ and Δ' are approximately the same, according to Equations 1 and 2, the ripple component of CDAC 300 and the ripple component generated within ripple canceller 500 have the same absolute value but opposite signs. Therefore, when these are added at the output terminal of comparator 400, the ripple component of CDAC 300 is canceled. By canceling the ripple component, it is possible to reduce errors in the comparison result of comparator 400.

[0100] FIG. 9 is a circuit diagram showing an example of the configuration of a ripple canceller in a comparative example. This comparative example is a circuit described in Non-Patent Document 1. In this comparative example, the resolution is M bits, and M comparator sections and M capacitance sections are arranged in the ripple canceller. Each comparator section is arranged with a differential pair of nMOS transistors and a switch transistor, and each capacitance section is arranged with four capacitances and six switches. In addition, the capacitance and size of the differential pair are largest for the LSB, and the capacitance and size are halved from the second bit onwards.

[0101] In the comparative example, the ripple component of the CDAC can be canceled by controlling the switches. However, four capacitors must be arranged for each bit, and the higher the resolution, the larger the circuit scale becomes.

[0102] Furthermore, in the comparative example, the larger the capacitance value in the capacitance section, the lower the on-resistance of the switch connected to that capacitance must be. Therefore, when implementing the switch using an nMOS transistor, the larger the capacitance value, the larger the size of the transistor must be. This nMOS transistor must be driven in conjunction with the CDAC 300, but the larger the size of the nMOS transistor, the greater the power consumption required to drive it.

[0103] Furthermore, in the comparative example, the higher the resolution, the more wiring there is connecting the capacitance unit and the comparator unit. When the switch to which the common voltage VCOM of the capacitance unit is connected is open, each wiring becomes very high impedance. This can lead to the possibility of being affected by disturbances. In particular, the farther the capacitance unit and the differential pair are from each other, the longer the wiring between them needs to be routed, making them more susceptible to disturbances.

[0104] 6, the gates of M pairs of transistors (positive-side transistor 539 and negative-side transistor 540) of different sizes are commonly connected to positive-side common capacitance 513 and negative-side common capacitance 514. In this configuration, only two capacitances are required regardless of the resolution, and therefore the circuit scale can be reduced compared to the comparative example.

[0105] 6, by providing switches 531 to 536 on the drain side of the transistors in the capacitor unit, the size of these switches can be made smaller than in the comparative example, thereby reducing the power consumption for driving these switches.

[0106] Furthermore, in FIG. 6, regardless of the resolution, only three wires are required between the capacitance section and the comparator section, so that the influence of disturbances can be suppressed more effectively than in the comparative example.

[0107] [Example of SARADC in action] 10 is a timing chart showing an example of the operation of the SADAC 200 according to the first embodiment of the present technology. The sampling clock CLK goes high during a sampling period from timing T0 to T1. During this period, the CDAC 300 captures and holds the sampled differential signal.

[0108] During the period from timing T1 to timing T2, the differential amplifier circuit 420 in the comparator 400 performs M comparisons in synchronization with the enable signal En_Comp. Based on the results of these comparisons, the SAR logic circuit 220 updates the control signals Dac_p and Dac_n M times.

[0109] In accordance with the update of the control signals Dac_p and Dac_n, the CDAC 300 switches the connection destination of the capacitor to either the positive reference voltage VREFP or the negative reference voltage VREFN. At this time, a ripple component occurs in the positive reference voltage VREFP or the negative reference voltage VREFN. Meanwhile, a ripple component Δ p and Δ n These Δ p and Δ n This removes the ripple component generated in the CDAC 300.

[0110] 11 is an example of an overall diagram of the SAR ADC 200 according to the first embodiment of the present technology. When a differential signal is input to the SAR ADC 200, the CDAC 300 generates an analog differential signal based on a control signal from the SAR logic circuit 220 and outputs the signal to the comparator 400. On the other hand, when a single-ended signal is input to the SAR ADC 200, the CDAC 300 generates an analog single-ended signal and outputs the signal to the comparator 400. In this way, the CDAC 300 generates at least one of a pair of analog signals and outputs the signal to the comparator 400. The CDAC 300 is an example of a digital-to-analog converter as defined in the claims.

[0111] The comparator 400 compares the input differential signals and generates a comparison result. The latch circuit 430 holds the comparison result and supplies it to the SAR logic circuit 220. The SAR logic circuit 220 generates a control signal based on the comparison result and supplies it to the CDAC 300, the comparator unit 521, etc. The SAR logic circuit 220 is an example of a logic circuit as defined in the claims.

[0112] In the ripple canceller 500, one end of the positive-side common capacitance 513 is connected to the node of the positive-side reference voltage VREFP, and one end of the negative-side common capacitance 514 is connected to the node of the negative-side reference voltage VREFN.

[0113] The sampling switches 511 and 512 open and close the paths between the other ends of the positive-side common capacitance 513 and the negative-side common capacitance 514 and the node of the common voltage VCOM, respectively, in synchronization with the sampling clock CLK.

[0114] The gates of the M positive-side transistors 539 of different sizes are commonly connected to a positive-side common capacitor 513 via a positive-side signal line 508. The gates of the M negative-side transistors 540 of different sizes are commonly connected to a negative-side common capacitor 514 via a negative-side signal line 509.

[0115] The gates of M pairs of common-side transistors of different sizes are commonly connected to a node of a common voltage VCOM.

[0116] The switches 531 to 536 open and close paths between the drains of the transistors, such as the common-side transistors, and the output terminal of the comparator 400 based on control signals.

[0117] As described above, according to the first embodiment of the present technology, M comparator units are commonly connected to the positive side common capacitance 513 and the negative side common capacitance 514, thereby making it possible to reduce the circuit size compared to when multiple capacitances are arranged for each bit.

[0118] <2. Second embodiment> In the first embodiment described above, the sampling switches 511 and 512 in the ripple canceller 500 perform sampling within the sampling period. These sampling switches 511 and 512 preferably perform sampling in a stable voltage state without ripple. The SARADC 200 of this second embodiment differs from the first embodiment in that the sampling switches 511 and 512 perform sampling within the period from the end of conversion to the start of sampling.

[0119] 12 is an example of an overall diagram of the SARADC 200 according to the second embodiment of the present technology. The SARADC 200 according to the second embodiment differs from the first embodiment in that sampling switches 511 and 512 open and close in accordance with a comparison completion flag Conv_End from the SAR logic circuit 220.

[0120] The SAR logic circuit 220 of the second embodiment closes the sampling switches 511 and 512 using the comparison completion flag Conv_End within the period from the end of AD (Analog to Digital) conversion to the start of sampling.

[0121] 13 is a timing chart showing an example of the operation of the SAR ADC 200 according to the second embodiment of the present technology. The SAR logic circuit 220 according to the second embodiment supplies a high-level comparison completion flag Conv_End within a period from timing T11 at the end of AD conversion to timing T12 at the start of the next sampling.

[0122] In response to the comparison completion flag Conv_End going high, the sampling switches 511 and 512 transition to the closed state and perform sampling.

[0123] Depending on the SARADC200, the voltage state may be more stable during the period from the end of AD conversion to the start of sampling than during the sampling period. In this case, the effects of ripple can be reduced by performing the control shown in the figure.

[0124] As described above, according to the second embodiment of the present technology, the sampling switches 511 and 512 transition to a closed state within the period from the end of AD conversion to the start of sampling, so that sampling can be performed when the voltage state is stable.

[0125] <3. Third Embodiment> In the first embodiment described above, a differential pair of nMOS transistors is arranged in the differential amplifier circuit 420 and the ripple canceller 500, but a differential pair of pMOS transistors can also be arranged instead. The SARADC 200 of this third embodiment differs from the first embodiment in that a differential pair of pMOS transistors is arranged instead of a differential pair of nMOS transistors.

[0126] 14 is a circuit diagram showing a configuration example of a differential amplifier circuit 460 according to a third embodiment of the present technology. The differential amplifier circuit 460 according to the third embodiment includes pMOS transistors 461 to 463 and nMOS transistors 464 and 465. The circuit configuration of the differential amplifier circuit 460 is similar to that of the differential amplifier circuit 420 shown in FIG. 4, except that the polarities of the respective transistors are opposite. In the fourth embodiment, the differential amplifier circuit 460 starts a comparison operation when the enable signal En_Comp changes from high level to low level. Furthermore, an inverter 450 is inserted in a stage preceding the positive input terminal of the differential amplifier circuit 460.

[0127] 15 is a circuit diagram showing a configuration example of a latch circuit 470 according to the third embodiment of the present technology. The latch circuit 470 according to the third embodiment includes pMOS transistors 471 to 476 and nMOS transistors 477 to 480. The circuit configuration of the latch circuit 470 is similar to that of the latch circuit 430 illustrated in FIG. 13, except that the polarities of the respective transistors are reversed.

[0128] 16 is a circuit diagram showing a configuration example of a ripple canceller 500 according to the third embodiment of the present technology. The ripple canceller 500 according to the third embodiment includes a switch transistor 551, common-side transistors 552 and 553, a positive-side transistor 554, a negative-side transistor 555, and switches 531 to 536 in a comparator unit 521. pMOS transistors are used as these transistors. The same applies to the comparator units after the comparator unit 522.

[0129] The second embodiment can also be applied to the third embodiment.

[0130] As described above, according to the third embodiment of the present technology, a differential pair of pMOS transistors is used instead of a differential pair of nMOS transistors, so that the comparator 400 starts a comparison operation when the enable signal En_Comp changes from a high level to a low level.

[0131] <4. Fourth embodiment> In the first embodiment described above, the common voltage VCOM was supplied to the ripple canceller 500 in addition to the reference voltages (VREFP and VREFN). However, this configuration requires a circuit to generate the common voltage VCOM. Furthermore, if the input common voltage of the SARADC200 differs from VCOM, the ripple cancellation effect may be reduced. The SARADC200 of this fourth embodiment differs from the first embodiment in that it does not require the supply of the common voltage VCOM to the ripple canceller 500.

[0132] 17 is a circuit diagram showing a configuration example of a ripple canceller 500 according to the fourth embodiment of the present technology. The ripple canceller 500 according to the fourth embodiment includes positive-side common capacitors 611 and 612, sampling switches 613 to 616, and negative-side common capacitors 617 and 618 in a capacitance section 510.

[0133] One end of each of the positive-side common capacitors 611 and 612 is commonly connected to a node of the positive-side reference voltage VREFP. The capacitance value of each of these positive-side common capacitors 611 and 612 is set to half that of the positive-side common capacitor 513 of the first embodiment. The positive-side common capacitors 611 and 612 are an example of the first positive-side common capacitor and the second positive-side common capacitor set forth in the claims.

[0134] The sampling switch 613 opens and closes the path between the other end of the positive-side common capacitance 611 and the sampling switch 615 in synchronization with the sampling clock CLK. The sampling switch 614 opens and closes the path between the other end of the positive-side common capacitance 612 and the sampling switch 616 in synchronization with the sampling clock CLK.

[0135] One end of each of the negative common capacitors 617 and 618 is commonly connected to a node of the negative reference voltage VREFN. The capacitance value of each of these negative common capacitors 617 and 618 is set to half that of the negative common capacitor 514 of the first embodiment. The negative common capacitors 617 and 618 are an example of the first negative common capacitor and the second negative common capacitor set forth in the claims.

[0136] The sampling switch 615 opens and closes the path between the other end of the negative-side common capacitance 617 and the sampling switch 613 in synchronization with the sampling clock CLK. The sampling switch 616 opens and closes the path between the other end of the negative-side common capacitance 618 and the sampling switch 614 in synchronization with the sampling clock CLK.

[0137] The connection node between the positive-side common capacitor 611 and the sampling switch 613 is connected to the positive-side signal line 501 , and the connection node between the positive-side common capacitor 612 and the sampling switch 614 is connected to the positive-side signal line 502 .

[0138] The connection node of the sampling switches 613 and 615 is connected to a common signal line 503, and the connection node of the sampling switches 614 and 616 is connected to a common signal line 504. The common signal line 503 is connected to the positive input terminal of the comparator 400 (i.e., the positive output terminal of the CDAC 300), and V cdac_p The common signal line 504 is connected to the negative input terminal of the comparator 400 (i.e., the negative output terminal of the CDAC 300) and V cdac_n is supplied.

[0139] The connection node between the negative common capacitor 617 and the sampling switch 615 is connected to the negative signal line 505 , and the connection node between the negative common capacitor 618 and the sampling switch 616 is connected to the negative signal line 506 .

[0140] 18 is a circuit diagram showing a configuration example of a comparator unit 521 according to a fourth embodiment of the present technology. In the comparator unit 521 according to the fourth embodiment, common-side transistors 621 to 624 are arranged instead of the common-side transistors 537 and 538. In addition, positive-side transistors 625 and 626 are arranged instead of the positive-side transistor 539, and negative-side transistors 627 and 628 are arranged instead of the negative-side transistor 540. The size of each of the transistors in the fifth embodiment is set to half that of the first embodiment. The sizes of the transistors in the comparator units 521, 522, 523, 524, and 525 are set to "8," "4," "2," "1," and "1 / 2," respectively.

[0141] The drains of the common-side transistors 621 and 622 are connected to the switch 531, and the gates thereof are connected to the common signal line 503. The drains of the common-side transistors 623 and 624 are connected to the switch 532, and the gates thereof are connected to the common signal line 504.

[0142] The common side transistors 621 and 622 are an example of a first common side transistor set forth in the claims, and the common side transistors 623 and 624 are an example of a second common side transistor set forth in the claims.

[0143] The drains of the positive side transistors 625 and 626 are connected to both the switches 533 and 534. The gate of the positive side transistor 625 is connected to the positive side signal line 501, and the gate of the positive side transistor 626 is connected to the positive side signal line 502. The positive side transistors 625 and 626 are examples of the first positive side transistor and the second positive side transistor set forth in the claims.

[0144] The drains of negative-side transistors 627 and 628 are connected to both switches 535 and 536. The gate of negative-side transistor 627 is connected to negative signal line 505, and the gate of negative-side transistor 628 is connected to negative signal line 506. Note that negative-side transistors 627 and 628 are examples of the first negative-side transistor and second negative-side transistor set forth in the claims.

[0145] When the switches 531 and 532 on the common side are closed, the four transistors on the common side perform a discharge operation. The transconductance of a transistor with a size of 8 / 32 (=1 / 4) is 1 / 4 × g m Then, the current I flowing through the switches 531 and 532 c is expressed by the following formula: I c =(g m / 4)×(V cdac_p +V cdac_n ) =(g m / 2)×(V cdac_com )...Equation 3

[0146] where V cdac_com is the differential signal V cadc_p and V cadc_n It is equal to the common voltage of V cdac_com If =VCOM, then I cis the same as the current that the common-side transistors 537 and 538 in the first embodiment attempt to pass. In this way, even when there is no common voltage VCOM, it is possible to pass a current equivalent to that in the first embodiment, thereby achieving the desired circuit operation.

[0147] On the other hand, when one of switches 533 and 534 and one of switches 535 and 536 are closed, the transistors to which they are connected also discharge at the timing of the comparison operation. At this time, the current flowing through the drain-side switch is expressed by the following equation. I p =(g m / 4)×(V cdac_p +V cdac_n +2×Δ p ) =(g m / 2)×(V cdac_com +Δ p )...Equation 4 I n =(g m / 4)×(V cdac_p +V cdac_n +2×Δ n ) =(g m / 2)×(V cdac_com +Δ n )...Equation 5

[0148] Δ in Equation 4 and Equation 5 p and Δ n are the ripple components that occur in the positive reference voltage VREFP and the negative reference voltage VREFN, respectively. cdac_com = VCOM, then the current I c and I n is the same as the current that the positive-side transistor and negative-side transistor in the first embodiment attempt to pass. In this way, even when there is no common voltage VCOM, it is possible to pass a current equivalent to that in the first embodiment, thereby achieving the desired circuit operation.

[0149] The second and third embodiments can also be applied to the fourth embodiment.

[0150] As described above, according to the fourth embodiment of the present technology, each of the transistors is separated into two parts with half the size, and each of the capacitors is separated into two parts with half the capacitance value, thereby generating a current equivalent to that in the first embodiment, and therefore the common voltage VCOM is not required.

[0151] <5. Application examples for mobile devices> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0152] FIG. 19 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0153] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 19, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0154] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0155] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0156] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0157] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0158] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0159] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0160] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0161] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0162] The audio / video output unit 12052 transmits at least one output signal of audio and / or video to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 19, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0163] FIG. 20 is a diagram showing an example of the installation position of the imaging unit 12031.

[0164] In FIG. 20, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0165] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0166] 20 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0167] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0168] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0169] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0170] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0171] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 of the above-described configuration. Specifically, the electronic device 100 in FIG. 1 can be applied to the image capturing unit 12031. By applying the technology according to the present disclosure to the image capturing unit 12031, the circuit size can be reduced.

[0172] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0173] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0174] The present technology can also be configured as follows. (1) a digital-to-analog converter that generates at least one of a pair of analog signals in accordance with a predetermined control signal; a comparator that compares the pair of analog signals to generate and output a comparison result; a logic circuit that generates the control signal based on the comparison result; A plurality of positive-side transistors of different sizes; A plurality of negative-side transistors of different sizes; a plurality of switches that open and close paths between one of the sources and drains of each of the plurality of positive-side transistors and the plurality of negative-side transistors and an output terminal of the comparator based on the control signal; a positive-side common capacitor having one end connected to a node of a predetermined positive-side reference voltage and the other end connected in common to the gates of the plurality of positive-side transistors; a negative-side common capacitor having one end connected to a node of a negative-side reference voltage lower than the positive-side reference voltage and the other end connected in common to the gates of the plurality of negative-side transistors; An analog-to-digital converter comprising: (2) the pair of analog signals are differential signals; The digital-to-analog converter generates the differential signal. The analog-to-digital converter according to (1) above. (3) The analog-to-digital converter according to (1) or (2), further comprising a sampling switch that opens and closes a path between the other end of each of the positive-side common capacitance and the negative-side common capacitance and a common voltage between the positive-side reference voltage and the negative-side reference voltage. (4) The sampling switch transitions to a closed state within a predetermined sampling period. The analog-to-digital converter according to (3) above. (5) The sampling switch transitions to a closed state within the period from the end of analog-to-digital conversion to the start of sampling. The analog-to-digital converter according to (3) above. (6) The analog-to-digital converter according to any one of (1) to (5), further comprising a latch circuit that holds the comparison result and supplies it to the logic circuit. (7) Each of the plurality of positive-side transistors and the plurality of negative-side transistors is an nMOS transistor. The analog-to-digital converter according to any one of (1) to (6). (8) Each of the plurality of positive-side transistors and the plurality of negative-side transistors is a pMOS transistor. The analog-to-digital converter according to any one of (1) to (6). (9) Further comprising a plurality of pairs of common-side transistors of different sizes; The gates of the plurality of pairs of common-side transistors are connected to a node of a common voltage between the positive-side reference voltage and the negative-side reference voltage. The analog-to-digital converter according to any one of (1) to (8). (10) a plurality of pairs of first common-side transistors of different sizes; Multiple pairs of second common-side transistors of different sizes Further comprising: the positive-side common capacitance includes a first positive-side common capacitance and a second positive-side common capacitance, the negative common capacitance includes a first negative common capacitance and a second negative common capacitance, The plurality of positive-side transistors a plurality of first positive side transistors of different sizes; A plurality of second positive transistors of different sizes; Including, The plurality of negative-side transistors a plurality of first negative-side transistors having different sizes; a plurality of second negative-side transistors of different sizes; Including, the gates of the plurality of first positive-side transistors are commonly connected to the first positive-side common capacitance; the gates of the plurality of second positive-side transistors are commonly connected to the second positive-side common capacitance; the gates of the plurality of first negative-side transistors are commonly connected to the first negative-side common capacitance; The gates of the plurality of second negative-side transistors are commonly connected to the second negative-side common capacitance. The analog-to-digital converter according to any one of (1) to (8). (11) a digital-to-analog converter that generates at least one of a pair of analog signals in accordance with a predetermined control signal; a comparator that compares the pair of analog signals to generate and output a comparison result; a logic circuit that generates the control signal based on the comparison result and outputs a digital signal; A plurality of positive-side transistors of different sizes; A plurality of negative-side transistors of different sizes; a plurality of switches that open and close paths between one of the sources and drains of each of the plurality of positive-side transistors and the plurality of negative-side transistors and an output terminal of the comparator based on the control signal; a positive-side common capacitor having one end connected to a node of a predetermined positive-side reference voltage and the other end connected in common to the gates of the plurality of positive-side transistors; a negative-side common capacitor having one end connected to a node of a negative-side reference voltage lower than the positive-side reference voltage and the other end connected in common to the gates of the plurality of negative-side transistors; a digital signal processing circuit that processes the digital signal; An electronic device comprising: [Explanation of symbols]

[0175] 100 Electronic equipment 110 Analog signal generation unit 120 Digital Signal Processing Unit 200 SARADC 211, 212, 511, 512, 613-616 Sampling switch 220 SAR logic circuit 300 CDAC 311~316 Positive side capacitance 317~322 Negative side capacitance 330 Positive side switching unit 331~336 Positive side switching circuit 340 Negative side switching unit 341~346 Negative side switching circuit 351~353, 531~536 Switches 400 Comparator 410 Enable control section 411 Inverter 412 NOR (Negative OR) Gate 413 AND gate 420, 460 differential amplifier circuit 421, 422, 431-434, 461-463, 471-476 pMOS transistors 423~425, 435~440, 464, 465, 477~480 nMOS transistors 430, 470 Latch circuit 500 Ripple Canceller 510 Capacity part 513, 611, 612 Positive common capacity 514, 617, 618 Negative common capacitance 521~525 Comparator section 537, 538, 552, 553, 621-624 Common side transistors 539, 554, 625, 626 Positive transistor 540, 555, 627, 628 Negative transistor 541, 551 Switch transistor 12031 Imaging unit

Claims

1. a digital-to-analog converter for generating at least one of a pair of analog signals in accordance with a predetermined control signal; a differential amplifier circuit that compares the pair of analog signals to generate and output a comparison result; a latch circuit that holds and outputs the comparison result; a logic circuit that generates the control signal based on the output comparison result; a ripple canceller that generates a component having an opposite sign to the ripple component of the output signal of the digital-to-analog converter and supplies the component to an output terminal of the differential amplifier circuit; Equipped with The ripple canceller is M (M is an integer) positive-side transistors of different sizes; M negative transistors of different sizes; a plurality of switches that open and close paths between the output terminal and one of the sources and drains of the positive-side transistor and the negative-side transistor based on the control signal; a positive-side common capacitor having one end connected to a node of a predetermined positive-side reference voltage and the other end connected in common to the gates of the positive-side transistors; a negative common capacitor having one end connected to a node of a negative reference voltage lower than the positive reference voltage and the other end connected in common to the gates of the negative transistors; Equipped with a size of the m-th (m is an integer from 1 to M) positive-side transistor is twice a size of the (m+1)-th positive-side transistor, a size of the m-th negative-side transistor is twice a size of the (m+1)-th negative-side transistor; The other of the source and the drain of each of the positive-side transistors and the other of the source and the drain of each of the negative-side transistors are connected to a node of a ground voltage. A successive approximation analog-to-digital converter.

2. the pair of analog signals are differential signals, The digital-to-analog converter generates the differential signal.

2. The analog-to-digital converter according to claim 1.

3. 2. The analog-to-digital converter according to claim 1, further comprising a sampling switch that opens and closes a path between the other end of each of the positive-side common capacitance and the negative-side common capacitance and a common voltage between the positive-side reference voltage and the negative-side reference voltage.

4. The sampling switch transitions to a closed state within a predetermined sampling period.

4. The analog-to-digital converter according to claim 3.

5. The sampling switch transitions to a closed state within a period from the end of analog-to-digital conversion to the start of sampling.

4. The analog-to-digital converter according to claim 3.

6. Each of the positive-side transistor and the negative-side transistor is an nMOS transistor.

2. The analog-to-digital converter according to claim 1.

7. Each of the positive-side transistor and the negative-side transistor is a pMOS transistor.

2. The analog-to-digital converter according to claim 1.

8. The ripple canceller further comprises a plurality of pairs of common-side transistors of different sizes, The gates of the plurality of pairs of common-side transistors are connected to a node of a common voltage between the positive-side reference voltage and the negative-side reference voltage.

2. The analog-to-digital converter according to claim 1.

9. The ripple canceller comprises: a plurality of pairs of first common-side transistors having different sizes; a plurality of pairs of second common-side transistors of different sizes; Furthermore, the positive-side common capacitance includes a first positive-side common capacitance and a second positive-side common capacitance, the negative common capacitance includes a first negative common capacitance and a second negative common capacitance, The plurality of positive-side transistors a plurality of first positive side transistors having different sizes; a plurality of second positive-side transistors of different sizes; Including, The plurality of negative-side transistors a plurality of first negative side transistors having different sizes; a plurality of second negative-side transistors of different sizes; Including, the gates of the plurality of first positive-side transistors are commonly connected to the first positive-side common capacitance; the gates of the plurality of second positive-side transistors are commonly connected to the second positive-side common capacitance; the gates of the plurality of first negative-side transistors are commonly connected to the first negative-side common capacitance; The gates of the plurality of second negative-side transistors are commonly connected to the second negative-side common capacitance.

2. The analog-to-digital converter according to claim 1.

10. a successive approximation type analog-to-digital converter including: a digital-to-analog converter that generates at least one of a pair of analog signals in accordance with a predetermined control signal; a differential amplifier circuit that compares the pair of analog signals to generate and output a comparison result; a latch circuit that holds and outputs the comparison result; a logic circuit that generates the control signal based on the output comparison result and outputs a digital signal; and a ripple canceller that generates a component whose sign is opposite to that of a ripple component of the output signal of the digital-to-analog converter and supplies the component to an output terminal of the differential amplifier circuit; a digital signal processing circuit that processes the digital signal; Equipped with The ripple canceller is M (M is an integer) positive-side transistors of different sizes; M negative transistors of different sizes; a plurality of switches that open and close paths between the output terminal and one of the sources and drains of the positive-side transistor and the negative-side transistor based on the control signal; a positive-side common capacitor having one end connected to a node of a predetermined positive-side reference voltage and the other end connected in common to the gates of the positive-side transistors; a negative common capacitor having one end connected to a node of a negative reference voltage lower than the positive reference voltage and the other end connected in common to the gates of the negative transistors; Equipped with a size of the m-th (m is an integer from 1 to M) positive-side transistor is twice a size of the (m+1)-th positive-side transistor, a size of the m-th negative-side transistor is twice a size of the (m+1)-th negative-side transistor; The other of the source and the drain of each of the positive-side transistors and the other of the source and the drain of each of the negative-side transistors are connected to a node of a ground voltage. electronic equipment.

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