Semiconductor structure and method of manufacturing same

Abstract

To provide a semiconductor structure in which a snubber circuit is formed on a chip and a device is miniaturized.SOLUTION: In a vertical type power semiconductor device 1, a semiconductor structure includes: a substrate having a first front surface 12A and a second front surface 12B opposite to each other; and a unit region R1 and a terminal region R2 adjacent to each other. An electrode structure 50 in the substrate extends from a first surface toward a second surface in the unit region. A trench structure 60 in the substrate extends from the first surface toward the second surface in the unit region and being adjacent to the terminal region. The trench structure includes an N-type semiconductor material layer 12 extending up to the first surface. A capacitive structure on the first surface of the substrate in the terminal region is adjacent to the trench structure. The capacitive structure has capacitive electrodes 163, 164 having the same material as the semiconductor material layer and connected to the semiconductor material layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims priority to Chinese Application No. 202310440130.6, entitled "Semiconductor Structure and Manufacturing Method Thereof," filed on April 21, 2023, and is incorporated herein by reference as if reproduced in its entirety.

[0002] TECHNICAL FIELD

[0002] The present disclosure relates to the field of semiconductors, and more particularly to semiconductor structures and methods for fabricating the same. Particular embodiments relate to vertical power semiconductor structures having RC (resistor-capacitor) snubbers. [Background technology]

[0003] Snubber circuits (or simply snubbers) are frequently used in electrical systems with inductive loads. In electrical systems, a sudden interruption of current flow through the load causes a sudden increase in voltage across the current-switching device (or switching device). The resulting current transients can cause electromagnetic interference (EMI) in other circuits. Furthermore, if the voltage developed across the switching device exceeds the voltage the switching device can tolerate, the switching device may be damaged or destroyed. A snubber provides an alternative current path around the switching device for a short period of time, allowing the inductive components to safely discharge.

[0004]

[0004] RC (resistor-capacitor) snubbers are a fundamental component of switching circuits. They are commonly used to control EMI (electromagnetic interference) and excessive peak voltage stresses that occur during switching. For example, RC snubbers are a standard design element in various synchronous voltage converters and regulators. A simple RC snubber uses a resistor (R) connected in series with a capacitor (C). When switching inductive loads on and off using direct current (DC) or alternating current (AC), a properly designed RC snubber can be used to limit the peak voltage across the switching device. The voltage across the capacitor does not change immediately, so reduced transient currents flow through the capacitor for a short period of time, allowing the voltage across the switching device to increase more slowly when the switching device is turned on.

[0005]

[0005] The RC snubber is an external component and is placed together with the switching device in an adjacent area on the same PCB (printed circuit board). Therefore, it needs to occupy additional chip surface area, which increases the total surface area of ​​the device and the total process cost, and becomes a technological bottleneck in device miniaturization. Summary of the Invention

[0006] Technical advantages are generally achieved by embodiments of the present disclosure that describe semiconductor structures and methods for fabricating the same.

[0007]

[0007] According to one aspect of the present disclosure, a semiconductor structure is provided, the semiconductor structure including: a substrate including a first surface and a second surface opposing each other, the substrate including a unit area and a terminal area adjacent to each other when the substrate is viewed from above; a first electrode structure within the substrate, extending from the first surface toward the second surface and arranged within the unit area; a first trench structure within the substrate, extending from the first surface toward the second surface and arranged within the unit area, adjacent to the terminal area, the first trench structure including a first semiconductor material layer extending to the first surface; and a capacitive structure on the first surface of the substrate, arranged in the terminal area and adjacent to the first trench structure, the capacitive structure having the same material as the first semiconductor material layer and including a first capacitive electrode and a second capacitive electrode, the first capacitive electrode being connected to the first semiconductor material layer.

[0008] According to another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor structure, the method including the steps of: forming a first trench and a second trench in a substrate, the substrate including a unit area and a terminal area adjacent to each other in a top view of the substrate; forming a first dielectric layer on the substrate underlying the first trench and the second trench; forming a first electrode material layer on the first dielectric layer, the first electrode material layer being disposed in the first trench and the second trench and covering a top surface of the substrate; and disposing at least a portion of the first electrode material layer on the top surface of the substrate within the unit area. The method includes: performing a first etching on the first electrode material layer to remove the first electrode material layer, wherein the first electrode material layer after the first etching includes a first portion in the first trench, a second portion in the second trench, and a third portion on the top surface of the substrate and connected to the second portion, the third portion including a first capacitive electrode and a second capacitive electrode that define a capacitance of the capacitive structure; and forming a body-doped region in the substrate within the unit area and a source-doped region on the body-doped region.

[0009]

[0009] Aspects of embodiments of the present disclosure may be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of illustration.

[0010]

[0010] The technical solutions and beneficial effects of the present disclosure will become apparent through the detailed description of the embodiments of the present disclosure in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view of an exemplary vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a top view of an exemplary vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 3] FIG. 2 is another top view of an exemplary vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 4] 1A-1C illustrate an example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 5] 1A-1C illustrate an example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 6] 1A-1C illustrate an example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 7] 1A-1C illustrate an example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 8] 1A-1C illustrate an example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 9] 1A-1C illustrate an example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 10]1A-1C illustrate an example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 11] 1A-1C illustrate an example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 12] 1A-1C illustrate an example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 13] 1A-1C illustrate an example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 14] 1A-1C illustrate an example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 15] 1A-1C illustrate an example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 16] 1A-1C illustrate an example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 17] 1A-1C illustrate an example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 18] 1A-1C are cross-sectional views of an exemplary vertical power semiconductor device during a manufacturing method according to an embodiment of the present disclosure. [Figure 19] 5A-5C illustrate another example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 20] 5A-5C illustrate another example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 21] 5A-5C illustrate another example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 22] 5A-5C illustrate another example of one or more stages in a method for manufacturing a vertical power semiconductor device according to an embodiment of the present disclosure. [Figure 23] 1A-1C are cross-sectional views of an exemplary vertical power semiconductor device during a manufacturing method according to an embodiment of the present disclosure. [Figure 24] 1A-1C are cross-sectional views of an exemplary vertical power semiconductor device during a manufacturing method according to an embodiment of the present disclosure. [Figure 25] 1A-1C are cross-sectional views of an exemplary vertical power semiconductor device during a manufacturing method according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0019]

[0013] The same or similar components are designated by the same reference numerals in the drawings and the detailed description.

[0014] Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013]

[0020] The making and using of embodiments of the present disclosure are described in detail below. However, it should be understood that the concepts disclosed herein can be embodied in a wide variety of specific contexts, and that the specific embodiments described herein are merely illustrative and do not serve to limit the scope of the claims. Furthermore, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure, as defined by the appended claims.

[0014]

[0021] The following disclosure provides a variety of different embodiments or examples for implementing different features of the present disclosure. Specific embodiments of components and configurations are described below. Admittedly, these are merely examples and are not intended to be limiting. In the present disclosure, a reference to forming a first feature on or over a second feature can include embodiments in which the first and second features are formed in direct contact with each other, and can also include embodiments in which an additional feature is formed between the first and second features such that the first and second features are not in direct contact with each other. Furthermore, the present disclosure may repeat reference numerals and / or letters in various embodiments. Such repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations described.

[0015]

[0022] DETAILED DESCRIPTION OF THE INVENTION

[0021] The following detailed description of the present disclosure provides applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments described herein are illustrative only and are not intended to limit the scope of the present disclosure.

[0016]

[0023] The embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. Compared with a typical semiconductor power device, the semiconductor power device of the embodiments of the present disclosure has an RC snubber structure formed in the same step as the electrode structure. The manufacturing method of the semiconductor structure of the embodiments of the present disclosure integrates the RC snubber process into the front-end process of semiconductor manufacturing. Compared with a method of separately manufacturing the RC snubber and the transistor chip and arranging the RC snubber and the transistor chip adjacent to each other on the same PCB, the semiconductor structure manufacturing method of the embodiments can reduce the total device surface area and the total process cost.

[0017]

[0024] FIG. 1 is a cross-sectional view of a vertical power semiconductor structure 1 according to a specific embodiment of the present disclosure. The vertical power semiconductor structure 1 may include various types of semiconductor power devices and may be fabricated by various techniques. For example, the vertical power semiconductor structure 1 may include a power metal-oxide-semiconductor field-effect transistor (MOSFET), a double-diffused MOSFET (DMOSFET), an insulated-gate bipolar transistor (IGBT), or a junction-gate field-effect transistor (JFET). Specifically, the vertical power semiconductor structure 1 may have a vertical current conduction path. For example, current in the vertical power semiconductor structure 1 may flow in a direction perpendicular to the active surface of the vertical power semiconductor structure 1. In one example, current in the vertical power semiconductor structure 1 may be conducted vertically through the vertical power semiconductor structure 1. Note that the vertical power semiconductor structure 1 in FIG. 1 includes a split-gate vertical power semiconductor device formed in a unit region R1, but this is merely an example and does not limit the application of the present disclosure.

[0018]

[0025] In some embodiments, the vertical power semiconductor structure 1 may include a semiconductor material layer 12, an electrode structure 50 (including an electrode material layer 161, a dielectric layer 20, and an electrode material layer 171), a trench structure 60 (including an electrode material layer 172, a dielectric layer 20, and an electrode material layer 162), and a capacitor structure (including capacitive electrodes 163, 164).

[0019]

[0026] The semiconductor material layer 12 may include, for example, an N-type or P-type single crystal silicon material, an epitaxial silicon material, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor material. In some embodiments, the semiconductor material layer 12 has a first-type lightly doped region 25 of epitaxial silicon material. For convenience of explanation, the following description uses the N-type as an example of the first type. However, the present disclosure is not limited thereto, and the semiconductor material layer 12 may be an N-type (first type) or a P-type (second type) depending on the conductivity type of the vertical power semiconductor structure 1.

[0020]

[0027] Semiconductor material layer 12 may have a surface 12A and a surface 12B opposite surface 12A. In some embodiments, surface 12A and surface 12B may be located on opposite sides of drain contact region 11. In some embodiments, surface 12A and surface 12B may be horizontal. For ease of explanation, the direction perpendicular to surfaces 12A and 12B is referred to as the vertical direction, and the direction perpendicular to the vertical direction is referred to as the horizontal direction. In some embodiments, surface 12A may be an active surface of semiconductor material layer 12. Semiconductor material layer 12 may also be referred to as a substrate.

[0021]

[0028] In some embodiments, a unit region R1 and a terminal region R2 adjacent to each other may be defined in the semiconductor material layer 12. The unit region R1 may be used to accommodate active components, such as the vertical power semiconductor device described above. The terminal region R2 may be used to accommodate passive components and / or circuit terminals. That is, active components may be formed in the unit region R1 in a later step, and passive components and / or circuit terminals may be formed in the terminal region R2 in a later step. In some embodiments, the terminal region R2 may be adjacent to one side of the unit region R1 (as shown in FIG. 2, which will be described in more detail below). In some embodiments, the terminal region R2 surrounds the unit region R1 (as shown in FIG. 3, which will be described in more detail below).

[0022]

[0029] The electrode structure 50 is located within the semiconductor material layer 12 and extends from the surface 12A toward the surface 12B of the semiconductor material layer 12. In some embodiments, the electrode structure 50 may be an electrode structure for a split-gate vertical power semiconductor device and is disposed within the unit region R1. In the embodiment shown in FIG. 1 , the electrode structure 50, also known as a split-gate structure, includes an electrode material layer 171 near the surface 12A, an electrode material layer 161 located below the electrode material layer 171, and a dielectric layer 20 surrounding the electrode material layer 171 and the electrode material layer 161. The dielectric layer 20 is used to electrically isolate the semiconductor material layer 12, the electrode material layer 161, and the electrode material layer 171. In other words, the dielectric layer 20 is located between the semiconductor material layer 12 and the electrode material layer 161, between the semiconductor material layer 12 and the electrode material layer 171, and between the electrode material layer 161 and the electrode material layer 171. In the split-gate vertical power semiconductor device embodiment, the electrode material layer 171 can function as a gate electrode and can be referred to as a gate electrode layer, and the electrode material layer 161 can function as a shield electrode and can be referred to as a shield electrode layer. The vertical power semiconductor structure 1 can include multiple electrode structures 50, for example, two electrode structures 50 adjacent to each other as shown in FIG.

[0023]

[0030] The trench structure 60 is located in the semiconductor material layer 12 and extends from the surface 12A to the surface 12B of the semiconductor material layer 12. In some embodiments, the trench structure 60 may be disposed in the unit region R1 and adjacent to the terminal region R2. The trench structure 60 may be formed in the same step as the electrode structure 50 (the related steps will be described in detail later with reference to the related drawings), and therefore may have a similar configuration / shape to the electrode structure 50. However, because the trench structure 60 does not have the function of separating the gate electrodes, the trench structure 60 is not considered to be an electrode structure.

[0024]

[0031] Taking the vertical power semiconductor structure 1 shown in FIG. 1 as an example, the trench structure 60 includes an electrode material layer 172 near the surface 12A, an electrode material layer 162 extending from below the electrode material layer 172 to the surface 12A, and a dielectric layer 20 surrounding the electrode material layer 172 and the electrode material layer 162. The electrode material layer 162 has a first portion 162a located below the electrode material layer 172 and a second portion 162b connected to the first portion 162a and located along a side of the electrode material layer 172. When the trench structure 60 and the electrode structure 50 have the same width, the width of the electrode material layer 171 is greater than the width of the electrode material layer 172. In some embodiments, the first portion 162a has opposing sidewalls 601 and 602, and the second portion 162b has opposing sidewalls 603 and 604, and the sidewalls 601 and 603 are continuous sidewalls. In some embodiments, the first portion 162a has an upper surface 605 connected to the second portion 162b. In some embodiments, the sidewall 604 terminates at the upper surface 605 of the first portion 162a. In some embodiments, the sidewall 604 and the sidewall 602 are discontinuous sidewalls. In some embodiments, the upper surface 605 of the first portion 162a and the upper surface of the electrode material layer 161 are at approximately the same horizontal level. In some embodiments, the width of the first portion 162a of the electrode material layer 162 is approximately equal to the width of the electrode material layer 161, and the width of the first portion 162a is greater than the width of the second portion 162b.

[0025]

[0032] In this manner, trench structure 60 and electrode structure 50 may be formed in the same step. Therefore, the bottom of electrode structure 50 and the bottom of trench structure 60 may be located at approximately the same horizontal level. In some embodiments, the bottom of electrode material layer 171 and the bottom of electrode material layer 172 may be located at approximately the same horizontal level. In some embodiments, electrode material layer 171 has the same material as electrode material layer 172, such as a metal material or other material suitable for a gate electrode. In some embodiments, the bottom of electrode material layer 161 and the bottom of electrode material layer 162 may be located at approximately the same horizontal level. In some embodiments, electrode material layer 162 has the same material as electrode material layer 161, such as a polysilicon material or other material suitable for a shield electrode.

[0026]

[0033] The capacitive structure includes capacitive electrodes 163 and 164. The capacitor structure is disposed on the surface 12A of the semiconductor material layer 12 in the terminal region R2 and adjacent to the trench structure 60. In the embodiment shown in FIG. 1 , the capacitive electrode 163 is connected to the second portion 162b of the electrode material layer 162. The capacitive electrodes 163 and 164 may be formed in the same step, and the thickness of the capacitive electrode 163 at the surface 12A is approximately the same as the thickness of the capacitive electrode 164 at the surface 12A. In some embodiments, the top surface of the capacitive electrode 163 may be flush with the top surface of the capacitive electrode 164. In some embodiments, the bottom surface of the capacitive electrode 163 at the surface 12A may be flush with the bottom surface of the capacitive electrode 164 at the surface 12A. In some embodiments, the capacitive electrodes 163 and 164 may be formed in the same step as the electrode material layers 161 and 162. Thus, the capacitive electrodes 163, 164 may have the same material as the electrode material layers 161, 162.

[0027]

[0034] The vertical power semiconductor structure 1 also includes a trench structure 70 located in the semiconductor material layer 12 and extending from the surface 12A toward the surface 12B. The trench structure 70 is disposed in the terminal region R2 and may function as an EQR (equal potential ring). In some embodiments, the trench structure 70 may include an electrode material layer 165 and a dielectric layer 20 surrounding the electrode material layer 165. The trench structure 70 may be formed in the same step as the electrode structure 50 and the trench structure 60. Specifically, the electrode material layer 165 may be formed in the same step as the electrode material layers 161, 162 and the capacitive electrodes 163, 164. Therefore, the electrode material layer 165 may have the same material as the electrode material layers 161, 162 or the capacitive electrodes 163, 164. In some embodiments, the electrode material layer 165 may extend to the surface 12A, and the electrode material layer 165 may be connected to the capacitive electrode 164.

[0028]

[0035] In addition to the lightly doped region 25, the vertical power semiconductor structure 1 may also have a plurality of doped regions 13, 141, 142, 151, 152, and a plurality of conductive plugs (such as conductive plugs 311, 312, 313, 314, hereinafter collectively referred to as conductive plugs 31).

[0029]

[0036] The doped regions 13 function as body-doped regions (hereinafter collectively referred to as body-doped regions 13) of the vertical power semiconductor structure 1. The body-doped regions 13 are located in the semiconductor material layer 12 within the unit region R1 adjacent to the electrode structures 50, with the body-doped regions 13 being close to the surface 12A. In some embodiments, the body-doped regions 13 may be located between adjacent electrode structures 50 and between the electrode structures 50 and the trench structure 60. In some embodiments, the body-doped regions 13 may be located above and adjacent to the lightly doped regions 25. The body-doped regions 13 have a different conductivity type, e.g., P-type, than the lightly doped regions 25. The depth of the body-doped regions 13 may be less than the depth of the electrode structures 50.

[0030]

[0037] The doped region 141 functions as a source (hereinafter generally referred to as the source-doped region 141) of the split-gate vertical power semiconductor device and is located within the body-doped region 13 adjacent to the surface 12A of the semiconductor material layer 12. The depth of the source-doped region 141 may be less than the depth of the body-doped region 13, and the conductivity type of the source-doped region 141 may be different from the conductivity type of the body-doped region 13, such as N-type. In some embodiments, the source-doped region 141 may be adjacent to the surface 12A of the semiconductor material layer 12. In some embodiments, the doping concentration of the source-doped region 141 may be higher than the doping concentration of the body-doped region 13. In some embodiments, the electrode structure 50 extends vertically through the source-doped region 141. In some embodiments, the source-doped region 141 may be located between adjacent electrode structures 50, as shown in FIG. 1 .

[0031]

[0038] The doped region 142 is located in the lightly doped region 25 of the terminal region R2 and is adjacent to the surface 12A of the semiconductor material layer 12. The depth of the doped region 142 may be approximately the same as the depth of the source doped region 141 and has the same conductivity type as the source doped region 141, e.g., N-type. The primary function of the doped region 142 is to limit the expansion of the depletion region and prevent external free charges or ions from entering the active region of the device, thereby preventing normal electrical behavior from being affected. In some embodiments, the doped region 142 may be adjacent to the surface 12A of the semiconductor material layer 12. In some embodiments, a conductive plug 312 passes through the doped region 142. In some embodiments, the doped region 142 is adjacent to the trench structure 70, as shown in FIG. 1 .

[0032]

[0039] The doped region 151 is located within the body doped region 13 and functions as a heavily doped region within the body doped region 13 (hereinafter collectively referred to as the heavily doped region 151). The heavily doped region 151 has the same conductivity type as the body doped region 13, such as P-type. In some embodiments, the doping concentration of the heavily doped region 151 may be lower than that of the source doped region 141 and higher than that of the body doped region 13. In some embodiments, the heavily doped region 151 may be located within the body doped region 13 and separated from the lightly doped region 25. In some embodiments, the heavily doped region 151 may be separated from the source doped region 141. In some embodiments, the heavily doped region 151 may be disposed between adjacent electrode structures 50 and between the electrode structure 50 and the trench structure 60. The heavily doped region 151 may be separated from the electrode structure 50 and the trench structure 60 through a portion of the body doped region 13. In other words, a portion of the body doped region 13 may be located between the heavily doped region 151 and the electrode structure 50, and another portion of the body doped region 13 may be located between the heavily doped region 151 and the trench structure 60. The heavily doped region 151 may surround the bottom of the conductive plug 311 disposed in the body doped region 13 to reduce ohmic contact resistance.

[0033]

[0040] The doped region 152 (hereinafter collectively referred to as the heavily doped region 152) is located in a heavily doped region within the lightly doped region 25 of the terminal region R2. The heavily doped region 152 has the same conductivity type as the heavily doped region 151, such as P-type. In some embodiments, the doping concentration of the heavily doped region 152 is lower than that of the source doped region 141 and higher than that of the body doped region 13. In some embodiments, the heavily doped region 152 is located below the doped region 142 and is separated from the doped region 142. In some embodiments, the heavily doped region 151 is separated from the source doped region 141. In some embodiments, the heavily doped region 152 is close to the trench structure 70. The heavily doped region 152 may be separated from the trench structure 70 via a portion of the lightly doped region 25. The heavily doped region 151 may surround the bottom of the conductive plug 312 located in the lightly doped region 25 to reduce ohmic contact resistance.

[0034]

[0041] The conductive plug 31 extends vertically from above the surface 12A toward the surface 12B of the semiconductor material layer 12 and is connected to the heavily doped regions 151, 152 and the capacitive electrodes 163, 164 of the capacitor structure. The conductive plug 311 is provided in a unit region R1 between adjacent electrode structures 50 and between the electrode structure 50 and the trench structure 60. The conductive plug 311 may be electrically connected to a source electrode of the split-gate vertical power semiconductor device. The conductive plug 312 may be disposed in a terminal region R2. In some embodiments, the conductive plug 312 may be disposed adjacent to the trench structure 70. The conductive plug 312 may be electrically connected to a gain electrode of the split-gate vertical power semiconductor device. The conductive plugs 313 and 314 are located on the capacitor structure and are connected to the capacitive electrodes 163 and 164, respectively. In some embodiments, the conductive plug 313 is connected to the capacitive electrode 163, and the conductive plug 314 is connected to the capacitive electrode 164. Since the conductive plug 31 can be formed in the same step, the uppermost surfaces of the conductive plugs 311, 312, 313, and 314 can be positioned at approximately the same horizontal level.

[0035]

[0042] The vertical power semiconductor device 1 may include a drain contact region 11 , an interlayer dielectric layer 18 , and a metal layer 32 .

[0036]

[0043] The drain contact region 11 is located on the surface 12B in contact with a drain metal layer (not shown, but which may be formed as a metal layer for the drain function on the surface 11B in contact with the drain contact region 11). The drain contact region 11 has the same conductivity type doping as the lightly doped region 25. The drain contact region 11 may be disposed on an upper surface proximate to a substrate of a silicon wafer or other semiconductor material. In some embodiments, the drain contact region 11 may be part of the silicon wafer or substrate. The material of the drain contact region 11 may be, for example, a single-crystal silicon material, an epitaxial silicon material, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide arsenide (GaAsP), or other semiconductor material. In some embodiments, the doping concentration of the drain contact region 11 may be higher than the doping concentration of the lightly doped region 25.

[0037]

[0044] The interlayer dielectric layer 18 is located on the surface 12A of the semiconductor material layer 12 and separates the metal layer 32 in the interlayer dielectric layer 18 from the semiconductor material layer 12. In some embodiments, the conductive plug 31 penetrates the interlayer dielectric layer 18. In some embodiments, the metal layer 32 is used to adjust the electrical path according to actual operational requirements and may be a patterned metal wiring layer including multiple metal wirings connected to different conductive plugs 31. In some embodiments, the metal layer 32 may be the first metal layer (M1) of an interconnect structure. In some embodiments, the metal layer 32 may include a metal wiring 321 connecting the conductive plugs 311 and 313 so that the electrode capacitance 163 and the source of the split-gate vertical power semiconductor device have the same potential. In some embodiments, the metal layer 32 includes a metal wiring 322 connecting the conductive plugs 312 and 314 so that the electrode capacitance 164 and the drain of the split-gate vertical power semiconductor device have the same potential.

[0038]

[0045] 2 and 3 are top views of vertical power semiconductor structures 2 and 3, respectively, according to different embodiments of the present disclosure, illustrating different configurations that the capacitor structures can have. Note that the capacitor structure configurations shown in FIGS. 2 and 3 are for illustrative purposes only and are not intended to limit the present disclosure.

[0039]

[0046] As shown in FIG. 2 , in some embodiments, the terminal region R2 may be adjacent to one side of the unit region R1. Therefore, a capacitor structure is provided on one side of the semiconductor power device in the unit region R1. The configuration of the capacitor structure can be adjusted based on different implementation methods and different requirements. For example, the capacitive electrodes 163 and 164 may be interdigitated electrodes, as shown in the top view of FIG. 2 . The capacitive electrode 163 may have a contact 163a located at one end of the capacitive electrode 163. In some embodiments, the contact 163a is located within the unit region R1 and is connected to the trench structure 60 adjacent to the terminal region R2 (e.g., the first portion 162a of the trench structure 60 in FIG. 1 ). The capacitive electrode 164 may have a contact 164a. The contact 164a is located at one end of the capacitive electrode 164 and is arranged opposite the contact 163a. ​​In some embodiments, the contact 164a is connected to the trench structure 70 (e.g., the electrode material layer 165 of the trench structure 70 in FIG. 1 ) in the terminal region R2.

[0040]

[0047] As shown in FIG. 3 , in some embodiments, the terminal region R2 may surround the unit region R1. Therefore, the capacitor structure may be designed as a semiconductor power device surrounding the unit region R1. The configuration / shape of the capacitor structure can be adjusted according to different implementations and needs. For example, the capacitive electrode 163 may be a spiral electrode extending outward from the unit region R1. As shown in the top view of FIG. 3 , the capacitive electrode 164 may have a spiral configuration similar to the capacitive electrode 163 and be arranged alternately with the capacitive electrode 163. The capacitive electrode 163 shown in FIG. 3 may have a contact pad 163a located at one end of the capacitive electrode 163. In some embodiments, the contact pad 163a is connected to a trench structure in the unit region R1 adjacent to the terminal region R2 (not shown in FIG. 3 , but see the first portion 162a of the trench structure 60 in FIG. 1). The capacitive electrode 164 may have a contact pad 164a, which is located at one end of the capacitive electrode 164 relative to the contact pad 163a. ​​In some embodiments, the contact pad 164a is connected to the trench structure 70 in the terminal region R2 (not shown in FIG. 3, but see the electrode material layer 165 of the trench structure 70 in FIG. 1).

[0041]

[0048] According to the above-described concept of the present invention, the configuration / shape of the capacitor structure can be adjusted according to requirements such as chip area, capacitance, and resistance. For example, the capacitive electrodes may be fishbone-shaped, dendritic, or comb-shaped. Furthermore, different portions of the capacitive electrodes 163 and 164 may have different widths to facilitate calculation of the resistance. As shown in FIG. 2 , the capacitive electrode 163 includes an electrode bus bar 163b connected to a contact pad 163a, a combiner bus 163c connected to the electrode bus bar 163b, and a finger-shaped portion 163d connected to the combiner bus 163c. The width of the electrode bus bar 163b is greater than the width of the combiner bus 163c or the width of the finger-shaped portion 163d. By adjusting the width of the electrode bus bar 163b so that the proportion of the resistance of the electrode bus bar 163b in the resistance of the capacitive electrode 163 is increased, the resistance of the capacitive electrode 163 can be roughly determined using the resistance of the electrode bus bar 163b.

[0042]

[0049] 4-17 illustrate an example of one or more stages in a method for fabricating a vertical power semiconductor device according to certain embodiments of the present disclosure. At least some of the drawings have been simplified to facilitate a better understanding of aspects of the present disclosure.

[0043]

[0050] Referring to FIG. 4 , the manufacturing method includes epitaxially growing a surface 11A of drain contact region 11 to form semiconductor material layer 12. Drain contact region 11 may be located on the top surface adjacent to a substrate or silicon wafer and may have surface 11A and surface 11B opposite surface 11A. In some embodiments, surface 11A is the top surface of the substrate or silicon wafer. In some embodiments, surface 11B of drain contact region 11 may be located within the substrate or silicon wafer. In some embodiments, ions having N-type electrical properties may be implanted during epitaxial growth to form N-type semiconductor material layer 12, and lightly doped region 25 may be formed without the need for additional ion implantation. In some embodiments, semiconductor material layer 12 may have surface 12A and surface 12B opposite surface 12A. In some embodiments, surface 12A and surface 12B may be located on opposite sides of drain contact region 11. In some embodiments, surface 12A and surface 12B may be horizontal surfaces. In some embodiments, surface 12A may be the active surface of semiconductor material layer 12. In some embodiments, surface 12B of semiconductor material layer 12 is in contact with surface 11A of drain contact region 11.

[0044]

[0051] Trenches 41, 42, and 43 may be formed in the semiconductor material layer 12 and may each extend from the surface 12A toward the surface 12B. The trenches 41 and 42 are located in the unit region R1, and the trench 43 is located in the terminal region R2. The trench 42 represents a trench in the unit region R1 adjacent to the terminal region R2. The trench 41 represents a trench in the unit region R1 other than the trench 42. The unit region R1 and the terminal region R2 may be two adjacent regions in a top view, as shown in FIG. 2 or FIG. 3 described above. The trenches 41, 42, and 43 may have vertical sidewalls. The trenches 41, 42, and 43 may have arc-shaped bottom surfaces. Furthermore, the trenches 41, 42, and 43 may also be circular, elliptical, rectangular, or polygonal. The trenches 41, 42, and 43 may be disposed and patterned through photoresist and then formed by an etching process (such as a plasma dry etching process). In some embodiments, the sidewalls of trench 42 may be aligned with the boundaries of unit area R1 and terminal area R2. In some embodiments, the bottoms of trenches 41, 42, and 43 may be at approximately the same horizontal level.

[0045]

[0052] 5, the fabrication method includes forming a dielectric layer 21 on semiconductor material layer 12. In some embodiments, dielectric layer 21 covers surface 12A of semiconductor material layer 12 and may underlie trenches 41, 42, and 43. Dielectric layer 21 may be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or other deposition process. In some embodiments, dielectric layer 21 may be formed by thermal oxidation techniques. In some embodiments, dielectric layer 21 may be conformally deposited on the inner surfaces of trenches 41, 42, 43 (including opposing sidewalls and extending to the bottom between the sidewalls).

[0046]

[0053] Referring to FIG. 6 , this manufacturing method includes forming a dielectric layer 21 followed by forming an electrode material layer 16. In some embodiments, the dielectric layer 21 may be provided to fill trenches 41, 42, and 43 and cover surface 12A of semiconductor material layer 12. The dielectric layer 21 may surround electrode material layer 16 within trenches 41, 42, and 43. In some embodiments, the electrode material layer 16 may be formed by physical vapor deposition (PVD), such as sputtering or spraying. In some embodiments, the electrode material layer 16 may be formed by electroplating or CVD. In some embodiments, after electroplating or deposition, a grinding process, such as a chemical-mechanical polishing (CMP) process, may be performed on electrode material layer 16 to ensure that electrode material layer 16 has a flat top surface. In some embodiments, electrode material layer 16 includes polysilicon or a conductive material.

[0047]

[0054] 7 , the manufacturing method includes performing a first etching process on the electrode material layer 16 to remove at least a portion of the electrode material layer 16 on the surface 12A of the semiconductor material layer 12 in the unit region R1. In some embodiments, before performing the first etching process, a patterned photomask may be formed on the electrode material layer 16 to define the portion of the electrode material layer 16 to be removed by the first etching process. The first etching step may remove the portion of the electrode material layer 16 located in the trench 41, the portion of the electrode material layer 16 located in the trench 42, the portion of the electrode material layer 16 on the surface 12A of the semiconductor material layer 12 in the unit region R1, and the portion of the electrode material layer 16 on the surface 12A of the semiconductor material layer 12 in the terminal region R2 but outside the capacitor structure region. It should be noted that the first etching process may include one or more etching steps, and this is not a limitation of the present disclosure.

[0048]

[0055] After the first etching process, the electrode material layer 16 has a first portion 161 located in the trench 41, a second portion 162 located in the trench 42, a third portion 166 located on the surface 12A of the semiconductor material layer 12 and connected to the second portion 162, and a fourth portion 165 located in the trench 43.

[0049]

[0056] The first portion 161 is located at the bottom of the trench 41 and serves as a shield electrode for a subsequently formed semiconductor power device. The second portion 162 has a lower portion 162a located at the bottom of the trench 42 and an upper portion 162b covering the sidewall of the trench 42 adjacent to the terminal region R2. The upper portion 162b is located on the lower portion 162a and connected to an upper surface 605 of the lower portion 162a. Because the lower portion 162a of the second portion 162 and the first portion 161 are etched by the same first etching step, the upper surface 615 of the first portion 161 and the upper surface 605 of the lower portion 162a of the second portion 162 may be located at approximately the same horizontal level. In some embodiments, the first etching process can expose a portion of the dielectric layer 21 located above the upper surface 615 of the first portion 161 in the trench 41. The upper portion 162b of the second portion 162 covers a portion of the dielectric layer 21 located within the trench 42 and adjacent to the terminal region R2. Thus, in some embodiments, a portion of the dielectric layer 21 located on the sidewall of the trench 42 away from the terminal region R2 is exposed above the upper surface 605 of the lower portion 162a within the trench 42.

[0050]

[0057] After etching, the second portion 162 of the electrode material layer 16 has the configuration and shape described above with reference to FIG. 1 . The lower portion 162a may have opposing sidewalls 601 and 602, and the upper portion 162b may have opposing sidewalls 603 and 604. In some embodiments, the sidewalls 601 and 603 may be continuous. In some embodiments, the upper portion 162b may be connected to the upper surface 605 of the lower portion 162a. In some embodiments, the sidewall 604 may terminate at the upper surface 605 of the lower portion 162a. In some embodiments, the sidewalls 604 and 602 may be discontinuous. In some embodiments, the width of the lower portion 162a of the second portion 162 is approximately the same as the width of the first portion 161, and the width of the lower portion 162a is greater than the width of the upper portion 162b.

[0051]

[0058] The third portion 166 may cover the surface 12A of the semiconductor material layer 12 located between the terminal region R2 and the trenches 42, 43. The third portion 166 is patterned into the capacitive electrodes 163, 164 in a later step. The fourth portion 165 is located in the trench 43. In some embodiments, the fourth portion 165 may fill the trench 43. In some embodiments, the third portion 166 may be connected to the fourth portion 165 and the upper portion 162b of the second portion 162. In some embodiments, the patterned photomask described above may be removed after the first etching process is performed. In some embodiments, the third portion 166 may have a flat top surface even after the first etching process is performed.

[0052]

[0059] 8 , the manufacturing method performs a second etching process on dielectric layer 21 to remove portions of dielectric layer 21 in trenches 41, 42 above first portion 161 and above lower portion 162a of second portion 162, and remove portions of dielectric layer 21 on surface 12A of semiconductor material layer 12 that are not covered by third portion 166. In some embodiments, the second etching process exposes the sidewall of trench 41 above first portion 161. In some embodiments, the second etching process exposes the partial sidewall of trench 42 above lower portion 162a and away from terminal region R2. In some embodiments, the portion of dielectric layer 21 in trench 43 may be completely retained after the second etching process is performed.

[0053]

[0060] Referring to FIG. 9 , this manufacturing method includes a step of performing a third etching process on the third portion 166 to form capacitive electrodes 163 and 164. The configuration and shape of the capacitive electrodes 163 and 164 may be adjusted depending on the required resistance and capacitance values. For example, the capacitive electrodes 163 and 164 in the area marked by the dashed block in FIG. 9 may have the configuration / shape shown in FIG. 2 or 3 in a top view. In other words, the capacitance and resistance values ​​of the capacitor structure can be defined based on the capacitive electrodes 163 and 164 and do not change with the operating voltage. In some embodiments, the upper surfaces of the capacitive electrodes 163 and 164 may be positioned at approximately the same horizontal level. In some embodiments, before performing the third etching process, a patterned photomask having a pattern corresponding to the capacitive electrodes 163 and 164 may be formed to cover the third portion 166, and the third etching process is performed using the patterned photomask. In some embodiments, after the third etching process is performed, the patterned photomask is removed.

[0054]

[0061] 10 , this manufacturing method includes conformally forming a dielectric layer 22 on the semiconductor material layer 12 and the electrode material layer 16. In some embodiments, the thickness of the dielectric layer 22 is smaller than the thickness of the dielectric layer 21. Considering the operating voltage, the dielectric layer 21 may need to have a thickness sufficient to withstand a sufficient voltage. The dielectric layer 22 can function as a gate dielectric layer for a gate electrode formed in a subsequent step, and therefore the dielectric layer 22 can have a smaller thickness than the dielectric layer 21.

[0055]

[0062] 11 , the manufacturing method includes a step of forming a dielectric layer 23 on the planar portion of the dielectric layer 22. By controlling the process parameters and deposition conditions, the dielectric layer 23 may be formed only on the planar portion of the dielectric layer 22, but not on the vertical portion of the dielectric layer 22. The thickness of the dielectric layer 22 may not be large enough to electrically insulate the shield electrode and gate electrode, which will be formed later. Therefore, an additional step may be required to increase the thickness of the planar portion of the dielectric layer 22, particularly the thickness of the bottom of the dielectric layer 22 in the trenches 41, 42, i.e., the thickness of the planar portion of the dielectric layer 22 on the upper surfaces 615, 605 of the electrode material layer 16 located in the trenches 41, 42. Thus, dielectric layer 23 may be formed on the bottom of dielectric layer 22 in trenches 41, 42 (i.e., on upper surface 615 of first portion 161 and on upper surface 605 of lower portion 162a of second portion 162), the top surface of capacitive electrode 163, the top surface of capacitive electrode 164, and the surface 12A of dielectric layer 22 and semiconductor material layer 12 exposed by capacitive electrodes 163, 164. In some embodiments, thickness T21 of dielectric layer 21 may be greater than thickness T23, which is the sum of the thicknesses of dielectric layer 22 and dielectric layer 23. In some embodiments, thickness of dielectric layer 23 may be greater than thickness T22 of dielectric layer 22.

[0056]

[0063] In some embodiments, dielectric layers 21, 22, and 23 can have the same dielectric material. For simplicity of illustration, the dividing lines between dielectric layers 21, 22, and 23 are omitted in subsequent figures, and dielectric layers 21, 22, and 23 are collectively referred to as dielectric structure 20 or dielectric layers 20. In some embodiments, dielectric structure 20 disposed within trenches 41, 42, and 43 is referred to as an intra-trench dielectric layer.

[0057]

[0064] 12 , the manufacturing method includes forming an electrode material layer 17 in trench 41 and trench 42. The electrode material layer 17 has a first portion 171 formed in trench 41 and a second portion 172 formed in trench 42. As described above, because the electrode material layer 16 is located only at the bottom of trench 41, the width of the first portion 171 located in trench 41 is approximately the same. Furthermore, because trench 42 has an upper portion 162b adjacent to second portion 172, the width of second portion 172 is smaller than the width of first portion 171. In some embodiments, the electrode material layer 17 covering the entire semiconductor material layer 12 can be formed by electroplating or CVD, and then an etching process can be performed to remove the electrode material layer 17 outside trenches 41 and 42 to form first portion 171 and second portion 172. In some embodiments, the electrode material layer 17 includes a metal. In some embodiments, the upper surface of the first portion 171 may be flush with the upper surface of the second portion 172. In some embodiments, the first portion 171 and the second portion 172 may be referred to as a gate electrode. For convenience of explanation, the dielectric layer 20 located in the trench 41, the first portion 161 of the electrode material layer 16, and the first portion 171 of the electrode material layer 17 are collectively referred to as a trench structure 50. The dielectric layer 20, the second portion 162 of the electrode material layer 16, and the second portion 172 of the electrode material layer 17 located in the trench 42 are collectively referred to as a trench structure 60. The dielectric layer 20 in the trench 43 and the fourth portion 165 of the electrode material layer 16 are collectively referred to as a trench structure 70. The trench structure 50 may also be used as an electrode of a semiconductor power device, and therefore the trench structure 50 may also be referred to as an electrode structure 50.

[0058]

[0065] 13 , the manufacturing method includes forming a body-doped region 13 in the semiconductor material layer 12 of the unit region R1. The body-doped region 13 may be a second-type doped region formed by a diffusion or ion implantation process from the surface 12A. The depth of the body-doped region 13 is smaller than the depth of the trench structure 50, 60, or 70. In other words, the bottom of the body-doped region 13 is higher than the bottom of the trench structure 50, 60, or 70. In addition, since the body-doped region 13 electrically cancels the conductivity of the lightly doped region 25, the covering of the lightly doped region 25 may be defined as a portion of the semiconductor material layer 12 outside the body-doped region 13. In some embodiments, after performing the ion implantation process to form the body-doped region 13, an annealing process may be performed to diffuse the doping ions.

[0059]

[0066] 13 , the manufacturing method includes forming a source-doped region 141 on the body-doped region 13 in the semiconductor material layer 12 of the unit region R1 and forming a doped region 142 in the semiconductor material layer 12 of the terminal region R2 adjacent to the trench structure 70. The source-doped region 141 and the doped region 142 may be first-type doped regions formed by a diffusion or ion implantation process from the surface 12A. The doping concentrations of the source-doped region 141 and the doped region 142 are approximately the same. The doping concentration of the source-doped region 141 may be higher than the doping concentration of the body-doped region 13. The depth of the source-doped region 141 may be shallower than the depth of the body-doped region 13. The source-doped region 141 may be distributed between adjacent trench structures 50. In some embodiments, the source-doped region 141 may also be formed on the body-doped region 13 between the trench structure 50 and a trench structure 60 (not shown). In some embodiments, the source doped region 141 may not be formed between the trench structure 50 and the trench structure 60 because the location between the trench structure 50 and the trench structure 60 is too close to the high-voltage region of the terminal region R2, to ensure product safety and stability. In some embodiments, the doped region 142 may be distributed on the exposed semiconductor material layer 12 in the terminal region R2. In some embodiments, after an ion implantation process is performed to form the source doped region 141 and the doped region 142, an annealing process may be performed to diffuse the doping ions.

[0060]

[0067] In some embodiments, before performing the ion implantation process for the source doped region 141 and the doped region 142, an etching process can be performed on the dielectric layer 20 to reduce the thickness of the planar portion of the dielectric layer 20 above the surface 12A, as shown in FIG. 13 . Reducing the thickness of the planar portion of the dielectric layer 20 above the surface 12A facilitates the ion implantation process. In some embodiments, the thickness of the planar portion of the dielectric layer 20 above the surface 12A is greater than zero. In other words, the dielectric layer 20 covers at least the surface 12A of the semiconductor material layer 12 to protect the semiconductor material layer 12 and reduce damage to the surface 12A caused by the ion implantation process, as well as to reduce the channel effect.

[0061]

[0068] 14, the manufacturing method includes forming an interlevel dielectric layer 18 on a surface 12A of the semiconductor material layer 12. The interlevel dielectric layer 18 can be formed by ALD, CVD, or other deposition process.

[0062]

[0069] 15 , the manufacturing method includes partially removing the interlayer dielectric layer 18 and partially removing the semiconductor material layer 12 and the capacitive electrodes 163 and 164 using the upper and lower dielectric layers 18 as masks to form openings 411, 412, 413, 414, and 415. The opening 411 is located between adjacent trench structures 50 and penetrates the source-doped region 141. The opening 412 is located between the trench structures 50 and 60 and terminates in the body-doped region 13. The openings 411 and 412 are located within the unit region R1 and may have approximately the same width and depth. The openings 413 and 414 are located on the electrode structures in the terminal region R2 and expose portions of the capacitive electrodes 163 and 164, respectively. In some embodiments, the openings 413 and 414 pass through the capacitive electrodes 163 and 164, respectively. Opening 415 is located in terminal region R2, which extends through doped region 142. Opening 415 may have approximately the same depth as openings 411 or 412. The width of opening 414 may be different from the width of openings 411 or 412. In some embodiments, the width of opening 414 is smaller than the width of openings 411 or 412.

[0063]

[0070] The openings 411, 412, 413, 414, and 415 can be formed by one or more etching processes. For example, a fourth etching step that partially removes the interlayer dielectric layer 18 can be performed, followed by a fifth etching step that partially removes the exposed portions of the semiconductor material layer 12 and the capacitive electrodes 163 and 164. In some embodiments, the fourth etching process stops at the surface 12A of the semiconductor material layer 12 or the surfaces of the capacitive electrodes 163 and 164. In some embodiments, a fifth etching process can be performed to etch the semiconductor material layer 12 and the capacitive electrodes 163 and 164 using the dielectric layer 18 as a mask. In some embodiments, the thickness of the capacitive electrodes 163 and 164 is less than the predetermined depth of the openings 411 and 412, so that the capacitive electrodes 163 and 164 are penetrated. In some embodiments, the fifth etching process stops at the upper surface of the dielectric layer 20 underlying the capacitive electrodes 163 and 164.

[0064]

[0071] 16 , the manufacturing method performs an ion implantation process on the semiconductor material layer 12 according to the openings 411, 412, and 415 to form a heavily doped region 151 in the unit region R1 and a heavily doped region 152 in the terminal region R2. Ions may be vertically implanted into the semiconductor material layer 12 at the bottoms of the openings 411, 412, and 415. The heavily doped regions 151 and 152 are respectively formed in the semiconductor material layer 12 near the bottoms of the openings 411, 412, and 415. In some embodiments, an annealing process can be performed after the ion implantation process to form the heavily doped regions 151 and 152, as shown in FIG.

[0065]

[0072] 17 , the manufacturing method includes forming conductive plugs 31 in the openings 411, 412, 413, 414, and 415. The conductive plugs 31 can be formed by filling the openings 411, 412, 413, 414, and 415 with a conductive material by electroplating or CVD. The material of the conductive plugs 31 can include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), or other metals or alloys. In some embodiments, an optional planarization process may be performed after electroplating or CVD. Therefore, in some embodiments, the upper surfaces of the multiple conductive plugs 31 may be coplanar or at approximately the same horizontal level.

[0066]

[0073] The configuration / shape of the conductive plug 31 is determined by the configuration / shape of the openings 411, 412, 413, 414, and 415, and therefore the conductive plug 31 has the same configuration / shape as the openings 411, 412, 413, 414, and 415. The conductive plug 31 includes a plurality of conductive plugs 311 in contact with the semiconductor material layer 12 in the unit region R1, at least one conductive plug 312 in contact with the semiconductor material layer 12 in the terminal region R2, at least one conductive plug 313 in contact with the capacitive electrode 163, and at least one conductive plug 314 in contact with the capacitive electrode 164.

[0067]

[0074] Referring also to FIG. 17 , this manufacturing method includes forming a metal layer 32 on the interlayer dielectric layer 18. The metal layer 32 can be formed by electroplating or CVD and can be patterned according to electrical properties and operational requirements. The metal layer 32 can be made of a metal or alloy, such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), or tin (Sn). In some embodiments, an etching process can be used to define the metal layer 32 as a plurality of metal interconnects. In some embodiments, the metal layer 32 includes a metal interconnect 321 electrically connected to the conductive plugs 311 and 313. In some embodiments, the metal layer 32 includes a metal interconnect 322 electrically connected to the conductive plugs 312 and 314.

[0068]

[0075] Because source-doped region 141 is not formed between trench structures 50 and 60, trench structure 60 may be referred to as a gap electrode structure. In other embodiments described above, source-doped region 141 may be formed in semiconductor material layer 12 between trench structures 50 and 60. In these embodiments, due to the presence of source-doped region 141, trench structure 60 can operate as a normal electrode structure, and therefore trench structure 60 can be referred to as an electrode structure. Second portion 172 of electrode material layer 17 may also be referred to as a gate electrode.

[0069]

[0076] The vertical power semiconductor device 4 formed through the above steps as shown in FIG. 17 may be the same as the vertical power semiconductor device 1 shown in FIG. 1. The vertical power semiconductor device 4 includes a capacitor structure (including capacitive electrodes 163 and 164), which allows the RC snubber process to be well integrated with the general vertical power semiconductor device process (or the previous process of semiconductor manufacturing), providing stable resistance and capacitance values, and achieving the effects of saving process costs and reducing the total surface area of ​​the device while providing good damping.

[0070]

[0077] According to the structures and processes of the embodiments of the present disclosure described above, the steps of the above processes can be adjusted or the order of the steps can be changed to result in the same or similar vertical power semiconductor devices with the same purpose and concept. FIGS. 18-24 show another example of one or more stages in a method for manufacturing a vertical power semiconductor device according to another embodiment of the present disclosure. At least some of the drawings have been simplified to better understand aspects of the present disclosure. For ease of explanation, only differences from the process described with reference to FIGS. 4-17 will be described below, and identical or similar steps will not be described repeatedly.

[0071]

[0078] Referring to FIG. 18 , a vertical power semiconductor device 5 can be formed by following the steps of FIGS. 4 to 17 as described above. The difference is that in the embodiment of FIG. 18 , the trench 43 is not formed in the step of FIG. 4 . The vertical power semiconductor device 5 as shown in FIG. 18 is formed through the steps as described with reference to FIGS. 5 to 17 . The difference between the vertical power semiconductor device 5 as shown in FIG. 17 and the vertical power semiconductor device 4 is that the vertical power semiconductor device 5 does not have the trench structure 70 included in the vertical power semiconductor device 4. The vertical power semiconductor device 4 can achieve a better EQR effect under the same conditions as the vertical power semiconductor device 5, such as size and operating voltage.

[0072]

[0079] 19, the steps of FIGS. 4 to 12 are performed, and the electrode material layer 17 may include different portions depending on the patterned photomask used in the step of forming the electrode material layer 17 as described with reference to FIG. 12. As shown in FIG. 19, the electrode material layer 17 may further include a third portion 173 located above the capacitive structure. In some embodiments, the third portion 173 may be formed in the same step as the first portion 171 and the second portion 172. The third portion 173 of the electrode material layer 17 is located above the capacitor structure and overlaps with at least one of the capacitive electrode 163 and the capacitive electrode 164. In other words, the third portion 173 covers a portion of the capacitive electrode 163 and / or a portion of the capacitive electrode 164. The third portion 173 is used to increase the capacitance value of the capacitor structure without increasing the total surface area and process cost of the device. In some embodiments, the third portion 173 may cover a portion of the capacitive electrode 163 and a portion of the capacitive electrode 164. In some embodiments, the third portion 173 may also be disposed between the capacitive electrode 163 and the capacitive electrode 164 .

[0073]

[0080] 20, after performing the step of FIG. 19, the vertical power semiconductor device 6 may be formed through the steps of FIGS. 13 to 17. Because the vertical power semiconductor device 6 has an additional third portion 173 compared to the vertical power semiconductor device 4, another opening for exposing the third portion 173 needs to be formed in the step of FIG. 15. In some embodiments, the opening may pass through the third portion 173. Also, in the step of FIG. 17, a conductive plug 315 may be formed in the opening and electrically connected to the third portion 173. In some embodiments, the conductive plug 315 may be electrically connected to the conductive plugs 311 and 313 via a metal wiring 321. In some embodiments, the conductive plug 315 is flush with or at approximately the same horizontal level as the upper surfaces of the other conductive plugs 311, 312, 313, and 314. In some embodiments, after the step of forming the third portion 173, the dielectric layer 20 may be subjected to the etching process described with reference to FIG. 13 to reduce the thickness of the planar portion of the dielectric layer 20 on the surface 12A. In some embodiments, the portion of dielectric layer 20 covered by third portion 173 has a thickness that is greater than the thickness of other planar portions of dielectric layer 20 on surface 12A.

[0074]

[0081] 21 and 22, a vertical power semiconductor device 7 can be formed by integrating the process of the dual trench semiconductor power device and following the steps and technical concepts of FIGS. 4 to 17 described above. The vertical power semiconductor device 7 includes a plurality of shield electrode structures 51 in a unit region R1, a trench structure 61 located in the unit region R1 and adjacent to a terminal region R2, a gate electrode structure 52 between adjacent shield electrode structures 51 in the unit region R1, and a trench structure 70 located in the terminal region R2. The trench structure 70 of the vertical power semiconductor device 7 is similar to the trench structure 70 of the vertical power semiconductor device 4, and therefore will not be described here.

[0075]

[0082] The shield electrode structure 51 and the trench structure 61 may be formed through the steps described with reference to FIGS. 4 to 7. In some embodiments, the shield electrode structure 51 and the trench structure 61 have approximately the same depth. In some embodiments, the first portion 161 of the conductive material layer 16 of the shield electrode structure 51 and the second portion 162 of the conductive material layer 16 of the trench structure 61 extend from the surface 12A toward the surface 12B, and the first portion 161 and the second portion 162 have approximately the same depth. In some embodiments, the first portion 161 and the second portion 162 have approximately the same width on the surface 12A. Note that, to form the shield electrode structure 51 and the trench structure 61 as shown in FIG. 22, the etching processes in each step of FIG. 7 need to be appropriately adjusted. Following the steps of FIG. 7, electrode capacitors 163 and 164 may be formed together with the electrode material layers 161 and 162 of the shield electrode structure 51 and the trench structure 61. In some embodiments, the electrode capacitors 163, 164 and the first, second, and fourth portions 161, 162, and 165 of the electrode material layer 16 may be defined by the same photomask, as shown in FIG. 21 . In some embodiments, after the step of FIG. 21 is performed and before the step of forming the electrode material layer 17 of FIG. 12 is performed, a portion of the semiconductor material layer 12 may be removed to form trenches having a depth smaller than that of the shield electrode structures 51 and positioned between adjacent shield electrode structures 51 to define the positions of the gate electrode structures 52. After the dielectric layer 24 is formed below the trenches, the step of forming the electrode material layer 17 described above is performed to form the electrode material layer 17 in the trenches, and the electrode material layer 17 is surrounded by the dielectric layer 24. The vertical power semiconductor device 7 is then formed through the steps described with reference to FIGS. 14 to 17 . The vertical power semiconductor device 7 also includes a conductive plug 316 in contact with the electrode material layer 161 of the shield electrode structure 51. In some embodiments, the conductive plug 316 is flush with or positioned at approximately the same horizontal level as the upper surfaces of the other conductive plugs 311, 312, 313, 314.

[0076]

[0083] Referring to FIG. 23 , the vertical power semiconductor device 8 is similar to the vertical power semiconductor device 7 and further includes a third portion 173 of the electrode material layer 17 similar to the vertical power semiconductor device 6. Due to the difference in structure between the double-trench semiconductor power device and the split-gate vertical power semiconductor device, the steps of FIGS. 10 and 11 are not required for the vertical power semiconductor device 8. That is, in the vertical power semiconductor device 8, the dielectric layers 22 and 23 are not formed before forming the electrode material layer 17. In some embodiments, during the formation of the dielectric layer 24 of the gate electrode structure 52 of FIG. 22 , a portion of the dielectric layer 24 on the capacitive electrodes 163 and 164 can be retained by using a photomask to define the pattern of the dielectric layer 24. As shown in FIG. 23 , the dielectric layer 24 has a first portion 241 of the gate electrode structure 52 located in the unit region R1 and a second portion 242 on the capacitive electrodes 163 and 164 in the terminal region R2. The third portion 173 of the electrode material layer 17 is spaced from the capacitive electrodes 163, 164 by the second portion 242 of the dielectric layer 24. In some embodiments, the third portion 173 of the electrode material layer 17 overlaps at least one of the capacitive electrodes 163 or 164.

[0077]

[0084] Referring to FIG. 24 , the vertical power semiconductor device 9 is a single-trench semiconductor power device and has a similar structure to the vertical power semiconductor device 7, except that the electrode structure 52 of the vertical power semiconductor device 7 is omitted (since the gate electrode structure and the shield electrode structure of the single-trench semiconductor power device are not distinguished, the gate electrode structure and the shield electrode structure are generally referred to as electrode structures when describing the single-trench semiconductor power device). As with the vertical power semiconductor devices 7 and 8, the capacitive electrodes 163 and 164 can be formed in the same step together with the electrode material layer 161 of the electrode structure 51. Those skilled in the art will understand the differences between the single-trench semiconductor power device and the dual-trench semiconductor power device, and other components can be adjusted accordingly as necessary.

[0078]

[0085] Referring to FIG. 25 , the vertical power semiconductor device 10 is similar to the vertical power semiconductor device 9, except that a source-doped region 143 is provided between the conductive plug 311 adjacent to the trench structure 61 and the trench structure 51 adjacent to the conductive plug 311. As described above, the trench structure 61 and the trench structure 51 may include a source-doped region according to requirements or specifications. In some embodiments, to maximize the formation of a functional semiconductor power structure, the source-doped region 143 may be provided between the conductive plug 311 near the trench structure 61 and the adjacent trench structure 51 (the trench structure 51 adjacent to the conductive plug 311). Since no source-doped region is provided between the trench structure 61 and its adjacent conductive plug 311, the stability and safety of the vertical power semiconductor device 10 can be ensured. The source-doped region 143 as shown in FIG. 25 can be applied to, but is not limited to, the vertical power semiconductor devices 1, 4, 5, 6, 7, 8, and 9. Furthermore, the third portion 173 of the conductive material layer 17 of FIGS. 20 and 23 can also be applied to the embodiments of FIGS. 24 and 25, but is not limited thereto.

[0079]

[0086] In this disclosure, for convenience of explanation, spatially relative terms such as “lower,” “below,” “lower side,” “upper,” “upper side,” “left side,” and “right side” may be used to describe the relationship of one component or feature to another component or feature, as shown in the accompanying drawings. Spatially relative terms are not only used to indicate the orientation of the accompanying drawings, but are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or at other orientations), and the spatially relative terms used herein may be interpreted in a similarly corresponding manner. When a component is referred to as being “coupled” or “connected” to another component, it should be understood that it may be directly connected or coupled to the other component, or that there may be intervening components.

[0080]

[0087] As used herein, the terms "approximately," "essentially," "substantially," and "about" are used to describe and account for minor variations. When used in connection with an event or instance, these terms can refer to embodiments of the exact occurrence of the event or instance, as well as embodiments in which the event or instance is close to occurring. When used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges herein can be referred to as being from one endpoint to the other endpoint or between two endpoints. All ranges disclosed herein include endpoints unless otherwise indicated. The term "substantially coplanar" can mean that the difference in the position of two surfaces relative to the same plane is within a few micrometers (μm), for example, within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm. When referring to a value or characteristic being "substantially" the same, the term can refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the mean of the value.

[0081]

[0088] The foregoing outlines features and detailed aspects of several embodiments of the present disclosure. The embodiments described in this disclosure may readily be used as a basis for designing or modifying other processes and structures to carry out the same or similar purposes and / or achieve the same or similar advantages of the embodiments presented herein. Such equivalent constructions do not depart from the spirit of the present disclosure, and various changes, substitutions, and alterations may be made thereto without departing from the spirit of the present disclosure.

[0082]

[0089] Although the description has been set forth in detail, it should be understood that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present disclosure, as defined by the appended claims. Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments described herein, as those skilled in the art will readily appreciate from this disclosure that now-existing or later-developed processes, machines, manufacture, compositions of matter, means, methods, or steps may perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. [Explanation of symbols]

[0083] 1 Vertical power semiconductor device 1~3 Vertical power semiconductor structure 4~10 Vertical power semiconductor devices 11 Drain contact region 11A surface 11B Surface 12 N-type semiconductor material layer 12A surface 12B surface 13 Body dope region 16 Conductive material layer, electrode material layer 17 Conductive material layer, electrode material layer 18 Interlayer Dielectric Layer 20 Dielectric Structure 20~24 dielectric layers 25 Lightly doped region 31 Conductive plug 32 metal layer 41~43 Trench 42a Lower part 50 Trench structure, electrode structure 51 Trench structure, shield electrode structure 52 Gate electrode structure 60 Trench structure 61 Trench structure 70 Trench structure 141 Source doped region 142 doped region 143 Source-doped region 151 Highly doped region 152 Highly doped region 161 First portion, electrode material layer 162 second part, electrode material layer 162a First part, lower part 162b Second part, upper part 163 Capacitive electrodes, electrode capacitance 163a Contact pad, contact point 163b Electrode bus bar 163c Combiner Bus 163d Finger-shaped part 164 Capacitive electrode, electrode capacitance, electrode capacitor 164a Contact pad, contact 165 Fourth part, electrode material layer 166 Third Part 171 First portion, electrode material layer 172 second part, electrode material layer 173 Third Part 241 First Part 242 Second Part 311~316 Conductive plug 321 Metal wiring 322 Metal wiring 411~415 Opening 601~604 Side wall 605 Upper surface 615 Upper surface

Claims

1. 1. A semiconductor structure comprising: a substrate including a first surface and a second surface facing each other, the substrate including a unit region and a terminal region adjacent to each other when viewed from above; a first gate electrode structure in the substrate, extending from the first surface toward the second surface, and disposed within the unit area; a first trench structure in the substrate, extending from the first surface toward the second surface, disposed within the unit area, adjacent to the terminal area, the first trench structure including a first semiconductor material layer extending to the first surface; a capacitive structure on the first surface of the substrate, disposed in the terminal region and adjacent to the first trench structure, the capacitive structure having the same material as the first semiconductor material layer and including a first capacitive electrode and a second capacitive electrode, the first capacitive electrode being connected to the first semiconductor material layer.

2. a second trench structure in the substrate, extending from the first surface toward the second surface and disposed within the terminal region, the second trench structure including a second semiconductor material layer extending to the first surface, the second capacitive electrode connected to the second semiconductor material layer; The semiconductor structure of claim 1 .

3. 2. The semiconductor structure of claim 1, wherein a bottom of said first gate electrode structure and a bottom of said first trench structure are at the same horizontal level.

4. the first gate electrode structure includes a first gate electrode layer and a first shield electrode layer below the first gate electrode layer; the first trench structure includes a second gate electrode layer adjacent to the first semiconductor material layer, the width of the first gate electrode layer being greater than the width of the second gate electrode layer; The semiconductor structure of claim 1 .

5. a bottom of the first gate electrode layer and a bottom of the second gate electrode layer are at the same horizontal level; a first portion of the first semiconductor material layer underlying the second gate electrode layer, and a second portion of the first semiconductor material layer connected to the first portion and disposed on a side of the second gate electrode layer; The semiconductor structure of claim 4 .

6. the first portion includes a first sidewall and a second sidewall opposed to each other; the second portion includes a third sidewall and a fourth sidewall opposed to each other; the first sidewall and the third sidewall are continuous sidewalls, the fourth sidewall terminates on an upper surface of the first portion, and the fourth sidewall and the second sidewall are discontinuous sidewalls. The semiconductor structure of claim 5 .

7. a width of the first portion of the first semiconductor material layer and a width of the first shield electrode layer are the same; the width of the first portion of the first semiconductor material layer is greater than the width of the second portion of the first semiconductor material layer; The semiconductor structure of claim 5 .

8. the first portion of the first semiconductor material layer includes an upper surface connected to the second portion of the first semiconductor material layer; the upper surface of the first portion of the first semiconductor material layer and the upper surface of the first shield electrode layer are at the same horizontal level; The semiconductor structure of claim 5 .

9. the first gate electrode structure includes a first electrode material layer extending from the first surface toward the second surface; a width of the first semiconductor material layer at the first surface being the same as a width of the first electrode material layer at the first surface; The semiconductor structure of claim 1 .

10. 10. The semiconductor structure of claim 9, wherein a bottom of the first electrode material layer and a bottom of the first semiconductor material layer are at the same horizontal level.

11. a top surface of the first capacitive electrode is coplanar with a top surface of the second capacitive electrode; a bottom surface of the first capacitive electrode on the first surface is coplanar with a bottom surface of the second capacitive electrode on the first surface; The semiconductor structure of claim 1 .

12. 2. The semiconductor structure of claim 1, wherein a thickness of the first capacitive electrode on the first surface is the same as a thickness of the second capacitive electrode on the first surface.

13. further comprising a conductive material layer overlying the capacitive structure and overlapping at least one of the first capacitive electrode and the second capacitive electrode. The semiconductor structure of claim 1 .

14. the first capacitive electrode and the second capacitive electrode comprise a semiconductor material; 14. The semiconductor structure of claim 13.

15. a first conductive plug on the first capacitive electrode, the first conductive plug being electrically connected to the first capacitive electrode; a second conductive plug on the second capacitive electrode, the second conductive plug being electrically connected to the second capacitive electrode; 10. The semiconductor structure of claim 1, further comprising:

16. a third conductive plug extending from above the first surface toward the second surface, the third conductive plug being disposed in the unit region and adjacent to the first gate electrode structure, the third conductive plug having an uppermost surface at the same horizontal level as an uppermost surface of the first conductive plug or the second conductive plug; 16. The semiconductor structure of claim 15.

17. a fourth conductive plug extending from above the first surface toward the second surface, the fourth conductive plug being disposed in the terminal region and adjacent to the second capacitive electrode, the second capacitive electrode being electrically connected to the fourth conductive plug via a metal wiring layer provided above the second conductive plug and the fourth conductive plug; 16. The semiconductor structure of claim 15.

18. 1. A method for manufacturing a semiconductor structure, comprising: forming a first trench and a second trench in a substrate, the substrate including a unit region and a terminal region adjacent to each other in a top view of the substrate; forming a first dielectric layer over the substrate underlying the first trench and the second trench; forming a first electrode material layer on the first dielectric layer, the first electrode material layer being disposed in the first trench and the second trench and covering a top surface of the substrate; performing a first etching on the first electrode material layer to remove at least a portion of the first electrode material layer on the top surface of the substrate within the unit area, wherein the first electrode material layer after the first etching includes a first portion in the first trench, a second portion in the second trench, and a third portion on the top surface of the substrate and connected to the second portion; forming a body-doped region in the substrate within the unit area and forming a source-doped region on the body-doped region, The first portion covers a bottom of the first trench, the second portion covers a bottom of the second trench and is adjacent to a first sidewall of the second trench, the first etching exposes a second sidewall of the second trench, the second sidewall being opposite the first sidewall. method.

19. 20. The method of claim 18, wherein the first trench and the second trench are disposed within the unit area, the second trench is adjacent to the terminal area, and the first trench is farther from the terminal area than the second trench.

20. The method of claim 18 , wherein the first portion and the second portion are disposed within the unit area, and the third portion is disposed within the terminal area.

21. performing a second etch on the first dielectric layer to remove portions of the first dielectric layer above the first and second portions in the first and second trenches and to remove portions of the first dielectric layer on a top surface of the substrate that are not covered by the third portion; performing a third etching on the third portion to form a first capacitive electrode and a second capacitive electrode; conformally forming a second dielectric layer over the substrate and the first electrode material layer; increasing a thickness of a bottom portion of the second dielectric layer in the first trench and the second trench; forming a second electrode material layer in the first trench and the second trench; 20. The method of claim 18, further comprising:

22. forming a conductive material layer over the third portion, the conductive material layer and the second electrode material layer being formed simultaneously; 22. The method of claim 21.

23. forming a third trench in the substrate adjacent to the first trench after the first etching, the third trench having a depth less than the depth of the first trench or the second trench; forming a third electrode material layer in the third trench; 20. The method of claim 18, further comprising:

24. 24. The method of claim 23, wherein the patterns of the first portion, the second portion, and the third portion are defined by use of the same photomask.

25. forming a conductive material layer over the third portion, wherein the conductive material layer and the third electrode material layer are formed simultaneously; 24. The method of claim 23.

26. performing a fourth etch after forming the body doped region and the source doped region to remove a portion of the substrate, a portion of the first capacitive electrode, and a portion of the second capacitive electrode; forming conductive plugs in contact with the substrate, the first capacitive electrode, and the second capacitive electrode, respectively, after the fourth etching is performed; 22. The method of claim 21 further comprising:

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