P-type dipole for P-FET

Abstract

To provide a method of controlling a threshold voltage of a semiconductor device.SOLUTION: An electronic device 200 comprises: a channel 206 located between a source 204a and a drain 204b; and a dipole region 208 having an interlayer dielectric (ILD) 210 deposited on a top surface 205 of the channel 206, a high-κ dielectric material 212 deposited on a top surface 211 of the ILD 210, and a dipole layer 214 deposited on a top surface 213 of the high-κ dielectric material 212. The dipole layer 214 contains one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular to transistors. More particularly, embodiments of the present disclosure are directed to FinFET devices and methods of manufacturing FinFET devices. [Background technology]

[0002] Integrated circuits have evolved into complex devices that can contain millions of transistors, capacitors, and resistors on a single chip. During the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be made using a manufacturing process) has decreased.

[0003] A transistor is a circuit component or element that is often formed on a semiconductor device. Many transistors may be formed on a semiconductor device along with capacitors, inductors, resistors, diodes, conductive lines, or other elements, depending on the circuit design. Integrated circuits incorporate planar field-effect transistors (FETs), which conduct current through a semiconductor channel between a source and a drain in response to an applied voltage to a control gate.

[0004] As device sizes have decreased, device structures and materials have experienced difficulty maintaining switching speeds without introducing failures. Several new technologies have emerged that allow chip designers to continue to reduce gate lengths. Controlling the size of device structures is a key challenge for current and future technology generations. Since 1970, the number of components per chip has doubled every two years. As a result of this trend, circuit miniaturization by shrinking transistors has become a major driver for semiconductor technology roadmaps.

[0005] There are challenges associated with developing novel p-type dipole materials that provide Vt shift but without the equivalent oxide thickness (EOT) penalty. The transition from planar to FinFET transistor technology requires conformal work function layers with multiple threshold voltage solutions. The Vt tuning range will be limited by thickness variations with further shrinking of device size. Dipole layers serve as an efficient measure to shift the work function on both the PMOS and NMOS sides, simplifying material requirements along with band edge requirements. Summary of the Invention

[0006] One or more embodiments are directed to an electronic device and a method of fabricating the electronic device, the electronic device having a source region, a drain region, and a channel separating the source and drain regions, and further having a dipole region on a top surface of the channel, the dipole region including an interlayer insulating film, a high-κ dielectric material, and a dipole layer.

[0007] In one or more embodiments, a method of fabricating an electronic device includes depositing an interlayer dielectric on a top surface of a channel located between a source and a drain on a substrate, depositing a high-κ dielectric material on the interlayer dielectric, and depositing a dipole layer on the high-κ dielectric material.

[0008] One or more embodiments are directed to a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform the following operations: depositing an interlayer dielectric on a top surface of a channel located between a source and a drain on a substrate; depositing a high-κ dielectric material on the interlayer dielectric; and depositing a dipole layer on the high-κ dielectric material.

[0009] In order that the above-mentioned features of the present disclosure may be understood in detail, a more detailed description of the present disclosure (briefly summarized above) will be obtained by reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered to limit the technical scope of the present disclosure, since the present disclosure may also admit of other equally effective embodiments. The embodiments described herein are illustrated by way of example and not by way of limitation to the accompanying drawings, in which like reference numerals indicate like elements. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a process flow diagram of one embodiment of a method according to embodiments described herein. [Figure 2] 1 is a cross-sectional view of a substrate according to one or more embodiments. [Figure 3A] 1 is a cross-sectional view of a substrate according to one or more embodiments. [Figure 3B] 1 is a cross-sectional view of a substrate according to one or more embodiments. [Figure 4] 1 illustrates a cluster tool in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of structure or process steps set forth in the following description as the present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0012] As used herein, the term "about" means "approximately" or "nearly," and in the context of a stated numerical value or range of values, refers to a variation of no more than ±15% of that numerical value. For example, values ​​that vary by ±14%, ±10%, ±5%, ±2%, or ±1% meet the definition of "about."

[0013] As used herein and in the appended claims, the term "substrate" or "wafer" refers to a surface or portion of a surface upon which a process acts. It will also be well understood by those skilled in the art that, unless the context clearly indicates otherwise, a reference to a substrate may refer to only a portion of that substrate. Additionally, a reference to a deposition on a substrate may refer to a bare substrate as well as a substrate having one or more films or features deposited or formed thereon.

[0014] As used herein, "substrate" refers to any substrate or any material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatments can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material (e.g., metals, metal nitrides, metal alloys, and other conductive materials), depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may undergo predetermined treatments to polish, etch, remove, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film treatments directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film treatment steps may also be performed on underlying layers formed on the substrate, as disclosed in more detail below. The term "substrate surface" is intended to include underlying layers when the context indicates. Thus, for example, where a film / layer, or partial film / layer, is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0015] As used herein and in the appended claims, the terms "precursor," "reactant," "reactant gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0016] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit layers of material on a substrate surface. A substrate, or portions of a substrate, are separately exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay, allowing each compound to adhere to and / or react with the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, any location on the substrate is not substantially exposed to multiple reactive compounds simultaneously, and different portions of the substrate surface or materials on the substrate surface are simultaneously exposed to multiple reactive compounds. The term "substantially" in this sense, as used herein and in the appended claims, means that, as will be understood by those skilled in the art, it is possible that a small portion of the substrate may be exposed to multiple reactive gases simultaneously due to diffusion, but such simultaneous exposure is not intended.

[0017] In one embodiment of a time-domain ALD process, a first reactant gas (i.e., a first precursor or compound A) is intermittently introduced into the reaction zone, followed by a first time delay. Then, a second precursor or compound B is intermittently introduced into the reaction zone, followed by a second delay. During each time delay, a purge gas (e.g., argon) is introduced into the processing chamber to purge the reaction zone or to remove any remaining reactive compound or reaction by-products from the reaction zone. Alternatively, the purge gas can flow continuously throughout the deposition process, with only the purge gas flowing during the time delays between intermittent introductions of the reactive compound. The reactive compound is instead intermittently introduced until the desired film or film thickness is formed on the substrate surface. In either procedure, an ALD process that intermittently introduces compound A, purge gas, compound B, and purge gas is one cycle. A cycle can begin with compound A or compound B, and the respective sequence of cycles can be continued until a film having a predetermined thickness is reached.

[0018] In a spatial ALD process embodiment, a first reactant gas and a second reactant gas (e.g., nitrogen gas) are simultaneously supplied to a reaction zone but separated by an inert gas curtain and / or a vacuum curtain, and the substrate is moved relative to the gas supply system so that every location on the substrate is exposed to the first reactant gas and the second reactant gas.

[0019] A transistor is a circuit component or element often formed on a semiconductor device. Depending on the circuit design, transistors may be formed on the semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Typically, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of a substrate and exhibit a doping profile appropriate for a particular application. The gate is disposed over the channel region and includes a gate dielectric disposed between the gate electrode and the channel region of the substrate.

[0020] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. A field effect transistor is a voltage-controlled device in which the ability of the field effect transistor to carry current is altered by applying an electric field. Field effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field of the device. The electric field is generated by a voltage difference between the body and gate of the device. The three terminals of a FET are the source (S), where carriers enter the channel, the drain (D), where carriers exit the channel, and the gate (G), which is the terminal that adjusts the channel conductivity. Conventionally, the current entering the channel at the source (S) is expressed as I S and the current entering the channel at the drain (D) is I D The drain to source voltage is V DS By applying a voltage to the gate (G), a current (i.e., I D) can be controlled.

[0021] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET) used in integrated circuits and high-speed switching applications. MOSFETs have an insulated gate, and the voltage across the gate determines the device's conductivity. This ability to change conductivity with the amount of applied voltage is used to amplify or switch electronic signals. MOSFETs rely on the modulation of charge concentration through metal-oxide-semiconductor (MOS) capacitance between the body electrode and the gate electrode. The gate electrode is located on the body and is insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET contains two additional terminals (source and drain). Each of the additional terminals (source and drain) is connected to a separate highly doped region. The separate highly doped regions are separated by a body region. These regions can be p-type or n-type. Both are of the same conductivity type, opposite to that of the body region. The source and drain (unlike the body) are highly doped, as indicated by the "+" sign after the doping conductivity type.

[0022] If the MOSFET is n-channel, or nMOSFET, the source and drain are n+ regions and the body is the p-type substrate region. If the MOSFET is p-channel, or pMOSFET, the source and drain are p+ regions and the body is the n-type substrate region. The source is so named because it is the source of charge carriers (electrons for n-channel and holes for p-channel) that flow through the channel. Similarly, the drain is where the charge carriers exit the channel.

[0023] An nMOSFET is made from an n-type source and drain and a p-type substrate. When a voltage is applied to the gate, holes in the body (p-type substrate) are driven away from the gate. This allows an n-type channel to form between the source and drain, and current flows from the electrons through the induced n-type channel from source to drain. Logic gates and other digital devices implemented using NMOSs are said to have NMOS logic. NMOS has three modes of operation: cutoff, triode, and saturation. Because direct current flows through the logic gate when the output is low, circuits with NMOS logic gates waste static power when the circuit is idle.

[0024] A pMOSFET is made from a p-type source and p-type drain and an n-type substrate. When a positive voltage is applied between the source and gate (a negative voltage between the gate and source), a p-type channel of the opposite polarity is formed between the source and drain. Current flows from the source to the drain via holes through the induced p-type channel. A high voltage on the gate makes the PMOS non-conductive, while a low voltage on the gate makes it conductive. Logic gates and other digital devices implemented using PMOS are said to have PMOS logic. PMOS technology is low cost and has good noise immunity.

[0025] In NMOS, the carriers are electrons, while in PMOS, the carriers are holes. When a high voltage is applied to the gate, PMOS does not conduct, while NMOS does. Furthermore, when a low voltage is applied to the gate, NMOS does not conduct, while PMOS does. NMOS is considered faster than PMOS because NMOS carriers, which are electrons, move twice as fast as PMOS carriers, which are holes. However, PMOS devices are more noise-resistant than NMOS devices. Furthermore, because NMOS can provide half the impedance presented by PMOS (with the same geometric and operating conditions), an NMOS IC is smaller than a PMOS IC (for the same functionality).

[0026] As used herein, the term "fin field effect transistor (FinFET)" refers to a MOSFET transistor fabricated on a substrate in which the gate is located on two, three, or four sides of the channel or wrapped around the channel, forming a double-gate structure. FinFET devices were given the generic name FinFETs because the source / drain regions form "fins" on the substrate. FinFET devices have fast switching times and high current densities.

[0027] One or more embodiments are directed to materials that can be used as effective dipoles for p-FETs that advantageously improve Vt and do not affect equivalent oxide thickness (EOT). Embodiments with new types of materials can be used for p-dipoles without EOT increase. Embodiments of the present disclosure significantly improve Vt without EOT penalty through novel integration schemes.

[0028] In one or more embodiments, materials are advantageously provided that exhibit p-metal behavior. Materials of one or more embodiments include, but are not limited to, titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium aluminum carbide (TiAlC), or tantalum oxide (TaO). Other embodiments are directed to methods of incorporating dipolar materials for p-FETs.

[0029] In one or more embodiments, films including p-metal materials are provided. The films deposited by atomic layer deposition exhibit PMOS work function performance. The growth of the p-dipole material is achieved in an ALD chamber at temperatures ranging from 150°C to 500°C. An in-situ capping layer, such as TiN or TiAl, can be used to control oxidation of the film after deposition.

[0030] In some embodiments, the growth of TiAlN / TiTaN is carried out in an ALD chamber having a temperature range of 200° C. to 500° C. In some embodiments, the amount of aluminum (Al) and tantalum (Ta) is adjusted by varying the intermittent introduction cycle of the titanium (Ti) precursor and the intermittent introduction cycle of the aluminum (Al) and tantalum (Ta) precursors.

[0031] Some embodiments provide tantalum oxide (TaO) films. In some embodiments, the growth of TaO is by ALD at a temperature range of 150°C to 500°C.

[0032] Embodiments of the present disclosure include dipole materials that provide a Vfb shift of more than 100 mV with minimal EOT increase. In some embodiments, this alleviates the need to develop extreme p-type work function materials. The p-type TiAlN / TiTaN is capped with TiN in situ (e.g., in a cluster tool) to prevent oxidation and EOT increase. In some embodiments, the Al or Ta content of the TiAlN / TiTaN can be adjusted to adjust the work function shift. Some embodiments enable multi-Vt tuning. In one or more embodiments, multi-Vt tuning can be achieved through both composition and dipole film thickness.

[0033] Some embodiments of the present disclosure are directed to atomic layer deposition methods for depositing titanium aluminum nitride (TiAlN) films. According to some embodiments, an ALD cycle includes exposing a substrate to an intermittent introduction of a titanium precursor to form a titanium-containing layer on the substrate surface. The titanium precursor is then purged from the processing chamber or removed from the reaction zone adjacent to the substrate surface. The substrate with the titanium-containing layer is then exposed to an intermittent introduction of a nitrogen reactant (e.g., ammonia) to form a titanium nitride-containing layer on the substrate surface. The nitrogen reactant is then purged from the processing chamber or removed from the reaction zone adjacent to the substrate surface. The substrate with the titanium nitride-containing layer is then exposed to an intermittent introduction of an aluminum reactant to form a titanium aluminum nitride film. The aluminum reactant is then purged from the processing chamber or removed from the reaction zone adjacent to the substrate surface.

[0034] In some embodiments, the titanium precursor comprises a titanium halide, TiX4. In some embodiments, the titanium halide comprises TiCl4. In other embodiments, the precursor is any suitable titanium metal organic precursor.

[0035] In some embodiments, the precursor comprises a tantalum halide, TaX4. In some embodiments, the tantalum halide comprises TaCl4. In other embodiments, the precursor is any suitable tantalum metal organic precursor.

[0036] In some embodiments, the aluminum precursor comprises aluminum amine. In some embodiments, the aluminum precursor comprises triethyl aluminum, trimethyl aluminum, tri-tert-butyl aluminum, and the like.

[0037] In some embodiments, the reactant comprises a nitriding agent. In some embodiments, the nitriding agent comprises ammonia. In some embodiments, the nitriding agent comprises a plasma.

[0038] In some embodiments, the reactants include an oxidizer. In some embodiments, the oxidizer includes O2 or water. In some embodiments, the oxidizer includes plasma.

[0039] In some embodiments, the reaction pressure is in the range of about 0 mTorr to about 100 Torr, or in the range of about 100 mTorr to about 50 Torr, or in the range of about 1 Torr to about 40 Torr, or in the range of about 10 Torr to about 35 Torr, or in the range of about 20 Torr to about 30 Torr.

[0040] In some embodiments, the growth rate of TiAlN films grown using trimethylaluminum as a reactant ranges from about 0.2 Å / cycle to about 2 Å / cycle, or from about 0.5 Å / cycle to about 1.5 Å / cycle, or from about 0.8 Å / cycle to about 1.2 Å / cycle, or about 1 Å / cycle.

[0041] In some embodiments, the surface of the TiAlN film has (atomic) titanium in the range of about 5% to about 20% and aluminum in the range of about 1% to about 20% as measured by XPS. In some embodiments, the surface of the TiAlN film has (atomic) titanium in the range of about 8% to about 17% and aluminum in the range of about 1% to about 9% as measured by XPS. In some embodiments, the surface of the TiAlN film has (atomic) titanium in the range of about 10% to about 15% and aluminum in the range of about 1% to about 7%.

[0042] One or more embodiments provide a method for fabricating an electronic device. In some embodiments, the method includes depositing an interlayer dielectric on a top surface of a channel located between a source and a drain on a substrate, depositing a high-κ dielectric material on the interlayer dielectric, and depositing a dipole layer on the high-κ dielectric material. In one or more embodiments, the dipole layer includes one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC). In one or more embodiments, depositing the dipole layer includes atomic layer deposition of alternating cycles of titanium nitride (TiN) and a dipole precursor at a temperature ranging from about 200°C to about 500°C. In one or more embodiments, the dipole precursor includes one or more of titanium halide, triethylaluminum, tantalum halide, tantalum metal organic precursor, titanium metal organic precursor, aluminum nitride (AlN), or tantalum nitride (TaN).

[0043] Some embodiments of the present disclosure are directed to methods of forming a metal-oxide-semiconductor capacitor (MOSCAP). A substrate including a high-κ dielectric layer and an optional high-κ cap layer is subjected to one or more processes to form a dipole adjustment layer and an optional dipole cap layer (e.g., TiN) on the dipole adjustment layer. In some embodiments, an amorphous silicon (a-Si) film is formed on the dipole adjustment layer or the dipole cap layer. In some embodiments, the a-Si layer and the film stack on which the a-Si layer is formed are annealed to adjust the dipole of the high-κ dielectric layer and form a tuned high-κ dielectric layer. In some embodiments, the a-Si layer, the optional dipole cap layer, and the dipole adjustment layer are removed using one or more suitable etching or stripping processes. In some embodiments, a work function metal layer is deposited on the dipole-tuned high-κ dielectric layer. In some embodiments, a filler metal layer is formed on the work function metal layer.

[0044] In some embodiments, the flatband voltage of the resulting MOSCAP increases by about 20 mV or more, 30 mV or more, 40 mV or more, 50 mV or more, 60 mV or more, 70 mV or more, 80 mV or more, 90 mV or more, or 100 mV or more. In some embodiments, the equivalent oxide thickness (EOT) of the high-κ dielectric layer increases by an amount ranging from about 0 Angstroms to about 1.0 Angstroms.

[0045] Several embodiments of the present disclosure are described using drawings. The drawings illustrate devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The processes shown are merely exemplary possible applications for the disclosed processes, and one skilled in the art will recognize that the disclosed processes are not limited to the applications shown.

[0046] 1 shows a flow diagram of a method 100 according to one or more embodiments of the present disclosure. Referring to FIG. 1, the method 100 begins at operation 102 by depositing an interlayer dielectric on a top surface of a channel located between a source and a drain on a substrate. In operation 104, a high-κ dielectric material is deposited on the interlayer dielectric. In operation 106, a dipole layer is deposited on the high-κ dielectric material. In operation 108, an optional cap layer is deposited on the dipole layer.

[0047] 2, 3A, and 3B are cross-sectional views of an electronic device (e.g., a transistor) 200 according to one or more embodiments. Referring to FIGS. 2 and 3A, the electronic device 200 includes a semiconductor substrate 202 having a top surface 203. The semiconductor substrate 202 can be any suitable substrate material. In one or more embodiments, the semiconductor substrate 202 includes a semiconductor material (e.g., silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphate (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), copper indium gallium selenide (CIGS), other semiconductor materials, or any combination thereof). In one or more embodiments, the semiconductor substrate 202 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), copper (Cu), or selenium (Se). While several examples of materials from which the substrate 202 can be formed are described herein, any material that can serve as a substrate upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic elements, or any other electronic device) can be built is within the spirit and scope of the present disclosure.

[0048] In one or more embodiments, the semiconductor substrate 202 is a p-type or n-type substrate. As used herein, the term "n-type" refers to a semiconductor created by doping an intrinsic semiconductor with an electron-donating element during fabrication. The term n-type comes from the negative charge of the electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a higher hole concentration than electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers.

[0049] 2 and 3A, source region 204a is on top surface 203 of semiconductor substrate 202. In one or more embodiments, source region 204a has a source and a source contact (not shown). Drain region 204b is on the opposite side of top surface 203 of semiconductor substrate 202 from source region 204a. In one or more embodiments, drain region 204b has a drain and a drain contact (not shown).

[0050] In one or more embodiments, the source region 204a and / or the drain region 204b can be any suitable material known to those skilled in the art. In one or more embodiments, the source region 204a and / or the drain region 204b can have two or more layers. For example, the source region 204a and / or the drain region 204b can each include three layers. In one or more embodiments, the source region 204a and the drain region 204b can each include one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), platinum (Pt), phosphorous (P), germanium (Ge), silicon (Si), aluminum (Al), or zirconium (Zr). In some embodiments, the source region 204a and the drain region 204b can each include a bottom layer of silicon with doped epi (e.g., SiGe, SiP, etc.), a second layer of silicide which may include nickel (Ni), titanium (Ti), aluminum (Al), etc., and a third or top layer which may be a metal such as, but not limited to, cobalt, tungsten, ruthenium, etc.

[0051] In some embodiments, the source region 204a and the drain region 204b are formed by epitaxial growth and may be elevated source / drain regions.

[0052] In one or more embodiments, the source and / or drain contacts may each be selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In one or more embodiments, the formation of the source and / or drain contacts is done by any suitable process known to those skilled in the art, including, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art.

[0053] In one or more embodiments, the channel 206 is located between the source 204a and the drain 204b.

[0054] In one or more embodiments, the dipole region 208 overlies the channel 206 and is in contact with one or more of the channel 206, the source region 204a, and the drain region 204b. In one or more embodiments, the dipole layer has a thickness of less than about 50 angstroms.

[0055] In one or more embodiments, the dipole region 208 includes one or more of an interlayer dielectric (ILD) 210, a high-κ dielectric material 212, and a dipole layer 214. In some embodiments, the dipole region 208 includes an interlayer dielectric (ILD) 210, a high-κ dielectric material 212, and a dipole layer 214.

[0056] In one or more embodiments, an interlayer dielectric (ILD) 210 is deposited on the top surface 205 of the channel 206. In one or more embodiments, the interlayer dielectric 210 can be any suitable material known to those skilled in the art. For example, in one or more embodiments, the interlayer dielectric 210 comprises a low-κ dielectric. In one or more embodiments, the low-κ dielectric is selected from one or more of silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, SiCONH, doped silicon, doped silicon oxide, doped silicon nitride, doped silicon oxynitride, spin-on dielectric, or diffusion-seeded grown material. In one or more embodiments, the interlayer dielectric 210 comprises silicon oxide. The interlayer dielectric (ILD) 210 can be deposited using one or more deposition techniques known to those skilled in the art of microelectronic device fabrication. In one or more embodiments, the interlayer dielectric (ILD) 210 is deposited using one of several deposition techniques (such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art). In one or more embodiments, the interlayer dielectric (ILD) 210 may be formed by etching and oxide formation on the surface.

[0057] In one or more embodiments, high-κ dielectric material 212 is deposited on top surface 211 of interlayer dielectric (ILD) 210. High-κ dielectric material 212 can be any suitable high-κ dielectric material known to those of skill in the art. In one or more embodiments, high-κ dielectric material 212 comprises a hafnium oxide or a lanthanum (La) doped high-κ dielectric. In one or more embodiments, high-κ dielectric material 212 is deposited using one of several deposition techniques (such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those of skill in the art).

[0058] Typically, a high-κ cap layer (such as, for example, titanium nitride (TiN)) is deposited on top of the high-κ dielectric material. However, in one or more embodiments, a dipole layer 214 is deposited instead of the high-κ dielectric material.

[0059] In one or more embodiments, the dipole layer 214 is deposited on the upper surface 213 of the high-κ dielectric material 212. In one or more embodiments, the dipole layer 214 is deposited using one of a number of deposition techniques (e.g., ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art). In one or more specific embodiments, the dipole layer 214 is deposited by atomic layer deposition (ALD). In one or more embodiments, the dipole layer 214 is deposited by atomic layer deposition at a temperature ranging from about 150°C to about 500°C.

[0060] In one or more embodiments, the channel 206 includes a p-type material and the dipole layer 214 includes one or more of aluminum nitride (AlN), titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), and tantalum oxide (TaO).

[0061] 3A and 3B, in one or more embodiments, the dipole layer 214 comprises a p-dipole material film deposited by atomic layer deposition between about 150°C and about 500°C. In one or more embodiments, the p-dipole material film is deposited by alternating cycles of TiN and, for example, aluminum nitride (AlN). In one or more embodiments, the aluminum content of the combined dipole layer 214 can be adjusted by adjusting the cycle ratio between TiN and TiAlN. With reference to FIG. 3B, in one or more embodiments, the p-dipole material film 214 on the PFET side 250 is removed by patterning.

[0062] In one or more embodiments, the channel 206 includes a p-type material and the dipole layer 214 includes one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).

[0063] In one or more embodiments, a high temperature thermal anneal is performed to drive the metal in the high-κ material 212 to form n- and p-dipoles. The remaining TiN is used directly as the high-κ cap layer.

[0064] Without intending to be bound by theory, it is believed that a dipole layer including one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC) simplifies existing integration flows and reduces integration costs. In addition, it is believed that when one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), or titanium oxide (TiO) are embedded in a TiN layer, oxidation may be reduced, which may reduce the required annealing temperature. Furthermore, the above-described composite dipole layer 214 method provides excellent control over the amount of one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC), enabling multi-voltage endurance of electronic devices.

[0065] In one or more embodiments, an in-situ cap layer (eg, of titanium nitride (TiN) or titanium aluminum (TiAl)) may be used to control oxidation of the film after deposition.

[0066] In one or more embodiments, a gate including one or more of a gate metal (not shown) or a gate contact (not shown) may optionally be formed or deposited on the exposed surface of the dipole region 208. The gate metal may be any material known to those skilled in the art. In one or more embodiments, the gate metal includes one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), aluminum (Al), or platinum (Pt). In one or more particular embodiments, the gate metal comprises a metal selected from one or more of nitrogen (N), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), iridium (Ir), aluminum (Al), or platinum (Pt). In other particular embodiments, the gate metal 226 comprises a metal selected from one or more of nitrogen (N), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), or ruthenium (Ru). In one or more embodiments, the gate contact may be any suitable material known to those skilled in the art. In one or more embodiments, the gate contact is selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), aluminum (Al), or platinum (Pt).

[0067] In one or more embodiments, a cap layer may be deposited on the surfaces exposed to the dipole region 208. In one or more embodiments, the cap layer may include one or more of titanium nitride (TiN) or titanium aluminum (TiAl).

[0068] One or more embodiments are directed to an electronic device including a source region (a source region on an upper surface of a substrate) having a source and a source contact, a drain region (a drain region on an upper surface of a substrate) having a drain and a drain contact, a channel located between the source and drain, and a dipole region on an upper surface of the channel. The dipole region includes an interlayer insulating film, a high-κ dielectric material, and a dipole layer. The dipole layer includes one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).

[0069] Further embodiments of the present disclosure are directed to a processing tool 900 for the formation of logic / memory devices, as shown in FIG. 4, and methods described therein.

[0070] The cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are disposed within the central transfer stations 921, 931 and configured to move a robot blade and a wafer toward each of the multiple sides.

[0071] Cluster tool 900 includes multiple processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918 (also referred to as processing stations and connected to a central transfer station). The various processing chambers provide separate processing regions isolated from adjacent process stations. The processing chambers may be any suitable chamber, including, but not limited to, pre-clean chambers, buffer chambers, transfer spaces, wafer orienter / degas chambers, cryo-cooling chambers, deposition chambers, annealing chambers, etch chambers, thermal processing (RTP) chambers, plasma oxidation chambers, plasma nitridation chambers, and atomic layer deposition (ALD) chambers. The specific arrangement of process chambers and components may vary depending on the cluster tool and should not be construed as limiting the scope of the present disclosure.

[0072] In one or more embodiments, the cluster tool 900 includes a silicon oxide (SiO) chamber to deposit silicon oxide (SiO). In some embodiments, the silicon oxide (SiO) deposition chamber includes an atomic layer deposition chamber, a plasma-enhanced atomic layer deposition chamber, or a spatial atomic layer deposition chamber. In one or more embodiments, the cluster tool 900 includes a pre-clean chamber connected to a central transfer station.

[0073] 4, factory interface 950 connects to the front of cluster tool 900. Factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front 951 of factory interface 950. While loading chamber 954 is shown on the left and unloading chamber 956 is shown on the right, one skilled in the art will understand that this is merely an example of one possible configuration.

[0074] The size and shape of the loading chamber 954 and unloading chamber 956 can vary depending on, for example, the substrate being processed in the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and unloading chamber 956 are sized to hold a wafer cassette with multiple wafers disposed within the cassette.

[0075] The robot 952 resides within the factory interface 950 and can move between a loading chamber 954 and an unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 through the factory interface 950 to a load lock chamber 960. The robot 952 can also transfer wafers from the load lock chamber 962 through the factory interface 950 to a cassette in the unloading chamber 956. As will be appreciated by those skilled in the art, the factory interface 950 can include multiple robots 952. For example, the factory interface 950 can include a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960 and a second robot that transfers wafers between the load lock chamber 962 and the unloading chamber 956.

[0076] The illustrated cluster tool 900 has a first section 920 and a second section 930. The first section 920 is connected to a factory interface 950 via load lock chambers 960 and 962. The first section 920 includes a first transfer chamber 921 having at least one robot 925 disposed therein. The robot 925 is also referred to as a robotic wafer transport mechanism. The first transfer chamber 921 is centrally located relative to the load lock chambers 960 and 962, the process chambers 902, 904, 916, and 918, and the buffer chambers 922 and 924. In some embodiments, the robot 925 is a multi-arm robot capable of independently moving multiple wafers at a time. In one or more embodiments, the first transfer chamber 921 includes multiple robotic wafer transport mechanisms. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Individual wafers are transported on a wafer transport blade at the end of the first robotic mechanism.

[0077] After processing the wafer in the first section 920, the wafer may be passed through a pass-through chamber to the second section 930. For example, chambers 922, 924 may be one-way or two-way pass-through chambers. The pass-through chambers 922, 924 may be used, for example, to cool the wafer to a low temperature before processing in the second section 930, or to allow cooling or post-processing of the wafer before returning to the first section 920.

[0078] A system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 may be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 may be a computer including a central processing unit, memory, appropriate circuitry, and storage devices.

[0079] The processes may generally be stored in the memory of the system controller 990 as software routines that, when executed by a processor, cause the process chamber to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the processes may be implemented in software and executed in hardware using a computer system, for example, as an application-specific integrated circuit or other type of hardware implementation, or may be performed in a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls chamber operation such that processes are performed.

[0080] In one or more embodiments, the processing tool 900 includes a central transfer station 921, 931 including at least one robot 925, 935 configured to transfer wafers; one or more of a rapid thermal processing (RTP) station, a decoupled plasma oxidation (DPO) station, or a decoupled plasma nitridation (DPN) station connected to the central transfer station; an atomic layer deposition (ALD) station connected to the central transfer station; an optional pre-clean station connected to the central transfer station; and at least one controller connected to one or more of the central transfer station, the RTP station, the DPO station, the DPN station, the ALD station, or the optional pre-clean station. In one or more embodiments, the at least one controller has at least one configuration selected from the following: to transfer wafers between stations using a robot; to perform a rapid thermal process; to perform a decoupled plasma process; to control the flow of oxidizing gas into the RTP station or the DPO station; to control the flow of nitriding gas into the RTP station or the DPN station; to deposit a silicon oxide film by atomic layer deposition; and to pre-clean wafers.

[0081] For ease of description, spatially relative terms (e.g., "below," "below," "below," "above," "above," etc.) may be used herein to describe the relationship of one element or feature to other elements or features as shown in the figures. It will be understood that spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the orientation of the device in the figures were reversed, an element described as "below" or "below" another element or feature would be oriented "above" the other element or feature. Thus, the exemplary term "below" can encompass both an up and down orientation. The device may be oriented in another orientation (rotated 90 degrees or otherwise), and the spatially relative descriptions used herein would be interpreted accordingly.

[0082] The use of the terms "a," "an," and "said," and similar references in the context of describing the materials and methods set forth herein (particularly in the context of the claims below), should be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of referring individually to each separate value within that range, unless otherwise indicated herein, and each separate value is incorporated herein as if it were individually referred to herein. Unless otherwise indicated herein or clearly contradicted by context, all methods described herein can be performed in any suitable order. Any and all examples or exemplary phrases (e.g., "such as") presented herein are intended merely to further clarify the materials and methods and do not state a limitation on the scope unless otherwise recited in a claim. No language herein should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0083] References throughout this specification to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that the particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0084] Although the present disclosure has been described herein with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. depositing an interlayer insulating film on an upper surface of a channel located between a source and a drain on a substrate; depositing a high-κ dielectric material on the interlayer dielectric; depositing a p-type dipole layer on the high-κ dielectric material, the p-type dipole layer comprising one or more of aluminum nitride, titanium oxide (TiO), and tantalum oxide (TaO); depositing in-situ a cap layer comprising one or both of titanium nitride and titanium aluminum; thermally annealing the device; A method for fabricating a p-FET, comprising:

2. The method of claim 1 , wherein the p-type dipole layer comprises aluminum nitride and has a thickness of less than 50 Å.

3. 10. The method of claim 1, further comprising depositing a gate metal on the p-type dipole region including the interlayer dielectric, the high-κ dielectric material, and the p-type dipole layer.

4. 4. The method of claim 3, wherein the gate metal comprises one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), aluminum (Al), and platinum (Pt).

5. 10. The method of claim 1, wherein the source and the drain each comprise one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), platinum (Pt), phosphorous (P), germanium (Ge), silicon (Si), aluminum (Al), and zirconium (Zr).

6. The method of claim 1 , wherein the interlayer dielectric comprises a low-κ dielectric.

7. 7. The method of claim 6, wherein the low-κ dielectric is selected from one or more of silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, doped silicon, doped silicon oxide, and spin-on dielectrics.

8. The method of claim 1 , wherein the high-κ dielectric material comprises one or both of hafnium oxide and a lanthanum (La) doped high-κ dielectric.

9. The p-type dipole layer is formed by ionizing ammonia (NH ３ 10. The method of claim 1, wherein the p-type dipole precursor is formed by exposing the substrate to alternating cycles of titanium halides, aluminum amines, aluminum nitride, tantalum nitride, triethylaluminum, trimethylaluminum, tri-tert-butylaluminum, tantalum halides, titanium metal organic precursors, and tantalum metal organic precursors.

10. When executed by the process chamber controller, depositing an interlayer insulating film on an upper surface of a channel located between a source and a drain on a substrate; depositing a high-κ dielectric material on the interlayer dielectric; depositing a p-type dipole layer comprising one or more of aluminum nitride, titanium oxide (TiO), and tantalum oxide (TaO) on the high-κ dielectric material, wherein the p-type dipole layer is deposited by ion implantation of ammonia (NH ) at a temperature in the range of 150°C to 500°C; ３ ) and a p-type dipole precursor; depositing in-situ a cap layer comprising one or both of titanium nitride and titanium aluminum; thermally annealing the device; a non-transitory computer-readable medium comprising instructions for causing the processing chamber to perform operations including:

11. 11. The non-transitory computer-readable medium of claim 10, comprising instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform further operations including depositing a gate metal on a p-type dipole region comprising the interlayer dielectric, the high-κ dielectric material, and the p-type dipole layer.

12. 1. A method for fabricating a p-FET, comprising: depositing an interlayer insulating film on an upper surface of a channel located between a source and a drain on a substrate; depositing a high-κ dielectric material on the interlayer dielectric; Ammonia (NH ３ depositing a p-type dipole layer on the high-κ dielectric material by exposing the substrate to alternating cycles of a p-type dipole precursor comprising one or more of aluminum nitride, aluminum amine, tantalum nitride, triethylaluminum, tantalum halide, and tantalum metal organic precursor, and the p-type dipole layer comprising one or more of aluminum nitride, titanium oxide (TiO), and tantalum oxide (TaO); depositing in-situ a cap layer comprising one or both of titanium nitride and titanium aluminum; A method comprising:

13. The method of claim 12 , wherein the p-type dipole layer has a thickness of less than 50 Å.

14. 13. The method of claim 12, further comprising depositing a gate metal on the interlayer dielectric, the high-κ dielectric material, and a dipole region including the p-type dipole layer.

15. The method of claim 12 , wherein the interlayer dielectric comprises a low-κ dielectric.

16. 13. The method of claim 12, wherein the high-κ dielectric material comprises one or both of hafnium oxide and a lanthanum (La) doped high-κ dielectric.

Images