Gallium nitride semiconductor device manufacturing method and gallium nitride semiconductor device

Abstract

To provide a method of manufacturing a gallium nitride semiconductor device and a gallium nitride semiconductor device capable of reducing a level density at an interface between gallium nitride and an oxide film.SOLUTION: A method of manufacturing a gallium nitride semiconductor device includes the following steps of: forming an oxide film on gallium nitride; and applying heat treatment to the oxide film and the gallium nitride in an atmosphere gas containing nitrogen oxide.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a gallium nitride semiconductor device and a gallium nitride semiconductor device. [Background technology]

[0002] There are states at the interface between gallium nitride (GaN) and silicon oxide (SiO2). When SiO2 on GaN is used as the gate insulating film of a MOSFET, a high state density at the GaN / SiO2 interface can reduce the channel mobility of the MOSFET and cause carrier traps, which can lead to an increase in the on-resistance of the MOSFET and a decrease in reliability.

[0003] It has been predicted from theoretical calculations that the levels at the GaN / SiO2 interface arise when O atoms occupy N vacancies that are generated by the desorption of N on the GaN side near the interface between GaN and SiO2 (see, for example, Non-Patent Document 1).

[0004] Therefore, it would be ideal not to oxidize the GaN surface during SiO2 film formation, but in plasma CVD, the GaN surface is irradiated with O plasma in the early stages of SiO2 film formation, resulting in the formation of gallium oxide (GaOx).In the transition region where GaOx is formed at the GaN / SiO2 interface, spatially localized levels are formed within the band gap of GaN, which becomes a carrier trap source, which is undesirable.

[0005] A conventional technique for reducing the interface state density is to deposit an SiO2 film by remote plasma CVD (see, for example, Non-Patent Document 2). This method does not introduce defects due to plasma damage into the GaN surface during SiO2 film deposition, so it is possible to prevent an increase in levels due to defects. However, nitrogen atoms (N) are desorbed from GaN during annealing after SiO2 film deposition. It has been difficult to avoid the formation of levels due to this N desorption.

[0006] It should be noted that a technique for reducing SiC / SiO2 interface states by heat treatment in an atmosphere containing NO is known (see, for example, Patent Document 1). In SiC, this NO treatment can terminate dangling bonds of excess C at the SiC / SiO2 interface with N atoms. However, this technique is merely a technique for reducing C (carbon)-related defects in SiC. GaN does not contain C to begin with, and therefore does not have excess C. The level formation caused by N desorption in GaN, which is the subject of the present invention, occurs through a mechanism that is completely different from the C-related defects in SiC. For this reason, the technique for reducing C-related defects in SiC cannot provide a clue to solving the problem of the present invention. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-67917 [Non-patent literature]

[0008] [Non-Patent Document 1] The 82nd Autumn Meeting of the Japan Society of Applied Physics, 23a-P10-11 [Non-patent document 2] J.Vac.Sci.TechNOl.A22,2402(2004) Summary of the Invention [Problem to be solved by the invention]

[0009] It is desirable to reduce the state density at the interface between gallium nitride and an oxide film.

[0010] The present invention has been made in light of the above-mentioned problems, and aims to provide a method for manufacturing a gallium nitride semiconductor device that can reduce the state density at the interface between gallium nitride and an oxide film, and a gallium nitride semiconductor device. [Means for solving the problem]

[0011] In order to solve the above problems, a method for manufacturing a gallium nitride semiconductor device according to one aspect of the present invention includes the steps of forming an oxide film on gallium nitride and subjecting the oxide film and the gallium nitride to a heat treatment in an atmosphere gas containing nitrogen oxides.

[0012] A gallium nitride semiconductor device according to one aspect of the present invention includes gallium nitride, an oxide film provided on the gallium nitride, and an electrode provided on the oxide film. The trap charge density at the interface between the gallium nitride and the oxide film in the band gap E=Ev+0.9 eV is 5×10 11 cm -2 where E is an arbitrary energy and Ev is the energy of the valence band. [Effects of the Invention]

[0013] According to the present invention, it is possible to provide a method for manufacturing a gallium nitride semiconductor device and a gallium nitride semiconductor device that are capable of reducing the state density at the interface between gallium nitride and an oxide film. [Brief explanation of the drawings]

[0014] [Figure 1] 1A to 1C are cross-sectional views illustrating a method for manufacturing a GaN semiconductor device according to a first embodiment of the present invention. [Figure 2] 2A to 2C are cross-sectional views illustrating a method for manufacturing the GaN semiconductor device according to the first embodiment of the present invention. [Figure 3] FIG. 3 is a cross-sectional view showing an example of the configuration of a MOS capacitor for measuring the trapped charge density. [Figure 4] FIG. 4 is a CV characteristic diagram that schematically shows a method for measuring the trapped charge density. [Figure 5] FIG. 5 is a graph schematically showing the band gap at the GaN / SiO 2 interface of the MOS capacitor shown in FIG. [Figure 6] 6A to 6C are cross-sectional views showing the steps of a method for manufacturing a GaN semiconductor device according to a comparative example of the present invention. [Figure 7]FIG. 7 is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the second embodiment of the present invention. [Figure 8] FIG. 8 is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the second embodiment of the present invention. [Figure 9] FIG. 9 is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the third embodiment of the present invention. [Figure 10] FIG. 10 is a cross-sectional view showing a method for manufacturing a GaN semiconductor device according to the third embodiment of the present invention. [Figure 11] FIG. 11 is a plan view showing a configuration example of a GaN semiconductor device according to a fourth embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] An embodiment of the present invention will be described below. In the following description of the drawings, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each component, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0016] In the following description, directions may be described using the terms X-axis, Y-axis, and Z-axis. For example, the X-axis and Y-axis directions are parallel to the surface 1a of the GaN substrate 1 described below. The X-axis and Y-axis directions are also referred to as horizontal directions. The Z-axis direction is a direction perpendicular to the surface 1a of the GaN substrate 1. The X-axis, Y-axis, and Z-axis directions are orthogonal to each other.

[0017] In the following description, the positive direction of the Z axis may be referred to as "up" and the negative direction of the Z axis may be referred to as "down." "Up" and "down" do not necessarily refer to the vertical direction relative to the ground. In other words, the "up" and "down" directions are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship between regions, layers, films, substrates, etc., and do not limit the technical concept of the present invention. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up."

[0018] In the following description, + or - attached to p or n indicating the conductivity type means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the same p and p (or n and n) are attached to semiconductor regions, this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0019] <Embodiment 1> (GaN semiconductor device manufacturing method) A method for manufacturing a gallium nitride semiconductor device (hereinafter, GaN semiconductor device) according to embodiment 1 of the present invention will be described below. Figures 1 and 2 are cross-sectional views illustrating the method for manufacturing the GaN semiconductor device according to embodiment 1 of the present invention.

[0020] GaN semiconductor devices are manufactured using various types of equipment, such as film formation equipment (e.g., plasma CVD (Chemical Vapor Deposition) equipment, thermal CVD equipment, remote plasma CVD equipment, and thermal oxidation equipment), heat treatment equipment, ion implantation equipment, exposure equipment, etching equipment, and CMP (Chemical Mechanical Polishing) equipment. Hereinafter, these equipment will be collectively referred to as manufacturing equipment.

[0021] In step ST1 of FIG. 1, the manufacturing equipment forms an oxide film 2 on a surface 1a of a GaN substrate 1 (an example of "gallium nitride" according to the present invention) by plasma CVD. The oxide film 2 contains at least one of Si oxide and Al oxide. For example, the oxide film 2 contains Si oxide. An example of Si oxide is a silicon oxide (SiO2) film. In the initial stage of the process of forming the oxide film 2, the surface 1a of the GaN substrate 1 is irradiated with plasma. This plasma irradiation causes desorption of nitrogen atoms (N) constituting the GaN substrate 1 (i.e., N vacancies) at and near the surface 1a of the GaN substrate 1.

[0022] The oxide film 2 may be an Al oxide, and an example of the Al oxide is an aluminum oxide (Al2O3) film.

[0023] Step ST2 in Fig. 1 shows the state after the oxide film 2 is formed. The thickness of the oxide film 2 is, for example, 100 nm. As shown in step ST2 in Fig. 1, N vacancies are generated due to desorption of nitrogen atoms (N) at the surface 1a of the GaN substrate 1 that contacts the oxide film 2 and in the vicinity thereof (hereinafter referred to as the interface IF).

[0024] 1, the manufacturing equipment performs a heat treatment (annealing) on ​​the oxide film 2 and the GaN substrate 1. This heat treatment is performed in an atmosphere gas 3 containing nitrogen oxides. The nitrogen oxides include, for example, at least one of NO and NO. Note that the atmosphere gas 3 containing nitrogen oxides may contain components other than nitrogen oxides (for example, inert gases such as nitrogen (N) and argon (Ar)).

[0025] The maximum temperature of the heat treatment in step ST3 is, for example, 500°C or higher and 1000°C or lower. Nitric oxide (NO) or nitrogen dioxide (NO2) decomposes more easily than nitrogen molecules (N2). For example, at temperatures of 500°C or higher and 1000°C or lower, NO or NO2 decomposes into N and O, but N2 hardly decomposes. The treatment time at the maximum temperature of this heat treatment is, for example, 10 to 60 minutes. The pressure of the atmospheric gas 3 is, for example, atmospheric pressure.

[0026] In the heat treatment of step ST3, NO or NO2 contained in the atmospheric gas 3 during the heat treatment decomposes and separates into N and O, and the separated N permeates the oxide film 2 and reaches the surface 1a of the GaN substrate 1. Then, as shown in step ST4 of Fig. 2, the N that has reached the surface 1a of the GaN substrate 1 fills the N vacancies that have occurred at the interface IF of the GaN substrate 1. This makes it possible to compensate for the N vacancies that have occurred at the interface IF of the GaN substrate 1 and to prevent O atoms from entering the N vacancies.

[0027] For example, as shown in step ST5 of Fig. 2, the number of O atoms entering N vacancies can be reduced compared to a comparative example (see Fig. 6) described later. This reduces the state density at the interface between the GaN substrate 1 and the oxide film 2. In this specification, this state density at the interface (i.e., interface state density) is also referred to as the trapped charge density.

[0028] (Method for measuring trapped charge density) FIG. 3 is a cross-sectional view showing an example of the configuration of a MOS capacitor for measuring trapped charge density. FIG. 4 is a CV characteristic diagram that schematically shows a method for measuring trapped charge density. The X axis of FIG. 4 represents the voltage (V) applied to the upper electrode of the MOS capacitor shown in FIG. 3, and the vertical axis represents the capacitance (F) of the MOS capacitor. FIG. 5 is a graph that schematically shows the band gap of the GaN / SiO2 interface of the MOS capacitor shown in FIG. 3. The horizontal axis of FIG. 5 represents the wave number (k), and the vertical axis represents the energy (eV). Furthermore, E represents an arbitrary energy, and Ev represents the energy of the valence band.

[0029] As shown in Figure 3, the trapped charge density is measured by forming a p-type MOS capacitor by disposing an oxide film 2 and a GaN substrate 1 between an upper electrode 5 and a lower electrode 6, and measuring the CV characteristics of this p-type MOS capacitor. For example, the GaN substrate 1 shown in Figure 3 has pThe upper electrode 5 is a gate electrode 22 of the MOSFET (see FIG. 12 described later), and the lower electrode 6 is a stage electrode of a CV measuring device (not shown). In a p-type MOS capacitor, when a negative voltage is applied to the upper electrode 5 with the lower electrode 6 fixed to a ground potential (for example, 0 (V)), p The surface 1a of the p-type GaN substrate 1 is Accumulation A layer is formed.

[0030] The trapped charge density ρ at the interface between the GaN substrate 1 and the oxide film 2 is defined by the following formula (1). ρ = (Cox / qS) × Vshift [cm -2 ]…(1)

[0031] In equation (1), Cox is the oxide film capacitance, q is the elementary charge, and S is the electrode area. Vshift is the voltage shift between the curve when sweeping from a positive bias to a negative bias and the curve when sweeping from a negative bias to a positive bias in the CV characteristics of the p-type MOS capacitor shown in Figure 4.

[0032] The trapped charge density ρ at the band gap E=Ev+0.9 eV (see FIG. 5) at the interface between the GaN substrate 1 formed by the manufacturing method according to the embodiment of the present invention and the oxide film 2 is, for example, 5×10 11 cm -2 The following is the result.

[0033] The trapped charge density depends on the value of the energy level (E-Ev) in the band gap. For example, even at the same interface, the trapped charge density at E-Ev=0.8 eV and the trapped charge density at E-Ev=0.9 eV will be different values. Therefore, when specifying the trapped charge density numerically, it is necessary to determine the value of E-Ev in advance. In the embodiment of the present invention, traps were confirmed when the energy level was 0.9 eV when a gate bias was applied, so the value of E-Ev was set to 0.9 eV.

[0034] (Comparative Example) 6 is a cross-sectional view showing the order of steps in a manufacturing method of a GaN semiconductor device according to a comparative example of the present invention. In step ST1R of FIG. 6, the process is the same as that of the first embodiment up to the step of forming an oxide film 2 on a GaN substrate 1. In the comparative example, after forming the oxide film 2, a heat treatment (annealing) is performed on the oxide film 2 and the GaN substrate 1. This heat treatment is performed in an atmospheric gas 3R containing only nitrogen (N2). N2 is less likely to decompose than NO and NO2, and hardly decomposes even at temperatures of, for example, 500°C or higher and 1000°C or lower.

[0035] Therefore, the N atom density in the atmosphere gas 3R is lower than in the first embodiment. Since the number of N atoms that penetrate the oxide film 2 and reach the surface 1a of the GaN substrate 1 is small, O atoms tend to enter the N vacancies at the interface IF, as shown in step ST2R in FIG. 6, and these O atoms tend to cause the trapped charge density to become high. According to the knowledge of the inventors, the trapped charge density in the comparative example is 3.6× 10 12 cm -2 The above is assumed.

[0036] (Effects of the First Embodiment) As described above, the method for manufacturing the GaN semiconductor device according to the first embodiment of the present invention includes the steps of forming an oxide film 2 on a GaN substrate 1 and performing a heat treatment on the oxide film 2 and the GaN substrate 1 in an atmospheric gas containing nitrogen oxides (e.g., NO or NO).

[0037] According to this, during the heat treatment, nitrogen oxides contained in the atmospheric gas decompose and separate into N and O, and the separated N permeates the oxide film 2 and reaches the surface 1a of the GaN substrate 1. The N that reaches the surface 1a of the GaN substrate 1 then fills the N vacancies that have occurred at the surface 1a of the GaN substrate 1 and in its vicinity (i.e., the interface IF). This makes it possible to compensate for the N vacancies that have occurred at the interface IF of the GaN substrate 1 and to prevent O atoms from entering the N vacancies. This makes it possible to reduce the interface state density (trapped charge density) between the GaN substrate 1 and the oxide film 2.

[0038] That is, to prevent nitrogen atoms (N) from being released from the GaN substrate 1, heat treatment is performed in an atmosphere containing nitrogen oxides in a temperature and pressure range where the GaN substrate 1 maintains a solid phase. This makes it possible to reduce the interface state density (trapped charge density) between the GaN substrate 1 and the oxide film 2. For example, the trapped charge density at the band gap E-Ev=0.9 eV at the interface between GaN and the oxide film can be reduced to 5×10 11 cm -2 It can be the following:

[0039] (Variation) In the above-described first embodiment, the oxide film 2 is formed by plasma CVD. However, in the first embodiment (and later-described second and third embodiments) of the present invention, the formation of the oxide film 2 is not limited to plasma CVD. For example, the oxide film 2 may be formed by thermal CVD or remote plasma CVD. Even in such a case, N vacancies generated at the interface IF of the GaN substrate 1 during the formation of the oxide film 2 can be filled with N generated by decomposition of NO or NO, thereby compensating for the N vacancies generated at the interface IF.

[0040] <Embodiment 2> In the above embodiment, the heat treatment is performed in an atmosphere containing nitrogen oxide after the oxide film 2 is formed. However, the present invention is not limited to this. In the embodiment of the present invention, the oxide film 2 may be formed in multiple steps, and the heat treatment may be performed in an atmosphere containing nitrogen oxide between the nth (n is an integer of 1 or more) film formation step and the (n+1)th film formation step.

[0041] (GaN semiconductor device manufacturing method) 7 and 8 illustrate a manufacturing method of a GaN semiconductor device according to embodiment 2 of the present invention. FIGS. 7 and 8 are cross-sectional views illustrating a manufacturing method of a GaN semiconductor device according to embodiment 2 of the present invention. In step ST11 of FIG. 7, the manufacturing equipment forms a first oxide film 2A on the surface 1a of the GaN substrate 1 by plasma CVD. The first oxide film 2A is a part of the oxide film 2 and is, for example, an SiO2 film. The thickness of the oxide film 2A is, for example, 20 nm or more and 50 nm or less. In the initial stage of the process of forming the first oxide film 2A, the surface 1a of the GaN substrate 1 is irradiated with plasma. This plasma irradiation causes desorption of nitrogen atoms (N) constituting the GaN substrate 1 from the surface 1a of the GaN substrate 1 and its vicinity.

[0042] Step ST12 in Fig. 7 shows the state after the formation of the first oxide film 2A. As shown in step ST12 in Fig. 7, N vacancies are generated due to desorption of nitrogen atoms (N) at the surface 1a of the GaN substrate 1 that contacts the oxide film 2 and in the vicinity thereof (i.e., the interface IF).

[0043] 7, the manufacturing equipment performs a heat treatment (annealing) on ​​the first oxide film 2A and the GaN substrate 1. This heat treatment is performed in an atmosphere gas 3 containing nitrogen oxides (e.g., NO or NO), as in the first embodiment. The atmosphere gas 3 containing nitrogen oxides may contain components other than nitrogen oxides (e.g., inert gases such as N and Ar).

[0044] The maximum temperature of the heat treatment in step ST13 is, for example, 500° C. to 1000° C. The treatment time at the maximum temperature of this heat treatment is, for example, 10 to 60 minutes. The pressure of the atmospheric gas 3 is, for example, normal pressure.

[0045] In the heat treatment of step ST13, NO or NO2 contained in the atmospheric gas 3 during the heat treatment decomposes and separates into N and O, and the separated N penetrates the first oxide film 2A and reaches the surface 1a of the GaN substrate 1. The N that has reached the surface 1a of the GaN substrate 1 then fills the N vacancies that have occurred at the interface IF of the GaN substrate 1. This makes it possible to compensate for the N vacancies that have occurred at the interface IF of the GaN substrate 1 and to prevent O atoms from entering the N vacancies.

[0046] 7, the number of O atoms entering N vacancies can be reduced compared to the comparative example (see FIG. 6), thereby reducing the level density (i.e., trapped charge density) at the interface between the GaN substrate 1 and the first oxide film 2A.

[0047] Next, as shown in step ST15 of FIG. 7, the manufacturing equipment forms a second oxide film 2B on the first oxide film 2A by plasma CVD. The first oxide film 2A is a part of the oxide film 2 and is, for example, an SiO2 film. The thickness of the second oxide film 2B is, for example, 50 nm to 80 nm. In the second embodiment, the total thickness of the first oxide film 2A and the second oxide film 2B is, for example, 100 nm.

[0048] In the initial stage of the process of forming second oxide film 2B, plasma is irradiated onto the surface of first oxide film 2A. Since surface 1a of GaN substrate 1 is covered with first oxide film 2A, desorption of nitrogen atoms (N) from surface 1a of GaN substrate 1 and its vicinity hardly occurs.

[0049] (Effects of the second embodiment) According to the method for manufacturing a GaN semiconductor device according to the second embodiment of the present invention, the step of forming oxide film 2 includes the steps of forming a first oxide film 2A, which is a part of oxide film 2, on GaN substrate 1, and forming a second oxide film 1B, which is a part of oxide film 2, on first oxide film 2A. The step of subjecting oxide film 2 to a heat treatment is performed on first oxide film 2A and GaN substrate 1 in an atmospheric gas containing nitrogen oxide (e.g., NO or NO2) before forming second oxide film 2B.

[0050] Even with this manufacturing method, it is possible to compensate for nitrogen (N) vacancies that have occurred at the interface IF of the GaN substrate 1, and to prevent O atoms from entering the N vacancies. This makes it possible to reduce the interface state density (trapped charge density) between the GaN substrate 1 and the oxide film 2. For example, the trapped charge density at the band gap E-Ev=0.9 eV at the interface between the GaN and the oxide film can be reduced to 5×10 11 cm -2 It can be the following:

[0051] Furthermore, the oxide film through which nitrogen atoms (N) permeate during heat treatment is the first oxide film 2A, and the thickness of the oxide film through which N permeates during heat treatment can be made thinner than in the first embodiment. This makes it possible to further increase the amount of N that reaches the surface 1a of the GaN substrate 1. This may further reduce the trapped charge density.

[0052] (Variation) In the above-described second embodiment, the first oxide film 2A and the second oxide film 2B are described as being films of the same composition (e.g., SiO2 film) and formed by the same film formation method (e.g., plasma CVD method). However, the second embodiment of the present invention is not limited to this. The first oxide film 2A and the second oxide film 2B do not have to be films of the same composition. For example, the first oxide film 2A may be a SiO2 film, and the second oxide film 2B may be an Al2O3 film. Alternatively, the first oxide film 2A may be formed by the remote plasma CVD method, and the second oxide film 2B may be formed by the plasma CVD method. Even in such a case, the effects of the second embodiment can be achieved.

[0053] <Embodiment 3> In the embodiment of the present invention, nitrogen atoms (N) may be ion-implanted into the oxide film 2 before the oxide film 2 is subjected to a heat treatment in an atmospheric gas containing nitrogen oxides.

[0054] 9 and 10 are cross-sectional views showing a manufacturing method of a GaN semiconductor device according to embodiment 3 of the present invention. Steps ST21 and ST22 in FIG. 9 are the same as steps ST1 and ST2 in FIG. 1. As shown in steps ST21 and ST22, the manufacturing equipment forms an oxide film 2 by plasma CVD. The thickness of the oxide film 2 is, for example, 100 nm. Plasma irradiation during the formation of the oxide film 2 causes desorption of nitrogen atoms (N) constituting the GaN substrate 1 (i.e., N vacancies) at and near the surface 1a of the GaN substrate 1.

[0055] 9, the manufacturing equipment ions-implants nitrogen atoms (N) into the oxide film 2. In this ion implantation, the ion implantation conditions for N are set so that the implantation peak of N is located at the interface between the oxide film 2 and the GaN substrate 1 and in the vicinity thereof.

[0056] As shown in the comparative example above, the trapped charge density of the comparative example is 3.6× 10 12 cm -2 Based on this, it is assumed that the dose of N in step ST23 is 5.0×, which is higher than the trapped charge density in the comparative example. 10 12 cm -2 However, the dose of N is preferably 5.0× or more. 10 12 cm -2 It is not limited to the above, but can be 5.0 x 10 12 cm -2 It may be less than.

[0057] The subsequent steps are the same as those in embodiment 1. In step ST24 of Fig. 10, the manufacturing equipment performs a heat treatment (annealing) on ​​the oxide film 2 and the GaN substrate 1. This heat treatment is performed in an atmosphere gas 3 containing nitrogen oxides (e.g., NO or NO2), as in embodiment 1. The atmosphere gas 3 containing nitrogen oxides may contain components other than nitrogen oxides (e.g., inert gases such as N2 and Ar).

[0058] The maximum temperature of the heat treatment in step ST24 is, for example, 500° C. to 1000° C. The treatment time at the maximum temperature of this heat treatment is, for example, 10 to 60 minutes. The pressure of the atmospheric gas 3 is, for example, normal pressure.

[0059] In the heat treatment of step ST24, NO or NO2 contained in the atmospheric gas 3 during the heat treatment decomposes and separates into N and O. The separated N penetrates the oxide film 2 and reaches the surface 1a of the GaN substrate 1. Nitrogen atoms (N) ion-implanted into the oxide film 2 also reach the surface 1a of the GaN substrate 1 by thermal diffusion. Then, as shown in step ST25, the N atoms that have reached the surface 1a of the GaN substrate 1 fill N vacancies that have occurred at the interface IF of the GaN substrate 1, thereby compensating for the N vacancies. This makes it possible to prevent O atoms from entering the N vacancies and reduce the trapped charge density at the interface between the GaN substrate 1 and the oxide film 2.

[0060] (Effects of the third embodiment) As described above, in the method for manufacturing a GaN semiconductor device according to the third embodiment of the present invention, nitrogen atoms (N) are ion-implanted into oxide film 2 before the step of performing heat treatment.

[0061] Even with this manufacturing method, it is possible to compensate for nitrogen (N) vacancies that have occurred at the interface IF of the GaN substrate 1, and to prevent O atoms from entering the N vacancies. This makes it possible to reduce the interface state density (trapped charge density) between the GaN substrate 1 and the oxide film 2. For example, the trapped charge density at the band gap E-Ev=0.9 eV at the interface between the GaN and the oxide film can be reduced to 5×10 11 cm -2 It can be the following:

[0062] Furthermore, the ion implantation of N can further increase the amount of N supplied to the interface IF of the GaN substrate 1. This may further reduce the trapped charge density.

[0063] <Embodiment 4> Next, an example of a GaN semiconductor device manufactured using any one of the methods for manufacturing a GaN semiconductor device according to the first to third embodiments will be described.

[0064] Fig. 11 is a plan view showing a configuration example of a GaN semiconductor device 100 according to embodiment 4 of the present invention. Fig. 12 is a cross-sectional view showing the configuration example of a GaN semiconductor device 100 according to embodiment 4. Fig. 12 shows a cross section of the plan view shown in Fig. 11 taken along line X1-X'1 parallel to the X-axis direction.

[0065] As shown in FIGS. 11 and 12, a GaN semiconductor device 100 according to the fourth embodiment includes a GaN substrate 1 and a lateral MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 20 provided on the GaN substrate 1.

[0066] The GaN substrate 1 includes, for example, a GaN single crystal substrate 11, an n-type GaN layer 12 provided on the GaN single crystal substrate 11, and a p-type GaN layer 13 provided on the n-type GaN layer 12.

[0067] The GaN single crystal substrate 11 is, for example, an n+ type c-plane GaN single crystal substrate. The n-type impurities contained in the GaN single crystal substrate 11 are one or more of Si (silicon), O (oxygen), and Ge (germanium). For example, the GaN single crystal substrate 11 contains Si as an n-type impurity, and the impurity concentration of Si in the GaN single crystal substrate 11 is 5×10 17 cm -3 The thickness of the GaN single crystal substrate 11 is, for example, 350 μm.

[0068] The GaN single crystal substrate 11 has a dislocation density of 1×10 7 cm -2The GaN single crystal substrate 11 may be a low-dislocation freestanding substrate having a dislocation density of less than 1000 nm. When the GaN single crystal substrate 11 is a low-dislocation freestanding substrate, the dislocation density of the GaN layer 13 formed on the GaN single crystal substrate 11 is also low. Furthermore, by using a low-dislocation freestanding substrate, leakage current in the power device can be reduced even when a large-area power device is formed on the GaN substrate 1. This allows the manufacturing equipment to manufacture power devices with a high yield rate. Furthermore, it is possible to prevent ion-implanted impurities from diffusing deeply along dislocations during heat treatment.

[0069] The GaN layer 12 is a layer epitaxially grown on the surface of the GaN single crystal substrate 11, and contains, for example, Si as an n-type impurity. Si is doped during the epitaxial growth of the GaN layer 12. The donor concentration (for example, Si concentration) in the GaN layer 12 is, for example, 5×10 15 cm -3 5x10 or more 16 cm -3 is less than 2×10 16 cm -3 The thickness of the GaN layer 12 is, for example, 1 μm or less.

[0070] The GaN layer 13 is a layer epitaxially grown on the surface of the GaN layer 12, and contains Mg (magnesium) as a p-type impurity. Mg is doped during the epitaxial growth of the GaN layer 13. The Mg concentration in the GaN layer 13 is, for example, 1×10 16 cm -3 More than 1×10 18 cm -3 is less than 1×10 17 cm -3 The thickness of the GaN layer 13 is, for example, 4 μm.

[0071] The configuration of GaN substrate 1 is not limited to the above. For example, there may be no n-type GaN layer 12, and p-type GaN layer 13 may be provided directly on n+-type GaN single crystal substrate 11. GaN substrate 1 may also be composed of only a Mg-doped p-type single crystal GaN layer. That is, GaN substrate 1 may be a Mg-doped p-type GaN single crystal substrate.

[0072] The lateral MOSFET 20 includes an oxide film 2 provided on a p-type GaN layer 13 doped with Mg, a gate electrode 22 (an example of an "electrode" in the present invention) provided on the oxide film 2, an n+ type source region 23 provided in the GaN layer 13, an n+ type drain region 24 provided in the GaN layer 13, a source electrode 25 provided above the GaN layer 13 and in contact with the source region 23, and a drain electrode 26 provided above the GaN layer 13 and in contact with the drain region 24. In the MOSFET 20, the oxide film 2 functions as a gate insulating film.

[0073] The oxide film 2 is, for example, an SiO2 film or an Al2O3 film, as described in the first to third embodiments. The thickness of the SiO2 film, which is the oxide film 2, is, for example, 100 nm.

[0074] The gate electrode 22 is adjacent to the channel region via the oxide film 2. The gate electrode 22 is made of, for example, aluminum (Al) and has a thickness of 200 nm. The gate electrode 22 may also be made of a material other than Al. For example, the gate electrode 22 may be made of polysilicon doped with a metal such as Ti, Ni, or W, or an impurity, or may be made of a silicide such as WSi or NiSi.

[0075] The source region 23 and the drain region 24 are provided in the GaN layer 13 below both sides of the gate electrode 22. The source region 23 and the drain region 24 are, for example, n+ type impurity-implanted layers. The source region 23 and the drain region 24 are doped with Si at a concentration of 1×10 19 cm -3 5x10 or more 20 cm -3Contains the following concentrations:

[0076] 12, the source electrode 25 is in contact with the source region 23 and the p-type GaN layer 13 through an opening h1 provided in the oxide film 2. This allows the potential of the p-type GaN layer 13 to be fixed to the potential of the source electrode 25. The drain electrode 26 is in contact with the drain region 24 through an opening h2 provided in the oxide film 2. The drain electrode 26 is not in contact with the p-type GaN layer 13.

[0077] The source electrode 25 and the drain electrode 26 are made of Al or an Al-Si alloy, Ni, a Ni alloy, a Ti-Al alloy, a Ni-Au alloy, or the like. The source electrode 25 may have a barrier metal layer between it and the source region 23. The drain electrode 26 may have a barrier metal layer between it and the drain region 24. The barrier metal layer may be made of Ti (titanium). That is, the source electrode 25 and the drain electrode 26 may be a stack of a Ti layer and an Al layer, or a stack of a Ti layer and an Al-Si alloy layer. The source electrode 25 may also serve as a source pad (not shown), or may be an electrode provided separately from the source pad. The drain electrode 26 may also serve as a drain pad (not shown), or may be an electrode provided separately from the drain pad.

[0078] The source electrode 25 may be directly connected to the p-type GaN layer 13 or may be indirectly connected via a p-type layer (not shown). In this way, the potential of the p-type GaN layer 13 may be fixed to the potential of the source electrode 25.

[0079] Furthermore, the portion of source electrode 25 that contacts source region 23 and the portion that contacts p-type GaN layer 13 (i.e., the portion that functions as a body electrode) may be made of the same material or different materials.

[0080] 12 shows an example in which source electrode 25 also serves as a body electrode connected to p-type GaN layer 13 (i.e., they are integrated), but the fourth embodiment of the present invention is not limited to this. GaN semiconductor device 100 may also include a body electrode connected to p-type GaN layer 13 in addition to source electrode 25. Even in this case, source electrode 25 and body electrode may be made of the same material or different materials.

[0081] That is, the source electrode 25 shown in FIG. 12 may be divided into a first electrode portion in contact with the n+ type source region 23 and a second electrode portion (body electrode) in contact with the p-type GaN layer 13. The first electrode portion and the second electrode portion may be separated from each other, and an interlayer insulating film may be disposed between the first electrode portion and the second electrode portion. The second electrode portion may be connected to wiring having the same potential as the first electrode portion, or may be connected to wiring having a different potential from the first electrode portion. The first electrode portion and the second electrode portion may be made of the same material or different materials.

[0082] The method for manufacturing GaN semiconductor device 100 according to the fourth embodiment includes the steps of forming oxide film 2 on GaN substrate 1 and performing a heat treatment on oxide film 2 and GaN substrate 1 in an atmospheric gas containing nitrogen oxide (e.g., NO or NO2). After this heat treatment, gate electrode 22 is formed on oxide film 2.

[0083] This makes it possible to compensate for nitrogen (N) vacancies generated at the interface IF (see, for example, FIG. 1) of the GaN substrate 1, and reduce the trapped charge density at the interface between the GaN substrate 1 and the oxide film 2. For example, the trapped charge density at the band gap E-Ev=0.9 eV at the interface between the GaN and the oxide film can be reduced to 5×10 11 cm -2 This makes it possible to improve the electrical characteristics of the MOSFET 20.

[0084] (Other embodiments) As described above, the present invention has been described by the embodiments and modifications thereof, but the descriptions and drawings forming part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure.

[0085] For example, in the fourth embodiment described above, the GaN semiconductor device 100 has been described as having a horizontal MOSFET 20. However, the MOSFET included in the GaN semiconductor device 100 is not limited to a horizontal type in which a current flows horizontally relative to the GaN substrate 1, and may be a vertical type in which a current flows vertically relative to the GaN substrate 1. The vertical MOSFET may have a planar structure or a trench gate structure.

[0086] In either structure, after the formation of the oxide film 2 and before the formation of the gate electrode 22, a heat treatment is performed in an atmospheric gas containing nitrogen oxide such as NO or NO. This compensates for N vacancies generated at the interface IF of the GaN substrate 1, and reduces the trapped charge density at the interface between the GaN substrate 1 and the oxide film 2.

[0087] As such, the present technology naturally includes various embodiments not described herein. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the above-described embodiments and modifications. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present. [Explanation of symbols]

[0088] 1. GaN substrate 1a surface 1B Second oxide film 2. Oxide film 2A First oxide film 2B Second oxide film 3. 3R Atmospheric Gas 5 Upper electrode 6 Lower electrode 11 GaN single crystal substrate 12 GaN layers 13 GaN layer 20 MOSFET 22 gate electrode 23 Source Region 24 Drain region 25 Source electrode 26 Drain electrode 100 GaN semiconductor devices h1 opening h2 opening IF interface

Claims

1. forming an oxide film on the gallium nitride; and performing a heat treatment on the oxide film and the gallium nitride in an atmosphere gas containing nitrogen oxides, The step of forming the oxide film includes: forming a first oxide film, which is a part of the oxide film, on the gallium nitride; forming a second oxide film, which is a part of the oxide film, on the first oxide film; The heat treatment step includes: before forming the second oxide film, the first oxide film and the gallium nitride are subjected to the treatment in an atmosphere gas containing nitrogen oxide.

2. The method for manufacturing a gallium nitride semiconductor device according to claim 1 , further comprising the step of forming an electrode on the oxide film that has been subjected to the heat treatment.

3. 3. The method for manufacturing a gallium nitride semiconductor device according to claim 1, wherein the maximum temperature of the heat treatment is 500°C or higher and 1000°C or lower.

4. In the step of forming the oxide film, 4. The method for manufacturing a gallium nitride semiconductor device according to claim 1, wherein the oxide film is formed by thermal CVD, plasma CVD, or remote plasma CVD.

5. 5. The method for manufacturing a gallium nitride semiconductor device according to claim 1, further comprising the step of ion-implanting nitrogen atoms into said oxide film before said heat treatment step.

6. The method for manufacturing a gallium nitride semiconductor device according to claim 1 , wherein the oxide film contains at least one of a silicon oxide and an aluminum oxide.

7. Gallium nitride and an oxide film provided on the gallium nitride; an electrode provided on the oxide film, The trapped charge density at the band gap E=Ev+0.9 eV at the interface between the gallium nitride and the oxide film is 5×10 １１ cm －２ The following is a gallium nitride semiconductor device. however, E is an arbitrary energy, Ev is the energy of the valence band.

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