SOI wafer and its manufacturing method

Abstract

To provide SOI wafers suitable for use in MEMS devices while suppressing warpage and a method for manufacturing the same.SOLUTION: It is an SOI wafer having a silicon wafer for a support substrate, an intermediate layer on the silicon wafer for the support substrate, and a single crystal silicon layer on the intermediate layer, and the intermediate layer has a BOX layer made of SiOx (0.59≤x≤0.78).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an SOI wafer and a method for manufacturing the same. [Background technology]

[0002] An SOI wafer (silicon on insulator) has a structure in which an insulating film such as silicon oxide (SiO2) and a single-crystal silicon layer used as a device active layer are sequentially formed on a support substrate. One of the typical manufacturing methods for SOI wafers is the bonding method. In this bonding method, an oxide film (BOX (buried oxide) layer) is formed on at least one of the support substrate and the active layer substrate, and then these substrates are stacked together with the oxide film interposed between them, followed by a bonding heat treatment at a high temperature of approximately 1200°C to produce an SOI wafer (see, for example, Patent Document 1). In recent years, SOI wafers have also been increasingly used as materials for MEMS devices such as acceleration sensors. When using SOI wafers for MEMS device applications, the BOX layer is required to not only function as a conventional insulating layer but also to be easy to handle, which necessitates new approaches. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 8-78644 Summary of the Invention [Problem to be solved by the invention]

[0004] The BOX layer used in conventional SOI wafers is made of silicon dioxide (SiO2). Silicon dioxide (SiO2) has a thermal expansion coefficient that differs significantly from the adjacent single-crystal silicon. As a result, warpage occurs in the wafer during the processing and heating steps used to fabricate MEMS devices due to the difference in thermal expansion coefficient. In MEMS devices with microstructures for sensor applications, this warpage has a direct adverse effect on the detection signal, so it is necessary to eliminate warpage in SOI wafers. Therefore, the object of the present invention is to provide an SOI wafer suitable for use in MEMS devices while suppressing warpage, and a method for manufacturing the same. [Means for solving the problem]

[0005] The present inventors have conducted research to solve the above problems, and have discovered that silicon-rich SiO 2 is used as the BOX layer instead of silicon oxide, which has been generally used as the BOX layer in SOI wafers. x The inventors have investigated the use of an intermediate layer having a BOX layer made of (x<2). If the composition is made closer to that of silicon (Si), which is the composition of the adjacent support substrate and active layer, the difference in thermal expansion coefficient can be suppressed, and it is expected that warpage will be eliminated. However, a slight change in composition cannot sufficiently eliminate warpage, and on the other hand, if the composition is made too close to that of silicon, the etching rate with acid will drop significantly, making it unsuitable for the fabrication of MEMS devices. Therefore, the inventors have investigated the use of SiO in the BOX layer. x Further investigations were carried out into the composition x of the BOX layer, and a composition suitable for use in MEMS devices was found. The present invention was completed based on the above findings, and the gist of the present invention is as follows.

[0006] <1> An SOI wafer comprising a silicon wafer for a support substrate, an intermediate layer on the silicon wafer for the support substrate, and a single-crystal silicon layer on the intermediate layer, wherein the intermediate layer is SiO x An SOI wafer having a BOX layer consisting of (0.59≦x≦0.78).

[0007] <2> The intermediate layer has an adhesion layer made of amorphous silicon or silicon oxide. <1> 2. The SOI wafer according to claim 1 .

[0008] <3> The intermediate layer has an adhesive layer directly on the BOX layer, and the adhesive layer is made of amorphous silicon. <2> 2. The SOI wafer according to claim 1 .

[0009] <4> The intermediate layer has an adhesive layer directly below the BOX layer, and the adhesive layer is made of amorphous silicon. <2> 2. The SOI wafer according to claim 1 .

[0010] <5> The intermediate layer has an adhesive layer directly on the BOX layer, and the adhesive layer is made of silicon oxide. <2> 2. The SOI wafer according to claim 1 .

[0011] <6> The intermediate layer has an adhesive layer directly under the BOX layer, and the adhesive layer is made of silicon oxide. <2> 2. The SOI wafer according to claim 1 .

[0012] <7> Claim <1> ~ <6> 10. A method for producing an SOI wafer according to claim 9, wherein the BOX layer is formed by using a plasma CVD method (PE-CVD).

[0013] Hereinafter, the method of forming an activation region on each of the silicon wafer for the support substrate and the silicon wafer for the single crystal silicon layer and bonding the two wafers together at their activation regions in a vacuum at room temperature will be referred to as the "vacuum room temperature bonding method." [Effects of the Invention]

[0014] According to the present invention, it is possible to provide an SOI wafer suitable for use in MEMS devices while suppressing warpage, and a method for manufacturing the same. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a schematic cross-sectional view illustrating an outline of an SOI wafer according to the present invention. [Figure 2] 1 is a schematic cross-sectional view illustrating a first embodiment of an SOI wafer according to the present invention. [Figure 3]FIG. 2 is a schematic cross-sectional view illustrating a second embodiment of an SOI wafer according to the present invention. [Figure 4] FIG. 10 is a schematic cross-sectional view illustrating a third embodiment of an SOI wafer according to the present invention. [Figure 5] FIG. 10 is a schematic cross-sectional view illustrating a fourth embodiment of an SOI wafer according to the present invention. [Figure 6] FIG. 10 is a schematic cross-sectional view illustrating a fifth embodiment of an SOI wafer according to the present invention. [Figure 7] FIG. 1 is a conceptual diagram showing an example of an apparatus used when performing vacuum room temperature bonding in one embodiment of a method for producing bonded silicon wafers according to the present invention. [Figure 8] 1 is a graph showing the evaluation results of the amount of warpage in SOI wafers according to an example and a comparative example. [Figure 9] 1 is a graph showing evaluation results of etching rates in SOI wafers according to an example and a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments of the present invention will be described in order with reference to the drawings. For the sake of convenience, the thickness of each component is exaggerated in each drawing. Therefore, the thickness of each component differs from the actual thickness ratio.

[0017] (SOI wafer) An SOI wafer 1 according to the present invention will be described with reference to the schematic cross-sectional view of Fig. 1. The SOI wafer 1 comprises a support substrate silicon wafer 10, an intermediate layer 30 on the support substrate silicon wafer 10, and a single crystal silicon layer 21 on the intermediate layer 30. The intermediate layer 30 has a composition of SiO x (0.59≦x≦0.78) (not shown in FIG. 1). In this case, the intermediate layer 30 may have an adhesive layer made of amorphous silicon or silicon oxide (not shown in FIG. 1). By having the adhesive layer in the intermediate layer 30, the BOX layer can be formed from silicon-rich SiO xEven in the case of a layer consisting of [the following], it is possible to bond the silicon wafer 10 for a support substrate and the single-crystalline silicon layer 21 through a BOX layer.

[0018] <BOX layer> SiO that constitutes the BOX layer x has its coefficient of thermal expansion changed due to the difference in the composition ratio x. By setting the range of the composition ratio x of SiO x to be 0.59 or more and 0.78 or less, the coefficient of thermal expansion of the BOX layer can be made close to the coefficients of thermal expansion of the silicon wafer 10 for a support substrate and the single-crystalline silicon layer 21. When the composition ratio x is greater than 0.78, the difference in the coefficients of thermal expansion from the adjacent support substrate silicon wafer 10 and single-crystalline silicon layer 21 becomes large, so warping occurs when used as a MEMS device. The smaller the composition ratio x, the smaller the difference in the above-described coefficient of thermal expansion can be made, and as a result, the occurrence of warping can be suppressed. However, when the composition ratio x is less than 0.59, the etching rate with respect to an acid becomes too slow and is not suitable for forming a fine structure during the fabrication of a MEMS device. For these reasons, the composition ratio x is preferably 0.60 or more and 0.75 or less, and more preferably 0.65 or more and 0.70 or less.

[0019] <<Composition of the BOX layer>> The composition x of the BOX layer can be identified by EDX analysis. In the examples of this specification, the composition at the center of the wafer was analyzed by EDX analysis (INCA manufactured by OXFORD Instruments). At this time, the acceleration voltage of the electron beam to the BOX layer surface was set to 1 kV, the current value was accelerated at 10 μA, irradiated to a region with a depth of 1 μm in an area of 100 μm × 100 μm, and the X-rays generated on the BOX layer surface were detected. Then, the ratio of the maximum amount detected with respect to the Si element component and the O element component of the detected X-rays can be adopted as the value of x in SiO x

[0020] ​The thickness of the BOX layer is preferably 1 μm or more from the viewpoint of ensuring a sufficient vertical drive region for the MEMS device, and the upper limit is preferably set to 20 μm from the viewpoint of miniaturizing the SOI wafer 1. Furthermore, in order to achieve both objectives, a thickness of 2 μm or more and 5 μm or less is particularly preferable. However, depending on the application of the SOI wafer 1, the thickness of the single crystal silicon layer 21 may be 5 μm or more, 10 μm or more, 20 μm or less, or 15 μm or less.

[0021] As described above, the SOI wafer 1 includes the intermediate layer 30 having the above-described BOX layer, and therefore, warpage can be suppressed and the SOI wafer 1 is suitable for use in MEMS devices.

[0022] Specific embodiments of the SOI wafer according to the present invention will be described below with reference to FIGS.

[0023] -First embodiment- 2, the SOI wafer 100 includes a support substrate silicon wafer 110, an intermediate layer 130 on the support substrate silicon wafer 110, and a single crystal silicon layer 121 on the intermediate layer 130. The intermediate layer 130 is made of SiO x The intermediate layer 130 has a BOX layer 131 made of (0.59≦x≦0.78). Here, the intermediate layer 130 has an amorphous silicon adhesion layer 132 made of amorphous silicon directly below the BOX layer 131. The SOI wafer 100 can be manufactured as follows.

[0024] First, SiO 2 was deposited on the surface of the silicon wafer 120 for the single crystal silicon layer. xForm a BOX layer 131 consisting of (0.59 ≦ x ≦ 0.78). The BOX layer 131 can be formed using the PE-CVD method described later. Next, perform an activation treatment on the surface of the silicon wafer 110 for the support substrate at room temperature under vacuum to form an amorphous silicon adhesive layer 132 as an adhesive layer on the surface of the silicon wafer 110 for the support substrate. This amorphous silicon adhesive layer 132 only needs to function as an adhesive layer, and its thickness is not particularly limited. For example, it is sufficient if amorphous silicon with a thickness of 5 nm or less can be formed. Further, continue at room temperature under vacuum, bring the silicon wafer 110 for the support substrate and the silicon wafer 120 for the single crystal silicon layer into contact with the amorphous silicon adhesive layer 132 and the BOX layer 131, and bond them by vacuum room temperature bonding. And finally, obtain the SOI wafer 100 of the final first embodiment by thinning the silicon wafer 120 for the single crystal silicon layer to obtain the single crystal silicon layer 121. Also, from the viewpoint of preventing warping, which is an issue in the present invention, a warping prevention film 150 for the purpose of preventing warping may be provided on the back surface of the silicon wafer for the support substrate. The composition of the warping prevention film 150 is not particularly limited, but SiO y If it is in the range of (0 < y < 0.6), it can avoid elution and remain even after acid etching, so it is preferable. The thickness of the warping prevention film 150 is not particularly limited, but from the viewpoint of preventing warping, a thicker one is preferable, and examples thereof include 1 μm or more and 20 μm or less. In FIG. 2, the location that actually becomes the bonding surface is shown by a dashed line together with each component.

[0025] - Second Embodiment - Refer to FIG. 3. The SOI wafer 200 includes a silicon wafer 210 for the support substrate, an intermediate layer 230 on the silicon wafer 210 for the support substrate, and a single crystal silicon layer 221 on the intermediate layer 230. The intermediate layer 230 is SiO xThe SOI wafer 200 has a BOX layer 231 made of amorphous silicon (0.59≦x≦0.78). Here, the intermediate layer 230 has an amorphous silicon adhesive layer 232 made of amorphous silicon directly on the BOX layer 231. Instead of forming the BOX layer on the surface of the silicon wafer 220 for the single crystal silicon layer in the first embodiment, the SOI wafer 200 can be manufactured by forming the BOX layer 231 on the silicon wafer 210 for the support substrate and forming the amorphous silicon adhesive layer 232 on the surface of the silicon wafer 220 for the single crystal silicon layer. In Figure 3, each component is shown with a dashed line, and the actual bonding surfaces are indicated.

[0026] -Third embodiment- 4, the SOI wafer 300 includes a support substrate silicon wafer 310, an intermediate layer 330 on the support substrate silicon wafer 310, and a single crystal silicon layer 321 on the intermediate layer 330. The intermediate layer 330 is made of SiO x (0.59≦x≦0.78). As will be described with reference to the manufacturing process below, the BOX layer 331 includes a first BOX layer 331b directly above the support substrate silicon wafer 310 and a second BOX layer 331a directly below the single crystal silicon layer 321.

[0027] First, SiO 2 was applied to the surface of the silicon wafer 310 for the support substrate. x The first BOX layer 331b is made of (0.59≦x≦0.78), and the surface of the single crystal silicon layer 321 is provided with SiO xThe second BOX layer 331a, each having a molecular weight of 0.59≦x≦0.78, is formed using a PE-CVD method. Then, a silicon target is sputtered onto the first BOX layer 331b and the second BOX layer 331a on the surface of each BOX layer under vacuum at room temperature to deposit atomic-level silicon for bonding the two BOX layers. The first BOX layer 331b and the second BOX layer 331a are then stacked via the deposited silicon and bonded under vacuum at room temperature to produce the SOI wafer 300. While the silicon deposited on the surface of each BOX layer contributes to bonding the BOX layers, its thickness is so thin that it cannot be observed even when the SOI wafer 300 is evaluated using a transmission electron microscope (TEM). In other words, no silicon layer is observed between the first BOX layer 331b and the second BOX layer 331a in the SOI wafer 300. For this reason, silicon at the bonding surface is not shown in FIG. 4 . Similar to the other embodiments, the thickness of the single crystal silicon layer 321 may be reduced and an anti-warpage film 350 may be optionally formed on the back surface of the support substrate silicon wafer 310. In Figure 4, each configuration is shown, with the actual bonding surfaces indicated by dotted lines.

[0028] -Fourth embodiment- 5, the SOI wafer 400 includes a silicon wafer 410 for a support substrate, an intermediate layer 430 on the silicon wafer 410 for a support substrate, and a single-crystal silicon layer 421 on the intermediate layer 430. The intermediate layer 430 is made of SiO x (0.59≦x≦0.78) where intermediate layer 430 has silicon oxide (SiO2) adhesive layer 435 directly below BOX layer 431. SOI wafer 400 can be manufactured as follows.

[0029] First, SiO 2 was deposited on the surface of the silicon wafer 420 for the single crystal silicon layer. xA BOX layer 431 having a thickness of (0.59≦x≦0.78) can be formed by a PE-CVD method. Next, the support substrate silicon wafer 410 is subjected to a thermal oxidation treatment to form a silicon oxide adhesive layer 435a that functions as an adhesive layer on one side of the support substrate silicon wafer 410. At this time, the opposite side is generally also oxidized to form a silicon oxide layer 435b. The silicon oxide adhesive layer 435a only needs to function as an adhesive layer, and its thickness is not particularly limited, but it can be, for example, 20 nm or less. Then, the support substrate silicon wafer 410 and the single crystal silicon layer silicon wafer 420 are brought into contact with each other via the silicon oxide adhesive layer 435a and the BOX layer 431, and bonded by a bonding heat treatment. Finally, the single crystal silicon layer silicon wafer 420 is reduced in thickness to obtain the single crystal silicon layer 421, thereby obtaining the final SOI wafer 400 of the fourth embodiment. In this embodiment, a warpage prevention film 450 for preventing warpage may be provided on the surface of the silicon oxide layer 435b formed on the back surface of the support substrate silicon wafer 410. Alternatively, the silicon oxide layer 435b on the back surface of the support substrate silicon wafer 410 may be removed by etching or the like, and then the warpage prevention film 450 may be provided on the back surface of the support substrate silicon wafer 410. In Figure 5, each component is shown with a dashed line, with the actual bonding surfaces indicated.

[0030] -Fifth embodiment- 6, the SOI wafer 500 includes a silicon wafer 510 for a support substrate, an intermediate layer 530 on the silicon wafer 510 for a support substrate, and a single-crystal silicon layer 521 on the intermediate layer 530. The intermediate layer 530 is made of SiO xThe SOI wafer 500 has a BOX layer 531 made of (0.59≦x≦0.78). The intermediate layer 530 has a silicon oxide adhesive layer 532 made of silicon oxide directly on the BOX layer 531. Here, instead of forming the BOX layer on the surface of the silicon wafer 520 for single crystal silicon layer as in the fourth embodiment, the SOI wafer 500 can be manufactured by forming the BOX layer on the silicon wafer 510 for support substrate and forming a silicon oxide adhesive layer 535b on the surface of the silicon wafer 521 for single crystal silicon layer. In this embodiment, a warpage prevention film 550 for preventing warpage may be provided on the back side of the silicon wafer 410 for support substrate. In FIG. 6, each component is shown with a dashed line, and the actual bonding surfaces are indicated.

[0031] <Specific aspects> Specific embodiments of the silicon wafer for the support substrate that can be used in the present invention and the silicon wafer that can be applied to the single crystal silicon layer will be described below.

[0032] The surface orientation of the silicon wafer is arbitrary, and a (100) wafer or a (110) wafer may be used.

[0033] The thickness of the silicon wafer can be appropriately determined depending on the application, and can be 300 μm to 1.5 mm. As already mentioned, the thickness of the single crystal silicon layer made of single crystal silicon obtained from the silicon wafer for single crystal silicon layer is appropriately determined in the range of 100 nm to 1 mm.

[0034] The silicon wafer may be doped with a dopant such as boron (B), phosphorus (P), arsenic (As), or antimony (Sb), or may be doped with carbon (C) or nitrogen (N) to obtain desired properties.

[0035] The diameter of the silicon wafer is not limited in any way. The present invention can be applied to silicon wafers with common diameters such as 300 mm or 200 mm. Of course, the present invention can also be applied to silicon wafers with diameters larger than 300 mm and to silicon wafers with smaller diameters.

[0036] An epitaxial silicon wafer may be used as the silicon wafer. Although a natural oxide film with a film thickness of about several Å may be formed on the surface of the silicon wafer, such a natural oxide film may be present, or it may be removed using a known cleaning method or the like as necessary.

[0037] Next, specific embodiments of the manufacturing process applicable to the production of SOI wafers 100 to 500 according to the present invention described with reference to FIGS. 2 to 6 will be described.

[0038] <<Formation of BOX Layer by PE-CVD Method>> SiO x (0.59 ≦ x ≦ 0.78). The BOX layer can be formed on the surface of a silicon wafer for a support substrate or a silicon wafer for a single crystal silicon layer using a CVD method such as plasma CVD (PE-CVD). In the plasma CVD method, first, the silicon wafer for the single crystal silicon layer is maintained at a degree of vacuum of 1 × 10 -4 Pa or less and at a temperature of 300°C or higher and 700°C or lower. Then, with the plasma power of 500 W or more, a mixed gas of a silane gas such as tetramethylsilane gas (Si(CH3)4) and oxygen gas can be used as the source gas to be introduced. By adjusting the mixing ratio of this mixed gas to be the ratio of the desired SiO x (0.59 ≦ x ≦ 0.78) of the BOX layer to be formed and then forming the film, a BOX layer composed of SiO x (0.59 ≦ x ≦ 0.78) can be formed.

[0039] <<Bonding by Vacuum Room Temperature Bonding Method>> A bonding method using vacuum room-temperature bonding for performing the activation treatment and bonding will be described with reference to FIGS. 2 and 7 . The vacuum room-temperature bonding method is a method for bonding a support substrate silicon wafer 110 and a single-crystal silicon layer silicon wafer 120 at room temperature without heating them. In the illustrated embodiment 1, an activation treatment is performed by irradiating the surface of the BOX layer 131 formed on the single-crystal silicon layer silicon wafer 120 and the surface of the support substrate silicon wafer 110 with an ion beam or a neutral atom beam under vacuum at room temperature, converting each of the surfaces into activated regions. As a result, a very thin amorphous silicon region is formed on the surface of the support substrate silicon wafer 110, and dangling bonds appear. Therefore, when the two wafers are subsequently brought into contact under vacuum at room temperature, a bonding force is instantly generated, and the support substrate silicon wafer 110 and the single-crystal silicon layer silicon wafer 120 are firmly bonded together with the activated regions serving as bonding surfaces, thereby bonding the two together.

[0040] The activation process can be performed by accelerating ionized elements in a plasma atmosphere toward the substrate surface, or by accelerating ionized elements from an ion beam device toward the substrate surface. Referring to Figure 7, the activation process will be described using a conceptual diagram showing an example of an apparatus that realizes this process. A vacuum room-temperature bonding apparatus 930 includes a plasma chamber 931, a gas inlet 932, a vacuum pump 933, a pulse voltage application device 934, and wafer fixing tables 935a and 935b.

[0041] First, the support substrate silicon wafer 110 and the single crystal silicon layer silicon wafer 120 having the BOX layer 131 formed on its surface are placed and fixed on wafer fixing stages 935a and 935b in the plasma chamber 931, respectively. Next, the pressure inside the plasma chamber 931 is reduced by a vacuum pump 933, and then a source gas is introduced into the plasma chamber 931 through a gas inlet 932. Subsequently, a pulse voltage application device 934 applies a negative voltage in pulses to the wafer fixing stages 935a and 935b (together with the support substrate silicon wafer 110 and the single crystal silicon layer silicon wafer 120). This generates plasma of the source gas, and also accelerates and irradiates ions of the source gas contained in the generated plasma toward the surfaces of the BOX layers 131 formed on the surfaces of the support substrate silicon wafer 110 and the single crystal silicon layer silicon wafer 120.

[0042] The element to be irradiated may be at least one selected from the group consisting of Ar, Ne, Xe, H, He, and Si.

[0043] See FIG. 2. As described above, the activation process in the vacuum room-temperature bonding method forms an amorphous silicon region on the surface of the support substrate silicon wafer 110 to a depth of approximately 1 nm from the surface on the side irradiated with the beam, and also forms dangling bonds. In this embodiment, an amorphous silicon adhesive layer 132 is formed as an adhesive layer on the support substrate silicon wafer 110. Note that this amorphous silicon adhesive layer 132 formed on the support substrate silicon wafer 110 also functions as a gettering layer. For example, the amorphous silicon adhesive layer 132 made of amorphous silicon is useful in that it can suppress outward diffusion of oxygen and impurities in the support substrate silicon wafer 110 into the single-crystal silicon layer silicon wafer 120.

[0044] -Specific aspects of the vacuum room temperature bonding method- The chamber pressure in the plasma chamber 931 was 1×10 -5 Pa or less.-5 This is because, if the pressure is equal to or less than Pa, there is no risk of the sputtered elements re-adhering to the substrate surface, resulting in a decrease in the rate of dangling bond formation.

[0045] The pulse voltage applied to the support substrate silicon wafer 110 and the single crystal silicon layer silicon wafer 120 may be set so that the acceleration energy of the irradiated element relative to the substrate surface is 100 eV or more and 10 keV or less. If it is 100 eV or more, there is no risk of the irradiated element depositing on the substrate surface, and if it is 10 keV or less, there is no risk of the irradiated element being implanted into the substrate, so dangling bonds can be stably formed.

[0046] The frequency of the pulse voltage determines the number of times that the support substrate silicon wafer 110 and the single crystal silicon layer silicon wafer 120 are irradiated with ions or neutral atoms. The frequency of the pulse voltage may be 10 Hz or more and 10 kHz or less. If the frequency of the pulse voltage is 10 Hz or more, the variation in the irradiation of ions or neutral atoms can be absorbed, thereby stabilizing the amount of irradiation of ions or neutral atoms. If the frequency of the pulse voltage is 10 kHz or less, plasma formation by glow discharge is stable.

[0047] The pulse width of the pulse voltage determines the time during which the silicon wafer 110 for the support substrate and the silicon wafer 120 for the single crystal silicon layer are irradiated with ions or neutral atoms. The pulse width is preferably 1 μsec or more and 10 ms or less. If the pulse width is 1 μsec or more, the silicon wafer 110 for the support substrate and the silicon wafer 120 for the single crystal silicon layer can be stably irradiated with ions or neutral atoms. If the pulse width is 10 ms or less, plasma formation by glow discharge is stable.

[0048] As described above, the support substrate silicon wafer 110 and the single crystal silicon layer silicon wafer 120 are not heated, so the temperature of each wafer is room temperature (usually 30° C. to 90° C.). [Example]

[0049] The present invention will be described in more detail below using examples, but the present invention is not limited to the following examples in any way.

[0050] (Example 1) As the silicon wafer for the support substrate and the silicon wafer for the single crystal silicon layer, a p-type CZ silicon wafer (dopant: boron) with a diameter of 4 inches (101.6 mm) and a thickness of 525 μm was prepared. Next, the silicon wafer for the single crystal silicon layer was introduced into a plasma CVD apparatus, and the degree of vacuum in the apparatus was reduced to 1×10 -5 The pressure was kept below 50 Pa. Then, with the stage temperature maintained at 500°C, the plasma power was set to 700 W, and tetramethylsilane gas (Si(CH3)4) was flowed at 25 sccm and oxygen gas at 50 sccm as source gases, and Ar gas was flowed at 40 sccm as carrier gas, to form a BOX layer with a thickness of 2.5 μm on the surface of the silicon wafer for the single crystal silicon layer by the plasma CVD method.

[0051] Then, in order to reduce the surface roughness of the formed BOX layer, the surface of the BOX layer of the silicon wafer for single crystal layer on which the BOX layer was formed was polished by CMP with a polishing stock removal of 500 nm.

[0052] Next, both the silicon wafer for the support substrate and the silicon wafer for the single crystal silicon layer were introduced into a chamber, and the degree of vacuum was adjusted to 1×10 -5 The pressure was kept below 1 Pa. The surface of the silicon wafer for the support substrate was then activated by irradiating it with argon ions at 1.4 keV, forming an activated region (amorphous silicon) as an adhesive layer on the surface of the silicon wafer for the support substrate. The two substrates were then bonded together in a vacuum room temperature environment by bonding the activated region of the silicon wafer for the support substrate to the BOX layer on the surface of the silicon wafer for the single crystal silicon layer.

[0053] The silicon wafer for the single crystal silicon layer was ground and polished from the side opposite to the bonding surface so as to leave a thickness of 10 μm, thereby obtaining an SOI wafer according to Invention Example 1.

[0054] In addition, the composition of the wafer center of the silicon wafer for the single crystal silicon layer immediately after the BOX layer formation was analyzed by EDX analysis (INCA manufactured by OXFORD Instruments) in the same manner as described above. At this time, the acceleration voltage of the electron beam on the BOX layer surface was set to 1 kV, and the current value was accelerated to 10 μA, and a region of 100 μm × 100 μm in area and 1 μm deep was irradiated, and X-rays generated on the BOX layer surface were detected. The ratio of the maximum amount detected for the Si element component and the O element component of the detected X-ray was calculated as SiO x The value of x in Example 1 was 0.78. The evaluation results are shown in Table 1.

[0055] (Example 2) In Example 1, the BOX layer was formed using a plasma CVD method with an oxygen gas flow rate of 50 sccm, whereas in Example 2, the BOX layer was formed by flowing oxygen gas at 25 sccm. An SOI wafer according to Example 2 was produced under the same conditions as Example 1.

[0056] (Example 3) In Example 1, the BOX layer was formed using a plasma CVD method with an oxygen gas flow rate of 50 sccm, whereas in Example 3, the BOX layer was formed by flowing oxygen gas at 16 sccm. An SOI wafer according to Example 3 was produced under the same conditions as Example 1.

[0057] (Conventional Example 1) In Example 1, SiO x The oxygen gas flow rate in the plasma CVD method was set to 50 sccm to form a BOX layer made of (0.59≦x≦0.78), whereas in Conventional Example 1, Ar gas was used as the carrier gas and oxygen gas was flowed at 100 sccm to form a BOX layer made of an oxide film (SiO2 film). An SOI wafer according to Conventional Example 1 was fabricated under the same conditions as those of Invention Example 1, except that a BOX layer made of an oxide film (SiO2 film) was formed by flowing Ar gas as the carrier gas.

[0058] (Comparative Example 1) In Example 1, the BOX layer was formed using a plasma CVD method with an oxygen gas flow rate of 50 sccm, whereas in Comparative Example 1, the BOX layer was formed using Ar gas as the carrier gas and oxygen gas flow rate of 68 sccm. An SOI wafer according to Comparative Example 1 was produced under the same conditions as in Example 1.

[0059] (Comparative Example 2) In Example 1, the BOX layer was formed using a plasma CVD method with an oxygen gas flow rate of 50 sccm, whereas in Comparative Example 2, the BOX layer was formed by using Ar gas as a carrier gas and flowing oxygen gas at 57 sccm. An SOI wafer according to Comparative Example 2 was produced under the same conditions as in Example 1, except that

[0060] (Comparative Example 3) In Example 1, the BOX layer was formed using a plasma CVD method with an oxygen gas flow rate of 50 sccm, whereas in Comparative Example 3, the BOX layer was formed using Ar gas as the carrier gas and oxygen gas at 7 sccm. An SOI wafer according to Comparative Example 3 was produced under the same conditions as in Example 1, except that the BOX layer was formed using Ar gas as the carrier gas and oxygen gas at 7 sccm.

[0061] Comparative Example 4 In Example 1, the BOX layer was formed using a plasma CVD method with an oxygen gas flow rate of 50 sccm, whereas in Comparative Example 4, the BOX layer was formed by using Ar gas as a carrier gas and flowing oxygen gas at 5 sccm. An SOI wafer according to Comparative Example 4 was produced under the same conditions as in Example 1, except that

[0062] (Comparative Example 5) In Example 1, the BOX layer was formed using a plasma CVD method with an oxygen gas flow rate of 50 sccm, whereas in Comparative Example 5, the BOX layer was formed using Ar gas as the carrier gas and oxygen gas at a flow rate of 2 sccm. An SOI wafer according to Comparative Example 5 was produced under the same conditions as in Example 1.

[0063] (Comparative Example 6) In Example 1, the BOX layer was formed using a plasma CVD method with an oxygen gas flow rate of 50 sccm, whereas in Comparative Example 6, the BOX layer was formed by using Ar gas as a carrier gas and flowing oxygen gas at 1 sccm. An SOI wafer according to Comparative Example 6 was produced under the same conditions as in Example 1.

[0064] (Evaluation: Evaluation of wafer warpage) To evaluate the amount of wafer warpage, a thin film stress measurement device (FLX-2320-S, manufactured by Toho Technology Co., Ltd.) was used to irradiate the surface of the single crystal silicon layer with a laser and evaluate the reflected light. For the evaluation, a silicon wafer for the single crystal silicon layer immediately after the BOX layer formation in each example was used. The reflected light was measured to determine the distance displaced from the incident light, thereby calculating the amount of warpage at the measurement point on the wafer. Then, the difference in the amount of warpage between the center and edge of the wafer in each example was divided by the thickness of the BOX layer to obtain the evaluation result of the amount of wafer warpage.

[0065] (Evaluation: Etching rate evaluation) To accurately evaluate the etching rate of the BOX layer, a silicon wafer for the single-crystal silicon layer immediately after the BOX layer formation in each example was used for evaluation. The wafer was cleaved into chips, and the etching rate of each chip was evaluated. First, a portion of the chip surface sampled from the center of the wafer was masked with acid-resistant tape and immersed in a 30% aqueous solution of hydrofluoric acid. After 10 minutes, the acid-resistant tape was removed, and the film thickness of the BOX layer was measured with a step gauge to evaluate the etching rate of the BOX layer.

[0066] The results are shown in Table 1 below. The amount of wafer warpage and etching rate are shown in Table 1. x Graphs showing the behavior of SiO 2 with respect to the composition ratio x are shown in FIGS. xIt can be seen that the amount of wafer warpage is sufficiently reduced by decreasing the composition ratio x. On the other hand, in Comparative Products 3 to 6, although it can be confirmed that the amount of wafer warpage is reduced as the composition ratio x decreases, the etching rate drops significantly, and it was found that these cannot be used for MEMS device applications.

[0067] [Table 1] [Industrial Applicability]

[0068] According to the present invention, it is possible to obtain an SOI wafer suitable for use in an MEMS device while suppressing warpage. [Explanation of symbols]

[0069] 1,100,200,300,400,500 SOI wafers 10,110,210,310,410,510 Silicon wafers for support substrates 120, 220, 320, 420, 520 Silicon wafers for single crystal silicon layers 30,130,230,430,530 Middle class 131,231,331,431,531 BOX layer 132,232 Amorphous silicon adhesive layer 435,535 Silicon oxide adhesive layer

Claims

1. a silicon wafer for a support substrate; an intermediate layer on the support substrate silicon wafer; a single crystal silicon layer on the intermediate layer, The intermediate layer has a thickness of 1 μm or more and 20 μm or less, and is made of SiO ｘ An SOI wafer having a BOX layer consisting of (0.59≦x≦0.78).

2. The intermediate layer has an adhesion layer made of amorphous silicon or silicon oxide. The SOI wafer according to claim 1 .

3. the intermediate layer has the adhesive layer directly on the BOX layer, the adhesive layer is made of the amorphous silicon; The SOI wafer according to claim 2 .

4. the intermediate layer has the adhesive layer directly under the BOX layer, the adhesive layer is made of the amorphous silicon; The SOI wafer according to claim 2 .

5. the intermediate layer has the adhesive layer directly on the BOX layer, The adhesive layer is made of silicon oxide. The SOI wafer according to claim 2 .

6. the intermediate layer has the adhesive layer directly under the BOX layer, The adhesive layer is made of silicon oxide. The SOI wafer according to claim 2 .

7. The method for producing an SOI wafer according to any one of claims 1 to 6, The method for producing an SOI wafer includes forming the BOX layer using a plasma CVD method (PE-CVD).

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