SOI wafer and its manufacturing method

Abstract

To provide SOI wafers suitable for use in MEMS devices, while improving etching resistance, and a method for manufacturing the same.SOLUTION: It is an SOI wafer having a silicon wafer for a support substrate, an intermediate layer on the silicon wafer for the support substrate, and a single crystal silicon layer on the intermediate layer, and the silicon wafer for the support substrate has an etching buffer layer on the back side and the etching buffer layer is SiOx (0<x≤0.60).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an SOI wafer and a method for manufacturing the same. [Background technology]

[0002] An SOI wafer (silicon on insulator) has a structure in which an insulating film such as silicon oxide (SiO2) and a single-crystal silicon layer used as a device active layer are sequentially formed on a support substrate. One of the typical manufacturing methods for SOI wafers is the bonding method. In this bonding method, an oxide film (BOX (buried oxide) layer) is formed on at least one of the support substrate and the active layer substrate, and then these substrates are stacked together with the oxide film interposed between them, followed by a bonding heat treatment at a high temperature of approximately 1200°C to produce an SOI wafer (see, for example, Patent Document 1). In recent years, SOI wafers have also been increasingly used as materials for MEMS devices such as acceleration sensors. When using SOI wafers for MEMS device applications, the BOX layer is required to not only function as a conventional insulating layer but also to be easy to handle, which necessitates new approaches. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 8-78644 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional SOI wafers, the protective layer made of silicon oxide (SiO2) provided on the backside of the support substrate has low acid etching resistance. Therefore, during microfabrication to fabricate MEMS devices, the protective layer is thinned or even lost due to its low acid etching resistance. When using SOI wafers for MEMS devices, the low etching resistance of this protective layer adversely affects processing accuracy, so the etching resistance of the protective layer must be improved. Therefore, an object of the present invention is to provide an SOI wafer with improved etching resistance that is suitable for use in MEMS devices, and a method for manufacturing the same. [Means for solving the problem]

[0005] The present inventors have conducted research to solve the above problems, and have discovered that silicon-rich SiO is used as a protective layer instead of silicon oxide, which has been generally used as a protective layer in SOI wafers. x However, the etching resistance could not be improved sufficiently by a slight change in the composition. x The present invention has been completed based on the above findings, and has the following gist: the relationship between the composition ratio x in the layer and the etching resistance was further investigated, and the composition of the protective layer (etching buffer layer in the present invention) suitable for use in MEMS devices was found.

[0006] <1> An SOI wafer comprising a silicon wafer for a support substrate, an intermediate layer on the silicon wafer for the support substrate, and a single-crystal silicon layer on the intermediate layer, wherein the silicon wafer for the support substrate has an etching buffer layer on the back surface thereof, and the etching buffer layer is made of SiO x (0 <x≦0.60)である、SOIウェーハ。

[0007] <2> The intermediate layer is SiO y (1.00≦y≦2.00) <1> The SOI wafer according to claim 1.

[0008] <3> an adhesive layer made of amorphous silicon or silicon oxide between the support substrate silicon wafer and the single crystal silicon layer; <2> The SOI wafer according to claim 1.

[0009] <4> The intermediate layer has an adhesive layer directly on the BOX layer, and the adhesive layer is made of amorphous silicon. <3> The SOI wafer according to claim 1.

[0010] <5> The intermediate layer has an adhesive layer directly below the BOX layer, and the adhesive layer is made of amorphous silicon. <3> The SOI wafer according to claim 1.

[0011] <6> The intermediate layer has an adhesive layer directly on the BOX layer, and the adhesive layer is made of silicon oxide. <3> The SOI wafer according to claim 1.

[0012] <7> The intermediate layer has an adhesive layer directly under the BOX layer, and the adhesive layer is made of silicon oxide. <3> The SOI wafer according to claim 1.

[0013] <8> <1> ~ <7> 10. A method for producing an SOI wafer according to claim 9, wherein the etching buffer layer is formed by using a plasma CVD method (PE-CVD).

[0014] Hereinafter, the method of forming an activation region on each of the silicon wafer for the support substrate and the silicon wafer for the single crystal silicon layer and bonding the two wafers together at their activation regions in a vacuum at room temperature will be referred to as the "vacuum room temperature bonding method." [Effects of the Invention]

[0015] According to the present invention, it is possible to provide an SOI wafer that is suitable for use in MEMS devices while improving etching resistance, and a method for manufacturing the same. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a schematic cross-sectional view illustrating an outline of an SOI wafer according to the present invention. [Figure 2]It is a schematic cross-sectional view for explaining the first embodiment of the SOI wafer according to the present invention. [Figure 3] It is a schematic cross-sectional view for explaining the second embodiment of the SOI wafer according to the present invention. [Figure 4] It is a schematic cross-sectional view for explaining the third embodiment of the SOI wafer according to the present invention. [Figure 5] It is a schematic cross-sectional view for explaining the fourth embodiment of the SOI wafer according to the present invention. [Figure 6] It is a schematic cross-sectional view for explaining the fifth embodiment of the SOI wafer according to the present invention. [Figure 7] It is a schematic cross-sectional view for explaining the sixth embodiment of the SOI wafer according to the present invention. [Figure 8] In one embodiment of the method for manufacturing a bonded silicon wafer according to the present invention, it is a conceptual diagram showing an example of an apparatus used when performing vacuum room-temperature bonding. [Figure 9] It is a graph showing the evaluation results of the etching rate in the SOI wafers according to the examples and comparative examples.

Mode for Carrying Out the Invention

[0017] Hereinafter, embodiments of the present invention will be sequentially described with reference to the drawings. For convenience of explanation in each drawing, the thickness of each component is shown exaggerated. Therefore, the thickness of each component is different from the ratio of the actual thickness.

[0018] (SOI Wafer) Referring to the schematic cross-sectional view of FIG. 1, the SOI wafer 1 according to the present invention will be described. The SOI wafer 1 includes a silicon wafer 10 for a support substrate, an intermediate layer 30 on the silicon wafer 10 for a support substrate, and a single-crystal silicon layer 21 on the intermediate layer 30. And the silicon wafer 10 for a support substrate has an etching buffer layer 50 having a composition of SiO x (0 < x ≦ 0.60) on the back surface of it).

[0019] <Etching Buffer Layer> In the present invention, the protective layer formed on the surface of the surface (back surface) opposite to the bonding surface of the silicon wafer for the support substrate is particularly referred to as an etching buffer layer. The SiO x that constitutes the etching buffer layer has its etching resistance to acid changing due to the difference in the composition ratio x. The smaller the composition ratio x, the smaller the etching rate can be made. By setting the range of the composition ratio x of SiO x to be 0.60 or less (excluding 0), the etching resistance on the back side required when processing the SOI wafer 1 into a MEMS device can be improved. On the other hand, when the composition ratio x is greater than 0.60, the etching rate cannot be made sufficiently small. Therefore, by having the etching buffer layer 50 composed of SiO x (0 < x ≤ 0.60), even when the SOI wafer 1 is impregnated with an etching solution during the formation of a MEMS device and a part such as the intermediate layer 30 is microfabricated, a significant reduction in the thickness of the etching buffer layer 50 can be avoided. Also, for such reasons, the composition ratio x is preferably 0.10 or more and 0.50 or less, and more preferably 0.10 or more and 0.40 or less.

[0020] <<Composition of the etching buffer layer>> The composition ratio x of the etching buffer layer can be identified by EDX analysis respectively. In the examples of this specification, the composition at the center of the wafer was analyzed by EDX analysis (INCA manufactured by OXFORD Instruments). At this time, the acceleration voltage of the electron beam on the surface of the etching buffer layer was set to 1 kV, the current value was accelerated at 10 μA, and irradiated to a region with a depth of 1 μm in an area of 100 μm × 100 μm, and the X-rays generated on the surface of the etching buffer layer were detected. Then, the ratio of the maximum amount detected for the Si element component and the O element component of the detected X-rays can be adopted as the x value in SiO x . Note that the same applies to the y value in SiO y of the BOX layer.

[0021] The thickness of the etching buffer layer is preferably 100 nm or more from the viewpoint of etching durability, and the upper limit is preferably set to 20 μm from the viewpoint of miniaturizing the SOI wafer. Furthermore, to achieve both objectives, the thickness is more preferably 1 μm or more and 5 μm or less. The thickness of the BOX layer is preferably 1 μm or more from the viewpoint of ensuring a sufficient vertical drive region for the MEMS device, and the upper limit is preferably set to 20 μm from the viewpoint of miniaturizing the SOI wafer 1. Furthermore, depending on the application of the SOI wafer 1, the thickness of the single crystal silicon layer 21 may be 5 μm or more, 10 μm or more, 20 μm or less, or 15 μm or less.

[0022] As described above, the SOI wafer 1 includes the etching buffer layer 50 described above, and therefore has improved etching resistance and is suitable for use in MEMS devices.

[0023] <Middle class> The composition of the intermediate layer 30 may be SiO2, which is generally used as a BOX layer, or a composition of SiO y (1.00≦y≦2.00) and an adhesive layer made of amorphous silicon or silicon oxide. In particular, when the composition ratio y is 1.00 or more and less than 2.00, the intermediate layer 30 has an adhesive layer, and the BOX layer is made of silicon-rich SiO y Even if the BOX layer is made of a layer of SiO , it is possible to bond the silicon wafer 10 for support substrate and the single crystal silicon layer 21 via the BOX layer. y As with the etching buffer layer, the etching rate also varies depending on the composition ratio y. If the etching rate becomes too small, it is not suitable for forming a fine structure when fabricating an MEMS device, so the composition ratio y is preferably 1.00 or more and 2.00 or less, and more preferably 1.10 or more and 1.90 or less.

[0024] Specific embodiments of the SOI wafer in which the intermediate layer 30 has a BOX layer in which the composition ratio y is 1.00 or more and less than 2.00 will be described below with reference to FIGS.

[0025] - First Embodiment - Refer to FIG. 2. The SOI wafer 100 includes a silicon wafer 110 for a support substrate, an intermediate layer 130 on the silicon wafer 110 for a support substrate, and a single-crystal silicon layer 121 on the intermediate layer 130. The silicon wafer 110 for a support substrate has an etching buffer layer 150 made of SiO x [[ID=,7]](0 < x ≤ 0.60) on its back surface. Here, the intermediate layer 130 has an amorphous silicon adhesive layer 132 made of amorphous silicon directly above the BOX layer 131. The SOI wafer 100 can be manufactured as follows.

[0026] ] First, a BOX layer 131 is formed on the surface of the silicon wafer 110 for a support substrate. The composition of the BOX layer 131 is preferably SiO x (1.00 ≤ x ≤ 2.00), and it can be formed using the PE-CVD method described later. Next, the surface of the silicon wafer 120 for a single-crystal silicon layer is subjected to an activation treatment at room temperature under vacuum to form an amorphous silicon adhesive layer 132 as an adhesive layer on the surface of the silicon wafer 120 for a single-crystal silicon layer. This amorphous silicon adhesive layer 132 only needs to function as an adhesive layer, and its thickness is not particularly limited. For example, it is sufficient if amorphous silicon with a thickness of 5 nm or less can be formed. Further, subsequently at room temperature under vacuum, the silicon wafer 110 for a support substrate and the silicon wafer 120 for a single-crystal silicon layer are brought into contact with the amorphous silicon adhesive layer 132 and the BOX layer 131, and are joined by vacuum room-temperature bonding. Then, on the surface of the surface of the silicon wafer 110 for a support substrate opposite to the bonding surface (back surface), an etching buffer layer 150 made of SiO x (0 < x ≤ 0.60) is formed using the PE-CVD method. Finally, the silicon wafer 120 for a single-crystal silicon layer is thinned to obtain a single-crystal silicon layer 121, thereby obtaining the final SOI wafer 100 of the first embodiment. Note that the formation of the etching buffer layer 150 may be performed before the vacuum room-temperature bonding. Also, from the viewpoint of improving the etching resistance of the etching buffer layer, which is an issue in the present invention, the composition of the BOX layer 131 is not particularly limited, but SiOy If it is within the range of (1.00 ≦ y ≦ 2.00), it is preferable because the BOX layer 131 can be etched while maintaining the etching resistance of the etching buffer layer. In FIG. 2, the location that actually becomes the bonding surface is indicated by a broken line together with each configuration.

[0027] - Second Embodiment - Refer to FIG. 3. The SOI wafer 200 includes a silicon wafer 210 for a support substrate, an intermediate layer 230 on the silicon wafer 210 for a support substrate, and a single crystal silicon layer 221 on the intermediate layer 230. The silicon wafer 210 for a support substrate has, on its back surface, SiO x It has an etching buffer layer 250 composed of (0 < x ≦ 0.60). Here, the intermediate layer 230 has an amorphous silicon adhesive layer 232 made of amorphous silicon directly under the BOX layer 231. The SOI wafer 200 can be manufactured by forming the BOX layer 231 on the silicon wafer 220 for a single crystal silicon layer instead of forming the BOX layer on the surface of the silicon wafer 210 for a support substrate in the first embodiment, and forming the amorphous silicon adhesive layer 232 on the surface of the silicon wafer 210 for a support substrate. In FIG. 3, the location that actually becomes the bonding surface is indicated by a broken line together with each configuration.

[0028] - Third Embodiment - Refer to FIG. 4. The SOI wafer 300 includes a silicon wafer 310 for a support substrate, an intermediate layer 330 on the silicon wafer 310 for a support substrate, and a single crystal silicon layer 321 on the intermediate layer 330. The silicon wafer 310 for a support substrate has, on its back surface, SiO x It has an etching buffer layer 350 composed of (0 < x ≦ 0.60). Here, the SOI wafer 300 can be manufactured as follows.

[0029] First, the silicon wafer 310 for the support substrate is subjected to a thermal oxidation treatment to form a silicon oxide layer 335a that functions as a BOX layer on one side of the silicon wafer 310 for the support substrate. At this time, generally, the opposite side is also oxidized to form a silicon oxide layer 335b. The silicon oxide layer 335a only needs to function as a BOX layer, and its thickness is not particularly limited, but it can be, for example, 1 μm or more. Next, the surface of the silicon wafer 320 for the single crystal silicon layer is subjected to an activation treatment at room temperature under vacuum to form an amorphous silicon adhesive layer 332 as an adhesive layer on the surface of the silicon wafer 320 for the single crystal silicon layer. Further, subsequently at room temperature under vacuum, the silicon wafer 310 for the support substrate and the silicon wafer 320 for the single crystal silicon layer are brought into contact with the amorphous silicon adhesive layer 332 and the silicon oxide layer 335a and joined by vacuum room temperature bonding. Then, on the surface of the side (back surface) of the silicon wafer 310 for the support substrate opposite to the bonding surface, an etching buffer layer 350 having a composition of SiO x (0 < x ≤ 0.60) is formed using the PE-CVD method. Finally, the silicon wafer 320 for the single crystal silicon layer is thinned to obtain a single crystal silicon layer 321, thereby obtaining the final SOI wafer 300 of the first embodiment. Note that the formation of the etching buffer layer 350 may be performed before the vacuum room temperature bonding. In FIG. 4, the location that actually becomes the bonding surface is indicated by a dashed line together with each component.

[0030] - Fourth Embodiment - Referring to FIG. 5. The SOI wafer 400 includes a silicon wafer 410 for the support substrate, an intermediate layer 430 on the silicon wafer 410 for the support substrate, and a single crystal silicon layer 421 on the intermediate layer 430. The silicon wafer 310 for the support substrate has an etching buffer layer 350 having a composition of SiO x (0 < x ≤ 0.60) on its back surface. Also, the intermediate layer 430 is composed of a first BOX layer 431b directly above the silicon wafer 410 for the support substrate and a second BOX layer 431a directly below the single crystal silicon layer 421, as will be described referring to the following manufacturing process.

[0031] First, a first BOX layer 431b is formed on the surface of the silicon wafer 410 for the support substrate, and a second BOX layer 431a is formed on the surface of the single-crystalline silicon layer 421 using the PE-CVD method. Then, under vacuum and normal temperature, a silicon target is sputtered onto the first BOX layer 431b and the second BOX layer 431a on the surfaces of each BOX layer to deposit silicon at the atomic size level for bonding the two BOX layers. Next, the first BOX layer 431b and the second BOX layer 431a are overlapped through the deposited silicon and joined under vacuum and normal temperature. And on the surface of the surface (back surface) of the silicon wafer 410 for the support substrate opposite to the bonding surface, an etching buffer layer 450 composed of SiO x (0 < x ≤ 0.60) is formed using the PE-CVD method. Note that the formation of the etching buffer layer 450 may be performed before the vacuum and normal temperature bonding. Here, although the silicon deposited on the surfaces of each BOX layer contributes to the bonding between the BOX layers, it is substantially as thin as its thickness can be ignored, so its presence cannot be observed even when the SOI wafer 400 is evaluated using a transmission electron microscope (TEM). That is, in the SOI wafer 40, no silicon layer is observed between the first BOX layer 431b and the second BOX layer 431a. For this reason, the silicon at the bonding surface is not shown in FIG. 5 either. The point of thinning the single-crystalline silicon layer 421 (420) is the same as in other embodiments. In FIG. 5, the location that actually becomes the bonding surface is indicated by a dotted line together with each configuration.

[0032] - Fifth Embodiment - Referring to FIG. 6. The SOI wafer 500 includes a silicon wafer 510 for the support substrate, an intermediate layer 530 on the silicon wafer for the support substrate 510, and a single-crystalline silicon layer 521 on the intermediate layer 530. The silicon wafer 510 for the support substrate has SiO on its back surface xIt has an etching buffer layer 550 consisting of (0 < x ≤ 0.60). Here, the intermediate layer 530 is made of silicon oxide. The SOI wafer 500 can be manufactured by forming a silicon oxide layer 535b on a silicon wafer for a single crystal silicon layer in this embodiment, instead of forming an amorphous silicon adhesive layer on a silicon wafer for a single crystal silicon layer in the second embodiment.

[0033] Also, in this fifth embodiment, although the silicon wafer 510 for the support substrate and the silicon wafer 520 for the single crystal silicon layer are joined by room-temperature vacuum bonding, as a modified form of the fifth embodiment, instead of this, by contacting the silicon oxide layer 535b formed on the surface of the silicon wafer 510 for the support substrate and the silicon oxide layer 535c formed on the surface of the silicon wafer 520 for the single crystal silicon layer, and joining them by bonding heat treatment, through the same steps as in the above fifth embodiment, the SOI wafer 500 shown in FIG. 6 can also be manufactured. In FIG. 6, the location that actually becomes the bonding surface is indicated by a dashed line together with each component.

[0034] - Sixth Embodiment - Refer to FIG. 7. The SOI wafer 600 includes a silicon wafer 610 for a support substrate, an intermediate layer 630 on the silicon wafer 610 for the support substrate, and a single crystal silicon layer 621 on the intermediate layer 630. The silicon wafer 610 for the support substrate has, on its back surface, SiO x It has an etching buffer layer 650 consisting of (0 < x ≤ 0.60). Here, the intermediate layer 630 is a silicon oxide layer 635a. Here, the SOI wafer 600 can be manufactured as follows.

[0035] First, a silicon wafer 610 for support substrate is subjected to thermal oxidation treatment to form silicon oxide layers 635a and 635b on both sides of the silicon wafer 610 for support substrate. Then, the surface of the silicon wafer 610 for support substrate and the silicon oxide layer 635a formed on the surface of the silicon wafer 620 for single crystal silicon layer are brought into contact with each other and bonded by a bonding heat treatment. The thickness of the single crystal silicon layer 621 (620) is reduced in the same manner as in the other embodiments. In Figure 7, each component is shown, with the actual bonding surfaces indicated by dotted lines.

[0036] <Specific aspects> Specific embodiments of the silicon wafer for the support substrate that can be used in the present invention and the silicon wafer that can be applied to the single crystal silicon layer will be described below.

[0037] The surface orientation of the silicon wafer is arbitrary, and a (100) wafer or a (110) wafer may be used.

[0038] The thickness of the silicon wafer can be appropriately determined depending on the application, and can be 300 μm to 1.5 mm. As already mentioned, the thickness of the single crystal silicon layer made of single crystal silicon obtained from the silicon wafer for single crystal silicon layer is appropriately determined in the range of 100 nm to 1 mm.

[0039] The silicon wafer may be doped with a dopant such as boron (B), phosphorus (P), arsenic (As), or antimony (Sb), or may be doped with carbon (C) or nitrogen (N) to obtain desired properties.

[0040] There is no limitation on the diameter of the silicon wafer. The present invention can be applied to silicon wafers with a general diameter of 300 mm or 200 mm. Of course, the present invention can also be applied to silicon wafers with a diameter larger than 300 mm or smaller than 300 mm.

[0041] An epitaxial silicon wafer may be used as the silicon wafer. Although a native oxide film with a film thickness of about several Å may be formed on the surface of the silicon wafer, such a native oxide film may be present, or it may be removed using a known cleaning method or the like as necessary.

[0042] Next, a specific embodiment of the manufacturing process applicable to the production of SOI wafers 100 to 600 according to the present invention described with reference to FIGS. 2 to 7 will be described.

[0043] <<Formation of an etching buffer layer by PE-CVD method>> SiO x (0 < x ≤ 0.60) The etching buffer layer can be formed on the surface of the silicon wafer for the support substrate using a CVD method such as plasma CVD (PE-CVD). In the plasma CVD method, first, the silicon wafer for the single crystal silicon layer is held at a degree of vacuum of 1 × 10 -4 Pa or less and a temperature of 300°C or higher and 700°C or lower. Then, with the plasma power of 5,000 W or more, a mixed gas of a silane gas such as tetramethylsilane gas (Si(CH3)4) and oxygen gas can be used as the source gas to be introduced. And if the mixing ratio of this mixed gas is adjusted to be the ratio of the desired SiO x (0 < x ≤ 0.60) for the BOX layer to be formed, an etching buffer layer composed of (0 < x ≤ 0.60) can be formed. Note that the same applies to the BOX layer composed of SiO y (1.00 ≤ y ≤ 2.00).

[0044] <<Bonding by vacuum room temperature bonding method>> A bonding method using vacuum room-temperature bonding for performing the activation treatment and bonding will be described with reference to FIGS. 3 and 8 . The vacuum room-temperature bonding method is a method for bonding a support substrate silicon wafer 210 and a single-crystal silicon layer silicon wafer 220 at room temperature without heating them. In the second embodiment, which is illustrated as an example, an activation treatment is performed by irradiating the surface of the BOX layer 231 formed on the single-crystal silicon layer silicon wafer 220 and the surface of the support substrate silicon wafer 210 with an ion beam or a neutral atom beam under vacuum at room temperature, thereby converting both surfaces into activated regions. As a result, a very thin amorphous silicon region is formed on the surface of the support substrate silicon wafer 210, and dangling bonds appear. Therefore, when the two wafers are subsequently brought into contact under vacuum at room temperature, a bonding force is instantly generated, and the support substrate silicon wafer 210 and the single-crystal silicon layer silicon wafer 220 are firmly bonded together with the activated regions serving as bonding surfaces, thereby bonding the two.

[0045] The activation process can be performed by accelerating ionized elements in a plasma atmosphere toward the substrate surface, or by accelerating ionized elements from an ion beam device toward the substrate surface. Referring to Figure 8, the activation process will be described using a conceptual diagram showing an example of an apparatus that realizes this process. A vacuum room-temperature bonding apparatus 930 includes a plasma chamber 931, a gas inlet 932, a vacuum pump 933, a pulse voltage application device 934, and wafer fixing tables 935a and 935b.

[0046] First, the support substrate silicon wafer 210 and the single crystal silicon layer silicon wafer 220 having the BOX layer 231 formed on its surface are placed and fixed on wafer fixing stages 935a and 935b in the plasma chamber 931, respectively. Next, the pressure inside the plasma chamber 931 is reduced by a vacuum pump 933, and then a source gas is introduced into the plasma chamber 931 through a gas inlet 932. Subsequently, a pulse voltage application device 934 applies a negative voltage in pulses to the wafer fixing stages 935a and 935b (together with the support substrate silicon wafer 210 and the single crystal silicon layer silicon wafer 220). This generates plasma of the source gas, and also accelerates and irradiates ions of the source gas contained in the generated plasma toward the surfaces of the BOX layers 231 formed on the surfaces of the support substrate silicon wafer 210 and the single crystal silicon layer silicon wafer 220.

[0047] The element to be irradiated may be at least one selected from the group consisting of Ar, Ne, Xe, H, He, and Si.

[0048] See FIG. 3. As described above, the activation process in the vacuum room-temperature bonding method forms an amorphous silicon region on the surface of the support substrate silicon wafer 210 to a depth of approximately 1 nm from the surface on the side irradiated with the beam, and also forms dangling bonds. In this embodiment, an amorphous silicon adhesive layer 232 is formed as an adhesive layer on the support substrate silicon wafer 210. Note that the amorphous silicon adhesive layer 232 formed on the support substrate silicon wafer 210 also functions as a gettering layer. For example, the amorphous silicon adhesive layer 232 made of amorphous silicon is useful in that it can suppress outward diffusion of oxygen and impurities in the support substrate silicon wafer 210 into the single-crystal silicon layer silicon wafer 220.

[0049] -Specific aspects of the vacuum room temperature bonding method- The chamber pressure in the plasma chamber 931 was 1×10 -5 Pa or less.-5 This is because, if the pressure is equal to or less than Pa, there is no risk of the sputtered elements re-adhering to the substrate surface, resulting in a decrease in the rate of dangling bond formation.

[0050] The pulse voltage applied to the support substrate silicon wafer 210 and the single crystal silicon layer silicon wafer 220 may be set so that the acceleration energy of the irradiated element relative to the substrate surface is 100 eV or more and 10 keV or less. If it is 100 eV or more, there is no risk of the irradiated element depositing on the substrate surface, and if it is 10 keV or less, there is no risk of the irradiated element being implanted into the substrate, so dangling bonds can be stably formed.

[0051] The frequency of the pulse voltage determines the number of times the support substrate silicon wafer 210 and the single crystal silicon layer silicon wafer 220 are irradiated with ions or neutral atoms. The frequency of the pulse voltage may be 10 Hz or more and 10 kHz or less. If the frequency of the pulse voltage is 10 Hz or more, the variation in the irradiation of ions or neutral atoms can be absorbed, thereby stabilizing the amount of irradiation of ions or neutral atoms. If the frequency of the pulse voltage is 10 kHz or less, plasma formation by glow discharge is stabilized.

[0052] The pulse width of the pulse voltage determines the time during which the silicon wafer 210 for the support substrate and the silicon wafer 220 for the single crystal silicon layer are irradiated with ions or neutral atoms. The pulse width is preferably 1 μsec or more and 10 ms or less. If the pulse width is 1 μsec or more, the silicon wafer 210 for the support substrate and the silicon wafer 220 for the single crystal silicon layer can be stably irradiated with ions or neutral atoms. If the pulse width is 10 ms or less, plasma formation by glow discharge is stable.

[0053] As described above, the support substrate silicon wafer 210 and the single crystal silicon layer silicon wafer 220 are not heated, so the temperature of each wafer is room temperature (usually 30° C. to 90° C.). [Example]

[0054] The present invention will be described in more detail below using examples, but the present invention is not limited to the following examples in any way.

[0055] (Example 1) As the silicon wafer for the support substrate and the silicon wafer for the single crystal silicon layer, a p-type CZ silicon wafer (dopant: boron) with a diameter of 4 inches (101.6 mm) and a thickness of 525 μm was prepared. Next, the silicon wafer for the single crystal silicon layer was introduced into a plasma CVD apparatus, and the degree of vacuum in the apparatus was reduced to 1×10 -5 The pressure was kept below 50 Pa. Then, with the stage temperature maintained at 500°C, the plasma power was set to 700 W, and tetramethylsilane gas (Si(CH3)4) was flowed at 25 sccm and oxygen gas at 68 sccm as source gases, and a BOX layer with a thickness of 2.5 μm was formed on the surface of the silicon wafer for the single crystal silicon layer by the plasma CVD method.

[0056] Then, in order to reduce the surface roughness of the formed BOX layer, the surface of the BOX layer of the silicon wafer for single crystal layer on which the BOX layer was formed was polished by CMP with a polishing stock removal of 500 nm.

[0057] On the other hand, the silicon wafer for the support substrate was introduced into a plasma CVD apparatus, and the degree of vacuum in the apparatus was set to 1×10 -5 The pressure was kept below 50 Pa. Then, with the stage temperature maintained at 500°C, the plasma power was set to 700 W, and tetramethylsilane gas (Si(CH3)4) was flowed at 25 sccm and oxygen gas at 1 sccm as source gases, and Ar gas was flowed at 40 sccm as carrier gas, and an etching buffer layer with a thickness of 2.5 μm was formed on the back side of the silicon wafer for support substrate (the surface opposite to the bonding surface) by plasma CVD.

[0058] Next, both the silicon wafer for the support substrate on which the etching buffer layer has been formed and the silicon wafer for the single crystal silicon layer on which the BOX layer has been formed were introduced into a chamber, and the degree of vacuum was adjusted to 1×10 -5The pressure was kept below 1 Pa. Then, the surface of the silicon wafer for the support substrate, which would become the bonding surface, was activated by irradiating it with argon ions at 1.4 keV, forming an activated region (amorphous silicon) as an adhesive layer on the surface of the silicon wafer for the support substrate.

[0059] Subsequently, both substrates were bonded together in a vacuum room temperature environment by attaching the BOX layer on the surface of the silicon wafer for the single crystal silicon layer to the activated region of the silicon wafer for the support substrate.

[0060] Finally, the silicon wafer for the single crystal silicon layer was ground and polished from the side opposite to the bonding surface so that a thickness of 10 μm remained, thereby obtaining an SOI wafer according to Invention Example 1.

[0061] The composition of the wafer center on the etching buffer layer side of the obtained SOI wafer was analyzed by EDX analysis (INCA manufactured by Oxford Instruments) in the same manner as described above. The electron beam acceleration voltage to the etching buffer layer was 1 kV, and the current value was 10 μA, irradiating a region of 100 μm × 100 μm in area and 1 μm deep, and X-rays generated on the surface of the BOX layer were detected. The composition of the BOX layer was also analyzed by evaluating the composition of the wafer center of the silicon wafer for the single crystal silicon layer immediately after the BOX layer was formed. The ratio of the maximum amount of the detected Si element component and O element component of the detected X-rays was calculated, and the composition of the etching buffer layer of Example 1 was SiO x The value of x in the formula is 0.12, and the composition of the BOX layer is SiO y The value of y in this case was 1.42. The evaluation results are shown in Table 1.

[0062] (Example 2) In Example 1, the etching buffer layer was formed using an oxygen gas flow rate of 1 sccm in the plasma CVD method, whereas in Example 2, the etching buffer layer was formed by flowing oxygen gas at 2 sccm. An SOI wafer according to Example 2 was produced under the same conditions as Example 1.

[0063] (Example 3) In Example 1, the etching buffer layer was formed using an oxygen gas flow rate of 1 sccm in the plasma CVD method, whereas in Example 3, the etching buffer layer was formed by flowing oxygen gas at 5 sccm. An SOI wafer according to Example 3 was produced under the same conditions as Example 1.

[0064] (Example 4) In Example 1, the etching buffer layer was formed using an oxygen gas flow rate of 1 sccm in the plasma CVD method, whereas in Example 3, the etching buffer layer was formed by flowing oxygen gas at 7 sccm. An SOI wafer according to Example 3 was produced under the same conditions as Example 1.

[0065] (Example 5) In Example 1, the etching buffer layer was formed using an oxygen gas flow rate of 1 sccm in the plasma CVD method, whereas in Example 3, the etching buffer layer was formed by flowing oxygen gas at 10 sccm. An SOI wafer according to Example 3 was produced under the same conditions as Example 1.

[0066] (Example 6) In Example 1, the etching buffer layer was formed using an oxygen gas flow rate of 1 sccm in the plasma CVD method, whereas in Example 3, the etching buffer layer was formed by flowing oxygen gas at 16 sccm. An SOI wafer according to Example 3 was produced under the same conditions as Example 1.

[0067] (Comparative Example 1) In Example 1, the etching buffer layer was formed using a plasma CVD method with an oxygen gas flow rate of 1 sccm, whereas in Comparative Example 1, the etching buffer layer was formed by using Ar gas as a carrier gas and flowing oxygen gas at 50 sccm. An SOI wafer according to Comparative Example 1 was produced under the same conditions as in Example 1.

[0068] (Comparative Example 2) In Invention Example 1, an etching buffer layer was formed with an oxygen gas flow rate of 1 sccm in the plasma CVD method. In Comparative Example 2, an SOI wafer according to Comparative Example 2 was fabricated under the same conditions as in Invention Example 1, except that Ar gas was used as the carrier gas and 57 sccm of oxygen gas was flowed to form the etching buffer layer.

[0069] (Conventional Example 1) In Invention Example 1, SiO x (0 < x ≤ 0.60) was used to form an etching buffer layer with an oxygen gas flow rate of 1 sccm in the plasma CVD method. In Conventional Example 1, an SOI wafer according to Conventional Example 1 was fabricated under the same conditions as in Invention Example 1, except that Ar gas was used as the carrier gas and 100 sccm of oxygen gas was flowed to form a BOX layer made of an oxide film (SiO2 film).

[0070] (Evaluation: Evaluation of etching rate) To accurately evaluate the etching rate of the etching buffer layer, the SOI wafers after forming the etching buffer layer in each example were cleaved into chip shapes, and the etching rate in the chips was evaluated. First, a part of the etching buffer layer on the chip surface sampled from the center of the wafer was masked with an acid-resistant tape and impregnated with a 30% aqueous solution of hydrofluoric acid. Then, after 10 minutes, the acid-resistant tape was peeled off, and the film thickness of the etching buffer layer was measured with a profilometer to evaluate the etching rate of the etching buffer layer.

[0071] The results are shown in Table 1 below, and a graph showing the behavior of the etching rate with respect to the composition ratio x of SiO x is shown in FIG. 9. From these evaluation results, it can be seen that in Invention Examples 1 to 6, the etching rate is sufficiently reduced as the composition ratio x of SiO x decreases. On the other hand, in Comparative Examples 1 and 2 and Conventional Example 1, it was found that the etching rate increases significantly as the composition ratio x increases, and it cannot be used for MEMS device applications.

[0072] (Evaluation: Evaluation of peak value of Si 2p spectrum) The oxidation state of Si in the etching buffer layer was also evaluated. The oxidation state of Si was evaluated by confirming the Si 2p peak position of the bonding state between Si and O in the etching buffer layer using XPS analysis. That is, since the 2p spectrum peak of SiO2, which has a tetrahedral structure, is 103 eV, the tetrahedral structure density in the etching buffer layer can be indirectly evaluated. The evaluation results are shown in Table 1. In Examples 1 to 6, the Si 2p peak position was less than 103 eV, indicating a low tetrahedral structure density. Based on the etching rate evaluation results, it is believed that the low tetrahedral structure density of SiO2, which undergoes an etching reaction with hydrofluoric acid, caused the hydrofluoric acid etching rate to decrease.

[0073] [Table 1] [Industrial Applicability]

[0074] According to the present invention, an SOI wafer suitable for use in an MEMS device can be obtained while improving etching resistance. [Explanation of symbols]

[0075] 1,100,200,300,400,500,600 SOI wafers 10,110,210,310,410,510,610 Silicon wafers for support substrates 120,220,320,420,520,620 Silicon wafers for single crystal silicon layers 30,130,230,330,430,530,630 Middle class 131,231,431 BOX layer 132,232 Amorphous silicon adhesive layer 335,535,635 Silicon oxide adhesion layer 50,150,250,350,450,550,650 Etching buffer layer

Claims

1. a silicon wafer for a support substrate; an intermediate layer on the support substrate silicon wafer; a single crystal silicon layer on the intermediate layer, the intermediate layer is a BOX layer having a thickness of 1 μm or more and 20 μm or less and made of SiO y (1.00≦y≦2.00), the silicon wafer for support substrate has an etching buffer layer on the back surface, The etching buffer layer has a thickness of 100 nm to 20 μm and is made of SiO ｘ (0<x≦0.60) SOI wafer.

2. The SOI wafer according to claim 1, wherein the etching buffer layer is SiO x (0<x≦0.54).

3. an adhesive layer made of amorphous silicon or silicon oxide between the support substrate silicon wafer and the single crystal silicon layer; The SOI wafer according to claim 1 .

4. the intermediate layer has the adhesive layer directly on the BOX layer, the adhesive layer is made of the amorphous silicon; The SOI wafer according to claim 3 .

5. the intermediate layer has the adhesive layer directly under the BOX layer, the adhesive layer is made of the amorphous silicon; The SOI wafer according to claim 3 .

6. the intermediate layer has the adhesive layer directly on the BOX layer, The adhesive layer is made of silicon oxide. The SOI wafer according to claim 3 .

7. the intermediate layer has the adhesive layer directly under the BOX layer, The adhesive layer is made of silicon oxide. The SOI wafer according to claim 3 .

8. The method for producing an SOI wafer according to any one of claims 1 to 7, The method for producing an SOI wafer includes forming the etching buffer layer using a plasma CVD method (PE-CVD).

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