Electronic components and circuit devices

Abstract

An electronic component (101) comprises a semiconductor substrate (1), an insulator layer (2) formed on the semiconductor substrate (1), a plurality of conductor layers formed on the insulator layer (2), a dielectric layer (4) formed on the semiconductor substrate (1), and a bottom surface electrode (8) formed on the bottom surface of the semiconductor substrate (1). At least one of the plurality of conductor layers is a wiring pattern. At least one of the plurality of conductor layers is a plate electrode that forms a pair with the semiconductor substrate (1) or the bottom surface electrode (8) to sandwich the dielectric layer (4). Conductor parts (7) having a higher conductivity than the semiconductor substrate (1) are located in a first region consisting of the dielectric layer (4) and the plate electrode in the semiconductor substrate (1) in a higher proportion than a second region that is different from the first region.

Description

[Technical Field]

[0001] The present invention relates to an electronic component that includes a semiconductor substrate and is configured by providing a capacitor, an inductor, etc. on the semiconductor substrate. [Background technology]

[0002] Patent Document 1 shows a high-frequency integrated circuit device in which passive devices such as inductors and capacitors are formed in an insulator layer stacked on a semiconductor substrate. All of the capacitors included in this high-frequency integrated circuit device have an MIM (metal-insulator-metal) structure, and their electrodes are arranged on the surface of the insulator layer stacked on the semiconductor substrate.

[0003] Patent Document 2 discloses a semiconductor device having a capacitor formed by laminating a dielectric layer and an electrode layer on a semiconductor substrate. One electrode of the capacitor is located on the surface of the insulating layer facing the semiconductor substrate, and the other electrode is located on the underside of the semiconductor substrate. Therefore, if the substrate on which this semiconductor device is mounted is a conductor at ground potential, the capacitor and ground are electrically connected directly, eliminating the need for wiring to connect the two. For convenience, a capacitor with this structure will be referred to as a "vertical capacitor" in this specification. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 98 / 012751 [Patent Document 2] Patent Publication No. 2021-93439 Summary of the Invention [Problem to be solved by the invention]

[0005] In the high-frequency integrated circuit device described in Patent Document 1, for example, when configuring a power amplifier for a communication device, it is assumed that the power amplifier will be placed on a copper foil surface at ground potential formed on a circuit board. Furthermore, such a high-frequency integrated circuit device includes a capacitor inserted between a signal line and ground. If this capacitor is configured using the aforementioned MIM, one electrode of the capacitor must be connected to ground via a wiring structure such as a wire. In this case, parasitic impedance due to the wiring structure is electrically inserted between the capacitor and ground, which can cause deterioration of the capacitor's electrical characteristics, such as its Q value.

[0006] The problem of deterioration of electrical circuit characteristics due to the wiring structure does not arise with a vertical capacitor as shown in Patent Document 2. However, as shown in Patent Document 1, when an attempt is made to form a vertical capacitor together with a passive device such as an inductor using a conductor pattern (hereinafter referred to as a "pattern inductor") on an insulator layer stacked on a semiconductor substrate, the electrical characteristics such as the Q value of the inductor deteriorate, as will be described below.

[0007] First, let's consider the equivalent series resistance (ESR) of a vertical capacitor. The equivalent series resistance of a vertical capacitor is determined by the conductivity of the internal wiring and semiconductor substrate, which are the paths of current flowing through the capacitor. Generally, semiconductor substrates have lower conductivity than internal wiring, and the current paths are longer. For this reason, the conductivity of the semiconductor substrate tends to be the main factor that increases the equivalent series resistance of a vertical capacitor. To reduce the equivalent series resistance of a vertical capacitor, it is necessary to increase the conductivity of the semiconductor substrate.

[0008] The equivalent series resistance (ESR) of a pattern inductor is also determined by the conductivity of the conductor pattern, including the internal wiring, and the semiconductor substrate. In other words, since the conductor pattern is part of the inductor's current path, the equivalent series resistance of a pattern inductor is directly affected by the conductivity of the conductor pattern.

[0009] However, as will be described later in [Means for Solving the Problems], the mechanism by which the conductivity of a semiconductor substrate causes equivalent series resistance differs between a vertical capacitor and a pattern inductor. An object of the present invention is to provide an electronic component and a circuit device that include an inductor with a high Q value and a capacitor with a high Q value when an inductor using a wiring pattern and a vertical capacitor are formed on an insulator layer stacked on a semiconductor substrate. [Means for solving the problem]

[0010] When a pattern inductor operates as an inductor, it generates a high-frequency magnetic field around it, which induces eddy currents in conductors near the pattern inductor, and these eddy currents generate Joule heat. This Joule heat is generally called eddy current loss, and increases the higher the conductivity of the conductor through which the eddy current flows. This eddy current loss appears as equivalent series resistance in the electrical characteristics of the inductor.

[0011] In a structure in which a pattern inductor is formed on an insulator layer stacked on a semiconductor substrate, the "semiconductor substrate" refers to the "conductor in the vicinity of the inductor." Therefore, in order to reduce the equivalent series resistance of the pattern inductor, it is necessary to reduce the conductivity of the semiconductor substrate.

[0012] However, the equivalent series resistance of a vertical capacitor and a pattern inductor is affected by the conductivity of the silicon substrate, so there is a trade-off between them. For example, if the conductivity of the silicon substrate is increased to improve the Q value of the vertical capacitor, the Q value of the pattern inductor will deteriorate, and if the conductivity of the silicon substrate is decreased to improve the Q value of the pattern inductor, the Q value of the vertical capacitor will deteriorate.

[0013] Therefore, an electronic component as an example of the present disclosure includes: a semiconductor substrate; an insulator layer formed on the semiconductor substrate; a plurality of conductive layers formed on the insulating layer; a dielectric layer formed on the semiconductor substrate; a lower surface electrode formed on a lower surface of the semiconductor substrate; Equipped with At least one of the plurality of conductive layers is a wiring pattern, at least one of the plurality of conductor layers is a flat electrode that is paired with the semiconductor substrate or the lower electrode with the dielectric layer interposed therebetween, a conductor portion having a higher conductivity than the semiconductor substrate is arranged in a first region of the semiconductor substrate where the dielectric layer and the plate electrode are formed, at a higher rate than in a second region other than the first region; It is characterized by:

[0014] Furthermore, a circuit device as an example of the present disclosure includes: the electronic component and a mounting substrate on which the electronic component is mounted, The ground pattern of the mounting board and the bottom electrode of the electronic component are connected to each other. [Effects of the Invention]

[0015] According to the present invention, an electronic component can be obtained that includes an inductor with a high Q value due to suppression of eddy currents flowing in a semiconductor substrate, and a capacitor with a high Q value due to a reduction in equivalent series resistance. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1A is a plan view of an electronic component 101 according to a first preferred embodiment, and FIG. 1B is a cross-sectional view taken along the line BB in FIG. 1A. [Figure 2] FIG. 2 is a circuit diagram of the electronic component 101. [Figure 3] FIG. 3 is a block diagram showing the circuit configuration of the transmitting section of the communication device. [Figure 4] FIG. 4(A) is a circuit diagram of an electronic component 101A that is different from the electronic component 101 shown in FIGS. 1(A) and 1(B), and FIG. 4(B) is a circuit diagram of an electronic component 101B that is different from the electronic component 101 shown in FIGS. 1(A) and 1(B). [Figure 5] FIG. 5 is a cross-sectional view of an electronic component 102 according to the second preferred embodiment. [Figure 6] FIG. 6 is a cross-sectional view of an electronic component 103 according to the third preferred embodiment. [Figure 7] FIG. 7 is a cross-sectional view of an electronic component 104 according to the fourth preferred embodiment. [Figure 8] FIG. 8 is a cross-sectional view of an electronic component 105 according to the fifth preferred embodiment. [Figure 9] FIG. 9A is a partial vertical cross-sectional view of an electronic component 106 according to a sixth embodiment, and FIG. 9B is a plan cross-sectional view taken along the line XX in FIG. 9A. [Figure 10] FIG. 10 is a partial cross-sectional plan view of an electronic component 107 according to the seventh preferred embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, several specific examples will be given with reference to the drawings to illustrate several embodiments for carrying out the present invention. The same reference numerals are used for the same parts in each drawing. For the sake of convenience, the embodiments are shown divided into several embodiments, taking into account ease of explanation and understanding of the main points, but partial substitution or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, a description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0018] First Embodiment Fig. 1(A) is a plan view of an electronic component 101 according to a first embodiment, and Fig. 1(B) is a cross-sectional view taken along line BB in Fig. 1(A). However, Fig. 1(A) is a plan view showing a state before a protective film 10, which will be described later, is formed.

[0019] This electronic component 101 comprises a semiconductor substrate 1, an insulator layer 2 formed on this semiconductor substrate 1, conductor layers 3A, 3B, 3C, 3D, 3E, 3F, 3G, and 3H formed in the insulator layer 2, a dielectric layer 4 formed on the semiconductor substrate 1, a dielectric layer 5 formed in the insulator layer 2, a first pad electrode 9A and a second pad electrode 9B formed on the conductor layers 3G and 3H, a protective film 10 formed on the upper surface side of the semiconductor substrate 1, and a lower surface electrode 8 formed on the lower surface of the semiconductor substrate 1.

[0020] The semiconductor substrate 1 is a substrate made of an impurity semiconductor such as a carrier-doped silicon substrate, the insulator layer 2 is, for example, a SiN film, the conductor layers 3A, 3B, 3C, 3D, and 3E are, for example, Al films, the conductor layers 3F, 3G, and 3H are, for example, Cu films, the dielectric layers 4 and 5 are, for example, SiO2 films, the first pad electrode 9A and the second pad electrode 9B are, for example, metal films with a Ni base and an Au surface, the protective film 10 is, for example, an organic insulating film such as solder resist, and the lower electrode 8 is, for example, a metal film with a Cu or Ni base and an Au surface.

[0021] The wiring pattern made of conductive layers 3A and 3B forms an inductor. Conductive layers 3C and 3D form capacitor electrodes formed in insulator layer 2. Conductive layer 3E forms a flat plate electrode formed on dielectric layer 4. Conductive layers 3F, 3G, and 3H form extraction electrodes. The first pad electrode 9A and the second pad electrode 9B are used, for example, as pads for wire bonding. The lower electrode 8 is used, for example, as an electrode for die bonding.

[0022] The wiring pattern of the conductor layers 3A and 3B forms an inductor region ZL in the semiconductor substrate 1. The region in the semiconductor substrate 1 where the conductor layer 3E and the dielectric layer 4 are formed as flat electrodes is a capacitor region ZC. This capacitor region ZC is an example of the first region according to the present invention. The region of the semiconductor substrate 1 other than the first region is a second region.

[0023] A conductor portion 7 is formed in the capacitor region ZC of the semiconductor substrate 1. In this example, the conductor portion 7 is arranged below the dielectric layer 4. In this embodiment, the inductor region ZL is part of the second region. The conductor portion 7 is arranged in a higher proportion in the capacitor region ZC (first region) of the semiconductor substrate 1 than in the second region of the semiconductor substrate 1 including the inductor region ZL. The conductor portion 7 is made of, for example, conductive polysilicon and has a higher conductivity than the semiconductor substrate 1. This conductor portion 7 is formed, for example, by digging a plurality of trenches in the semiconductor substrate 1 and filling the trenches with the conductive polysilicon or the like.

[0024] In this embodiment, the conductor layer 3E is configured with a side extending in the X-axis direction and a side extending in the Y-axis direction, and the plurality of conductor portions 7 extend parallel to one another in the Y-axis direction.

[0025] Conductive layers 3A and 3B are spiral conductive layers and form an inductor. Conductive layer 3E, dielectric layer 4, semiconductor substrate 1, conductor portion 7, and bottom electrode 8 form a capacitor. Here, conductive layer 3E is the first electrode of the capacitor, and semiconductor substrate 1, conductor portion 7, and bottom electrode 8 are the second electrode of the capacitor.

[0026] As described above, a higher proportion of conductor portions 7 with higher conductivity than that of semiconductor substrate 1 are arranged in capacitor region ZC of semiconductor substrate 1 compared to inductor region ZL. This allows the conductivity of semiconductor substrate 1 to be lowered, thereby suppressing eddy currents induced in semiconductor substrate 1 by the high-frequency magnetic field generated by the wiring pattern of conductor layers 3A and 3B, resulting in an inductor with a high Q value. Furthermore, the conductivity of capacitor region ZC, where conductor layer 3E is formed as a flat electrode, can be increased, resulting in a capacitor with a high Q value.

[0027] The electronic component 101 described above is mounted on a mounting substrate. This mounting substrate and the electronic component 101 form a circuit device. A ground pattern and other electrode patterns are formed on the mounting substrate. The first pad electrode 9A is electrically connected to the conductive layer 3E, and the second pad electrode 9B is electrically connected to one end of the conductive layer 3A that forms the inductor pattern, and the other end of the conductive layer 3A is electrically connected to the conductive layer 3E.

[0028] The lower surface electrode 8 of the electronic component 101 is connected to a ground pattern formed on the mounting substrate, and the first pad electrode 9A and the second pad electrode 9B are wire-bonded to electrode patterns other than the ground pattern formed on the mounting substrate.

[0029] FIG. 2 is a circuit diagram of electronic component 101. Ports P1 and P2 shown in FIG. 2 correspond to first pad electrode 9A and second pad electrode 9B of electronic component 101 shown in FIGS. 1(A) and 1(B), respectively, and the ground shown in FIG. 2 corresponds to bottom electrode 8 in FIGS. 1(A) and 1(B). Capacitor C1 shown in FIG. 2 is a capacitor formed by conductive layer 3E, dielectric layer 4, conductor portion 7, semiconductor substrate 1, and bottom electrode 8. Capacitor C2 shown in FIG. 2 is a capacitor formed by conductive layers 3C and 3D and dielectric layer 5. Inductor L1 shown in FIG. 2 is an inductor formed by conductive layers 3A and 3B. An impedance matching circuit is formed by such an LC circuit.

[0030] The capacitor C1 formed in the capacitor region ZC is connected to the ground pattern of the mounting board through the semiconductor substrate 1 and the conductor portion, so that the equivalent series resistance ESR can be suppressed compared to a routing device that uses wiring, and an impedance matching circuit with a high Q value can be obtained.

[0031] Figure 3 is a block diagram showing the circuit configuration of the transmitter of a communication device. This transmitter includes a transmitter circuit that receives a transmit signal, modulates it, and outputs a high-frequency transmit signal, a power amplifier PA, and an impedance matching circuit MC that matches the impedance between the transmitter circuit and the power amplifier PA. The output signal of the power amplifier PA is guided to an antenna. A communication device including the transmitter shown in Figure 3 is installed in, for example, a base station.

[0032] Fig. 4(A) is a circuit diagram of an electronic component 101A that is different from the electronic component 101 shown in Fig. 1(A) and Fig. 1(B), and Fig. 4(B) is a circuit diagram of an electronic component 101B that is different from the electronic component 101 shown in Fig. 1(A) and Fig. 1(B). The electronic component 101A is a π-type impedance matching circuit formed by capacitors C1 and C2 and an inductor L1, and the electronic component 101B is a T-type impedance matching circuit formed by inductors L1 and L2 and a capacitor C1.

[0033] In electronic component 101A, capacitors C1 and C2 connected in shunt between the signal line and ground are vertical capacitors configured in capacitor region ZC in Figures 1(A) and 1(B). Also, inductor L1 inserted in series with the signal line is an inductor configured in inductor region ZL in Figures 1(A) and 1(B).

[0034] In electronic component 101B, capacitor C1, which is shunt-connected between the signal line and ground, is a vertical capacitor configured in capacitor region ZC in Figures 1(A) and 1(B). Also, inductors L1 and L2, which are inserted in series with the signal line, are inductors configured in inductor region ZL in Figures 1(A) and 1(B).

[0035] In this way, an impedance matching circuit composed of a high Q capacitor and a high Q inductor is obtained.

[0036] 1 and 2, the lower electrode 8 formed on the lower surface of the semiconductor substrate 1 is connected to the ground of the impedance matching circuit in order to reduce the ESR of the capacitor C1 that is shunt-connected between the signal line and the ground, but the use of the first pad electrode 9A and the lower electrode 8 is not limited to this. For example, the first pad electrode 9A may be connected to the circuit ground, and the lower electrode 8 may be used as a port of the signal line. In other words, the lower electrode of the semiconductor substrate 1 may be used as a capacitor electrode.

[0037] Second Embodiment In the second embodiment, an electronic component will be described in which the configuration of a conductor portion disposed in a capacitor region is different from that of the example shown in the first embodiment.

[0038] FIG. 5 is a cross-sectional view of an electronic component 102 according to a second embodiment. The cross-sectional position corresponds to the position shown in FIG. 1(B). In the electronic component 101 shown in FIG. 1(B), the conductor portion 7 is formed in the upper part of the semiconductor substrate 1, but in the example shown in FIG. 5, the conductor portion 7 is formed in the lower part of the semiconductor substrate 1. Furthermore, the conductor portion 7 is in direct electrical contact with the lower electrode 8. That is, in the example of the electronic component 101 shown in FIG. 1(B), the conductor portion 7 is formed by digging multiple trenches in the upper part of the semiconductor substrate 1 and filling those trenches with a conductor, but in the example shown in FIG. 5, the conductor portion 7 is formed by digging multiple trenches in the lower part of the semiconductor substrate 1 and filling those trenches with a conductor.

[0039] As shown in this embodiment, the conductor portion 7 arranged in the capacitor region ZC may be formed below the semiconductor substrate 1. In the electronic component 102, the combined conductivity of the semiconductor substrate 1, the conductor portion 7, and the lower electrode 8 that constitute the second electrode of the vertical capacitor is high, so that a capacitor with a high Q value can be formed.

[0040] Third Embodiment In the third embodiment, an electronic component will be illustrated in which the configuration of a conductor portion disposed in a capacitor region is different from the examples shown in the previous embodiments.

[0041] Fig. 6 is a cross-sectional view of an electronic component 103 according to a third embodiment. The cross-sectional position corresponds to the position shown in Fig. 1(B). In the electronic component 101 shown in Fig. 1(B), the conductor portion 7 is formed near the upper portion of the semiconductor substrate 1, but in the example shown in Fig. 6, the conductor portion 7 is formed from the upper surface to the lower surface of the semiconductor substrate 1.

[0042] As shown in this embodiment, the conductor portion 7 arranged in the capacitor region ZC may be formed from the upper surface to the lower surface of the semiconductor substrate 1. In the electronic component 103, the combined conductivity of the semiconductor substrate 1, the conductor portion 7, and the lower electrode 8, which constitute the second electrode of the vertical capacitor, is high, so that a capacitor with a high Q value can be formed.

[0043] Fourth Embodiment In the fourth embodiment, an electronic component will be illustrated in which the configuration of a conductor portion disposed in a capacitor region is different from the examples shown in the previous embodiments.

[0044] Fig. 7 is a cross-sectional view of an electronic component 104 according to a fourth embodiment. The cross-sectional position corresponds to the position shown in Fig. 1(B). In the electronic component 101 shown in Fig. 1(B), the conductor portion 7 is formed near the upper portion of the semiconductor substrate 1, but in the example shown in Fig. 7, the conductor portion 7 is formed inside the semiconductor substrate 1.

[0045] As shown in this embodiment, the conductor portion 7 arranged in the capacitor region ZC may be formed inside the semiconductor substrate 1. In the electronic component 104, the combined conductivity of the semiconductor substrate 1, the conductor portion 7, and the lower electrode 8 that constitute the second electrode of the vertical capacitor is high, so that a capacitor with a high Q value can be formed.

[0046] Fifth Embodiment In the fifth embodiment, an electronic component will be illustrated in which the configuration of a conductor portion disposed in a capacitor region is different from the examples shown in the previous embodiments.

[0047] Fig. 8 is a cross-sectional view of an electronic component 105 according to a fifth embodiment. The cross-sectional position corresponds to the position shown in Fig. 1(B). In the electronic component 101 shown in Fig. 1(B), the conductor portions 7 are formed on the upper part of the semiconductor substrate 1, and in the electronic component 102 shown in Fig. 5, the conductor portions 7 are formed on the lower part of the semiconductor substrate 1. However, in the example shown in Fig. 8, some of the multiple conductor portions 7 are formed on the upper part of the semiconductor substrate 1 and some are formed on the lower part of the semiconductor substrate 1.

[0048] As shown in this embodiment, the conductor portion 7 arranged in the capacitor region ZC may be formed on both the upper and lower parts of the semiconductor substrate 1. In the electronic component 102, the combined conductivity of the semiconductor substrate 1, the conductor portion 7, and the lower electrode 8, which constitute the second electrode of the vertical capacitor, is high, so that a capacitor with a high Q value can be formed.

[0049] Sixth Embodiment In the sixth embodiment, an electronic component will be described in which the configuration of a vertical capacitor is different from the examples shown in the previous embodiments.

[0050] Fig. 9(A) is a partial vertical cross-sectional view of an electronic component 106 according to a sixth embodiment, and Fig. 9(B) is a plan cross-sectional view taken along the line XX in Fig. 9(A). Both Fig. 9(A) and Fig. 9(B) illustrate the vertical capacitor portion, and the configuration of other portions is the same as that of the electronic components shown in the previous embodiments.

[0051] Electronic component 106 of this embodiment includes semiconductor substrate 1, insulator layer 2 formed on semiconductor substrate 1, conductor layers 3E, 3F, and 3G formed on insulator layer 2, dielectric layer 4 formed on semiconductor substrate 1, first pad electrode 9A formed on conductor layer 3G, protective film 10 formed on the upper surface side of semiconductor substrate 1, and lower surface electrode 8 formed on the lower surface of semiconductor substrate 1. Examples of materials for each part are as described in the first embodiment.

[0052] In this embodiment, a plurality of trenches are dug in the upper surface of the semiconductor substrate 1, and a dielectric material is coated on the inner surfaces of these trenches and the upper surface of the semiconductor substrate 1 to form the dielectric layer 4. In addition, a conductor layer 3E is coated on the dielectric layer 4. The conductor portion 7 is formed by dug a plurality of trenches in the lower surface of the semiconductor substrate 1 and filling the trenches with a conductor.

[0053] According to this embodiment, the gap between the conductor portion 7 and the dielectric layer 4 can be reduced, thereby effectively increasing the Q value of the vertical capacitor. In addition, the effective area of ​​the dielectric layer 4 interposed between the conductor layer 3E and the semiconductor substrate 1 can be increased, thereby saving space in the vertical capacitor.

[0054] Seventh Embodiment In the seventh embodiment, an electronic component will be described in which the configuration of a vertical capacitor is different from the examples shown in the previous embodiments.

[0055] 10 is a partial cross-sectional plan view of an electronic component 107 according to the seventh preferred embodiment of the present invention. The cross-sectional position corresponds to the position shown in FIG.

[0056] In the example shown in Figures 9(A) and 9(B), the lower part of the conductor layer 3E and the conductor portion 7 are formed in a line shape, and the lower part of the dielectric layer 4 is formed in a groove shape, but in this embodiment, the lower part of the conductor layer 3E and the conductor portion 7 are formed in a cylindrical shape, and the lower part of the dielectric layer 4 is formed in a cylindrical shape.

[0057] According to this embodiment, as in the sixth embodiment, the gap between the conductor portion 7 and the dielectric layer 4 can be reduced, thereby effectively increasing the Q value of the vertical capacitor. In addition, the effective area of ​​the dielectric layer 4 interposed between the conductor layer 3E and the semiconductor substrate 1 can be increased, thereby saving space in the vertical capacitor.

[0058] In each of the above-described embodiments, the inductor pattern formed in the inductor region ZL is spiral, but the inductor pattern formed in the inductor region ZL is not limited to a spiral shape. For example, the inductor pattern may be loop-shaped, or may be helical in shape in which a plurality of loop-shaped conductor patterns are stacked and connected by interlayer connecting conductors.

[0059] 1 shows the conductor portion extending in the Y-axis direction, the shape of the conductor portion is not limited to this. For example, the conductor portion may be in the shape of multiple cylinders, multiple crosses, or multiple tubes.

[0060] Finally, the present invention is not limited to the above-described embodiments. Those skilled in the art can make appropriate modifications and variations. The scope of the present invention is defined not by the above-described embodiments but by the claims. Furthermore, the scope of the present invention includes modifications and variations from the embodiments within the scope of the claims and their equivalents.

[0061] In each embodiment, an electronic component including a capacitor and an inductor as a passive component is shown, but the present invention can be similarly applied to an electronic component including both a passive component and an active component.

[0062] 1(A) and 1(B), when viewed in a direction perpendicular to the plane of the semiconductor substrate 1, the conductor portion 7 is contained within the region where the dielectric layer 4 is formed in the X-axis direction and protrudes from the region where the dielectric layer 4 is formed in the Y-axis direction, but this is not limited to this. For example, the conductor portion 7 may also be disposed outside the region where the dielectric layer 4 is formed in the X-axis direction. Even in this case, it is effective for increasing the substantial conductivity of the current path flowing to the second electrode formed by the semiconductor substrate 1, the conductor portion 7, and the lower electrode 8.

[0063] In the above-described embodiments, the conductor portion 7 is disposed only in the capacitor region ZC of the vertical capacitor, but the conductor portion may be disposed outside the capacitor region. Even in this case, it is sufficient that the conductor portion 7 is disposed in the capacitor region ZC of the semiconductor substrate 1 at a higher ratio than in the inductor region ZL. [Explanation of symbols]

[0064] C1, C2...capacitors L1, L2...inductors MC...Impedance matching circuit P1, P2...Ports PA...power amplifier ZC: Capacitor region ZL: Inductor region 1...Semiconductor substrate 2...Insulator layer 3A,3B,3C,3D,3E,3F,3G,3H...Conductor layer 4,5...Dielectric layers 7...Conductor 8…Bottom electrode 9A...First pad electrode 9B...Second pad electrode 10...Protective film 101, 101A, 101B, 102, 103, 104, 105, 106, 107...Electronic components

Claims

1. a semiconductor substrate; an insulator layer formed on the semiconductor substrate; a plurality of conductive layers formed on the insulating layer; a dielectric layer formed on the semiconductor substrate; a lower surface electrode formed on a lower surface of the semiconductor substrate; Equipped with At least one of the plurality of conductive layers is a wiring pattern, at least one of the plurality of conductor layers is a flat electrode that is paired with the semiconductor substrate or the lower electrode with the dielectric layer interposed therebetween, a conductor portion having a higher conductivity than the semiconductor substrate is disposed in a first region of the semiconductor substrate where the dielectric layer and the plate electrode are formed, at a higher rate than in a second region other than the first region; the conductor portion is made of a material different from that of the semiconductor substrate, and a plurality of the conductor portions are embedded in the semiconductor substrate; Electronic components.

2. the conductor portion is formed in a region of the semiconductor substrate where the dielectric layer is formed, The electronic component according to claim 1 .

3. At least one of the plurality of conductive layers is a spiral or loop-shaped inductor pattern, the inductor pattern is formed in the second region of the semiconductor substrate, and the conductor portion is not formed in the inductor region of the semiconductor substrate where the inductor pattern is formed. The electronic component according to claim 1 or 2.

4. some of the plurality of conductive layers respectively constitute a first pad electrode and a second pad electrode for connection to other elements; the first pad electrode is electrically connected to the plate electrode, the second pad electrode is electrically connected to one end of the inductor pattern, the other end of the inductor pattern is electrically connected to the plate electrode; The electronic component according to claim 3 .

5. the conductor portion is in contact with the dielectric layer; The electronic component according to claim 1 .

6. the conductor portion is in contact with the lower electrode; The electronic component according to claim 1 .

7. The electronic component according to claim 1; a mounting substrate for mounting the electronic component, the bottom electrode of the electronic component is connected to the ground pattern of the mounting board.

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