Vertical Field-Effect Transistor with Cross-Linked Fin Array

Abstract

The semiconductor structure and method for manufacturing the same includes a semiconductor substrate having a top surface and a fin structure on the top surface of the semiconductor substrate, the fin structure including n first regions extending perpendicular to the top surface of the semiconductor substrate and n-1 second regions extending between and connecting each of the n first regions and parallel to the top surface of the semiconductor substrate, where n≧3.

Description

[Technical Field]

[0001] The present invention relates generally to the field of semiconductor devices, and more particularly to the fabrication of cross-linked fin structures in vertical field effect transistors (VFETs). [Background technology]

[0002] VFETs have been pursued as a potential device option for scaling complementary metal-oxide semiconductors (CMOS) to the 5-nanometer (nm) node and beyond. In contrast to planar CMOS devices, VFETs have vertically oriented vertical fins or nanowires extending upward from a substrate. The fins or nanowires form the transistor's channel region. Source and drain regions are positioned in electrical contact with the top and bottom ends of the channel region, while gates are positioned on the sidewalls of one or more fins or nanowires. Thus, in a VFET, the direction of current flow between the source and drain regions is perpendicular to the major surface of the substrate.

[0003] The advantages of the VFET architecture include improved electrostatic characteristics and a larger effective width (W) available in a given device footprint. eff ) and the ability to increase the amount of W without compromising area scaling. Continued scaling of fin width and fin pitch can present many challenges due to a combination of quantum effects, the realities of the patterning process, and limitations of contact architectures. eff Fin structures with various shapes have been investigated to improve W. eff C-, Pi-, and U-shaped fin structures have been implemented to improve the gate capacitance. However, their designs are not flexible, and high parasitic capacitances have been observed between the bottom source / drain contacts (CR) and the gate. Summary of the Invention

[0004] According to one aspect of the present invention, a semiconductor structure includes a semiconductor substrate having a top surface and a fin structure on the top surface of the semiconductor substrate, the fin structure including n first regions extending perpendicular to the top surface of the semiconductor substrate and n-1 second regions extending between and connecting each of the n first regions and parallel to the top surface of the semiconductor substrate, where n≧3.

[0005] According to another aspect of the invention, a method of forming a semiconductor structure includes forming a hard mask layer on a top surface of a semiconductor substrate, transferring a pattern into the hard mask layer defining a plurality of fin structures, and forming the plurality of fin structures on the top surface of the semiconductor substrate according to the transferred pattern, the plurality of fin structures including one or more vertical regions extending in a direction perpendicular to the top surface of the semiconductor substrate and parallel to one another, and at least two of the one or more vertical regions being connected by a horizontal region extending between the at least two vertical regions in a direction parallel to the top surface of the semiconductor substrate.

[0006] According to yet another aspect of the invention, a method of forming a semiconductor structure includes forming a hard mask layer on a top surface of a semiconductor substrate; forming a first array of mandrels on the hard mask layer; forming first sidewall spacers on opposing vertical sidewalls of each mandrel in the first array of mandrels; forming a second array of mandrels on the hard mask layer, wherein each mandrel in the second array of mandrels is laterally spaced from each mandrel in the first array of mandrels by the first sidewall spacer; forming second sidewall image-transferred spacers on laterally opposing sidewalls of the first array of mandrels and the second array of mandrels; and selectively removing a portion of the second sidewall image-transferred spacers to define a cross-link fin pattern.

[0007] Therefore, according to an embodiment of the present invention, W effImproved designs and techniques are provided for fabricating VFET devices with cross-linked fin structures that offer design flexibility while improving performance.

[0008] The following detailed description, given by way of example and not intended to limit the invention thereto, can be best understood in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0009] [Figure 1A] 2A is a cross-sectional view of a semiconductor structure taken along line AA at an initial step during a fin patterning process according to one embodiment of the present disclosure. FIG. [Figure 1B] 1 is a top view of a semiconductor structure. [Figure 2A] FIG. 2 is a cross-sectional view of a semiconductor structure taken along line AA after forming a first array of mandrels and first sidewall image transferred spacers according to one embodiment of the present disclosure. [Figure 2B] 1 is a top view of a semiconductor structure. [Figure 3A] FIG. 2 is a cross-sectional view of a semiconductor structure after depositing a second semiconductor material according to an embodiment of the present disclosure. [Figure 3B] FIG. 2 is a side view of the semiconductor structure along the Y-plane. [Figure 3C] 1 is a top view of a semiconductor structure. [Figure 4A] FIG. 2 is a cross-sectional view of the semiconductor structure along line AA after recessing the second semiconductor material according to one embodiment of the present disclosure. [Figure 4B] FIG. 1 is a side view of the semiconductor structure taken along line BB. [Figure 4C] 1 is a top view of a semiconductor structure. [Figure 5A] FIG. 2 is a cross-sectional view of the semiconductor structure along line AA after patterning of the second semiconductor material according to one embodiment of the present disclosure. [Figure 5B] FIG. 1 is a side view of the semiconductor structure taken along line BB. [Figure 5C] 1 is a top view of a semiconductor structure. [Figure 6A]FIG. 2 is a cross-sectional view of a semiconductor structure taken along line AA after forming second sidewall image transferred spacers according to one embodiment of the present disclosure. [Figure 6B] FIG. 1 is a side view of the semiconductor structure taken along line BB. [Figure 6C] 1 is a top view of a semiconductor structure. [Figure 7A] 2 is a cross-sectional view of a semiconductor structure taken along line AA after forming an organic planarization layer and a via opening according to one embodiment of the present disclosure. [Figure 7B] FIG. 1 is a side view of the semiconductor structure taken along line BB. [Figure 7C] 1 is a top view of a semiconductor structure. [Figure 8A] FIG. 2 is a cross-sectional view of a semiconductor structure taken along line AA after selectively removing a portion of a second sidewall image transfer spacer according to an embodiment of the present disclosure. [Figure 8B] FIG. 1 is a side view of the semiconductor structure taken along line BB. [Figure 8C] 1 is a top view of a semiconductor structure. [Figure 9A] FIG. 2 is a cross-sectional view of the semiconductor structure along line AA after removing the organic planarization layer, the first mandrel, and the second mandrel according to one embodiment of the present disclosure. [Figure 9B] FIG. 1 is a side view of the semiconductor structure taken along line BB. [Figure 9C] 1 is a top view of a semiconductor structure. [Figure 10A] FIG. 2 is a cross-sectional view of a semiconductor structure along line AA after transferring a pattern defined by first sidewall image-transferred spacers and second sidewall image-transferred spacers to a hard mask layer according to an embodiment of the present disclosure. [Figure 10B] FIG. 1 is a side view of the semiconductor structure taken along line BB. [Figure 10C] 1 is a top view of a semiconductor structure. [Figure 11A] FIG. 2 is a cross-sectional view of a semiconductor structure taken along line AA after forming a plurality of fin structures according to an embodiment of the present disclosure. [Figure 11B] FIG. 1 is a side view of the semiconductor structure taken along line BB. [Figure 11C] 1 is a top view of a semiconductor structure. DETAILED DESCRIPTION OF THE INVENTION

[0010] The drawings are not necessarily to scale. The drawings are merely schematic and are not intended to depict specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbers represent like elements.

[0011] Although detailed embodiments of the claimed structures and methods are disclosed herein, it should be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in various forms. However, the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments described herein. The description may omit details of well-known features and techniques to avoid unnecessarily obscuring the presented embodiments.

[0012] For purposes of the following description, terms such as "above," "below," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives refer to the disclosed structures and methods as oriented in the drawing figures. Terms such as "above," "overlying," "on," "upon," "disposed on," or "disposed above" mean that a first element, such as a first structure, is on a second element, such as a second structure, even if an intervening element, such as an interfacial structure, is present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive, insulating, or semiconducting layer at the interface between the two elements.

[0013] In order to avoid obscuring the presentation of embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be combined with each other for purposes of presentation and illustration, and in some cases may not be described in detail. In other instances, some process steps or operations known in the art may not be described at all. It should be understood that the following description instead focuses on unique features or elements of various embodiments of the present invention.

[0014] Non-planar transistor device architectures, such as VFETs, employ semiconductor fins and side gates that can contact the outside of the active region, resulting in higher device density than lateral devices. In VFETs, current flows from source to drain in a direction perpendicular to the major surface of the substrate. For example, in known VFET configurations, the major substrate surface is horizontal, and a vertical fin extends upward from the substrate surface. The fin forms the transistor's channel region. Source / drain regions are positioned in electrical contact with the top and bottom of the channel region (i.e., the top source / drain region and the bottom source / drain region), while a gate is positioned on one or more fin sidewalls.

[0015] As mentioned previously, the VFET architecture offers improved electrostatic performance and a larger effective width (W) available in a given device footprint. eff ) without compromising area scaling. Continued scaling of fin width and fin pitch can pose many challenges to VFET fabrication due to a combination of quantum effects, patterning process realities, and contact architecture limitations. eff To improve W, fin structures with various shapes have been investigated. eff To improve this, C-, Pi-, and U-shaped fin structures have been implemented. However, their designs are not flexible, and high parasitic capacitances have been observed between the bottom source / drain contacts (CR) and the gate.

[0016] Although reduced capacitance has been observed in devices with H-shaped 2D fin structures, their design is not flexible for VFET devices containing only one fin structure (fin=1) or having three or more fin structures (fin>3). Therefore, embodiments of the present disclosure provide VFET devices and methods for fabricating the same with cross-linked fin arrangements for devices with a number of fins greater than one (fin>1) and single fin arrangements for single-fin devices (fin=1). The proposed cross-link configurations are based on the W eff This can reduce the parasitic capacitance of the device while improving the capacitance and providing flexibility in device design.

[0017] As used herein, the term crosslink can refer to a shape having two or more vertical segments (or regions) connected or linked by a horizontal segment.

[0018] Embodiments of the present disclosure provide a semiconductor structure that includes a combination of a first vertical fin structure extending vertically from a semiconductor substrate having a cross-link architecture and a second vertical fin structure extending vertically from a semiconductor substrate having a single fin architecture. eff This can enable simultaneous fabrication of cross-link structures and single fin structures with desirable parameters (e.g., thickness, width, etc.) that enable increased power dissipation and reduced parasitic capacitance, which in turn can improve the overall performance of the VFET device. Embodiments by which a VFET device with a cross-link fin arrangement can be formed are described in detail below with reference to Figures 1A-11C of the accompanying drawings.

[0019] 1A, a cross-sectional view of a semiconductor structure 100 along line AA at an initial step in a fin patterning process is shown, in accordance with one embodiment of the present disclosure. In this embodiment, FIG. 1B is a top view of the semiconductor structure.

[0020] Known semiconductor fabrication processes have been used to form a semiconductor structure 100 having a semiconductor substrate 120 and a hard mask layer 140 on the semiconductor substrate 120. The various elements forming the semiconductor structure 100 extend along a first axis (e.g., the X-axis) to define a width dimension and extend along a second axis (e.g., the Y-axis) perpendicular to the X-axis to define a height (or thickness) dimension. Although not specifically shown, the various elements forming the semiconductor structure 100 also extend along a third axis (e.g., the Z-axis) perpendicular to the first and second axes to define a depth dimension.

[0021] The semiconductor substrate 120 may be any suitable substrate material, such as, for example, single crystal silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), a III-V compound semiconductor, a II-VI compound semiconductor, or a semiconductor-on-insulator (SOI) substrate. In some embodiments, the semiconductor substrate 120 includes a buried oxide layer (not shown). Typically, the semiconductor substrate 120 may be about several hundred microns thick. For example, the semiconductor substrate 120 may include a thickness ranging from about 0.5 μm to about 75 μm.

[0022] The hard mask layer 140 can be a dielectric material, such as silicon dioxide, silicon nitride, silicon carbide, or a combination of such materials forming a multilayer hard mask. The hard mask layer 140 can be deposited by any suitable deposition method known in the art. As known to those skilled in the art, the hard mask layer 140 is sometimes referred to as a "fin hard mask." The thickness of the hard mask layer 140 can vary from about 10 nm to about 200 nm, and ranges therebetween, although thicknesses less than 10 nm and greater than 200 nm are acceptable.

[0023] 2A, there is shown a cross-sectional view of semiconductor structure 100 along line AA after forming a first array of mandrels (hereinafter "first mandrels") 210 and first sidewall image transfer (SIT) spacers 230, in accordance with one embodiment of the present disclosure. In this embodiment, FIG. 2B is a top view of semiconductor structure 100.

[0024] In this embodiment, first mandrels 210 are formed on hard mask layer 140. For purposes of illustration only, and not intended to be limiting, a limited number of mandrel structures (i.e., first mandrels 210) are depicted in the figures, and one skilled in the art will appreciate that any number of mandrel structures can be formed in semiconductor structure 100 to meet design requirements.

[0025] First mandrels 210 may be formed from any of several known semiconductor materials, such as, for example, polycrystalline silicon (Si) or polycrystalline silicon-germanium (SiGe). The first semiconductor material (not shown) may be deposited and then patterned to form first mandrels 210. The first semiconductor material forming first mandrels 210 may be deposited by any suitable technique known in the art, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or plasma-enhanced chemical vapor deposition (PECVD). However, it should be noted that other materials may be used to form first mandrels 210, as long as they are etch-selective to the sidewall spacers subsequently formed thereon. The shape of first mandrels 210 may have a nearly vertical etch slope or a nearly vertical contact angle.

[0026] The first semiconductor material is then lithographically patterned to form first mandrels 210. As known to those skilled in the art, patterning the first semiconductor material to form first mandrels 210 involves exposing a photoresist (not shown) to light and transferring the pattern of the exposed photoresist into the first semiconductor material. After patterning, the width of the resulting first mandrels 210 can vary from about 10 nm to about 100 nm and ranges therebetween, although widths less than 10 nm and greater than 100 nm are acceptable.

[0027] Subsequently, a layer of dielectric material (not shown) can be conformally deposited on the semiconductor structure 100. A directional etching process, such as reactive ion etching (RIE), can be performed on the semiconductor structure 100 to remove portions of the dielectric material from the hard mask layer 140 and the top surfaces of the first mandrels 210. As shown, after the etching process, portions of the dielectric material remain along opposing sidewalls of the first mandrels 210, forming the first SIT spacers 230.

[0028] Etching generally refers to the removal of material from a substrate (or structures formed on the substrate) and is often performed with a mask in place to selectively remove material from certain areas of the substrate while leaving other areas unaffected. Generally, there are two categories of etching: (i) wet etching and (ii) dry etching. Wet etching is performed using solvents (e.g., acids) that may be chosen for their ability to selectively dissolve a given material (e.g., oxide) and leave another material (e.g., polysilicon) relatively intact. This ability to selectively etch a given material is fundamental to many semiconductor manufacturing processes. Wet etching generally isotropically etches homogeneous materials (e.g., oxides), but can also anisotropically etch single-crystalline materials (e.g., silicon wafers). Dry etching can be performed using plasma. Plasma systems can operate in several modes by adjusting the plasma parameters. Conventional plasma etching generates energetic, neutrally charged free radicals, which react on the wafer surface. The process is isotropic because neutral particles attack the wafer from all angles. Ion milling or sputter etching bombard the wafer with energetic ions of a noble gas that approach the wafer from roughly one direction, making the process highly anisotropic. RIE operates under conditions intermediate between sputtering and plasma etching and can be used to create deep, narrow features such as shallow trench isolation (STI) trenches.

[0029] Additionally, first mandrels 210 and SIT spacers 230 each include a material that allows first mandrels 210 to be selectively removed relative to SIT spacers 230. As described in more detail below, SIT spacers 230 define a fin pattern that may then ultimately be transferred to the underlying semiconductor substrate 120.

[0030] Any suitable dielectric material can be used to form the first SIT spacers 230. For example, suitable dielectric materials for forming the SIT spacers 230 can include silicon dioxide (SiO), oxygen-doped silicon carbide (SiCO), or similar dielectric materials. As previously mentioned, the dielectric material forming the first SIT spacers 230 should include a material that allows the first mandrels 210 to be selectively etched to avoid erosion of the first SIT spacers 230. The dielectric material forming the first SIT spacers 230 is deposited using a conformal deposition technique, such as, for example, ALD, or other suitable deposition technique. According to one embodiment, the SIT spacers 230 can have a width that varies from about 5 nm to about 50 nm.

[0031] 3A, there is shown a cross-sectional view of the semiconductor structure 100 after depositing a second semiconductor material 310, in accordance with one embodiment of the present disclosure. In this embodiment, FIG. 3B is a side view of the semiconductor structure 100 along the Y-axis, and FIG. 3C is a top view of the semiconductor structure 100.

[0032] The second semiconductor material 310 may be formed using similar steps and the same or similar semiconductor materials as the first semiconductor material (not shown) that forms the first mandrels 210. After deposition of the second semiconductor material 310, a planarization process, such as chemical mechanical polishing (CMP), may be performed on the semiconductor structure 100.

[0033] 4A, there is shown a cross-sectional view of semiconductor structure 100 along line AA after recessing second semiconductor material 310, in accordance with one embodiment of the present disclosure. In this embodiment, FIG. 4B is a side view of semiconductor structure 100 along line BB, and FIG. 4C is a top view of semiconductor structure 100.

[0034] In this embodiment, the second semiconductor material 310 and the first mandrels 210 are recessed relative to the exposed top ends of the first SIT spacers 230, as can be seen in Figures 4A and 4C. Any suitable etching technique, such as RIE, can be used to recess the second semiconductor material 310 and the first mandrels 210.

[0035] 5A, a cross-sectional view of semiconductor structure 100 along line AA is shown after patterning second semiconductor material 310 (FIGS. 4A-4C) in accordance with one embodiment of the present disclosure. In this embodiment, FIG. 5B is a side view of semiconductor structure 100 along line BB, and FIG. 5C is a top view of semiconductor structure 100.

[0036] In this embodiment, a patterning process is performed on the second semiconductor material 310 (FIGS. 4A-4C) to form a second array of mandrels (hereinafter "second mandrels") 510 on the semiconductor structure 100. As depicted in FIGS. 5A and 5C, the second mandrels 510 are formed on the outer sidewalls of the first SIT spacers 230. The inner sidewalls of the first SIT spacers 230 are separated by the first mandrels 210.

[0037] Similar to the first mandrels 210, the process of patterning the second semiconductor material 310 (FIGS. 4A-4C) to form the second mandrels 510 consists of steps well known in the art and generally includes forming a pattern on a photoresist layer (not shown) that is transferred to a patterned hard mask (not shown) and used to pattern the underlying semiconductor material 310 (FIGS. 4A-4C) by any suitable etching technique (e.g., RIE).

[0038] 6A, there is shown a cross-sectional view of the semiconductor structure 100 along line AA after forming second SIT spacers 620 in accordance with one embodiment of the present disclosure. In this embodiment, FIG. 6B is a side view of the semiconductor structure 100 along line BB, and FIG. 6C is a top view of the semiconductor structure 100.

[0039] The second SIT spacers 620 are formed by selectively depositing a second spacer material over the first semiconductor mandrel material (e.g., Si or SiGe) that forms the first SIT spacers 230. However, the growth of the second spacer material does not occur over other materials in the semiconductor structure 100, such as the first SIT spacers 230. After the selective growth of the second spacer material, the top portions of the second spacer material can be removed by anisotropic RIE.

[0040] Portions of the second spacer material perpendicular to the hard mask layer 140 remain on the opposing (lateral) sidewalls of the first mandrels 210, as shown in FIG. 6C , and the second mandrels 510, as shown in FIGS. 6B and 6C . In this embodiment, the second spacer material forming the second SIT spacers 620 comprises a different material than the first spacer material forming the first SIT spacers 230. For example, in one embodiment, the second spacer material forming the second SIT spacers 620 comprises titanium (Ti). By forming the second SIT spacers 620 using a spacer material different from that used to form the first SIT spacers 230, regions of the second SIT spacers 620 that are undesirable for design purposes can be selectively removed without damaging the adjacent (desired) remaining regions of the first SIT spacers 230 and second SIT spacers 620. As will be described in more detail below, the second SIT spacers 620 can be selectively removed to form a desired cross-link fin pattern that can then be transferred to the semiconductor substrate 120 .

[0041] 6C (i.e., a top view of semiconductor structure 100), first SIT spacers 230 cover opposing sidewalls of first mandrel 210 and second mandrel 510 in the vertical direction (y-direction), while second SIT spacers 620 cover opposing sidewalls of first mandrel 210 and second mandrel 510 in the horizontal direction (x-direction). In other words, the vertical and horizontal surfaces of each of first mandrel 210 and second mandrel 510 are surrounded by a set of first SIT spacers 230 (x-direction) and a set of second SIT spacers 620 (y-direction), respectively.

[0042] It should be apparent that the width of the first SIT spacer 230 and the width of the second SIT spacer 620 can be selected to be the same as the desired width of the final fin feature (taking into account any etch film erosion factors). Thus, the first SIT spacer 230 and the second SIT spacer are formed on the vertical sidewalls of the first mandrel 210 and the second mandrel 510 to determine the final pattern width and tolerance of the components formed in the semiconductor substrate 120.

[0043] 7A, there is shown a cross-sectional view of semiconductor structure 100 along line AA after forming an organic planarization layer (OPL) 710 and a via opening, in accordance with one embodiment of the present disclosure. In this embodiment, FIG. 7B is a side view of semiconductor structure 100 along line BB, and FIG. 7C is a top view of semiconductor structure 100.

[0044] As shown in FIGS. 7A-7B , OPL 710 is deposited on semiconductor structure 100 substantially covering first mandrel 210 and second mandrel 510. OPL 710 may be formed from any organic planarization material that can effectively prevent damage to underlying layers during subsequent etching processes. According to one embodiment, OPL 710 enables better depth control during subsequent via patterning processes. OPL 710 may include, but is not necessarily limited to, organic polymers containing C, H, and N. According to one embodiment, the OPL material may be free of silicon (Si). According to another embodiment, the OPL material may be free of Si and fluorine (F). As defined herein, a material is free of an atomic element if the level of the atomic element in the material is at or below trace levels detectable by analytical methods available in the art. Non-limiting examples of OPL materials that form OPL710 include JSR HM8006, JSR HM8014, AZ UM10M2, Shin Etsu ODL102, or other similar commercially available materials. OPL710 can be deposited, for example, by spin coating followed by a planarization process such as CMP.

[0045] 7A-7C, as shown, semiconductor structure 100 is subjected to a lithography process followed by an etching process to etch OPL 710 to form via opening 730. In some embodiments, etching of OPL 720 can be performed by OPL RIE, for example, with trace point detection. As can be seen in FIGS. 7B and 7C, via opening 730 formed in semiconductor structure 100 exposed selected regions or portions of second SIT spacer 620, which are subsequently removed, as described in more detail below.

[0046] The location of the via opening 730 is selected based on the desired fin shape. According to embodiments of the present disclosure, the proposed combination of cross-link and single fin structure can be achieved in the semiconductor structure 100 by selectively removing portions of the second SIT spacer 620.

[0047] 8A, there is shown a cross-sectional view of the semiconductor structure 100 along line AA after selectively removing a portion of the second SIT spacer 620, in accordance with one embodiment of the present disclosure. In this embodiment, FIG. 8B is a side view of the semiconductor structure 100 along line BB, and FIG. 8C is a top view of the semiconductor structure 100.

[0048] In this embodiment, the via opening 730 allows for selective removal of portions of the second SIT spacer 620 that are key to achieving the cross-link morphology of the subsequently formed fin structure. Because the first SIT spacer 230 and the second SIT spacer 620 are formed from different materials, portions of the second SIT spacer 620 that do not meet design requirements (i.e., unwanted portions) can be selectively removed without damaging the first SIT spacer 230. Any suitable isotropic etching process can be used to remove selected portions of the SIT spacer 620, including, for example, SC1. Note that for simplicity of illustration, the OPL 710 is not shown in FIG. 8C.

[0049] 9A, there is shown a cross-sectional view of semiconductor structure 100 along line AA after removing OPL 710, first mandrel 210, and second mandrel 510, in accordance with one embodiment of the present disclosure. In this embodiment, FIG. 9B is a side view of semiconductor structure 100 along line BB, and FIG. 9C is a top view of semiconductor structure 100.

[0050] First, OPL 710 (FIGS. 8A-8C) is removed from semiconductor structure 100. Exemplary techniques suitable for removing OPL 710 (FIGS. 8A-8C) include, but are not limited to, oxygen plasma, nitrogen plasma, hydrogen plasma, or other carbon strip or ashing processes that cause minimal or no damage to the underlying layers.

[0051] Subsequently, as shown, the first mandrel 210 and the second mandrel 510 are selectively removed relative to the first SIT spacer 230 and the second SIT spacer 620. Removal of the first mandrel 210 and the second mandrel 510 should not compromise the integrity of the first SIT spacer 230 and the second SIT spacer 620. In one embodiment, the first mandrel 210 and the second mandrel 510 can be removed using typical standard cleaning techniques, including ammonium hydroxide, hydrogen peroxide, hot ammonia, etc., without trimming the first SIT spacer 230 and the second SIT spacer 620.

[0052] According to one embodiment, the first SIT spacers 230 and the second SIT spacers 620 are then used as a hard mask such that an anisotropic etching process transfers the pattern defined by the first SIT spacers 230 and the second SIT spacers 620 into the underlying dielectric layer (i.e., hard mask layer 140).

[0053] 10A, there is shown a cross-sectional view of semiconductor structure 100 along line AA after transferring a pattern defined by first SIT spacers 230 and second SIT spacers 620 to hard mask layer 140, in accordance with one embodiment of the present disclosure. In this embodiment, FIG. 10B is a side view of semiconductor structure 100 along line BB, and FIG. 10C is a top view of semiconductor structure 100.

[0054] As previously described, an anisotropic etching process can be performed on the semiconductor structure 100 to transfer the pattern defined by the first SIT spacers 230 and the second SIT spacers 620 to the underlying hard mask layer 140, as shown in FIG. 10C. Suitable anisotropic etching processes include, for example, RIE. As can be appreciated, the first SIT spacers 230 and the second SIT spacers 620 define a cross-link pattern that is transferred to the hard mask layer 140 and ultimately to the semiconductor substrate 120, forming the proposed combination of cross-links and a single fin structure shown in FIGS. 11A-11C. The resulting fin structure can include vertical and horizontal segments having widths substantially equal to the widths of the first SIT spacers 230 and the second SIT spacers 620. Stated differently, the first SIT spacers 230 and the second SIT spacers 620 define the widths of the vertical and horizontal regions of the fin structure.

[0055] 11A, there is shown a cross-sectional view of the semiconductor structure 100 along line AA after forming a plurality of fin structures (hereinafter "fin structures") 1120, in accordance with one embodiment of the present disclosure. In this embodiment, FIG. 11B is a side view of the semiconductor structure 100 along line BB, and FIG. 11C is a top view of the semiconductor structure 100.

[0056] According to one embodiment, the patterned hard mask layer 140 is transferred to the semiconductor substrate 120 by an anisotropic etching process, such as RIE, to form the fin structures 1120. The depth of the anisotropic etching process can depend on the final function of the semiconductor structure 100. As can be seen in FIG. 11C, the resulting fin structures 1120 include a combination of cross-link and single architectures. Each of the fin structures 1120 having a cross-link configuration can include a first region extending vertically (or perpendicularly) from the semiconductor substrate 120, which is parallel to a second region of the fin structure 1120 that also extends vertically from the semiconductor substrate 120, and the first and second regions of the (cross-link) fin structure 1120 are connected by a third (lateral) region of the fin structure 1120, as shown in FIG. 11C. The cross-link fin configuration can be repeated as desired within the semiconductor structure 100. Therefore, the proposed embodiment can be applied to single-fin devices as well as multi-fin devices.

[0057] It should be noted that any number of single fin structures and cross-link fin structures 1120 can be formed within the semiconductor structure 100 applicable to meet a particular device design. In some embodiments, as shown, two or more H-shaped fin structures 1120 can be formed consecutively within the semiconductor structure 100. As previously mentioned, the proposed method is based on the W eff The present invention provides a flexible device design that allows for simultaneous formation of a combination of single fin structures and cross-linked fin structures 1120 that can improve performance and reduce parasitic capacitance.

[0058] After forming the fin structure 1120, the first SIT spacers 230 and the second SIT spacers 620 may then be selectively removed by an etching technique, which may include any suitable wet or dry etching technique. The etching of the first SIT spacers 230 and the second SIT spacers 620 should not compromise the integrity of the fin structure 1120. It should be noted that for simplicity of illustration, the semiconductor substrate 120 is not shown in FIG. 11C. As shown, it can be seen that a remaining portion of the hard mask layer 140 remains on the fin structure 1120.

[0059] Thus, according to an embodiment of the present disclosure, the final semiconductor structure 100 may include, for example, a first fin structure 1120 on a top surface of the semiconductor substrate 120, as shown in Figures 11A-11C, which includes a first vertical region extending perpendicular to the top surface of the semiconductor substrate 120, a second vertical region extending perpendicular to the top surface of the semiconductor substrate 120 and spaced laterally from the first vertical region, and a first horizontal region extending between and connecting the first and second vertical regions and parallel to the top surface of the semiconductor substrate 120.

[0060] 11A-11C, the final semiconductor structure 100 can further include, for example, a second fin structure 1120 on the top surface of the semiconductor substrate 120, the second fin structure 1120 including a third vertical region extending perpendicular to the top surface of the substrate, a fourth vertical region extending perpendicular to the top surface of the substrate, and a fifth vertical region extending perpendicular to the top surface of the substrate, the third vertical region being laterally spaced apart from the fourth vertical region and the fourth vertical region being laterally spaced apart from the fourth vertical region, and the second fin structure 1120 including a second horizontal region extending between and connecting the third and fourth vertical regions and parallel to the top surface of the semiconductor substrate 120, and a third horizontal region extending between and connecting the fourth and fifth vertical regions and parallel to the top surface of the substrate. It should be noted that the proposed method can be used to form fin structures with any number of vertical regions connected by horizontal regions. This configuration can be repeated as needed for any two or more adjacent fin structures (i.e., number of fins ≥ 2).

[0061] The final semiconductor structure 100 may further include a third fin structure 1120, which may include a single fin structure, as shown in Figures 11A-11C. It should be noted that the proposed method may be used to form any desired number of single fin structures in combination with any desired number of cross-linked fin structures.

[0062] 1A-11C illustrate the formation of VFETs having cross-linked fin structures in particular numbers, orientations, positions, and / or combinations thereof, it will be understood that any number, orientation, position, and combination of cross-linked fin structures can be formed in accordance with embodiments of the present disclosure, including substantially H-shaped fin structures.

[0063] Accordingly, embodiments of the present disclosure provide a fin structure including n vertical regions extending perpendicular to a top surface of a semiconductor substrate and n-1 horizontal regions extending between and connecting each of the n vertical regions and parallel to the top surface of the semiconductor substrate, where n≧1. In embodiments where n=1, the fin structure is a single fin structure, and in embodiments where n>1, the fin structure is a cross-link fin structure. Any combination of fin structures can be formed in a VFET device according to the foregoing embodiments.

[0064] The aforementioned methods are used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by manufacturers in raw wafer form (i.e., a single wafer containing multiple unpackaged chips) as bare dies, or in packaged form. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads affixed to a motherboard or other higher-level carrier) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or embedded interconnects). In either case, the chips are integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing integrated circuit chips, ranging from toys and other low-end applications to sophisticated computer products with displays, keyboards, other input devices, and central processing units.

[0065] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly dictates otherwise. As used herein, it can be further understood that the terms "comprises" and / or "comprising" specify the presence of stated features, integers, steps, processes, elements, or components, or all of these, but do not exclude the presence or addition of one or more other features, integers, steps, processes, elements, components, or groups thereof, or all of these. "Optional" or "optionally" means that the subsequently described event or circumstance may or may not occur, and that the description includes cases where the event occurs and cases where it does not occur.

[0066] Spatially relative terms such as "inside," "outside," "below," "below," "lower," "upper," "top," "bottom," and the like are used herein for ease of description to describe the relationship of one element or feature to another, as shown in the figures. Spatially relative terms may be intended to encompass various orientations of the device during use or operation in addition to the orientation shown in the figures. For example, if a device in the figures is turned over, elements described as "below" or "below" other elements or features would be oriented "above" the other elements or features. Thus, the example term "below" can encompass both an upward and downward orientation. The device may be oriented otherwise (rotated 90 degrees or at another orientation), and the spatially relative descriptors used herein would be interpreted accordingly.

[0067] Approximate terms used throughout this specification and claims may be applied to modify any quantitative expression that can vary within acceptable limits without resulting in a change in the relevant basic function. Thus, values ​​modified by terms such as "about," "approximately," and "substantially" should not be limited to the exact value specified. In at least some instances, approximation language may correspond to the precision of the instrument used to measure the value. Throughout this specification and claims, range limitations may be combined and / or interchanged, and such ranges are specified and include all subranges contained therein unless the context or language dictates otherwise. "Approximately" applied to a particular value in a range applies to both values ​​and may indicate + / - 10% of the stated value, unless otherwise dependent on the precision of the instrument used to measure the values. As used herein, the term "substantially H-shaped" may refer to a shape having three major line segments in the shape of the letter "H," but with some variation in the shape of the segments, the number of minor line segments, or both.

[0068] The description of various embodiments of the present invention has been presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications or technical improvements to technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. a semiconductor substrate having a top surface; a fin structure on the top surface of the semiconductor substrate; the fin structure includes three vertical regions aligned vertically on the top surface of the semiconductor substrate, two horizontal regions extending horizontally between a central vertical region and two vertical regions on either side of the three vertical regions to connect the vertical regions at their intermediate portions, and another single vertical region not connected to the horizontal regions.

2. 2. The semiconductor structure of claim 1, wherein said fin structure further comprises two vertical regions extending vertically side by side on said top surface of said semiconductor substrate, and one horizontal region extending horizontally between said two vertical regions and connecting said vertical regions at an intermediate portion of said vertical regions.

3. forming a hard mask layer on a top surface of a semiconductor substrate; transferring a pattern into the hard mask layer defining a plurality of fin structures; forming the plurality of fin structures on the top surface of the semiconductor substrate according to the transferred pattern; the plurality of fin structures include one or more vertical regions extending in a direction perpendicular to the top surface of the semiconductor substrate and parallel to one another, and at least two of the one or more vertical regions are connected by a horizontal region extending between the at least two vertical regions in a direction parallel to the top surface of the semiconductor substrate; forming a first array of mandrels on the hard mask layer; forming a second array of mandrels on the hard mask layer; forming first sidewall image transfer spacers on opposing vertical sidewalls of each of the first array of mandrels and the second array of mandrels; forming second sidewall image transfer spacers on opposing lateral sidewalls of each of the first array of mandrels and the second array of mandrels; Further comprising: the first sidewall image transfer spacers comprise SiCO and the second sidewall image transfer spacers comprise Ti; A method for forming a semiconductor structure.

4. The method of claim 3 , wherein the two or more vertical regions connected by the horizontal region define a cross-link fin architecture within the semiconductor structure.

5. The method of claim 3 , wherein at least one of the one or more vertical regions not connected by the horizontal region defines a single fin architecture.

6. forming an organic planarization layer substantially covering the first array of mandrels, the first sidewall image transfer spacers, the second array of mandrels, and the second sidewall image transfer spacers; Etching the organic planarization layer to form via openings over selected areas of the second sidewall image-transferred spacers; The method of claim 3 further comprising:

7. removing a portion of the second sidewall image-transferred spacer disposed on the selected area through the via opening; The method of claim 6 further comprising:

8. removing the organic planarization layer; The method of claim 6 further comprising:

9. removing the first array of mandrels and the second array of mandrels selectively relative to the first sidewall image transfer spacers and the second sidewall image transfer spacers; The method of claim 6 further comprising:

10. 4. The method of claim 3, further comprising patterning the hard mask layer, wherein the patterning comprises transferring a pattern defined by the first sidewall image transfer spacers and the second sidewall image transfer spacers into the hard mask layer.

11. removing the first sidewall image transfer spacer and the second sidewall image transfer spacer; The method of claim 9 further comprising:

12. etching the top surface of the semiconductor substrate based on the patterned hard mask layer to form the plurality of fin structures; The method of claim 9 further comprising:

13. 10. The method of claim 9, wherein the pattern defined by the first sidewall image-transferred spacers and the second sidewall image-transferred spacers comprises a combination of single fin features and cross-linked fin features.

14. forming a hard mask layer on a top surface of a semiconductor substrate; forming a first array of mandrels on the hard mask layer; forming first sidewall image transfer spacers on opposing vertical sidewalls of each mandrel in the first array of mandrels; forming a second array of mandrels on the hard mask layer, each mandrel in the second array of mandrels being laterally spaced from each mandrel in the first array of mandrels by the first sidewall image transfer spacers; forming second sidewall image transfer spacers on laterally opposed sidewalls of the first array of mandrels and the second array of mandrels; selectively removing portions of the second sidewall image-transferred spacers to define a cross-link fin pattern; 1. A method of forming a semiconductor structure, comprising:

15. Selectively removing the portion of the second sidewall image transferred spacers includes: forming an organic planarization layer substantially covering the first array of mandrels, the first sidewall image transfer spacers, the second array of mandrels, and the second sidewall image transfer spacers; Etching the organic planarization layer to form via openings over selected areas of the second sidewall image-transferred spacers; removing the portion of the second sidewall image-transferred spacer disposed on the selected area through the via opening; 15. The method of claim 14, comprising:

16. 15. The method of claim 14, further comprising transferring a cross-link fin pattern into the hard mask layer to form a plurality of fin structures including one or more vertical regions extending in a direction perpendicular to the top surface of the semiconductor substrate and parallel to one another, wherein at least two of the one or more vertical regions are connected by a horizontal region extending between the at least two vertical regions in a direction parallel to the top surface of the semiconductor substrate.

17. 17. The method of claim 16, wherein the at least two vertical regions connected by the horizontal region define a cross-link fin architecture within the semiconductor structure.

18. The method of claim 16 , wherein at least one of the one or more vertical regions not connected by the horizontal region defines a single fin architecture.

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