Schottky Diode

Abstract

To provide Schottky diodes suitable for use in thin and / or flexible electronics.SOLUTION: A Schottky diode includes: a first electrode 2; a second electrode 5; and a body 4 of a semiconducting material, which is connected to the first electrode at a first interface 42 and connected to the second electrode at a second interface 45. The first interface includes a first planar region 421 lying in a first plane P1, and the first electrode has a first projection onto the first plane in a first direction D1 normal to the first plane. The second interface includes a second planar region 452 lying in a second plane P2, and the second electrode has a second projection onto the first plane in the first direction. At least a part of the second projection lies outside the first projection. The second planar region is offset from the first planar region in the first direction, and one of the first interface and the second interface provides a Schottky contact.SELECTED DRAWING: Figure 1(a)

Description

[Technical Field]

[0001] The present invention relates to a Schottky diode and a method for fabricating the same, particularly but not exclusively. However, certain embodiments of the present invention are suitable for incorporation into thin and / or flexible electronic circuits. and certain embodiments relate to Schottky diodes for such or other applications. Thin-film Schottky diodes for semiconductors. [Background technology]

[0002] Schottky diodes are well-known electronic components, typically provides very fast switching from conducting to non-conducting state, hence the Schottky Diodes are particularly good at rectifying high frequency signals. Schottky diodes are also Cards are also well known for use in many other electronic applications and circuit configurations. are.

[0003] Schottky diodes are divided either laterally or vertically by the semiconductor. It has two conductive electrodes (one Schottky electrode and one Ohmic electrode) that are spaced apart. In flexible electronic circuits, several semiconductors, including metal oxide semiconductors and organic semiconductors, are used. Schottky diodes have been demonstrated using different material systems. A lateral diode is generally made up of parallel plate conductors separated by a semiconductor layer. It consists of two electrodes in the same plane, covered by a semiconductor.

[0004] The Schottky barrier height can be controlled by adjusting the work function of the Schottky electrode and the Fermi level of the semiconductor. This is achieved by optimizing the difference between the Schottky electrodes. Through the selection of conductors and / or by changing the semiconductor material (oxygen content in the case of metal oxides) This can be achieved through the control of the Fermi energy by

[0005] In a vertical diode configuration, the challenge is to create a diode with a semiconductor sandwiched between metal contacts. At the metal-semiconductor interface, achieving stable and reproducible barrier heights is central. Variations occur due to surface defects, and these variations affect the threshold voltage, breakdown voltage, and RC time constant. Further major developments in metal oxide semiconductor vertical stacks have been Problems are caused by oxygen reduction. For example, when making an ohmic contact on the top surface, To extract the metal oxide, a conductor is usually chosen that locally reduces the metal oxide. If the conductor is too thin and / or if the oxygen content of the metal oxide semiconductor is too low This results in a conductive path to the Schottky electrode, leading to premature device failure. There is a possibility that it may leak.

[0006] The lateral diode structure is formed by a Schottky contact through the semiconductor from the ohmic contact. Provides improved control over the current path to the contact. Lateral separation of the contacts This is the primary controlling factor, and therefore the influence of the semiconductor thickness or its oxygen content is small. However, in the case of lateral diodes, etching selectivity issues arise between Schottky and ohmic The choice of two different metals for the electrodes / contacts may be constrained. Summary of the Invention [Problem to be solved by the invention]

[0007] Certain embodiments of the present invention address at least one of the problems associated with the prior art. Certain embodiments are directed to thin and / or flat presents Schottky diodes suitable for use in flexible electronics. In particular embodiments, a thin film Schottky diode is provided. Certain embodiments provide a method for fabricating a Schottky diode. The methods are directed to thin and / or flexible electronic circuits and circuit structures. It is compatible with the techniques used in the fabrication of the components. [Means for solving the problem]

[0008] According to the first aspect of the present invention, a first electrode, a second electrode, and a first interface (junction) connected to the first electrode at (by) the second interface (junction) a Schottky die comprising a body (e.g., a layer) of semiconductor material connected to a second electrode; a first interface having a first flat region lying in a first plane; The electrode has a first protrusion onto the first plane in a first direction perpendicular to the first plane. the second interface includes a second flat region lying in a second plane, and the second electrode is and a second protrusion on the first plane in the direction of The second planar region is outside the first protrusion and is offset (separated, spaced apart) from the first planar region in the first direction, and one of the first interface and the second interface provides a Schottky (rectifying) contact.

[0009] In certain embodiments, for example, relative to a substrate or other support, the first electrode is a lower electrode. In certain alternative embodiments, the first electrode is the lower electrode and the second electrode is the upper electrode. The first electrode is the upper electrode and the second electrode is the lower electrode.

[0010] In certain embodiments, the diode may comprise, for example, supporting electrodes and a body of semiconductor material. The device further comprises a substrate.

[0011] In certain embodiments, the second plane is parallel to the first plane.

[0012] In certain embodiments, the first interface comprises the first flat region.

[0013] In certain embodiments, the second interface comprises the second flat region.

[0014] In certain embodiments, the second protrusion is entirely (completely) outside the first protrusion. a second flat area on the first plane, whereby the second flat area projects onto the first plane in a first direction; The portion is located completely outside the protrusion of the first flat area onto the first plane in the first direction. There is.

[0015] In certain embodiments, a portion of the first protrusion is located inside the second protrusion. do.

[0016] In certain embodiments, the first protrusion is entirely inside the second protrusion. do.

[0017] In certain embodiments, the projection of the second flat region onto the first plane in the first direction The protrusion is completely outside the protrusion of the first flat area onto the first plane in the first direction. exist.

[0018] In certain embodiments, the projection of the first flat region onto the first plane in the first direction A part of the protruding portion is a protrusion of the second flat region onto the first plane in the first direction. It is located inside the part.

[0019] In certain embodiments, the projection of the first flat region onto the first plane in the first direction The entire protrusion is located inside the protrusion of the second flat area onto the first plane in the first direction. exist.

[0020] In certain embodiments, the diode further comprises a substrate, and the first electrode is a is placed on the surface.

[0021] In certain embodiments, the diode comprises a body (e.g., a dielectric layer) of dielectric material. For example, a layer is further provided.

[0022] In a specific embodiment, the dielectric body is arranged to face the second electrode in the first direction. It is disposed so as to be spaced apart (separated) from the first electrode.

[0023] In certain embodiments, the dielectric body includes a window, and the first interface is located inside the window. will be placed in.

[0024] In certain embodiments, the body of semiconductor material at least partially fills the window. a first portion extending laterally from the window (i.e., in a direction parallel to the first plane); and a second portion covering at least a portion of the surface of the dielectric body.

[0025] In certain embodiments, the second electrode is disposed on at least a portion of the second portion of the dielectric body. It is placed so as to cover the part.

[0026] In certain embodiments, the diode comprises at least a portion of a body of semiconductor material and a second a further body (e.g., layer) of dielectric material disposed over at least a portion of the electrode; Further provided with:

[0027] In certain embodiments, a further body of dielectric material covers the entire body of semiconductor material. are arranged as follows.

[0028] In certain embodiments, at least one of the first interface and the second interface is a surface-treated portion of at least one of the electrode, the second electrode, and the body of semiconductor material; Equipped with.

[0029] According to another aspect of the present invention, a first electrode, a second electrode, and a first interface (junction) is connected to the first electrode at (by) the second interface (junction) a Schottky diode comprising a body (e.g., a layer) of semiconductor material connected to two electrodes; A first interface is provided, the first interface comprising a first flat region lying in a first plane, The face has a first protrusion onto the first plane in a first direction perpendicular to the first plane. The second interface comprises a second flat region lying in a second plane, and the second interface is a second protrusion on the first plane in the direction of the first axis, and at least a portion of the second protrusion is The second planar region is outside the first protrusion, the second planar region being offset (separated, spaced apart) from the first planar region in the first direction, and one of the first interface and the second interface providing a Schottky (rectifying) contact.

[0030] According to another aspect of the present invention, a first electrode and a second electrode are connected to the first electrode at (by) a first interface (junction) and connected to the second electrode at (by) a second interface (junction). a Schottky diode comprising a body (e.g., a layer) of semiconductor material connected to two electrodes; a first interface having a first flat region lying in a first plane, a first electrode having a first protrusion onto the first plane in a first direction perpendicular to the first plane, a second interface having a second flat region, and a second electrode having a second protrusion onto the first plane in the first direction, the second protrusion lying completely outside the first protrusion, one of the first and second interfaces providing a Schottky (rectifying) contact, the body having a first side and a second side, the second side being spaced from the first side in the first direction by a thickness of the body, the first flat region being on the first side of the body and the second flat region being on the second side of the body.

[0031] In certain embodiments, the second planar region lies in the first plane.

[0032] In certain embodiments, the second flat region lies in a second plane.

[0033] In certain embodiments, the second plane is parallel to the first plane.

[0034] In certain embodiments, the second plane is spaced apart from the first plane in the first direction. They are separated from each other.

[0035] In certain embodiments, the diode comprises a substrate disposed to support the first electrode. Prepare further.

[0036] In certain embodiments, the body of semiconductor material covers at least a portion of the surface of the first electrode. a first portion disposed over the first electrode and a second portion extending laterally from the first electrode; and a second electrode disposed over at least a portion of the second portion of the body of semiconductor material. can be.

[0037] In certain embodiments, the diode comprises at least a portion of a body of semiconductor material and a second a further body (e.g., a layer) of dielectric material disposed over at least a portion of the electrode; ) is further provided.

[0038] In certain embodiments, a further body of dielectric material covers the entire body of semiconductor material. are arranged as follows.

[0039] In certain embodiments, at least one of the first interface and the second interface is At least one of the electrode, the second electrode, and the body of semiconductor material is treated (e.g., , surface-treated) parts.

[0040] In certain embodiments, the body of semiconductor material comprises a first layer and a second layer, the first boundary The face comprises a portion (eg, a surface portion) of the first layer, and the second interface comprises a portion of the second layer.

[0041] Another aspect of the present invention is a method for manufacturing a semiconductor device comprising: a first electrode, a second electrode, and a first interface (junction) of the first electrode; a semiconductor material connected to one electrode and connected to a second electrode at a second interface (junction) a Schottky diode having a body and a first interface that is substantially flat; , which exists in a first plane, and the second interface is in a first direction perpendicular to the first plane, and offset from the first interface in a second direction parallel to the plane of the first interface. (Can be).

[0042] In certain embodiments, the second interface is offset from the first interface such that a projection of the second interface onto the first plane does not overlap the first interface, in alternative embodiments, it partially overlaps, and in further embodiments, it completely overlaps.

[0043] In certain embodiments, the projection of the second interface onto the first plane is separated from the first interface by a distance of at least 1 nm, although the actual separation will depend on numerous factors, such as the minimum feature size achievable by the manufacturing process / lithography tools, and the desired device parameters as discussed herein.

[0044] In certain embodiments, the second interface is substantially flat and lies in a second plane. The second plane is parallel to the first plane.

[0045] In certain embodiments, the diode further comprises a layer of dielectric material, The body extends from the first interface to the first plane in a direction perpendicular to the first plane. a first portion extending through the layer to a surface of the layer of dielectric material; and a second portion extending in a direction parallel to the first plane.

[0046] In certain embodiments, a second electrode overlaps an end of the second portion and a portion of the surface. become.

[0047] In certain embodiments, the first interface is a first portion of a substantially planar surface of the first electrode. a layer of dielectric material covering at least a second portion of the substantially planar surface of the first electrode; Covers (overlaps) the minutes.

[0048] In certain embodiments, the first interface is a Schottky junction and the second junction In an alternative embodiment, the first interface is an ohmic junction, and in an alternative embodiment, the second interface is a Schottky junction. In a specific embodiment, the first interface is an ohmic junction. one of the first and second interfaces is a Schottky junction, The other one passes through the Schottky diode when the Schottky junction is conducting. A junction is any junction through which an electric current can flow.

[0049] In certain embodiments, the first electrode is made of Au, Ti, Al, Mo, Pt, Pd, Ag , metals such as Cu, Ni, Cr, Ta, W, alloys such as MoNi, MoCr, AlSi Gold, transparent conductive oxides (ITO, IZO, AZO, etc.), metal nitrides such as TiN, Carbon black, carbon nanotubes, carbon materials such as graphene, polyaniline, Selected from a list including conductive polymers or semiconducting materials such as PEDOT:PSS It comprises or consists of a first material.

[0050] In certain embodiments, the second electrode is made of Au, Ti, Al, Mo, Pt, Pd, Ag , metals such as Cu, Ni, Cr, Ta, W, alloys such as MoNi, MoCr, AlSi Gold, transparent conductive oxides (ITO, IZO, AZO, etc.), metal nitrides such as TiN, Carbon black, carbon nanotubes, carbon materials such as graphene, polyaniline, Selected from a list including conductive polymers or semiconducting materials such as PEDOT:PSS It comprises or consists of a second material.

[0051] In certain embodiments, the semiconductor material is a compound semiconductor (GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb, etc.), ZnO, SnO2, NiO, SnO , Cu2O, In2O3, LiZnO, ZnSnO, InSnO(ITO), InZnO (IZO), HflnZnO(HIZO), InGaZnO(IGZO)(GaInZn O, sometimes called GIZO), metal oxides, metal oxynitrides, e.g., Zn xOyNz, inorganic semiconductors (such as amorphous, microcrystalline or nanocrystalline Si), organic semiconductors Conductors (CuPc, pentacene, PTCDA, methylene blue, orange G, rubrene, etc.) ), polymer semiconductors (PEDOT:PSS, POT, P3OT, P3HT, polyaniline, Polycarbazole, etc.), two-dimensional materials (2D materials) (graphene, etc.), MoS2, Ge Chalcogenides such as SbTe and perovskites (SrTiO3, CH3NH3Pb Cl3, H2NCHNH2PbCl3, CsSnl3), and may be doped or A lithography process comprising any of the above semiconductor materials includes a doping gradient and is n-type or p-type. The material may comprise or consist of a material selected from the group consisting of:

[0052] Examples of suitable materials for the dielectric material and / or substrate in certain embodiments are provided below. It is given to you.

[0053] In certain embodiments, at least the semiconductor material and the first and second electrodes are substantially transparent to at least visible light.

[0054] In certain embodiments, the semiconductor material is substantially transparent to at least visible light, while the first electrode and second electrode are at least partially reflective to visible light.

[0055] In certain embodiments, the dielectric material is substantially transparent to at least visible light.

[0056] In certain embodiments, one of the first electrode and the second electrode comprises a body (e.g., a layer) of titanium and a layer comprising or consisting of at least one titanium oxide or suboxide formed on a surface of the titanium body, and the interface providing the Schottky contact comprises or consists of the interface between the body of semiconductor material and the layer comprising or consisting of at least one titanium oxide or suboxide.

[0057] Another aspect of the invention provides a circuit comprising at least a first diode according to any preceding aspect or embodiment and a second diode according to any preceding aspect or embodiment, wherein the first and second planar regions of the first diode are offset (from each other) by a first distance and the first and second planar regions of the second diode are offset by a second distance, the second distance being different from the first distance.

[0058] Another aspect of the present invention is a circuit comprising a diode according to any preceding aspect or embodiment. For example, the circuit or circuit module may include logic gates (e.g., For example, OR gates and AND gates), or inverters (diode-loaded inverters etc.).

[0059] In certain embodiments, the circuit is an integrated circuit.

[0060] Another aspect of the present invention is an electronic device comprising a diode according to any preceding aspect or embodiment. For example, the device may be a source-gate transistor, a It can be a gated transistor, gated diode, etc.

[0061] Another aspect of the present invention is a method for manufacturing a semiconductor device including a first electrode, a second electrode, and a connecting device for connecting the first electrode and the second electrode. and a body of semiconductor material, The method includes forming a first electrode on a first region of a surface of a substrate (or support); forming a body of dielectric material overlying at least a second region of the substrate surface adjacent the region of and arranged over the first electrode, a first portion connected to the first electrode at the interface and a dielectric covering the second region of the substrate surface; a second portion disposed over a portion of the body of semiconductor material; forming a body of semiconductor material on the second portion of the body of semiconductor material at a second interface; and forming a second electrode connected to the body of material.

[0062] In certain embodiments, the first interface has a first protrusion on the substrate surface and the second interface has a second protrusion on the substrate surface, the second protrusion being offset from the first protrusion by a distance.

[0063] In certain embodiments, the method further comprises determining at least one desired characteristic of the diode or The method further includes predetermining the distance according to a parameter.

[0064] In certain embodiments, the first interface comprises a first surface portion of a first electrode, and the method further includes treating the first surface portion of the first electrode prior to forming the body of semiconductor material.

[0065] In certain embodiments, the second interface comprises a surface portion of the body of semiconductor material, and the method further comprises treating the surface portion of the body of semiconductor material before forming the second electrode.

[0066] In certain embodiments, the body of semiconductor material comprises at least two layers.

[0067] In certain embodiments, the method comprises selectively treating at least a portion of the body of semiconductor material. The method further includes implanting (e.g., implanting ions).

[0068] In certain embodiments, the body of dielectric material covers a portion of the first electrode.

[0069] In certain embodiments, the body of dielectric material is such that at least a portion of the first electrode is a window visible (exposed) therethrough, said first portion of the body of semiconductor material It is formed inside the window.

[0070] Another aspect of the present invention is a method for manufacturing a semiconductor device including a first electrode, a second electrode, and a connecting device for connecting the first electrode and the second electrode. and a body of semiconductor material, The method includes forming a first electrode on a first region of a surface of a substrate (or support); a first portion disposed over the first electrode and connected to the first electrode at a first interface; a second portion disposed over a second region of the substrate surface adjacent to the first region; forming a body of semiconductor material comprising a second portion; and forming a second portion of the body of semiconductor material on the second portion. forming a second electrode connected to the body of semiconductor material at the second interface. The features of the above aspects and embodiments of the present invention, together with the corresponding advantages, are described in this aspect. It can be used.

[0071] Another aspect of the present invention is a method for manufacturing a semiconductor device including a first electrode, a second electrode, and a connecting device for connecting the first electrode and the second electrode. and a body of semiconductor material, The method includes forming a first electrode on a first region of a surface of a substrate (or support); forming a second electrode on a second region of the surface separated from the first region by a third region; and a first interface disposed over the first electrode and connected to the first electrode. a first portion connected to the second electrode and disposed over the second electrode and having a second interface therebetween; a second portion connected to the electrode of the first portion and disposed over the third region; and forming a body of semiconductor material comprising a third portion connected to the second portion. Again, the features of the above aspects and embodiments of the present invention, together with the corresponding advantages, are incorporated herein by reference. It can be used for

[0072] In certain embodiments, the first interface comprises a first surface portion of a first electrode, and treating the first surface portion of the first electrode prior to forming the body of semiconductor material. Further includes:

[0073] In certain embodiments, the second interface comprises a first surface portion of a second electrode, treating the first surface portion of the second electrode prior to forming the body of semiconductor material. Further includes:

[0074] In certain embodiments, forming a first electrode and forming a second electrode These are performed simultaneously.

[0075] In certain embodiments, forming a first electrode is performed after forming a second electrode. It is executed before or after

[0076] In certain embodiments of any of the above aspects, the method can further include implanting ions to dope or enhance doping of at least a portion of the body of semiconductor material.

[0077] In certain embodiments of any of the above aspects, the first electrode comprises a body of titanium, and wherein treating the first surface portion of the first electrode comprises treating the first surface portion of the first electrode to form a layer comprising or consisting of at least one titanium oxide or suboxide.

[0078] Another aspect of the present invention provides a method of fabricating a Schottky diode comprising a first electrode, a second electrode, and a body of semiconductor material connecting the first electrode and the second electrode, the method comprising: forming the first electrode having a substantially planar (upper) surface; forming a layer of dielectric material having a substantially planar (upper) surface parallel to the substantially planar surface of the first electrode and having a window through which at least a portion of the planar surface of the first electrode is visible / exposed; forming a body of semiconductor material having a substantially planar (upper) surface, the body comprising a first portion filling the window and a second portion extending laterally from the window to cover a portion of the substantially planar (upper) surface of the layer of dielectric material; and forming a second electrode on the second portion.

[0079] In certain embodiments of any of the above aspects, the method further comprises modifying the work function; and treating the surface of the first electrode to introduce a barrier and / or and / or treating the surface of the second electrode. This process can be performed using implants, plasma treatments, SAM deposition, ALD, ozone UV, laser This may include thermal exposure, thermal annealing, etc. In certain embodiments, the first electrode A process can be chosen that is selective only for

[0080] In certain embodiments, the diode includes an upper dielectric layer. This may allow for selective deposition of the second electrode into the window. It can provide protection to semiconductors both during and after processing.

[0081] In certain embodiments, the first electrode is formed from a first conductive material and the second electrode is , formed from a second conductive material different from the first material.

[0082] Another aspect of the present invention provides a Schottky diode, The code is a first electrode; a second electrode; a body of semiconductor material connected to a first electrode at a first interface and connected to a second electrode at a second interface; The first interface provides the Schottky contact, and the first electrode is connected to the titanium body (e.g., a layer) and a layer comprising or consisting of at least one titanium oxide or suboxide formed on a surface of the titanium body, wherein the first interface comprises or consists of an interface between the body of semiconductor material and the layer comprising or consisting of at least one titanium oxide or suboxide.

[0083] In certain embodiments, the semiconductor material is an oxide semiconductor, such as IGZO.

[0084] Embodiments of certain aspects of the present invention will now be described with reference to the accompanying drawings. [Brief explanation of the drawings]

[0085] [Figure 1] 1 illustrates a thin film electronic device embodying the present invention and formed by a method embodying the present invention; [Figure 2] 2A-2C illustrate a series of process steps of a method suitable for fabricating the device shown in FIG. 1 embodying the present invention. [Figure 3] FIG. 1 illustrates another electronic device embodying the present invention. [Figure 4]FIG. 1 illustrates another electronic device embodying the present invention. [Figure 5] FIG. 1 illustrates another electronic device embodying the present invention. [Figure 6] FIG. 1 illustrates another electronic device embodying the present invention. [Figure 7] FIG. 1 illustrates another electronic device embodying the present invention. [Figure 8] FIG. 1 illustrates another electronic device embodying the present invention. [Figure 9] FIG. 3 shows typical current-voltage characteristics of an electronic device embodying the present invention fabricated according to the sequence of process steps shown in FIG. 2. [Figure 10] 1 is a circuit diagram embodying the present invention; [Figure 11] FIG. 1 illustrates a Schottky diode embodying one aspect of the present invention. [Figure 12] FIG. 1 illustrates another Schottky diode embodying an aspect of the present invention. [Figure 13] FIG. 1 illustrates another Schottky diode embodying an aspect of the present invention. [Figure 14] FIG. 10 illustrates two additional Schottky diodes embodying an embodiment of the present invention. [Figure 15] FIG. 1 illustrates another Schottky diode embodying an aspect of the present invention. [Figure 16] 1A-1C illustrate a method of fabricating a Schottky diode embodying one aspect of the present invention. [Figure 17] 1A-1C illustrate a method of fabricating a Schottky diode embodying one aspect of the present invention. [Figure 18] 1A-1C illustrate a method of fabricating a Schottky diode embodying one aspect of the present invention. [Figure 19] 1A-1C illustrate a method of fabricating a Schottky diode embodying one aspect of the present invention. [Figure 20] FIG. 1 illustrates a portion of a circuit embodying one embodiment of the present invention and incorporating two Schottky diodes. [Figure 21] 1 illustrates a source-gate transistor (SGT) embodying the present invention. [Figure 22] FIG. 1 illustrates a diode OR gate incorporating a Schottky diode embodying an embodiment of the present invention. [Figure 23] FIG. 1 illustrates a diode AND gate incorporating a Schottky diode embodying an aspect of the present invention. [Figure 24] FIG. 1 illustrates a diode-loaded inverter embodying an aspect of the present invention and incorporating a Schottky diode embodying an aspect of the present invention. [Figure 25] FIG. 1 illustrates a Schottky diode embodying another aspect of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0086] Referring now to FIG. 1(a), this shows an insulating FIG. 1 is a side view of a multilayer device on a substrate.

[0087] Layer 2 represents the patterned area of ​​the first electrode. Layer 3 represents the patterned area of ​​the thin film dielectric material. Layer 4 represents the patterned area of ​​thin film semiconductor material. Layer 5 represents the patterned area of ​​thin film semiconductor material. 1 represents the patterned area of ​​the second electrode.

[0088] FIG. 1(b) is a top view of the device layers depicted in FIG. 1(a).

[0089] FIG. 1(c) shows an example of a device including an extended contact area 21 of the first electrode 2. 1 is a top view of the layer extending laterally in the plane of the electrode 2 beyond the overlying semiconductor layer 4. Such contact areas may be used to connect the first electrode 2 to other locations on the substrate 1 or to other locations outside the substrate. During device fabrication, the dielectric material 3 The layer may then be subjected to a process, such as chemical or physical treatment, which may be carried out on the second electrode 5. It is possible to protect any extended contact area of ​​the first electrode 2 from excessive etching. In comparison with purely vertical or lateral approaches, the device of FIG. Compared with the case of the etch selectivity of the two conductor layers, here, the etch selectivity of the two conductor layers is considered to be the This does not affect the choice of materials that can be used for each.

[0090] 1(d) and 1(e) each illustrate a device having a radial shape; Cross-sectional and top views of the device layers. In this example, the first electrode 2 is connected to the second electrode 5. The semiconductor layer 4 is connected between the two electrodes. In d) a circular shape is shown, but the device is a first electrode 2 and a first layer of semiconductor layer 4. a desired offset between the interface 42 of the semiconductor layer 4 with the second electrode 5 and the second interface 45 of the semiconductor layer 4 with the second electrode 5; It can take any shape that gives

[0091] Referring again to FIG. 1, FIG. 1(a) shows one embodiment of the present invention as defined by claim 1. 1 is a schematic cross-sectional view of a Schottky diode embodying an embodiment of the present invention. The diode comprises a first electrode 2, a second electrode 5 and a first interface (which may be a junction or contact). A semiconductor connected to the first electrode at (or by) 42 (sometimes called a contact) and a body 4 of conductive material. The body 4 also has a second interface 452 (or , ) to the second electrode 5. In this example, the first electrode is a Schottky electrode. The first interface 42 provides a Schottky (i.e., rectifying) contact. The electrode 5 is an ohmic electrode so that the second interface 45 provides an ohmic contact. However, in an alternative embodiment, the first electrode 2 is a conductor that provides an ohmic It is reasonable to assume that the first electrode 5 can provide a Schottky electrode. It will be appreciated that those skilled in the art will appreciate that by selecting a conductive material versus a semiconducting material, and / or This can be achieved by appropriately treating the conductive electrode and / or the semiconductor body in the interface region. How do you typically implement Schottky and ohmic contacts? To describe one of the interface regions, we will use the term "ohmic Although the term "contact" has been used, this is actually a second Schottky contact. Any kind of junction or contact that allows a Schottky diode to function It will be understood that this "ohmic contact" may include any type of junction. When a Schottky diode is forward biased, the Schottky diode Low enough or low enough breakdown voltage so as not to significantly impede current flow through the diode When a barrier with a voltage is formed, the Schottky diode functions effectively. In other words, the ohmic contact is similar to the Schottky contact. When the diode is open, the current must flow through the Schottky diode. Not possible.

[0092] In this first embodiment, the first interface 42 lies entirely within the first plane P1. The first electrode 2 is formed of a first flat region 421 and is oriented in a first direction perpendicular to the first plane. The second interface 45 has a protrusion at D1 onto the first plane P1. The second flat area 452 is in the second plane P2, and a further flat area 453 is not in the second plane. Generally, this region 453 is located at the edge of the semiconductor body 4, where the second The second electrode 5 is a portion of the interface 45 between the first conductor 5 and the semiconductor body 4. In this example, has a second protrusion in the first direction D1 onto the first plane P1, the second protrusion being completely outside the first protrusion such that the second electrode 5 does not overlap the first electrode 2 at all. Thus, in this example, the second electrode 5 is laterally separated or laterally offset from the underlying first electrode 2. Specifically, the second flat portion 452 of the second interface 45 is laterally offset from the first flat portion or first flat region 421 (which in this example forms the entirety of the first interface 42) by a distance LO in the figure.

[0093] In this example, the second electrode 5 is also vertically offset or separated from the first electrode 2, and the second flat region 452 is offset (i.e., separated or spaced apart) by a distance S from the first flat region 421 in the first direction D1.

[0094] The device of FIG. 1(a) is formed by a method in which a first electrode 2 is formed on a substrate 1. A layer of dielectric material 3 is then formed over the first electrode 2 and substrate 1, with a window through the dielectric layer exposing an upper portion of the first electrode 2. A layer or body of semiconductor material 4 is then formed over the layer of dielectric material 3, such that the semiconductor material at least partially fills the window, forming a first interface 42 inside the window between the semiconductor material 4 and the first electrode 2. The layer of semiconductor material 4 extends to cover a portion of the upper surface of the dielectric material 3, thus leaving a portion of the semiconductor material 4 laterally away from the window, and therefore at the first interface 42. 42. A second electrode 5 is then applied to the body of semiconductor material 4 and the dielectric layer 3. In this example, the second electrode 5 is formed on the upper surface of the dielectric layer 3. and a portion that is in direct contact with a portion of the upper surface of the body 4 of semiconductor material. The overlapping portion is in contact with the upper surface of the main body 4 and has a second flat surface of the second interface 45. Advantageously, the first flat area 421 and the second flat area 452 are The lateral offset LO between the two can ultimately be precisely controlled by the manufacturing technique. This allows for accurate and precise control of the Schottky diode characteristics.

[0095] In the embodiment of FIG. 1(a), the second plane P2 is parallel to the first plane P1, but alternatively It will be appreciated that in alternative embodiments, the second plane P2 may not be parallel to P1.

[0096] 1(b) and 1(c) are plan views of variations of the embodiment shown in FIG. 1(a). 1 is a diagram illustrating non-overlapping (i.e., Different arrangements of the first and second electrodes 2 and 5 (i.e., laterally and vertically offset) Indicates the location.

[0097] Referring now to Figure 1(d), this is closely related to the embodiment shown in Figure 1(a). Figure 1(e) shows a plan view of the device shown in Figure 1(d). (FIG. 1(d) is a cross-sectional view.) As in the embodiment of FIG. 1(a), the second so that the projection of the electrode 5 is completely outside the projection of the first electrode 2 onto the plane P1, The second electrode 5 is completely laterally offset from the first electrode 2. In this example, The first electrode 2 is circular and the second electrode 5 is annular (i.e., ring-shaped). The second flat area 452 on the beam second interface 45 is at a distance LO from the first flat area 421. .times. ...

[0098] With continued reference to FIG. 1(a), the diagram shows a hologram with laterally and vertically separated electrodes. The present invention also illustrates, by way of example only, a diode configuration in which the bottom electrode is a Schottky capacitor. It will be understood that this is shown as a tact.

[0099] Generally, the operating frequency of a Schottky diode is determined by the RC time constant of the diode. The lateral diode configuration provides the smallest overlap capacitance. It benefits from the resistivity, which reduces the parasitic capacitance compared to the traditional vertical configuration. The overall resistance is reduced while still providing adequate separation between the two conductor contacts. By increasing the overlap of the conductor-semiconductor contacts while retaining the However, the series resistance of the diode and the Schottky-Ohmic There is a trade-off between contact separation (larger separation increases series resistance) This still ensures low parasitic capacitance and tight control of the channel length. This can be overcome by increasing the diode W / L ratio while maintaining the same.

[0100]

number

[0101]

number

[0102] Referring now to Figure 2, Figure 2(a) shows an insulating substrate 1. Figures 2(b) and 2(c) 1A and 1B show a side view and a top view of a substrate 1 completely covered by a layer of conductive material 2. Such complete coverage can be achieved by subtractive deposition techniques, e.g., conventional photolithography. Alternative means of creating the desired area of ​​the conductor layer are described in the present specification. Additive or selective deposition, such as one of the printing techniques mentioned later in this document. FIG. 2(d) shows a further step in which a layer of resist material 6 is applied, e.g. For example, photoresist patterned by photolithography or laser cutting Mechanical cutting by cutting or imprinting or embossing followed by oxygen plating Select part of the conductive layer 2, which is a polymer that has been patterned by Zuma ashing. Alternatively, in certain embodiments, a resist is deposited over the surface (610). Selectively covering portions of the conductor layer with resist material involves applying a resist over the desired area. In certain embodiments, this is achieved by first printing the entire conductive layer onto the material. and then selectively removing the resist material to expose selected areas of the conductor layer. A variety of techniques are used to form at least one layer of resist material. Various resist materials can be utilized in different embodiments of the present invention. These methods for forming at least one layer of resist material include coating (scanning). pin, dip, blade, bar, spray, slot die) or extrusion Suitable resist materials include polyhydroxybutyrate, polymethyl methacrylate, polyvinyl Alcohol, polyvinyl acetate, polyvinylpyrrolidone, polyvinylphenol, polychlorinated Vinyl, polystyrene, polyamide (e.g., nylon), polyhydroxyether, poly Polyurethane, polycarbonate, polysulfone, polyarylate, acrylonitrile butadiene Diene styrene, polyimide, benzocyclobutene (BCB), photoresist, acetic acid 1 -Methoxy-2-propyl (SU-8), polyhydroxybenzylsilsesquioxane ( polyhydroxybenzyl silsesquioxane) (HSQ), Fluorinated polymers, such as PTFE, UV-curable liquid resins (U.S. Pat. No. 6,284,072) (e.g., resins described in), silicones, siloxanes, and parylenes. Resists include Microchem / Microresist, Shipley and N It is commercially available from companies such as anolithosolution Inc.

[0103] In an alternative embodiment, desired areas or portions of the conductor layer are selectively deposited or printed. The area is then covered by applying a resist material to the area. e) the exposed areas 210 of the conductive layer 2 are removed, for example by etching (wet and / or dry etching techniques may be used), ablation and / or milling 2(f) shows a further step in which the level covering area 610 of conductive layer 2 is removed. The resist material 6 may be, for example, a photoresist developer, ablation, oxygen plasma, etc. 2(g) shows the subsequent step of removing the resist material 6 by using FIG. 10 is a side view of layer 2 after it has been removed.

[0104] Figure 2(h) shows a further stage in which a dielectric layer 3 is deposited on layer 2. Figure 2(i) shows the dielectric layer 3. is deposited on the dielectric layer 3 and penetrates the resist, exposing areas of the underlying dielectric layer 3. FIG. 2(j) shows the resist layer 7 patterned to form a window 710. The areas of the dielectric layer 3 exposed through the windows 710 in the insulating layer 7 are then exposed by, for example, etching ( wet and / or dry etching techniques may be used), ablation and and / or a further step of removing the resist material 7 by milling, e.g. After removal by using resist developer, ablation, oxygen plasma, etc. This indicates the next stage.

[0105] Figure 2(k) shows a further stage in which a semiconductor layer 4 is deposited on the dielectric layer 3. 2(d) as described above with reference to FIG. 2(d), the layer of resist material 8 is 8 shows a further step in which a semiconductor layer 4 is selectively deposited (810) over a portion of the semiconductor layer 4. The exposed areas are then removed by, for example, etching (wet and / or dry etching). removal by ablation and / or milling), In a subsequent step, the resist material 8 is applied to the substrate using, for example, a photoresist developer, an abrasive, or the like. The resist is removed by using oxygen plasma, etc. FIG. 1 is a side view of semiconductor layer 4 after material 8 has been removed.

[0106] FIG. 2(n) shows a further step in which a second electrode layer 5 is deposited on the semiconductor layer 4. o) shows a further step, in which the layer of resist material 9 is applied to, for example, a patterned photoresist. Laser cutting or mechanical cutting by imprinting or embossing The polymer was patterned by ablation followed by oxygen plasma ashing. , is deposited (910) to selectively cover a portion of the second electrode layer 5. Alternatively, In certain embodiments, selectively covering portions of the conductor layer with a resist material provides a desired effect. This is achieved by printing a resist material over the rear. In some embodiments, the entire conductor layer is first covered, and then the resist material is selectively removed. In an alternative embodiment, areas of the conductor layer are selectively covered by The desired area or portion can be selectively deposited, printed, or otherwise removed from the area. The exposed areas of the second electrode layer 5 are then covered with a resist material. After that, for example, etching (if wet and / or dry etching techniques are used) In subsequent steps, The resist material 9 may be, for example, a photoresist developer, ablation, oxygen plasma, etc. FIG. 2(p) shows the state after the resist material 9 has been removed. 2(p) is a side view of the second electrode layer 5. Therefore, FIG. 2(p) is a side view of the second electrode layer 5 shown in FIG. 1 shows a Schottky diode having the same overall structure as that described in

[0107] Referring now to FIG. 3, this is a semiconductor device in which a dielectric layer 3 is disposed between a first electrode layer 2 and a semiconductor layer 4. 1 illustrates a device formed by a method embodying the present invention, which method is not a method described above. Steps 2(h), 2(i) and 2(j) are omitted from the method, thereby allowing the device to: It has a simpler structure than the device of FIG. 1 and requires fewer manufacturing steps than the device of FIG. These advantages are due to the above-mentioned properties of the electrode material, which are made possible by the presence of the dielectric layer 3. This can be taken into consideration in exchange for more freedom of choice.

[0108] Referring again to FIG. 3, this is similar in some respects to the embodiment shown in FIG. 1(a). 3, but without the dielectric layer 3 (Schottky diode). The device embodies the aspect defined by claim 20. In the embodiment of FIG. A first electrode 2 is formed on the surface of the substrate 1, and then the first electrode 2 and The first electrode 2 and the substrate 1 are then completely covered with the upper surface of the substrate 1 extending laterally. A body of semiconductor material 4 was formed over the top of the semiconductor material 1. Thus, the body of semiconductor material 4 A first interface 42 is formed between the first electrode 2 and the first flat portion 421. (in this example, on the first electrode 2) or on the end interface portion 422 (generally on the first Then, a part of the semiconductor body 4 and a part of the upper surface of the substrate 1 are A second electrode 5 was formed on the semiconductor body 4 and the substrate 1 so as to cover the portion. By forming the second electrode 5 in this way, a second The second interface 45 is formed by the second flat portion 452 and the further end surface portion 4 In this example, the thickness T4 of the layer of semiconductor material 4 is 1 / 2 times the thickness T 2, and therefore the first flat region 421 and the second flat region 452 are In another example, the thickness of the layer of semiconductor material 4 and The thickness of the layers of the first electrode 2 is not the same, and the first flat area 421 and the second flat area 45 2 do not lie in the same plane. Advantageously, the first flat area 421 and the second flat area 452 A lateral offset LO is provided between the According to the method, precise and strict control of the isolated LO can be achieved, thereby This allows precise control of the Kettke diode characteristics.

[0109] Referring now to Figure 4, this is a diagram of a device formed by a method embodying the present invention. An insulating substrate 1 is provided and is completely covered by a layer of dielectric material 10. Such a layer of dielectric material underlying the device layer is necessary for the device stack from the substrate 1. They can provide a passivation or protective function for semiconductors that may adversely affect device performance. Without this, there is a possibility to increase the choice of materials that can be used for the substrate 1.

[0110] Referring again to FIG. 4, FIG. 4 shows the protrusion of the second electrode 5 onto the plane P1 of the first interface 42. The second electrode 5 is positioned so that its portion is completely outside the projection of the first electrode 2 onto the plane P1. Another embodiment is shown in which the first electrode 2 is offset both vertically and laterally from the first electrode 2. It will be understood that the projection of the second flat area 452 onto the plane P1 is It lies completely outside the upward projection of the first flat area 421 .

[0111] Referring now to FIG. 5, this shows that a further insulating layer 11 is provided on top of layers 3, 4 and 5. Also shown is a device formed by another method embodying the present invention. The semiconductor layer interface is improved and / or the device is deformed to minimize or eliminate the effects of It provides a protective coating to the chair.

[0112] Referring now to FIG. 6(a), this shows a device formed by a method embodying the present invention. The protrusion of the second interface onto the first plane partially overlaps the first interface. Additionally, a device is provided in which the second interface 45 is laterally offset from the first interface 42. FIG. 6(b) shows a device formed by a method embodying the invention. A device is provided in which the projection of the second interface onto the first plane completely overlaps the first interface. The overlap of the lateral interfaces within the device shown in Figures 6(a) and 6(b) This allows for greater control of the resistance and capacitance of the device, thereby increasing the current It affects voltage characteristics, operating frequency, etc.

[0113] Referring again to FIG. 6(a), this embodiment has a protrusion of the second electrode 5 onto the plane P1. partially overlaps the protrusion of the first electrode 2 onto the plane P1 and in fact overlaps the second flat area 4 The protrusion 52 (which is in a first direction onto the plane P1) partially overlaps the first flat area 421. It will be understood that this is an embodiment.

[0114] Referring again to FIG. 6(b), in this particular embodiment, the second electrode 5 on the plane P1 The protrusion of the first electrode 2 partially overlaps the protrusion of the first electrode 2 onto P1, but the first flat area 421 In this example, the second interface is the end surface portion 453, the second The flat region 452 includes a third flat region 454 and a fourth flat region 455. 52, 454 and 455 together completely overlap the first flat area 421. In this example , the second flat area 452 and the fourth flat area 455 are parallel to the plane P2 The third flat area 454 is in a third plane P3 that is also parallel to P1. exists in.

[0115] Referring now to Figure 7, this is a diagram of a device formed by a method embodying the present invention. The (upper) surface 21 of the first electrode 2 has been modified (e.g., by implantation, plasma treatment, Self-assembled monolayers (SAMs), atomic layer deposition (ALD), ozone UV, laser exposure and / or or by thermal annealing) to provide a device. can modify the work function of the electrode and / or introduce a Schottky barrier It is possible to select a surface modification process that is selective only for electrode 1.

[0116] For example, certain embodiments may include a titanium conductive electrode (e.g., layer) and an IGZO or other conductive material according to the present invention. Semiconductors of oxide semiconductors such as any other oxide semiconductors mentioned elsewhere in this specification. A Schottky barrier is formed between the body (e.g., layer). In some embodiments, one or more titanium oxide (e.g., titanium dioxide) layers are deposited thereon prior to deposition of the semiconductor body (e.g., layer). For example, a titanium electrode (e.g., The surface (e.g., upper surface) of the layer (or layer) or a portion of the surface can be modified. In practice, "one or more layers of titanium oxide" refers to a single titanium oxide or titanium suboxide. Composition, or titanium oxide (TiO), titanium trioxide (Ti2O3), titanium dioxide (Ti O2) and one or more titanium suboxides (TiOx, where x is 1-2 or 0-1, e.g. , 0.7 and 1.3), or In other words, it can consist of "one or more layers of titanium oxide" or "oxide". The "titanium oxide layer" comprises or consists of at least one titanium oxide or titanium suboxide. The formation of a titanium oxide layer is well known in the art. temperature, atmospheric composition and / or pressure, and / or plasma or other Therefore, certain embodiments of the present invention may be controlled by applying a stimulus. The method involves first depositing a titanium body (e.g., a layer) on a substrate or other support or structure. By depositing or otherwise forming a conductive electrode (e.g., a Schottky After that, a surface treatment step (e.g., annealing) can be performed. In the etching step, a titanium oxide layer is formed on the surface of the titanium body. The interface between the conductive material and the titanium oxide layer provides a Schottky barrier (contact). a semiconductor material (e.g., an oxide such as IGZO) at least partially overlapping the titanium oxide layer; A body (e.g., layer) of a titanium (or titanium-based semiconductor) is formed. A Schottky barrier comprising a titanium body having a titanium oxide layer formed on the surface of the body. In the diode, the titanium oxide layer is in contact with the semiconductor material and serves as a short circuit. Form a Tokey barrier.

[0117] Reference is now made to Figure 8(a), which shows a device formed by a method embodying the present invention. The (upper) surface 21 of the semiconductor layer 44 is modified (e.g., doped) , implantation, plasma treatment, self-assembled monolayer, atomic layer deposition, ozone UV, laser exposure and and / or by thermal annealing) or by using a material different from that forming the lower portion of the semiconductor layer 43. The device is provided as being formed from a semiconductor material having an upper surface of semiconductor layer 44. As known to those skilled in the art, the semiconductor layer 46 can be doped by a donor material deposited on its surface. For example, the donor material can be deposited on the semiconductor layer 4 before or after the deposition of the second electrode 5. FIG. 8(b) illustrates a device formed by a method embodying the present invention. Devices are provided in which the portion of the (upper) surface of the semiconductor layer 46 in contact with the second electrode 5 is modified (e.g., by doping, implantation, plasma treatment, self-assembled monolayer, atomic layer deposition, ozone UV, laser exposure, and / or thermal annealing) or is formed from a semiconductor material different from the material forming the remainder of the semiconductor layer 45. The portion of the upper surface of the semiconductor layer 46 can be doped by a donor material deposited on its surface, similar to the example described above in connection with FIG. 8(a). The surface modifications described with reference to FIGS. 8(a) and 8(b) allow for control of the Schottky barrier height by tuning the Fermi level of the semiconductor, thereby enabling control of the device characteristics.

[0118] 9 shows typical current-voltage characteristics of an electronic device embodying the present invention formed by a method embodying the present invention according to the sequence of process steps shown in FIG. 2. FIG. 9(a) shows the current-voltage characteristics of a lateral Schottky diode in which the second interface is offset from the first interface such that the protrusion of the second interface onto the first plane does not overlap the first interface; this configuration benefits from a high reverse breakdown voltage and low reverse leakage current (0.5 μA at a reverse bias of 30 V). FIG. 9(b) shows the current-voltage characteristics of a lateral Schottky diode in which the first interface is offset from the first interface such that the protrusion of the second interface onto the first plane does not overlap the first interface. The second interface is positioned over the first interface so that the protrusion of the second interface onto the plane partially overlaps the first interface. This configuration allows for high forward current (at 1V forward bias) Figure 9 shows the minimum number of process steps required. By integrating these, lateral structures with different interface offsets can be formed on the same substrate with different characteristics. It is shown that it is possible to provide multiple devices having the same.

[0119] FIG. 10 shows a typical circuit configuration utilizing a lateral Schottky diode embodying the present invention. These form a rectifier that converts AC (full wave (a) or half wave (b)) into DC. or electrostatic discharge to prevent sudden current flows due to the discharge of static charge. (c) can be configured as an ESD protection element or as a voltage regulator to maintain a constant voltage level Referring now to FIG. 10(a), this can be seen to be a Referring now to FIG. 10(b), this is a typical full-wave rectifier circuit diagram. 10(c) is a circuit diagram of an exemplary half-wave rectifier embodying the invention. This is a typical ESD protection circuit diagram embodying the present invention. 1, which is a typical voltage multiplier circuit diagram embodying the present invention. The number of process steps required for the fabrication of a Schottky diode is of these and / or other circuitry within the same integrated circuit without adding can be combined in one or more of the following ways:

[0120] Reference is now made to FIG. 11, which shows an embodiment of another aspect of the present invention, which aspect is It is generally defined by claim 31. The diodes are formed on the surface of the substrate 1. In this example, the electrodes are: A body 4 of semiconductor material is then formed on the common upper surface of the substrate 1 between the electrodes. Further portions 420, 450 of the body 4 are provided with a central portion covering a portion of the upper surface of the plate 1. The underlying electrodes and substrate are placed so as to overlap the upper portions of the first electrode 2 and the second electrode 5, respectively. A body of semiconductor material 4 was formed over the structure. A first interface 42 is formed between the first electrode 2 and the first flat region Similarly, a second boundary is formed between the semiconductor 4 and the second electrode 5. The surface 45 is formed with a second interface therebetween, which includes a second flat area 452 and a further end surface portion 453. In this example, the thickness of the first electrode and the second electrode are substantially the same, Therefore, the first flat area 421 and the second flat area 452 are substantially in the same plane P1. The first electrode and the second electrode are arranged on the plane P1 in a direction perpendicular to the plane P1. The protrusions do not overlap, and are laterally offset by a distance LO. In the example, the lateral offset LO is the first flatness of the first interface and the second interface, respectively. It also corresponds to the lateral separation between region 421 and second flat region 452 .

[0121] It will be appreciated that the embodiment of Figure 11 is a structure without a dielectric layer. The semiconductor material may be any semiconductor material disclosed herein or apparent to one of ordinary skill in the art. To fabricate the structure of FIG. 11, the materials selected for the first electrode 2 and the second electrode 5 are It is also understood that the material selected should be chosen to have suitable etch selectivity. Alternatively, one or more of the electrodes may be patterned by etching. Instead of being printed on a substrate, the substrate is patterned by, for example, lift-off patterning or printing. The method involves the selection of materials for the dielectric layer 3, the semiconductor layer 4, the electrode 2 and the electrode 5. This allows for greater flexibility.

[0122] Reference is now made to FIG. 12, which shows an embodiment similar to that shown in FIG. However, here the first electrode 2 and the second electrode 5 have different thicknesses. The first flat region 421 and the second flat region 452 do not lie in the same plane. These regions lie in a first plane P1 and a second plane P2, respectively, and these planes are spaced apart by a distance Only separation S occurs.

[0123] Referring now to FIG. 13, this is the general principle of the present invention as defined by claim 20. 1 is a cross-sectional view of another embodiment of one aspect, in which the first electrode 2 is a semiconductor layer or is formed below the body 4 and the second electrode 5 is formed entirely above the semiconductor body 4 . a first flat region 42 in which the interface between the semiconductor 4 and the first electrode 2 lies in a first plane P1; 1, a part of the semiconductor layer 4 overlaps the upper surface of the first electrode 2. In this example, The thickness of the layer of semiconductor material 4 (the thickness of which is indicated by T in the figure) is thickness, and therefore the second flat region 452 (which is the second electrode 5 and the semiconductor 4 The second interface 45 between the first and second electrodes 41 and 42 is formed in the direction perpendicular to the plane P1. In this example, P2 is nominally the plane of P1. Although in alternative embodiments, depending on the relative thicknesses of the electrode and the semiconductor body 4, It will be appreciated that the relative positions of planes P1 and P2 are different.

[0124] Referring now to FIG. 14(a), this is another Schottky die embodying the present invention. This embodiment shows a cross section of the first electrode 2, in which the dielectric layer 3 does not cover any part of the first electrode 2. This differs from the specific embodiment described above in that it does not The device is constructed by first forming a dielectric layer 3 on a substrate 1, and then passing through the dielectric layer to form a dielectric layer on the substrate 1. The glass substrate is fabricated using a method in which a window W extending downward to the surface (the upper surface in this figure) is formed. Then, a conductive material is deposited inside the window W to form the first electrode 2. The semiconductor material fills the window W and forms a first interface 42 with the first electrode 2 and laterally In the example, a semiconductor material is placed over the structure, extending in both directions away from the window W. A layer or body 4 of material is formed. Thus, in this example, the first electrode 2 is deposited on the plane P1. The protrusion of the first flat area 421 is exactly the same as the protrusion of the first flat area 421. The flat region 421 is the entire first interface 42. The second electrode 5 is formed on the upper side of the semiconductor body 4. on the surface by suitable techniques (e.g., by deposition, masking, and subsequent etching) , or alternatively by selective printing). Thus, in this example, the second The flat region 452 provides the entire second interface 45 between the second electrode 5 and the semiconductor 4, and is a planar The projection of the second electrode 5 onto P1 is the same as the projection of the second flat area 452. As in the previous embodiment, the plane P2 of the second electrode contact with the semiconductor layer 4 is The first flat area is parallel to the plane P1 of the contact or junction between the first electrode and the second electrode. The area 421 and the second flat area 452 are vertically offset by a distance VO and a distance L 14(b), this is the same as the present invention. 14(a) shows another Schottky diode that can be implemented. In other words, the dielectric layer 3 does not cover any part of the first electrode 2. However, in this embodiment In the figure, the first electrode 2 does not fill the entire window W in the dielectric layer 3, but only a part of the window W. The first electrode 2 may be formed by any suitable technique before or after the formation of the dielectric layer 3. Then, the semiconductor material fills the window W and forms a first boundary with the first electrode 2. The surface 42 extends laterally, in this example, in both directions away from the window W. A layer or body 4 of semiconductor material was formed over the structure. In this embodiment, the projection of the first electrode 2 onto the plane P1 is strictly aligned with the projection of the first flat area 421. However, in this embodiment, the first interface 42 is the first flat region. 421 and an end face portion 422.

[0125] Referring now to FIG. 15, this is another Schottky diode embodying one aspect of the present invention. The dielectric layer 3 surrounds the first electrode 2. The semiconductor 4 layer (or body) is formed so as to cover the exposed first electrode 2. The upper surface of the first electrode (first interface 42) is made up of a first flat region 421 in the plane P1. ) and around the first electrode (i.e., adjacent to the first electrode). The second electrode 5 is formed on a part of the semiconductor layer 4 so as to cover the part of the dielectric layer (which is connected to the semiconductor layer 4). The dielectric layer 3 is formed over the entire surface of the dielectric layer 3 and over a portion of the dielectric layer 3, and is located in the plane P2. a second flat region 452 and a further region 453 which is generally at the edge of the semiconductor layer; , a second interface 45 with the semiconductor material is formed. In this example, a second flat region 452 partially overlaps the first flat region 421 and therefore partially overlaps the first electrode 2.

[0126] By simply changing the lateral shape, the technique allows for the creation of different properties on the same wafer. The ability to provide devices that support the same technology, for example, within the same integrated circuit, allows for optimal performance for a given range of applications. Minimize the number of process steps required to fabricate optimized devices This is particularly advantageous (see the accompanying descriptions of Figures 6 and 9).

[0127] Reference is now made to Figure 16, which illustrates a method embodying one aspect of the present invention. The method involves (a) providing a substrate 1 (or other support / support structure), and (b) (c) forming a first electrode 2 on the first region; and (d) forming a first electrode 2 on the substrate surface adjacent to the first region. covering the second area, through which part of the surface of the first electrode 2 is visible / exposed forming a body of dielectric material 3 also having a window W; (d) filling the window and depositing a layer of dielectric material 3 on the first electrode; A first electrode is disposed across the first interface 42 (421) and connected to the first electrode. and a portion of the body of dielectric material overlying the second region of the substrate surface. (e) forming a body of semiconductor material 4 comprising a second portion disposed on the semiconductor material; a second interface 452 on the second portion of the body of semiconductor material. and forming a second electrode 5 over the first electrode 5. The method is carried out in a manner to achieve the desired characteristics of the diode. Thus, a lateral offset LO is set between the first interface 42 and the second interface 452. Includes.

[0128] Referring to FIG. 17, this is similar to the method shown by FIG. 16, but the dielectric material 1 shows another way of embodying an aspect of the present invention, which differs in that the body of material 3 does not have a window. Instead, the body 3 partially overlaps the first electrode and then (covered by the first electrode) The second portion extends laterally over a second portion of the substrate surface immediately adjacent the first portion (which may be a thin film). Thereafter, a second region of the substrate surface is formed overlying the uncovered portion of the upper surface of the first electrode. A body 4 of semiconductor material is formed over at least a portion of the overlying dielectric material (step Step (c)). Then, in step (d), a desired gap is formed between the first interface and the second interface. a second electrode 5 is formed on the surface of the second portion of the semiconductor body with a lateral offset LO of It is done.

[0129] Now referring to FIG. 18, this is a first electrode, a second electrode, and a first electrode and To fabricate a Schottky diode comprising a body of semiconductor material connecting two electrodes, 1 shows another method embodying one aspect of the present invention for forming a substrate 1 (or supporting (b) forming a first electrode 2 on a first region of a surface of the body; and (c) forming a first electrode 2 on a first region of the surface of the body; a first portion disposed across the first electrode and connected to the first electrode at a first interface 42; and a second portion disposed over a second region of the substrate surface adjacent to the first region. forming a body of semiconductor material 4 comprising a second portion of the semiconductor material; and forming a second and forming a second electrode 5 connected to the body of semiconductor material at the interface of the first electrode 5 and the second electrode 5. The lateral offset between the first interface and the second interface determines the device characteristics. LO is selected.

[0130] Reference is now made to Figure 19, which illustrates another method for implementing an aspect of the present invention. The method comprises (a) providing a substrate 1 (or support / support structure); (b) forming a surface of the substrate; A first electrode 2 is formed on a first region and a second electrode 5 is formed on a second region of the substrate surface. wherein the second region is separated from the first region by a third region, and the electrode is and (c) forming a third electrode and a substrate having a lateral offset of at least one of the electrodes and the substrate. (d) forming a body of dielectric material 3 overlying the region; and (e) forming a third layer of the electrode and the substrate surface. (e) forming a window W in the body of dielectric material to expose a portion of the region of (f) depositing a semiconductor material 4 at least inside the window; and (f) removing the remaining dielectric material 3. In this manner, the method includes removing the first electrode. a first portion connected to the first electrode at a first interface and a second portion extending above the second electrode; a second portion connected to the second electrode at a second interface; and a third region a third portion disposed over the first portion and connecting the second portion to the third portion; In certain embodiments, the electrodes are formed simultaneously (e.g., In an alternative embodiment, the layers may be formed sequentially. One rectifying contact and one ohmic contact are implemented in the final diode. Depositing dielectric and / or semiconductor materials to achieve desired surface properties Their upper surfaces can be treated beforehand.

[0131] Reference is now made to Figure 20, which shows a portion of a circuit embodying one aspect of the present invention. Two Schottky diodes were simultaneously formed on the same substrate. The electrodes 2a and 2b of the first electrode are formed in a single respective processing step, and the two semiconductor The same is true for the main bodies 4a and 4b and the two second electrodes 5a and 5b. This diode requires only the same number of processing steps to fabricate a single diode. However, the lateral offsets LO1 and LO2 are different. Therefore, simply by determining the lateral offset of each of the device's electrodes, This requires additional processing steps compared to fabricating only a single diode. Instead, a method embodying one aspect of the present invention allows for the efficient integration of different electrical connections on a single substrate. It will be understood by those skilled in the art that multiple diodes having the same electrical properties can be fabricated. Thus, other and / or further aspects of the geometric design of each device may be different from other devices in the same circuit. For example, the semiconductor body and / or the first electrode and / or of the second electrode, parallel to the surface of the substrate 1 but laterally offset LO The width in the direction perpendicular to the plane of the paper (i.e., perpendicular to the paper) is The width of an individual device in a circuit containing multiple devices may differ from the width of the device. The device may comprise any of the elements of the devices disclosed in Regarding the presence, absence or shape of any body of dielectric material 3 or The presence, absence or shape of any window W within the body of the device may differ from the standard.

[0132] A Schottky diode / device according to any of the above mentioned aspects and embodiments. The devices and methods are applicable to more complex devices, e.g., source-gate transistors, It can be incorporated into a clock transistor, gate diode, etc., or For example, FIG. 21 shows a method for manufacturing a semiconductor device according to one embodiment of the present invention. A source-gate transistor (SGT) incorporating a Schottky diode ) is shown. An SGT source electrode 2 is formed / provided on a substrate 1, and A barrier contact 42 is provided by the interface between a portion of the side surface and a portion of the body of semiconductor material 4. The semiconductor body 4 is formed over and over the first dielectric layer 31. The source electrode is contacted through a window in the dielectric layer 31. In this way, the semiconductor fills the window and , extending laterally above the upper surface of the first dielectric layer 31. The SGT is a semiconductor SG overlaps the upper edge of the body 4 and forms an ohmic contact 45 to the semiconductor The T-type semiconductor device further includes a drain electrode 5 (in other words, an ohmic contact). the semiconductor body and the drain electrode. A second dielectric layer 32 is formed over the entire surface of the second dielectric layer 32, and an SGT gate electrode is formed on the surface of the second dielectric layer 32. In this example, the gate electrode 500 overlaps with the drain electrode 5. Instead, it is positioned over and over the semiconductor layer 4 and is protected by a second dielectric layer 32. The method for manufacturing the SGT is also different. Schottky diode components (2, 3, 1, 4, 5) are fabricated using methods according to the present invention. ) and forming a second dielectric layer 3 over the semiconductor layer 4 and the drain electrode 5. forming a gate on the surface of the second dielectric layer. Cut.

[0133] Schottky diodes embodying aspects of the present invention may be implemented, for example, in the form of integrated circuits (ICs). Therefore, it is natural that it can be incorporated into a wide variety of circuits, circuit modules, and electronic devices. It will be understood that Schottky diodes embodying aspects of the present invention may be incorporated into logic gates. Such logic gates can be implemented with only one active element (e.g., a diode). in "diode-transistor logic") or in combination with a transistor ("diode-transistor logic"). The present invention also provides a method for fabricating a semiconductor device using a transistor logic circuit ("transistor logic"), which may include one or more diodes. An example of two diode logic incorporating Schottky diodes is shown in Figure 22. and 23. Figure 22 shows a diode OR gate embodying one aspect of the present invention. Each has its anode connected to its input terminal and its output terminal connected to its output terminal. The output terminals are connected to resistors. 23 shows a diode AND gate embodying one aspect of the present invention. Each has its cathode connected to its input terminal and its output terminal. The output terminals are connected to resistors. The Schottky diode is connected to the positive power rail 1000 through a resistor. Using a diode (e.g., as in these embodiments) has other advantages as well: , it can provide the advantages of fast response and small voltage drop.

[0134] A Schottky diode embodying aspects of the present invention may be implemented as a diode, as shown in FIG. Conventional unipolar inverters are usually used in high voltage base A transistor switch and a resistive load are placed between the inverter and the low voltage reference. The inverter output is connected to the transistor gate terminal, and the inverter output is connected to the transistor and resistor In a diode-loaded inverter, for example, as shown in Figure 24, , the resistor load is replaced by a diode. As shown in FIG. Using a Schottky diode embodying one aspect of the present invention as a load in an inverter Among other things, it has fast switching speed, low voltage drop and low power consumption. This can provide the advantage of being less.

[0135] Referring to FIG. 25, this is another Schottky diode embodying an aspect of the present invention. The Schottky diode is fabricated by a method embodying another aspect of the present invention. and can be incorporated into circuits and devices embodying other aspects of the present invention. The diode has a first electrode 2, a second electrode 5, and a first electrode 42 at a first interface 42. a body 4 of semiconductor material connected to the first electrode at a second interface 45 and connected to a second electrode at a second interface 46; The first electrode 2 is made of titanium, and the first interface 42 provides a Schottky contact. a titanium oxide 21 layer formed on the surface of the titanium body (i.e. , as discussed above, comprising at least one titanium oxide or suboxide; or The first interface 42 is formed by the interface between the semiconductor body 4 and the titanium oxide 21. In this example, the semiconductor material 4 is an oxide semiconductor, more specifically Typically, the semiconductor material is IGZO, although in alternative embodiments, other semiconductor materials may be utilized.

[0136] The particular lateral diodes described herein and embodying the present invention have metal contacts. It is a conventional semiconductor device in that the semiconductor layers are laterally and vertically separated. It will be understood from the above explanation that this is different from the conventional lateral diode. The structure can now be easily incorporated into manufacturing processes, eliminating the need for additional processing steps. This also provides several important benefits:

[0137] This configuration allows for the formation of ohmic contacts without the need for modification of materials or surface properties. By controlling the separation between the tact and Schottky contacts, Threshold voltage and breakdown voltage can be precisely controlled (higher by increasing the separation) This allows for a wide variety of applications, e.g., without the need for different semiconductor thicknesses, oxygen concentrations, or surface treatments. Diodes having different threshold voltages and / or breakdown voltages can be fabricated on the same substrate in the same process. By controlling the shape of the device, contact resistance, series Resistive and capacitive parameters such as resistance, maximum current level, capacitance and RC time constant Precise control of transistor-related device characteristics can also be achieved.

[0138] The structure is easy to fabricate because the conductor layers are vertically separated, and etching By mitigating selectivity issues, it allows for a wider range of material choices. The conductor layers are now separated by a dielectric layer. This dielectric layer provides a and the lower conductor layer is therefore performed with respect to the upper conductor layer. Protected from any process (chemical etching, physical etching, etc.) Purely vertical and Compared with the lateral approach, the etching selectivity of the two conductor layers is examined here. The choice of conductor layers that can be used is not affected, allowing for a wider choice of materials. .

[0139] In the case of metal oxide semiconductors, the semiconductor is locally reduced through ohmic contact. This reduces the chance of a current path reaching the Schottky contact. and a more robust process that is less dependent on metal oxide thickness and / or oxygen content This is because the local reduction is essentially just below the ohmic contact. This is because it is limited to only a portion of a semiconductor layer, and in certain embodiments, ohmic The contact is laterally separated from the Schottky contact. At the end of the contact, there may be a slight lateral extension, but the two contacts If the lateral separation of the gates is large enough, this can lead to short-circuiting from the ohmic contacts. There is no possibility of a conductive path extending all the way to the key contact. In other words, controlling the lateral separation of the two contacts ensures and extends the entire length from the ohmic contact to the Schottky contact. This can ensure that conductive paths are avoided.

[0140] material In certain embodiments, the layer of semiconductor material is a thin film, such as a compound semiconductor (Ga As, GaN, InP, CdSe, InGaAs, InGaAsSb, etc.), ZnO, S nO2, NiO, SnO, Cu2O, In2O3, LiZnO, ZnSnO, InSnO (ITO), InZnO(IZO), HflnZnO(HIZO), InGaZnO(I metal oxides such as ZnO, ZnO, and inorganic semiconductors (e.g., ZnO, ZnO, and ZnO). amorphous, microcrystalline or nanocrystalline Si, organic semiconductors (CuPc, pentacene , PTCDA, methylene blue, orange G, rubrene, etc.), polymer semiconductors (PEDO T:PSS, POT, P30T, P3HT, polyaniline, polycarbazole, etc.), 2 2D materials (e.g., graphene), chalcogenides such as MoS2 and GeSbTe and perovskites (SrTiO3, CH3NH3PbCl3, H2NCHNH2P bCl3, CsSnl3), which is a thin film of a semiconductor material selected from the list including These semiconductor materials may also be doped or contain a doping gradient, and may be n-type or p-type. It can be said that:

[0141] In certain embodiments, the layer of conductive material is selected from the group consisting of Au, Ti, Al, Mo, Pt, Pd, Metals such as Ag, Cu, Ni, Cr, Ta, and W, and alloys such as MoNi, MoCr, and AlSi alloys, transparent conductive oxides (ITO, IZO, AZO, etc.), metal nitrides such as TiN , carbon materials such as carbon black, carbon nanotubes, and graphene, polyaniline The conductive material may include a conductive polymer such as PEDOT:PSS or a semiconducting material.

[0142] In certain embodiments, the layer of dielectric material is Al2O3, ZrO2, HfO2, Y2 Metal oxides such as O3, Si3N5, TiO2, Ta2O5, and gold such as Al2POx Metal phosphates, metal sulfates / sulfites such as HfSOx, metal nitrides such as AlN, Metal oxynitrides such as lOxNy, inorganic insulators such as SiO2, Si3N4, and SiNx , spin-on glass (polyhydroxybenzylsilsesquioxane, HSQ, etc.), Polymer dielectric material (Cytop (commercially available amorphous fluoropolymer), 1-Methoxy-2-propyl ester (SU-8), benzocyclobutene (BCB), polyimide Polymethyl methacrylate, Polybutyl methacrylate, Polyethyl methacrylate , polyvinyl acetate, polyvinylpyrrolidone, polyvinylphenol, polyvinyl chloride, poly Styrene, polyethylene, polyvinyl alcohol, polycarbonate, parylene, silicon Cone, etc.), UV-curable resin, nanoimprint resist, or photoresist The dielectric material may have a relatively low dielectric constant (low κ, e.g., , HSQ, Parylene) or may have a relatively high dielectric constant (high κ , e.g., Ta2O5, HfO2).

[0143] In certain embodiments, the Schottky diode is disposed on a substrate or substrate structure. In other words, the method involves directly mounting a Schottky diode on a substrate. In certain embodiments, the substrate may further include abutting or indirectly supporting the substrate. can be flexible, and the substrate can be glass (rigid or flexible), polymer (e.g., polyethylene naphthalate or polyethylene terephthalate), polymer foil (p polymeric foil), paper, insulator-coated metal (e.g., coated stainless steel), cellulose, polymethyl methacrylate, polycarbonate, polyvinyl alcohol, poly Vinyl acetate, polyvinylpyrrolidone, polyvinylphenol, polyvinyl chloride, polystyrene polyethylene, polyethylene naphthalate, polyethylene terephthalate, polyimide, polyamide Poly(hydroxyether), polyurethane, polycarbonate Polysulfone, Parylene, Polyacrylate, Polyetheretherketone (PEE K), acrylonitrile butadiene styrene, 1-methoxy-2-propyl acetate (SU- 8), polyhydroxybenzylsilsesquioxane (HSQ), benzocyclobutene (B CB), Al2O3, SiOxNy, SiO2, Si3N4, UV curable resin, nano-insulator Print resist may contain materials selected from a list including photoresist do.

[0144] In certain embodiments, providing a layer of substrate / semiconductor / conductor / dielectric material may include vapor deposition. (physical, e.g., sputtering; chemical, e.g., PECVD); vacuum deposition (e.g., thermal or e-beam evaporation), coating (spin, dip, blade, bar, spray, lot die), printing (jet, gravure, offset, screen, flexo), Select from a list including pulsed laser deposition (PLD), atomic layer deposition (ALD) coatings forming said layer by a known technique.

[0145] In certain embodiments, the layer of substrate / semiconductor / conductor / dielectric material is thermally annealed, Plasma treatment (O2, Cl2, Ar, CF4, BCl3, N2, SF6, HBr, etc.), Self-assembled monolayer (SAM) (e.g., HMDS) by techniques such as RIE and ozone UV treatment It may have a surface modification.

[0146] Throughout the description and claims of this specification, the terms "comprise" and "include" are used interchangeably. The terms "se," "contain," and variations thereof mean "including, but not limited to." and may exclude other moieties, additives, components, integers or steps. It is not intended (and does not exclude) that: , singular includes plural unless the context otherwise requires. Where the definite article is used, unless the context requires otherwise, this specification refers to the singular It should be understood that not only one but also a plurality is contemplated.

[0147] Any features, integers, properties, compounds, etc., described in conjunction with particular aspects, embodiments, or examples of the present invention; The chemical moiety or chemical group may be any of the chemical moieties or groups described herein, except where incompatible. It should be understood that other aspects, embodiments or examples are applicable. All features disclosed in the accompanying claims, abstract and drawings, and / or or all steps of any method or process so disclosed may be modified to include such features. and / or excluding combinations in which at least some of the steps are mutually exclusive. , can be combined in all combinations. The present invention relates to any of the previous embodiments. The present invention is not limited to the details set forth herein (including any accompanying claims, abstract and Any novel feature or any novel feature disclosed in the specification (including drawings) or any method or process step so disclosed. It extends to any novel step or any novel combination.

[0148] The reader's attention is drawn to the following: , and all articles or documents published herewith, but all such articles The contents of the text or document are incorporated herein by reference. The following additional notes are provided regarding the above-described embodiments. (Appendix 1) A Schottky diode, a first electrode; a second electrode; A first interface is connected to the first electrode and a second interface is connected to the second electrode. a body of semiconductor material to be connected; The first interface comprises a first flat region lying in a first plane, and the first electrode a first protrusion onto the first plane in a first direction perpendicular to the first plane; and The second interface comprises a second planar region lying in a second plane, and the second electrode , a second protrusion onto the first plane in the first direction; At least a portion of the second protrusion is located outside the first protrusion, and the second flat the flat region is offset from the first flat region in the first direction; One of the first interface and the second interface provides a Schottky contact. , Schottky diode. (Appendix 2) 2. The diode of claim 1, wherein the second plane is parallel to the first plane. (Appendix 3) 3. The diode of claim 1, wherein the first interface comprises the first flat region. (Appendix 4) 4. The diode of claim 1, wherein the second interface comprises the second flat region. (Appendix 5) The second protrusion is located completely outside the first protrusion and is The protrusion of the second flat area onto the first plane is Item 1 to Item 4, which is entirely outside the protrusion of the first flat region onto the first plane. 10. The diode according to claim 9 . (Appendix 6) Any of Supplementary Notes 1 to 4, wherein a portion of the first protrusion is located inside the second protrusion. 3. The diode according to claim 1. (Appendix 7) Any of claims 1 to 4, wherein the first protrusion is entirely outside the second protrusion. 3. The diode according to claim 1. (Appendix 8) The protrusion of the second flat area onto the first plane in the first direction is completely outside the protrusion of the first flat area onto the first plane in a first direction 8. The diode of claim 6 or 7, (Appendix 9) A portion of the first flat area protruding onto the first plane in the first direction is , on the inside of the protrusion of the second flat area onto the first plane in the first direction. 8. The diode of claim 6 or 7, (Appendix 10) The total protrusion of the first flat area onto the first plane in the first direction is , on the inside of the protrusion of the second flat area onto the first plane in the first direction. 8. The diode of claim 6 or 7, (Appendix 11) 11. The method of claim 1, further comprising: The diode according to any one of claims 1 to 4. (Appendix 12) 12. The diode of any one of claims 1 to 11, further comprising a body of dielectric material. (Appendix 13) The dielectric body separates the second electrode from the first electrode in the first direction. 13. The diode of claim 12, arranged to (Appendix 14) The dielectric body includes a window, and the first interface is disposed inside the window. 14. The diode according to claim 13. (Appendix 15) The body of semiconductor material has a first portion at least partially filling the window and a second portion extending from the window. a second portion extending laterally from the first portion and covering at least a portion of the surface of the dielectric body; , the diode described in Appendix 14. (Appendix 16) The second electrode is disposed so as to cover at least a portion of the second portion of the dielectric body. 16. The diode of claim 15, (Appendix 17) a second electrode disposed on the second surface of the semiconductor material; 17. The method of claim 1, further comprising a further body of dielectric material arranged as follows: The diode described. (Appendix 18) The further body of dielectric material is disposed over the body of semiconductor material. , the diode described in Appendix 17. (Appendix 19) At least one of the first interface and the second interface is connected to the first electrode, A treated (e.g., surface) layer of at least one of the second electrode and the body of semiconductor material. 19. The diode of any one of claims 1 to 18, comprising a surface-treated portion. (Appendix 20) A Schottky diode, a first electrode; a second electrode; A first interface is connected to the first electrode and a second interface is connected to the second electrode. a body of semiconductor material to be connected; The first interface comprises a first flat region lying in a first plane, and the first electrode a first protrusion onto the first plane in a first direction perpendicular to the first plane; and The second interface has a second flat region, and the second electrode faces forward in the first direction. a second protrusion on the first plane; the second protrusion is completely outside the first protrusion; one of the first interface and the second interface provides a Schottky contact; The body has a first side and a second side, the second side being oriented in the first direction. and spaced from the first side by a thickness of the body, The first flat area is on the first side of the body and the second flat area is on the a Schottky diode on the second side of the body. (Appendix 21) 21. The diode of claim 20, wherein the second planar region lies in the first plane. (Appendix 22) 21. The diode of claim 20, wherein the second planar region lies in a second plane. (Appendix 23) 23. The diode of claim 22, wherein the second plane is parallel to the first plane. (Appendix 24) the second plane is spaced apart from the first plane in the first direction. The diode according to claim 1. (Appendix 25) 25. Any of clauses 20-24, further comprising a substrate positioned to support the first electrode. The diode according to any one of claims 1 to 4. (Appendix 26) The body of semiconductor material is disposed over at least a portion of a surface of the first electrode. a first portion extending laterally from the first electrode; and a second portion extending laterally from the first electrode; an electrode disposed over at least a portion of the second portion of the body of semiconductor material; 26. The diode according to any one of appendices 20 to 25. (Appendix 27) covering at least a portion of the body of semiconductor material and at least a portion of the second electrode; 27. Any one of clauses 20 to 26, further comprising a further body of dielectric material arranged so as to Item 1. A diode according to item 1. (Appendix 28) The further body of dielectric material is disposed over the body of semiconductor material. , the diode described in Appendix 27. (Appendix 29) At least one of the first interface and the second interface is connected to the first electrode, a second electrode and at least one surface-treated portion of the body of semiconductor material; The diode according to any one of appendices 20 to 28. (Appendix 30) The body of semiconductor material comprises a first layer and a second layer, and the first interface is any one of claims 1 to 29, wherein the second interface comprises a portion of the second layer. 10. The diode according to claim 9 . (Appendix 31) A Schottky diode, a first electrode; a second electrode; A first interface is connected to the first electrode and a second interface is connected to the second electrode. a body of semiconductor material to be connected; The first interface comprises a first flat region lying in a first plane, and the first electrode a first protrusion onto the first plane in a first direction perpendicular to the first plane; and The second interface has a second flat region, and the second electrode faces forward in the first direction. a second protrusion on the first plane; the second protrusion is completely outside the first protrusion; one of the first interface and the second interface provides a Schottky contact; The first electrode and the second electrode are formed on a substrate, and a portion of the body is in front of the electrodes. a second electrode disposed on the first surface of the substrate; a second electrode disposed on the second surface of the substrate; The body is formed over and over the electrode and the substrate so as to at least partially cover the electrode and the substrate. A Schottky diode. (Appendix 32) 32. The diode of claim 31, wherein the second planar region lies in the first plane. (Appendix 33) 32. The diode of claim 31, wherein the second planar region lies in a second plane. (Appendix 34) 34. The diode of claim 33, wherein the second plane is parallel to the first plane. (Appendix 35) the second plane is spaced apart from the first plane in the first direction. Or a diode according to claim 34. (Appendix 36) The first electrode is a Schottky electrode, and the second electrode is an ohmic electrode. 36. The diode of any one of claims 1 to 35. (Appendix 37) The first electrode is an ohmic electrode, and the second electrode is a Schottky electrode. 36. The diode of any one of claims 1 to 35. (Appendix 38) The first electrode is made of Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Metals such as Ta and W, alloys such as MoNi, MoCr, and AlSi, and transparent conductive oxides (ITO, IZO, AZO, etc.), metal nitrides such as TiN, carbon black, Carbon nanotubes, graphene-like carbon materials, polyaniline, PEDOT:PSS Attachment 1 or 2, which includes a material selected from the list including conductive polymers or semiconducting materials such as 38. A diode according to any one of claims 37 to 37. (Appendix 39) The second electrode is made of Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Metals such as Ta and W, alloys such as MoNi, MoCr, and AlSi, and transparent conductive oxides (ITO, IZO, AZO, etc.), metal nitrides such as TiN, carbon black, Carbon nanotubes, graphene-like carbon materials, polyaniline, PEDOT:PSS Attachment 1 or 2, which includes a material selected from the list including conductive polymers or semiconducting materials such as 39. A diode according to any one of claims 38 to 39. (Appendix 40) The semiconductor material is a compound semiconductor (GaAs, GaN, InP, CdSe, InGaA s, InGaAsSb, etc.), ZnO, SnO2, NiO, SnO, Cu2O, In2O 3, LiZnO, ZnSnO, InSnO(ITO), InZnO(IZO), Hfln Metal oxides such as ZnO (HIZO) and InGaZnO (IGZO), metal oxynitrides, For example, ZnxOyNz, inorganic semiconductors (amorphous, microcrystalline or nanocrystalline Si, etc. etc.), organic semiconductors (CuPc, pentacene, PTCDA, methylene blue, orange G, Rubrene, etc.), polymer semiconductors (PEDOT:PSS, POT, P3OT, P3HT, rianiline, polycarbazole, etc.), two-dimensional materials (2D materials) (graphene, etc.), M chalcogenides such as oS2, GeSbTe, and perovskites (SrTiO3, CH 3NH3PbCl3, H2NCHNH2PbCl3, CsSnl3), and doped Any of the above semiconductor materials, including a doping gradient, may be n-type or p-type. 40. The diode of any one of clauses 1 to 39, selected from the list including: (Appendix 41) 41. Any one of claims 1 to 40, wherein the diode is a thin-film Schottky diode. Item 1. A diode according to item 1. (Appendix 42) At least the semiconductor material and the first and second electrodes are at least as thick as possible. 42. The diode of any one of claims 1 to 41, which is substantially transparent to visible light. . (Appendix 43) 42. The dielectric material of claim 41, wherein the dielectric material is substantially transparent to at least visible light. diode. (Appendix 44) The semiconductor material is substantially transparent to at least visible light, but the first electrode and the second electrode is at least partially reflective to visible light. 10. The diode according to claim 9 . (Appendix 45) 43. The dielectric material is substantially transparent to at least visible light. diode. (Appendix 46) One of the first electrode and the second electrode comprises a body (e.g., a layer) of titanium and a layer comprising or consisting of at least one titanium oxide or suboxide formed on a surface of the titanium body, and the interface providing the Schottky contact is between the body of semiconductor material and a layer comprising or consisting of at least one titanium oxide or suboxide. Any of Supplementary Notes 1 to 45, comprising or consisting of an interface between the layer and the 10. The diode according to claim 9 . (Appendix 47) At least a first diode according to any one of claims 1 to 46 and a 6. A circuit comprising a second diode according to any one of claims 1 to 6, a first planar region and a second planar region of the diode are offset (from each other) by a first distance, and the first planar region and the second planar region of the second diode are offset by a second distance, the second distance being different from the first distance, and / or the circuit is an integrated circuit. (Appendix 48) a first electrode, a second electrode, and a semiconductor material connecting the first electrode and the second electrode; a body of a material; and forming a first electrode on a first region of a surface of a substrate (or support); a layer of dielectric material covering at least a second region of the substrate surface adjacent to the first region; Forming the body, a first interface disposed over the first electrode and connected to the first electrode; a first portion of the body of dielectric material overlying the second region of the substrate surface; forming a body of semiconductor material comprising a second portion disposed over the first portion; a second interface of the body of semiconductor material on the second portion of the body of semiconductor material; and forming a second electrode connected to the body. (Appendix 49) The first interface has a first protrusion on the substrate surface, and the second interface has a first protrusion on the substrate surface. A second protrusion is provided on the surface, the second protrusion being offset a distance from the first protrusion. The method of claim 48, wherein (Appendix 50) The distance is adjusted according to at least one desired characteristic or parameter of the diode. 50. The method of claim 49, further comprising predetermining. (Appendix 51) the first interface comprises a first surface portion of the first electrode, and the method comprises: 51. The method of any one of claims 48 to 50, further comprising treating the first surface portion of the first electrode prior to forming a body of material. (Appendix 52) The first electrode comprises a body of titanium, and the treating step treats the first surface portion to form a layer comprising or consisting of at least one titanium oxide or suboxide. 52. The method of claim 51, comprising: (Appendix 53) The second interface comprises a surface portion of the body of semiconductor material, and the method further comprises: further comprising treating the surface portion of the body of semiconductor material prior to forming the pole. 53. The method of any one of claims 48 to 52. (Appendix 54) 54. Any one of clauses 48-53, wherein the body of semiconductor material comprises at least two layers. The method described in paragraph . (Appendix 55) Clause 48 further comprising selectively processing at least a portion of the body of semiconductor material. 54. A method according to any one of claims 1 to 54. (Appendix 56) 56. Any one of clauses 48-55, wherein the body of dielectric material covers a portion of the first electrode. The method described in paragraph . (Appendix 57) The body of dielectric material has a thickness such that at least a portion of the first electrode is visible therethrough. a window through which the first portion of the body of semiconductor material is formed inside the window; 57. The method of any one of claims 48 to 56, wherein (Appendix 58) a first electrode, a second electrode, and a semiconductor material connecting the first electrode and the second electrode; a body of a material; and forming a first electrode on a first region of a surface of a substrate (or support); a first interface disposed over the first electrode and connected to the first electrode; a first portion of the substrate surface adjacent to the first region and extending over a second region of the substrate surface adjacent to the first region; forming a body of semiconductor material comprising a second portion disposed by the first portion; a second interface of the body of semiconductor material on the second portion of the body of semiconductor material; and forming a second electrode connected to the body. (Appendix 59) The first interface has a first protrusion on the substrate surface, and the second interface has a first protrusion on the substrate surface. A second protrusion is provided on the surface, the second protrusion being offset a distance from the first protrusion. The method of claim 58, wherein (Appendix 60) The distance is adjusted according to at least one desired characteristic or parameter of the diode. 60. The method of claim 59, further comprising predetermining. (Appendix 61) the first interface comprises a first surface portion of the first electrode, and the method comprises: and treating the first surface portion of the first electrode prior to forming the body of material. 61. The method of any one of appendices 58 to 60. (Appendix 62) The first electrode comprises a body of titanium, and the treating step treats the first surface portion to form a layer comprising or consisting of at least one titanium oxide or suboxide. 62. The method of claim 61, comprising: (Appendix 63) The second interface comprises a surface portion of the body of semiconductor material, and the method further comprises: further comprising treating the surface portion of the body of semiconductor material prior to forming the pole. 63. A method according to any one of claims 58 to 62. (Appendix 64) 64. Any one of clauses 58-63, wherein the body of semiconductor material comprises at least two layers. The method described in paragraph . (Appendix 65) Clause 58 further comprising selectively processing at least a portion of the body of semiconductor material. 64. A method according to any one of claims 1 to 64. (Appendix 66) a first electrode, a second electrode, and a semiconductor material connecting the first electrode and the second electrode; a body of a material; and forming a first electrode on a first region of a surface of a substrate (or support); a second region on the substrate surface, the second region being separated from the first region by a third region; forming a second electrode; a first interface disposed over the first electrode and connected to the first electrode; a first portion disposed over the second electrode and having a first interface therebetween; a second portion connected to the second electrode; and a third portion disposed over the third region and extending from the first portion to the second electrode. and a third portion connecting the first portion to the second portion. and (Appendix 67) The first interface has a first protrusion on the substrate surface, and the second interface has a first protrusion on the substrate surface. A second protrusion is provided on the surface, the second protrusion being offset a distance from the first protrusion. The method of claim 66, wherein (Appendix 68) The distance is adjusted according to at least one desired characteristic or parameter of the diode. 68. The method of claim 67, further comprising predetermining. (Appendix 69) the first interface comprises a first surface portion of the first electrode, and the method comprises: and treating the first surface portion of the first electrode prior to forming the body of material. 69. The method of any one of appendices 66 to 68. (Appendix 70) The first electrode comprises a body of titanium, and the treating step treats the first surface portion to form a layer comprising or consisting of at least one titanium oxide or suboxide. 70. The method of claim 69, comprising: (Appendix 71) The second interface comprises a first surface portion of the second electrode, and the method further comprises: further comprising treating the first surface portion of the second electrode prior to forming the body of material. 71. The method of any one of clauses 66 to 70, comprising: (Appendix 72) 72. Any of Clauses 66-71, wherein the body of semiconductor material comprises at least two layers. 10. The method according to claim 1. (Appendix 73) Clause 66 further comprising selectively processing at least a portion of the body of semiconductor material. 73. The method of any one of claims 1 to 72. (Appendix 74) The forming of the first electrode and the forming of the second electrode are performed simultaneously. 74. The method of any one of claims 66 to 73, wherein (Appendix 75) forming the first electrode before forming the second electrode; 75. The method of any one of clauses 66 to 74, wherein (Appendix 76) To dope or enhance the doping of at least a portion of the body of said semiconductor material. 76. The method of any one of claims 48 to 75, further comprising implanting ions into (Appendix 77) A Schottky diode, a first electrode; a second electrode; A first interface is connected to the first electrode and a second interface is connected to the second electrode. a body of semiconductor material to be connected; The first interface provides a Schottky contact and the first electrode is connected to the titanium body ( and at least one titanium oxide layer formed on the surface of the titanium body. and a layer including or consisting of a semiconductor material or a suboxide, a body of the material and a precursor comprising or consisting of at least one titanium oxide or suboxide; A Schottky diode comprising or consisting of an interface between a semiconductor layer and a gate electrode. (Appendix 78) 78. The diode of claim 77, wherein the semiconductor material is an oxide semiconductor. (Appendix 79) 79. The diode of claim 77 or 78, wherein the semiconductor material is IGZO.

Claims

1. A Schottky diode, a first electrode; a substrate positioned to support the first electrode, the substrate having a surface, the first electrode being formed on a first region of the surface; a second electrode; and a body of semiconductor material connected to the first electrode at a first interface and connected to the second electrode at a second interface; the first interface comprises a first flat region lying in a first plane parallel to the surface, and the first electrode has a first protrusion onto the first plane in a first direction perpendicular to the first plane; the second interface comprises a second flat region, and the second electrode has a second protrusion above the first plane in the first direction; the second protrusion is completely outside the first protrusion; one of the first interface and the second interface provides a Schottky contact; the body has a first side parallel to the surface and a second side parallel to the surface, the second side being spaced apart from the first side in the first direction by a thickness of the body; the first flat region is on the first side of the body and the second flat region is on the second side of the body; Schottky diode.

2. The diode of claim 1 , wherein the second planar region lies in the first plane.

3. The diode of claim 1 , wherein the second planar region lies in a second plane.

4. The diode of claim 3 , wherein the second plane is parallel to the first plane.

5. The diode of claim 4 , wherein the second plane is spaced apart from the first plane in the first direction.

6. 6. The diode of claim 1, wherein the body of semiconductor material comprises a first portion arranged to cover at least a part of a surface of the first electrode and a second portion extending laterally from the first electrode, the second electrode arranged to cover at least a part of the second portion of the body of semiconductor material.

7. 7. A diode according to claim 1, further comprising a further body of dielectric material arranged over at least a portion of the body of semiconductor material and over at least a portion of the second electrode.

8. 8. The diode of claim 7, wherein the further body of dielectric material is disposed over the body of semiconductor material.

9. 9. The diode of claim 1, wherein at least one of the first interface and the second interface comprises a surface treated portion of at least one of the first electrode, the second electrode, and the body of semiconductor material.

10. 10. The diode of claim 1, wherein the body of semiconductor material comprises a first layer and a second layer, the first interface comprising a portion of the first layer, and the second interface comprising a portion of the second layer.

11. The diode according to claim 1 , wherein the first electrode is a Schottky electrode and the second electrode is an ohmic electrode.

12. The diode according to claim 1 , wherein the first electrode is an ohmic electrode and the second electrode is a Schottky electrode.

13. 13. The diode of claim 1, wherein the first electrode comprises a material selected from the list comprising a metal, an alloy, a transparent conductive oxide, a metal nitride, a carbon material, a conductive polymer, or a semiconductor material.

14. 14. The diode of claim 1, wherein the second electrode comprises a material selected from the list comprising a metal, an alloy, a transparent conductive oxide, a metal nitride, a carbon material, a conductive polymer, or a semiconductor material.

15. 15. The diode of any one of claims 1 to 14, wherein the semiconductor material is selected from the list comprising compound semiconductors, metal oxides, metal oxynitrides, inorganic semiconductors, organic semiconductors, polymer semiconductors, 2D materials, chalcogenides, and perovskites, and any of the above semiconductor materials that are doped or comprise a doping gradient and are n-type or p-type.

16. 16. The diode of claim 1, wherein the diode is a thin film Schottky diode.

17. 17. The diode of claim 1, wherein at least the semiconductor material and the first and second electrodes are transparent to at least visible light.

18. At least the semiconductor material, the first electrode, and the second electrode are transparent to at least visible light, and 9. The diode according to claim 7 or 8, wherein the dielectric material is transparent to at least visible light.

19. 16. The diode of claim 1, wherein the semiconductor material is transparent to at least visible light, but the first electrode and the second electrode are at least partially reflective to visible light.

20. The semiconductor material is transparent to at least visible light, while the first electrode and the second electrode are at least partially reflective to visible light; and 9. The diode according to claim 7 or 8, wherein the dielectric material is transparent to at least visible light.

21. 21. Any one of claims 1 to 20, wherein one of the first electrode and the second electrode comprises a body of titanium and a layer comprising or consisting of at least one titanium oxide or suboxide formed on a surface of the body of titanium, and the interface providing the Schottky contact comprises or consists of an interface between the body of semiconductor material and the layer comprising or consisting of at least one titanium oxide or suboxide. The diode according to claim 1.

22. 22. A circuit comprising at least a first diode according to any one of claims 1 to 21 and a second diode according to any one of claims 1 to 21, wherein a first flat region and a second flat region of the first diode are offset by a first distance and wherein the first flat region and the second flat region of the second diode are offset by a second distance, the second distance being different from the first distance, and / or the circuit is an integrated circuit.

23. 1. A method of fabricating a Schottky diode comprising: a first electrode; a second electrode; and a body of semiconductor material connecting the first electrode and the second electrode, the method comprising: forming the first electrode on a first region of a substrate surface; forming a body of dielectric material overlying at least a second region of the substrate surface adjacent the first region; forming the body of semiconductor material comprising: a first portion disposed over the first electrode and connected to the first electrode at a first interface; and a second portion disposed over a portion of the body of dielectric material overlying the second region of the substrate surface; forming the second electrode on the second portion of the body of semiconductor material, the second electrode connected to the body of semiconductor material at a second interface; A method comprising:

24. 24. The method of claim 23, wherein the first interface has a first protrusion above the substrate surface and the second interface has a second protrusion above the substrate surface, the second protrusion being offset a distance from the first protrusion.

25. 25. The method of claim 24, further comprising predetermining the distance according to at least one desired characteristic or parameter of the diode.

26. 26. The method of any one of claims 23 to 25, wherein the first interface comprises a first surface portion of the first electrode, the method further comprising treating the first surface portion of the first electrode prior to forming the body of semiconductor material.

27. 27. The method of claim 26, wherein the first electrode comprises a body of titanium, and wherein the treating comprises treating the first surface portion to form a layer comprising or consisting of at least one titanium oxide or suboxide.

28. 28. The method of any one of claims 23 to 27, wherein the second interface comprises a surface portion of the body of semiconductor material, the method further comprising treating the surface portion of the body of semiconductor material before forming the second electrode.

29. 29. A method according to any one of claims 23 to 28, wherein the body of semiconductor material comprises at least two layers.

30. 30. The method of any one of claims 23 to 29, further comprising selectively processing at least a portion of the body of semiconductor material.

31. 31. The method of any one of claims 23 to 30, wherein the body of dielectric material covers a portion of the first electrode.

32. 32. The method of any one of claims 23 to 31, wherein the body of dielectric material comprises a window through which at least a portion of the first electrode is visible, and the first portion of the body of semiconductor material is formed inside the window.

33. 1. A method of fabricating a Schottky diode comprising: a first electrode; a second electrode; and a body of semiconductor material connecting the first electrode and the second electrode, the method comprising: forming the first electrode on a first region of a substrate surface; forming a body of semiconductor material comprising: a first portion disposed over the first electrode and connected to the first electrode at a first interface; and a second portion disposed over a second region of the substrate surface adjacent the first region; forming the second electrode on the second portion of the body of semiconductor material, the second electrode connected to the body of semiconductor material at a second interface; Including, the first interface comprises a first flat region lying in a first plane parallel to the substrate surface, and the first electrode has a first protrusion onto the first plane in a first direction perpendicular to the first plane; the second interface comprises a second flat region, and the second electrode has a second protrusion above the first plane in the first direction; the second protrusion is completely outside the first protrusion; one of the first interface and the second interface provides a Schottky contact; the body has a first side parallel to the substrate surface and a second side parallel to the substrate surface, the second side being spaced apart from the first side in the first direction by a thickness of the body; the first flat region is on the first side of the body and the second flat region is on the second side of the body; method.

34. 34. The method of claim 33, wherein the first interface has a first protrusion above the substrate surface and the second interface has a second protrusion above the substrate surface, the second protrusion being offset a distance from the first protrusion.

35. 35. The method of claim 34, further comprising predetermining the distance according to at least one desired characteristic or parameter of the diode.

36. 36. The method of any one of claims 33 to 35, wherein the first interface comprises a first surface portion of the first electrode, the method further comprising treating the first surface portion of the first electrode prior to forming the body of semiconductor material.

37. 37. The method of claim 36, wherein the first electrode comprises a body of titanium, and wherein the treating comprises treating the first surface portion to form a layer comprising or consisting of at least one titanium oxide or suboxide.

38. 38. The method of any one of claims 33 to 37, wherein the second interface comprises a surface portion of the body of semiconductor material, the method further comprising treating the surface portion of the body of semiconductor material before forming the second electrode.

39. 39. A method according to any one of claims 33 to 38, wherein the body of semiconductor material comprises at least two layers.

40. 40. The method of any one of claims 33 to 39, further comprising selectively processing at least a portion of the body of semiconductor material.

41. 41. The method of any one of claims 23 to 40, further comprising implanting ions to dope or enhance the doping of at least a portion of the body of semiconductor material.

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