Ridge-type semiconductor optical device

Abstract

To reduce parasitic capacitance caused by electrodes.SOLUTION: A ridge type semiconductor optical element has: a laminate 12 including a first region R1 and a second region R2 adjacent to both sides of an isolation groove 28; a mesa stripe structure 26 extending in a first direction D1 so as to be adjacent to the first region R1 on the laminate 12; a mound structure 30 extending in the first direction D1 so as to be adjacent to the second region R2 on the laminate 12; and an electrode pattern 34. An inner surface of the isolation groove 28 includes: a first wall surface S1 adjacent to the first region R1; a second wall surface S2 adjacent to the second region R2; and a bottom face S3. A ridge electrode 36 extends from a lateral face of the mesa stripe structure 26 along a second direction D2 orthogonal to the first direction D1 toward the mound structure 30 not to go over the second wall surface S2 of the isolation groove 28. A connection electrode 40 is thinner in width in the first direction D1 than both the ridge electrode 36 and a pad electrode 38.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a ridge-type semiconductor optical device. [Background technology]

[0002] Ridge-type semiconductor optical devices with a mesa stripe structure are known as light sources for optical communications. The mesa stripe structure is formed by carving a pair of regions into a stacked body including an intrinsic semiconductor layer and a multiple quantum well layer. Outside the pair of carved regions, a pair of bank structures are left to protect the mesa stripe structure. A trench is further formed in the region between the mesa stripe structure and the bank structure (Patent Documents 1 and 2). The trench limits the region through which current flows, thereby reducing parasitic capacitance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-69153 [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-89622 Summary of the Invention [Problem to be solved by the invention]

[0004] The top electrode on the mesa stripe structure extends to the top surface of the bank structure, but outside the grooves it does not substantially contribute to driving the light source. Furthermore, the intrinsic semiconductor layer and multiple quantum well layer in the bank structure increase parasitic capacitance, hindering high-speed operation. Placing an electrode only on the mesa stripe structure would eliminate the increase in parasitic capacitance, but the narrow width of the mesa stripe structure (less than a few microns) makes it difficult to form such an electrode.

[0005] The present disclosure aims to reduce the parasitic capacitance caused by electrodes. [Means for solving the problem]

[0006] The ridge-type semiconductor optical device includes an active layer or an absorption layer, an isolation trench separating the active layer or the absorption layer and extending in a first direction, a stack including a first region and a second region adjacent to both sides of the isolation trench, a mesa stripe structure extending in the first direction adjacent to the first region on the stack, a bank structure extending in the first direction adjacent to the second region on the stack, a ridge electrode on a top surface and a side surface of the mesa stripe structure, and a pad electrode on a top surface of the bank structure, and an electrode pattern including a connection electrode connecting pad electrodes, wherein the inner surface of the isolation groove includes a first wall surface adjacent to the first region, a second wall surface adjacent to the second region, and a bottom surface between the first region and the second region, the ridge electrode extends from the side surface of the mesa stripe structure toward the bank structure along a second direction perpendicular to the first direction so as not to exceed the second wall surface of the isolation groove, and the connection electrode is narrower in width in the first direction than both the ridge electrode and the pad electrode. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a plan view of a ridge-type semiconductor optical device according to a first embodiment. [Figure 2] 2 is a cross-sectional view taken along line II-II of the ridge-type semiconductor optical device shown in FIG. [Figure 3] FIG. 4 is a cross-sectional view of a ridge-type semiconductor optical device according to a second embodiment. [Figure 4] FIG. 10 is a cross-sectional view of a ridge-type semiconductor optical device according to a third embodiment. [Figure 5] FIG. 10 is a cross-sectional view of a ridge-type semiconductor optical device according to a fourth embodiment. [Figure 6] FIG. 10 is a cross-sectional view of a ridge-type semiconductor optical device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Elements with the same reference numerals in all the drawings have the same or equivalent functions, and their repeated explanation will be omitted. Note that the size of the figures does not necessarily correspond to the magnification.

[0009] [First embodiment] Fig. 1 is a plan view of a ridge-type semiconductor optical device according to a first embodiment. Fig. 2 is a cross-sectional view of the ridge-type semiconductor optical device shown in Fig. 1 taken along line II-II. The ridge-type semiconductor optical device is a directly modulated semiconductor laser in the 1.3 μm band, but it may be a ridge-type semiconductor optical device compatible with other wavelength bands, and may be an optical device having other optical functions other than a laser. For example, it may be a CW laser, an electroabsorption modulator, or a photodetector.

[0010] [Laminate] The ridge-type semiconductor optical device has a stack 12 on a substrate 10 made of a semiconductor of a first conductivity type. The stack 12 is made of a semiconductor and includes a buffer layer 14 of the first conductivity type, a lower SCH (Separated Confinement Heterostructure) layer 16 of the first conductivity type, an active layer 18, and an upper SCH layer 20 of a second conductivity type. The stack 12 includes the active layer 18 or an absorption layer.

[0011] Here, the first conductivity type is n-type and the second conductivity type is p-type, but the reverse is also possible. The substrate 10, buffer layer 14, and cladding layer 22 are made of InP. The lower SCH layer 16 and upper SCH layer 20 are made of InGaAsP. The active layer 18 is a multi-quantum well (MQW) in which multiple InGaAsP well layers and barrier layers are stacked. However, these materials are merely examples, and other materials may be selected depending on the corresponding light wavelength band and the required characteristics.

[0012] [Mesa stripe structure] The ridge-type semiconductor optical device has a mesa stripe structure 26 extending in a first direction D1. The mesa stripe structure 26 is continuous with the stack 12 and includes a cladding layer 22 of a second conductivity type and a contact layer 24 of a second conductivity type. A diffraction grating layer (not shown) is included between the upper SCH layer 20 and the cladding layer 22.

[0013] The stacked body 12 includes a first region R1. The mesa stripe structure 26 is adjacent to the first region R1 on the stacked body 12. The first region R1 is a pair of regions sandwiching the mesa stripe structure 26 therebetween.

[0014] [Isolation groove] The stack 12 has isolation trenches 28. The isolation trenches 28 extend in a first direction D1, separating the active layer 18 or the absorption layer. The isolation trenches 28 are formed for the purpose of preventing lateral diffusion of carriers from the active layer 18, and may have a depth that exceeds the active layer 18. The isolation trenches 28 may have a depth that reaches the buffer layer 14, or may have a depth that reaches the substrate 10. A first region R1 is present between the isolation trenches 28 and the mesa stripe structure 26.

[0015] The laminate 12 includes a second region R2. A first region R1 and a second region R2 are adjacent to both sides of the isolation groove 28. The second region R2 is adjacent to the isolation groove 28 on the side opposite to the first region R1. The isolation groove 28 is a pair of isolation grooves 28. The second region R2 is a pair of second regions R2 each adjacent to the pair of isolation grooves 28. The pair of isolation grooves 28 is each adjacent to the pair of first regions R1.

[0016] The inner surface of isolation groove 28 includes a first wall surface S1 adjacent to first region R1, a second wall surface S2 adjacent to second region R2, and a bottom surface S3 between first region R1 and second region R2. Note that the cross section of isolation groove 28 is not limited to a rectangular shape and may be other shapes (e.g., U-shaped or round).

[0017] [Embankment structure] The ridge-type semiconductor optical device has a bank structure 30 extending in a first direction D1. Like the mesa stripe structure 26, the bank structure 30 has a cladding layer 22 and a contact layer 24. The mesa stripe structure 26, the isolation grooves 28, and the bank structure 30 are formed in the first direction D1, extending from one end face to the opposite end face. The bank structure 30 is adjacent to the second region R2 on the stack 12. The bank structure 30 is a pair of bank structures 30 each adjacent to a pair of second regions R2.

[0018] [Passivation film] The ridge-type semiconductor optical device has an insulating passivation film 32 on its surface to protect the semiconductor layer from the external environment. The passivation film 32 is disposed on the top surface of the bank structure 30, the inner surface of the isolation trench 28, and the side surface of the mesa stripe structure 26.

[0019] [Electrode pattern] The ridge-type semiconductor optical device has an electrode pattern 34. The electrode pattern 34 has a laminated structure of a lower layer made of Ti / Pt and an upper layer made of Au. A passivation film 32 is interposed between the laminate 12 and the electrode pattern 34, avoiding at least a portion of the upper surface of the mesa stripe structure 26.

[0020] [Ridge electrode] The electrode pattern 34 includes a ridge electrode 36. The passivation film 32 is not formed on the top surface of the mesa stripe structure 26, but forms a through-hole for connecting the ridge electrode 36 to the contact layer 24. The ridge electrode 36 is made up of multiple layers including a stacked first layer L1 and second layer L2. Note that the edges of the first layer L1 and second layer L2 do not need to be aligned and may be offset as necessary.

[0021] The ridge electrode 36 is located on the top surface and side surfaces of the mesa stripe structure 26. The ridge electrode 36 extends from the side surfaces of the mesa stripe structure 26 toward the bank structure 30. The ridge electrode 36 extends along a second direction D2 that is perpendicular to the first direction D1. The width of the ridge electrode 36 in the first direction D1 is uniform overall.

[0022] The ridge electrode 36 has a part on the first wall surface S1 of the isolation groove 28, another part on the second wall surface S2, and still another part on the bottom surface S3. The ridge electrode 36 does not extend beyond the second wall surface S2 of the isolation groove 28.

[0023] [Pad electrode] The electrode pattern 34 includes a pad electrode 38 on the upper surface of the bank structure 30. The pad electrode 38 is used for electrical connection to the outside, and is bonded with a wire (not shown) or by solder.

[0024] [Connection electrode] The electrode pattern 34 includes a connection electrode 40. The connection electrode 40 connects the ridge electrode 36 and the pad electrode 38. The connection electrode 40 has a width in the first direction D1 that is narrower than both the ridge electrode 36 and the pad electrode 38.

[0025] [function] A back electrode 42 is disposed widely on the back side of the substrate 10. When a current is injected between the ridge electrode 36 and the back electrode 42, light is emitted in the active layer 18, and the light is emitted from the edge surface. The back electrode 42 does not necessarily have to be disposed on the back side of the substrate 10. For example, a groove (not shown) that reaches the buffer layer 14 or the substrate 10 may be formed in part of the bank structure 30, and an electrode (not shown) may be disposed so as to connect to the groove. In this case, the back electrode 42 will be disposed on the same side as the electrode pattern 34.

[0026] [effect] The large area of ​​the ridge electrode 36 is advantageous in terms of heat dissipation, but disadvantageous in terms of parasitic capacitance. In particular, because the active layer 18 is interrupted by the isolation grooves 28, the stacked body 12 from the isolation grooves 28 to the bank structures 30 does not contribute to light emission. However, because a pin structure exists below the electrode patterns 34 arranged in these regions, a capacitance component is generated. For example, an insulating passivation film 32 is arranged below the bottom of the isolation grooves 28, which also becomes a capacitance component. Outside the isolation grooves 28, in addition to the passivation film 32, the active layer 18, which is an intrinsic semiconductor layer, is also arranged, which also becomes a capacitance component.

[0027] In this embodiment, the ridge electrode 36 does not extend beyond the second wall surface S2 of the isolation groove 28, and the connection electrode 40 is narrower in width in the first direction D1 than both the ridge electrode 36 and the pad electrode 38, thereby preventing an increase in parasitic capacitance. As a result, a semiconductor optical device with excellent high-speed response can be provided.

[0028] [Manufacturing method] In the method for manufacturing a ridge-type semiconductor optical device, a multilayer film including a stacked body 12 is formed on a substrate 10 by crystal growth using metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). Next, a mask is formed using photolithography, and isolation grooves 28 are formed by etching. This process also forms a mesa stripe structure 26 and a bank structure. After forming a passivation film 32 over the entire surface, the passivation film 32 is removed only from the region in contact with the contact layer 24.

[0029] An electrode film is formed over the entire surface using a metal vapor deposition device. Next, the area that will become the electrode pattern 34 is masked, and the electrode film in other areas is removed. This process forms the electrode pattern 34. Finally, a backside electrode 42 is formed on the backside of the substrate 10. After the above wafer process is complete, the substrate 10 is separated by cleavage or etching, completing the ridge-type semiconductor optical device.

[0030] [Second embodiment] 3 is a cross-sectional view of a ridge-type semiconductor optical device according to the second embodiment. This embodiment differs from the first embodiment in the shape of the electrode pattern 234.

[0031] The parasitic capacitance can be reduced most if the ridge electrode 236 is located only on the top surface of the mesa stripe structure 226. However, the width of the mesa stripe structure 226 is several μm (for example, 1.7 μm in this case), and the width of the first region R1 is 5 μm.

[0032] In the method of forming the ridge electrode 236, an electrode film is deposited over the entire surface, and then the area where the ridge electrode 236 will remain is masked and the other areas are removed. The accuracy of mask alignment is several micrometers. Therefore, even if an attempt is made to mask only the top surface of the mesa stripe structure 226, there is a risk that the mask will be formed misaligned from above the mesa stripe structure 226. If the mask is misaligned, the position of the ridge electrode 236 will be misaligned. In the worst case, the ridge electrode 236 may not be formed at all on the top surface of the mesa stripe structure 226.

[0033] Therefore, in this embodiment, the ridge electrode 236 extends over the first region R1 so as not to reach the inner surface of the isolation groove 228. The width of the first region R1 is 5 μm, and the combined width of both first regions R1 and the width of the mesa stripe structure 226 is 11.7 μm. If the width of the ridge electrode 236 is determined within this region taking into account mask alignment accuracy, it becomes possible to reliably form the ridge electrode 236 on the upper surface of the mesa stripe structure 226. The stacked body 212 contributes to actual light emission below the mesa stripe structure 226 and the first regions R1 on both sides of it.

[0034] This embodiment is superior to the first embodiment in terms of parasitic capacitance, achieving both reduced parasitic capacitance and ease of manufacturing. Note that the edges of the first layer L1 and the second layer L2 do not need to be aligned, and may be shifted as necessary.

[0035] [Third embodiment] 4 is a cross-sectional view of a ridge-type semiconductor optical device according to the third embodiment. The ridge electrode 336 is partially present on the first wall surface S1 and bottom surface S3 of the isolation groove 328, but not on the second wall surface S2.

[0036] In the first embodiment, the ridge electrode 36 extends to the second wall surface S2 of the isolation groove 28, so the parasitic capacitance is large but the heat dissipation is excellent. The second embodiment is superior to the first embodiment in terms of parasitic capacitance but is inferior in terms of heat dissipation.

[0037] This embodiment is somewhere between them. In particular, since the amount of heat generated is greatest in the active layer 318, covering the side surfaces of the active layer 318 with the ridge electrode 336 ensures a heat dissipation path, and provides an effect that goes beyond the increase in heat dissipation achieved by simply increasing the area of ​​the ridge electrode 336.

[0038] While high-speed response is an important characteristic for ridge-type semiconductor optical devices, optical output intensity is also an important characteristic. Increasing the amount of heat dissipation leads to increased optical output intensity. Therefore, by positioning the end of the ridge electrode 336 according to the required characteristics, both high-speed response and ease of manufacturing can be achieved.

[0039] [Fourth embodiment] 5 is a cross-sectional view of a ridge-type semiconductor optical device according to the fourth embodiment. The ridge electrode 436 is partially present on the first wall surface S1 and bottom surface S3 of the isolation groove 428, but not on the second wall surface S2 of the isolation groove 428.

[0040] The ridge electrode 436 is made up of multiple layers including a first layer L1D and a second layer L2U stacked together. The first layer L1D is the lower layer, and the second layer L2U is the upper layer. The second layer L2U overlaps only a portion of the first layer L1D. A portion of the first layer L1D is on the inner surface of the isolation groove 428. The second layer L2U is not on the inner surface of the isolation groove 428.

[0041] The second layer L2U is made of Au. The second layer L2U is the outermost layer of the ridge electrode 436 and is thicker than the other layers for connection to the outside, which increases the stress on the semiconductor layers. The reliability and characteristics of the active layer 418 are particularly susceptible to being affected by stress. Therefore, not arranging the second layer L2U on the side of the active layer 418 leads to a reduction in the stress on the active layer 418. From the viewpoint of parasitic capacitance, this embodiment is equivalent to the third embodiment.

[0042] [Fifth embodiment] 6 is a cross-sectional view of a ridge-type semiconductor optical device according to the fifth embodiment. The ridge electrode 536 is partially present on the first wall surface S1 and bottom surface S3 of the isolation groove 528, but not on the second wall surface S2.

[0043] The ridge electrode 536 is made up of multiple layers including a first layer L1U and a second layer L2D stacked together. The first layer L1U is the upper layer, and the second layer L2D is the lower layer. The second layer L2D overlaps only a portion of the first layer L1U. A portion of the first layer L1U is on the inner surface of the isolation groove 528. The second layer L2D is not on the inner surface of the isolation groove 528.

[0044] An end of the second layer L2D is located in the first region R1, and an end of the first layer L1U is disposed on the inner surface of the isolation groove 528. From the viewpoint of stress, it is preferable that the thick first layer L1U made of Au is not disposed on the side surface of the active layer 518. However, from the viewpoint of heat dissipation, the thick first layer L1U made of Au is superior to the thin second layer L2D made of Ti / Pt. Therefore, this embodiment has better heat dissipation properties than the fourth embodiment. Furthermore, since the second layer L2D also causes stress, this embodiment is also superior in terms of stress compared to the third embodiment.

[0045] [Outline of the embodiment] (1) A stack 12 including an active layer 18 or an absorption layer, having an isolation groove 28 separating the active layer 18 or the absorption layer and extending in a first direction D1, and including a first region R1 and a second region R2 adjacent to both sides of the isolation groove 28, a mesa stripe structure 26 extending in the first direction D1 adjacent to the first region R1 on the stack 12, a bank structure 30 extending in the first direction D1 adjacent to the second region R2 on the stack 12, a ridge electrode 36 on an upper surface and a side surface of the mesa stripe structure 26, and a pad electrode 38 on an upper surface of the bank structure 30, connecting the ridge electrode 36 and the pad electrode 38. an electrode pattern 34 including a connection electrode 40, wherein the inner surface of the isolation groove 28 includes a first wall surface S1 adjacent to the first region R1, a second wall surface S2 adjacent to the second region R2, and a bottom surface S3 between the first region R1 and the second region R2, the ridge electrode 36 extends from the side of the mesa stripe structure 26 along a second direction D2 perpendicular to the first direction D1 toward the bank structure 30 so as not to exceed the second wall surface S2 of the isolation groove 28, and the connection electrode 40 is narrower in width in the first direction D1 than both the ridge electrode 36 and the pad electrode 38.

[0046] The ridge electrode 36 does not extend beyond the second wall surface S2 of the isolation groove 28, and the connection electrode 40 is narrower in width in the first direction D1 than both the ridge electrode 36 and the pad electrode 38, thereby preventing an increase in parasitic capacitance.

[0047] (2) A ridge-type semiconductor optical element according to (1), wherein the ridge electrode 236 extends over the first region R1 so as not to reach the inner surface of the isolation groove 228.

[0048] (3) A ridge-type semiconductor optical device according to (1), wherein the ridge electrode 36 has a part on the first wall surface S1 of the isolation groove 28.

[0049] (4) A ridge-type semiconductor optical device according to (3), wherein the ridge electrode 36 has another part on the bottom surface S3 of the isolation groove 28.

[0050] (5) A ridge-type semiconductor optical device according to (4), wherein the ridge electrode 36 has another part on the second wall surface S2 of the isolation groove 28.

[0051] (6) A ridge-type semiconductor optical device according to (4), wherein the ridge electrode 336 is not located on the second wall surface S2 of the isolation groove 328.

[0052] (7) A ridge-type semiconductor optical element according to any one of (1) to (6), wherein the ridge electrode 36 is made up of multiple layers including a stacked first layer L1 and a second layer L2.

[0053] (8) The ridge-type semiconductor optical device according to (7), wherein the second layer L2U overlaps only a portion of the first layer L1D.

[0054] (9) A ridge-type semiconductor optical element as described in (8), wherein the first layer L1D has a portion on the inner surface of the isolation groove 28, and the second layer L2U is not on the inner surface of the isolation groove 28.

[0055] (10) A ridge-type semiconductor optical device according to any one of (7) to (9), wherein the first layer L1D is a lower layer and the second layer L2U is an upper layer.

[0056] (11) A ridge-type semiconductor optical device according to any one of (7) to (9), wherein the first layer L1U is an upper layer and the second layer L2D is a lower layer.

[0057] (12) A ridge-type semiconductor optical element according to any one of (1) to (11), further comprising a passivation film 32 interposed between the laminate 12 and the electrode pattern 34, avoiding at least a portion of the upper surface of the mesa stripe structure 26.

[0058] (13) A ridge-type semiconductor optical element according to any one of (1) to (12), wherein the ridge electrode 36 has a uniform width in the first direction D1.

[0059] (14) A ridge-type semiconductor optical element according to any one of (1) to (13), wherein the first regions R1 are a pair of first regions R1 sandwiching the mesa stripe structure 26, the isolation grooves 28 are a pair of isolation grooves 28 respectively adjacent to the pair of first regions R1, the second regions R2 are a pair of second regions R2 respectively adjacent to the pair of isolation grooves 28, and the bank structures 30 are a pair of bank structures 30 respectively adjacent to the pair of second regions R2.

[0060] The present invention is not limited to the above-described embodiments and various modifications are possible. For example, the configurations described in the embodiments can be replaced with substantially the same configurations, configurations that achieve the same effects, or configurations that can achieve the same objectives. [Explanation of symbols]

[0061] 10 substrate, 12 stacked body, 14 buffer layer, 16 lower SCH layer, 18 active layer, 20 upper SCH layer, 22 cladding layer, 24 contact layer, 26 mesa stripe structure, 28 isolation groove, 30 bank structure, 32 passivation film, 34 electrode pattern, 36 ridge electrode, 38 pad electrode, 40 connection electrode, 42 back electrode, 212 stacked body, 226 mesa stripe structure, 228 isolation groove, 234 electrode pattern, 236 ridge electrode, 318 active layer, 328 isolation groove, 336 ridge electrode, 418 active layer, 428 isolation groove, 436 ridge electrode, 518 active layer, 528 isolation groove, 536 ridge electrode, D1 first direction, D2 second direction, L1 first layer, L1D 1st layer, L1U 1st layer, L2 2nd layer, L2D 2nd layer, L2U 2nd layer, R1 1st area, R2 2nd area, S1 1st wall, S2 2nd wall, S3 bottom.

Claims

1. a stack including an active layer or an absorption layer, an isolation trench separating the active layer or the absorption layer and extending in a first direction, and a first region and a second region adjacent to both sides of the isolation trench, respectively; a mesa stripe structure extending in the first direction on the stack adjacent to the first region; a bank structure extending in the first direction on the stack adjacent to the second region; an electrode pattern including a ridge electrode on the top surface and side surfaces of the mesa stripe structure, a pad electrode on the top surface of the bank structure, and a connection electrode connecting the ridge electrode and the pad electrode; and an inner surface of the isolation groove includes a first wall surface adjacent to the first region, a second wall surface adjacent to the second region, and a bottom surface between the first region and the second region; the ridge electrode extends beyond the side surface of the mesa stripe structure toward the bank structure along a second direction perpendicular to the first direction so as not to extend beyond the second wall surface of the isolation trench, the connection electrode is narrower in width in the first direction than both the ridge electrode and the pad electrode, the connecting electrode extends beyond the side surface of the mesa stripe structure along the second direction and connects to the ridge electrode at a position not extending beyond the second wall surface of the isolation groove;

2. 2. The ridge-type semiconductor optical device according to claim 1, The ridge electrode extends over the first region so as not to reach the inner surface of the isolation groove.

3. 2. The ridge-type semiconductor optical device according to claim 1, The ridge electrode has a portion on the first wall surface of the isolation groove.

4. 4. The ridge-type semiconductor optical device according to claim 3, The ridge electrode has another part on the bottom surface of the isolation groove.

5. 5. The ridge-type semiconductor optical device according to claim 4, The ridge electrode has another part on the second wall surface of the isolation groove.

6. 5. The ridge-type semiconductor optical device according to claim 4, The ridge electrode is not located on the second wall surface of the isolation groove.

7. 7. The ridge-type semiconductor optical device according to claim 1, The ridge electrode is a ridge-type semiconductor optical device made up of a plurality of layers including a first layer and a second layer that are stacked.

8. 8. The ridge-type semiconductor optical device according to claim 7, The second layer is a ridge-type semiconductor optical device that overlaps only a portion of the first layer.

9. 9. The ridge-type semiconductor optical device according to claim 8, the first layer has a portion on the inner surface of the isolation groove; The second layer is not on the inner surface of the isolation groove.

10. 10. The ridge-type semiconductor optical device according to claim 7, The first layer is a lower layer and the second layer is an upper layer.

11. 10. The ridge-type semiconductor optical device according to claim 7, The ridge-type semiconductor optical device has the first layer as an upper layer and the second layer as a lower layer.

12. 12. The ridge-type semiconductor optical device according to claim 1, The ridge-type semiconductor optical device further comprises a passivation film interposed between the laminate and the electrode pattern, avoiding at least a part of the upper surface of the mesa stripe structure.

13. 13. The ridge-type semiconductor optical device according to claim 1, The ridge electrode has a uniform width in the first direction.

14. 14. The ridge-type semiconductor optical device according to claim 1, the first regions are a pair of first regions sandwiching the mesa stripe structure, the isolation grooves are a pair of isolation grooves respectively adjacent to the pair of first regions, the second regions are a pair of second regions respectively adjacent to the pair of isolation trenches, The bank structure is a pair of bank structures respectively adjacent to the pair of second regions.

Images