Monitoring a memory location to identify whether data stored in the memory location has been modified

Abstract

The apparatus comprises address storage circuitry for storing indicators of memory locations in a first set of the shared memory, a capacity indicator for indicating whether the capacity of the address storage circuitry has been reached, and monitoring circuitry for monitoring a second set of memory locations in the shared memory identified in the first set of memory locations and the further storage circuitry to identify whether data stored in either set of memory locations has been modified, the monitoring circuitry responsive to determining that the data has been modified generates an indication that the data has been modified, and processing circuitry receives the indication and executes a monitor address instruction specifying an address of a new memory location in the shared memory, and updates the address storage circuitry or the further storage circuitry to indicate the new address in response to the capacity indicator.

Description

[Technical Field]

[0001] The present technology relates to the field of data processing.

[0002] In some data processing systems, multiple processing elements (e.g., multiple processing units or multiple sets of processing circuitry) access a shared structure via an interconnect. These shared structures may include a shared memory, and messages communicated between processing elements may be communicated via the shared memory. For example, one processing element may write a message for reception by another processing element to a memory location in a dedicated area of ​​the shared memory. The receiving processing element may then receive the message by accessing that memory location.

[0003] Looking at the first example of this technology, address storage circuitry for storing indices of memory locations in the first set of shared memory; a capacity indicator that indicates whether the capacity of the address storage circuitry has been reached; monitoring circuitry for monitoring the first set of memory locations and a second set of memory locations of the shared memory identified in the further storage circuitry to identify whether data stored in either set of memory locations has been modified, the monitoring circuitry generating an indication that the data has been modified in response to determining that the data has been modified; processing circuitry for receiving an indication that the data has been modified and for executing a watch address instruction specifying the address of a new memory location within the shared memory; determining whether the capacity of the address storage circuitry has been reached based on the capacity indicator; updating the address storage circuitry to indicate that a new memory location should be monitored by the monitoring circuitry in response to determining that the capacity of the address storage circuitry has not been reached; and processing circuitry for, in response to determining that the capacity of the address storage circuitry has been reached, updating the further storage circuitry to indicate that a new memory location should be monitored by the monitoring circuitry.

[0004] Looking at the second example of this technology, storing in address storage circuitry indexes of the first set of memory locations of the shared memory; providing a capacity indicator that indicates whether the capacity of the address storage circuitry has been reached; monitoring the first set of memory locations and a second set of memory locations of the shared memory identified in the further storage circuitry to identify whether data stored in either set of memory locations has been modified; generating an indication that the data has been modified in response to determining that the data has been modified; receiving, in the processing circuitry, an indication that the data has been modified; Execute a watch address instruction that specifies the address of a new memory location in shared memory, determining whether the capacity of the address storage circuitry has been reached based on the capacity indicator; updating the address storage circuitry to indicate that a new memory location should be monitored by the monitoring circuitry in response to determining that the capacity of the address storage circuitry has not been reached; and updating the further storage circuitry to indicate that a new memory location should be monitored in response to determining that the capacity of the address storage circuitry has been reached.

[0005] According to a third example of the present technology, there is provided a computer program for controlling a host data processing device to provide an instruction execution environment for executing target code, the computer program comprising: address storage program logic for maintaining an address storage structure in a memory or register of the host data processing device to store indices of memory locations of the first set of shared memory; capacity indicator program logic that maintains a capacity indicator in memory or a register to indicate whether the capacity of the address storage structure has been reached; monitor program logic for monitoring the first set of memory locations and a second set of memory locations identified in further storage circuitry maintained in memory or registers to identify whether data stored in either set of memory locations has been modified, and in response to determining that the data has been modified, generating an indication that the data has been modified; instruction decoding program logic for controlling a host data processing apparatus to decode instructions of the target code and perform data processing; The instruction decode program logic responds to a watch address instruction that specifies the address of a new memory location in the shared memory by: determining whether the capacity of the address storage structure has been reached based on the capacity indicator; updating the address storage structure to indicate that a new memory location should be monitored by the monitoring logic in response to determining that the capacity of the address storage structure has not been reached; A computer program is provided that, in response to determining that the capacity of the address storage structure circuitry has been reached, updates the further storage structure to indicate that new memory locations should be monitored by the monitoring logic.

[0006] Looking at the fourth example of this technology, means for storing indices of the first set of memory locations in the shared memory; means for indicating whether the capacity of the means for storing indices of the first set of memory locations has been reached; means for monitoring a second set of memory locations in the shared memory identified by the first set of memory locations and the means for further storing to identify whether data stored in either set of memory locations has been modified; means for generating an indication that the data has been modified in response to determining that the data has been modified; means for receiving an indication that the data has been modified; Execute a watch address instruction that specifies the address of a new memory location in shared memory, determining whether a capacity of the means for storing the indices of the first set of memory locations has been reached based on the capacity indicator; updating the means for storing indices of the first set of memory locations to indicate that new memory locations should be monitored by the means for monitoring in response to determining that the capacity of the means for storing indices of the first set of memory locations has not been reached; and means for updating the means for further storing to indicate that new memory locations should be monitored by the means for monitoring in response to determining that the capacity of the means for storing indices of the first set of memory locations has been reached. [Brief explanation of the drawings]

[0007] Further aspects, features, and advantages of the present technology will become apparent from the following description of examples, read in conjunction with the accompanying drawings. [Figure 1] 1 illustrates generally a system in which multiple processing elements access a shared memory via an interconnect. [Figure 2] 1 illustrates an example of address storage circuitry and further storage circuitry of the present technology, where the further storage circuitry comprises a cache. [Figure 3] 1 illustrates an example of a cache that includes a hardware transactional memory field. [Figure 4]1 illustrates an example of the address storage circuitry and further storage circuitry of the present technology, where the further storage circuitry comprises a register that stores a Bloom filter. [Figure 5A] FIG. 10 is a flow diagram illustrating the response of processing circuitry to a watch address command. [Figure 5B] FIG. 10 is a flow diagram illustrating the removal of a memory location from a first set of memory locations or a second set of memory locations. [Figure 6] FIG. 10 is a flow diagram illustrating the response of processing circuitry to a watch address instruction in an example using a Bloom filter. [Figure 7] FIG. 10 is a flow diagram illustrating the response of processing circuitry to a watch address instruction in an example using a cache. [Figure 8] Illustrates a virtual machine implementation of the present technology.

[0008] Before discussing the embodiments with reference to the accompanying drawings, the following description of exemplary embodiments and related advantages is provided.

[0009] When writing a message to a memory location in the shared memory, a technique for notifying a receiving processing element of a message sent by a sending processing element is to send an interrupt request to the receiving processing element. In this technique, the receiving processing element, in response to the interrupt request, stops execution of its current process and switches to execution of an interrupt service routine, which includes instructions that access the memory location in the shared memory to read the message written by the sending processing element. However, there can be a significant performance cost associated with this technique due to triggering the processing element to stop execution of its current process, particularly if the receiving processing element is executing instructions when the interrupt request is received. Additionally, this technique imposes constraints on the sending processing element; if the sending processing element is not configured to send an interrupt request in response to writing a message to a memory location, the receiving processing element will not be aware of the message and therefore will not read it.

[0010] Another approach is for the receiving processing element to periodically poll locations in shared memory where messages are expected to be written to determine whether the data at those locations has been modified. This avoids the need for the sending processing element to trigger an interrupt, but consumes a significant amount of energy. It also requires the receiving processing element to remain powered on even when its processing circuitry has no instructions to execute, further increasing the energy consumption of the data processing system.

[0011] The present technology aims to provide a more efficient approach to monitoring locations in shared memory without incurring the performance cost associated with triggering an interrupt when a message is written to the shared memory.

[0012] According to one exemplary configuration, address storage circuitry is provided that stores indices of a first set of memory locations of a shared memory. The address storage circuitry is configured, for example, to store addresses of the first set of memory locations that identify the first set of memory locations. Memory locations in the first set of memory locations are monitored by dedicated monitoring circuitry (e.g., separate from the processing circuitry) to identify any modifications to data stored in those locations. Providing separate monitoring circuitry for monitoring the first set of memory locations allows the processing circuitry to focus its resources on executing other processes. When there are no other processes for the processing circuitry to execute, providing separate monitoring circuitry allows the processing circuitry to enter a low-power mode, reducing its energy consumption.

[0013] However, the present inventors have recognized that a problem arises when the number of memory locations monitored by the monitoring circuitry exceeds the capacity of the address storage circuitry.

[0014] One approach to addressing this situation may be to default the system to processing circuitry monitoring memory locations by periodically polling these memory locations. Processing circuitry typically has access to more resources than monitoring circuitry, allowing it to monitor a much larger number of memory locations. However, as discussed above, this approach consumes a significant amount of energy.

[0015] An alternative approach could be to use monitoring circuitry and address storage circuitry to monitor some memory locations, while processing circuitry monitors other memory locations by polling those locations, however this still requires the processing circuitry to remain powered on even while not executing instructions, and therefore still consumes a significant amount of energy.

[0016] The present technology provides a more energy-efficient approach to monitoring memory locations. In particular, a second set of memory locations is identified in further storage circuitry, and monitoring circuitry monitors both the first set of memory locations and the second set of memory locations to identify whether data stored in either set of memory locations has been modified. The monitoring circuitry then generates an indication that the data has been modified in response to determining that the data has been modified, and processing circuitry is provided to receive the indication.

[0017] A capacity indicator is provided to indicate whether the capacity of the address storage structure has been reached. For example, the capacity indicator may be circuitry (e.g., circuitry that detects whether a particular entry in a table has a particular value (e.g., via an AND gate)) or an entry in a table or storage structure. The processing circuitry determines whether the capacity of the address storage circuitry has been reached based on the capacity indicator in response to a monitor address instruction that specifies a new memory location to be monitored by the monitor circuitry. When it is determined that the capacity of the address storage circuitry has not been reached, the processing circuitry updates the address storage circuitry to indicate that a new memory location should be monitored by the monitor circuitry (e.g., adds the new memory location to the first set of memory locations by storing an index of the new memory location in the address storage circuitry). When it is determined that the capacity of the address storage circuitry has been reached, the processing circuitry instead updates the further storage circuitry to indicate that a new memory location should be monitored by the monitor circuitry (e.g., adds the new memory location to the second set of memory locations).

[0018] The use of a capacity indicator that indicates when the capacity of the address storage circuitry is reached allows a second set of memory locations to be identified in the additional storage circuitry. This, in turn, allows the number of memory locations that can be monitored by the monitoring circuitry to be increased, which leads to significant power savings by reducing the likelihood that the processing circuitry will need to monitor the memory locations itself. The increase in circuit area required to implement this technique can be limited, especially if an existing memory structure is used to implement the additional storage circuitry (although this is not required, the additional storage circuitry could be an additional memory structure added to the device), as the addition of the capacity indicator adds a limited cost in terms of circuit area. Thus, significant power savings can be achieved while limiting the increase in cost associated with circuit area.

[0019] In some examples, the address storage circuitry includes a plurality of entries, each entry configured to store one of the indexes of the first set of memory locations, and the capacity indicator is configured to indicate that the capacity of the address storage circuitry has been reached unless the plurality of entries includes at least one available entry for storing an index of a new memory location.

[0020] For example, the capacity of the address storage circuitry is considered to be reached when there are no entries available in the address storage circuitry to store the index of a new memory location.

[0021] In some examples, the capacity indicator indicates whether the capacity of the address storage circuitry has been reached based on a value stored in the address storage circuitry.

[0022] For example, when the address storage circuitry includes multiple entries, one of the entries is used to indicate whether the capacity of the address storage circuitry is full by storing a particular value (e.g., a single bit—1 or 0) depending on whether the capacity of the storage circuitry has been reached. Using an entry in the address storage circuitry to implement the capacity indicator allows the technique, and in particular the capacity indicator, to be implemented with only a small increase in the size of the address storage circuitry (e.g., by a single entry, or by only a single bit if the capacity is indicated by 1 or 0). This allows the overall capacity for monitoring addresses to increase by a significant amount, limiting the increase in circuit area (e.g., the number of memory locations that the monitoring circuitry can monitor increases by multiple (e.g., two or more) memory locations, limiting the increase in the size of the address storage circuitry).

[0023] In some examples, the monitoring circuitry is configured to identify that the data has been modified in response to receiving a snoop request that identifies a memory location in the first set or the second set.

[0024] In these examples, the snoop request may be used as an indicator that data in the shared memory has been modified and that corresponding entries in any caches controlled by the processing circuitry should be updated or invalidated in order to maintain cache coherency. Leveraging existing cache coherency systems (e.g., snoop requests) allows the present technique to be easily implemented in typical systems.

[0025] In some examples, the further storage circuitry is configured to store the indices of the second set of memory locations in a format that differs from the indices of the first set of memory locations stored in the address storage circuitry.

[0026] For example, the further storage circuitry is not a separate address storage circuitry having the same configuration as the address storage circuitry or an additional entry added to the address storage circuitry, but instead is additional, different storage circuitry that stores indexes of the second set of memory locations in a format that differs from the indexes of the first set of memory locations indicated in the address storage circuitry. The different format is a different configuration of bits used to indicate each memory location; for example, one format may store the full memory address, another format may indicate the memory address with flags set in a cache, while yet another format may include merging the memory address with a Bloom filter. By storing the second set of memory locations in a format that differs from the first set of memory locations, these examples provide flexibility to store the indexes of the second set of memory locations in a more space-efficient manner and / or in a manner that utilizes existing structures within a processing system.

[0027] In some examples, the additional storage circuitry comprises a cache.

[0028] The cache in these examples is not a dedicated cache for identifying the second set of memory locations, but rather a general-purpose cache in the processing system, such as a data cache. An example of a general-purpose cache includes a data cache that stores indexes of memory locations in a shared memory and copies of data retrieved from those locations. This approach of using a cache to represent the second set of memory locations allows existing storage structures in the processing system (e.g., general-purpose caches such as data caches) to be used as additional storage circuitry. As such, the technique can be implemented with a limited increase in circuit area.

[0029] In some examples, the cache includes a plurality of entries indicating the second set of memory locations, each of the entries associated with a tag, and during execution of the monitor address instruction, the processing circuitry is configured to update the cache to indicate that the new memory location should be monitored by setting the tag associated with the new entry indicating the new memory location to a predetermined value.

[0030] For example, the tag is a field associated with each entry, e.g., a field that stores a single bit that is set to a particular value (e.g., 1 or 0) depending on whether the associated memory location is within the second set of memory locations. This approach allows the second set of memory locations to be identified using existing caches with limited modifications (e.g., adding a single field (in some examples, a single bit) to each entry), making the technique easy to implement in typical processing systems and requiring only a limited increase in circuit area.

[0031] In some examples, the tag is stored in a transactional memory field configured to indicate whether a cached memory location associated with the tag has been accessed by the processing circuitry during execution of the current transaction or will be accessed by the processing circuitry upon completion of execution of the current transaction.

[0032] For example, a transaction is a group of instructions that are executed atomically by processing circuitry. To maintain the atomicity of a transaction, the processing circuitry maintains a record of addresses read by instructions in the transaction (a read set of addresses) and / or addresses to which the processing circuitry will write data upon completion of the transaction (a write set of addresses). This allows the processing circuitry to monitor whether memory locations accessed in response to the transaction are accessed by other processes before the transaction is completed, thereby preventing the instructions in the transaction from executing atomically. In a cache having a transactional memory field, the read set and / or write set are identified in the transactional memory field (e.g., by setting the value stored in the transactional memory field to a particular value). In these examples of the present technology, all or a portion of the transactional memory field (e.g., a read set indicator, a write set indicator, or both) is reused as a tag to indicate whether a cached memory location is within a second set of memory locations. This allows the second set of memory locations to be identified without increasing the size of the cache, thus allowing the present technology to be implemented with a limited increase in circuit area.

[0033] One might find reusing transactional memory fields in this manner counterintuitive, as one would expect that transactional memory fields should be kept available to process transactions. However, the inventors have recognized that in practice transactions may be infrequent for some processors, and therefore reusing transactional memory fields may not necessarily have a significant impact on system performance. In particular examples, when a transaction is executed, the processing circuitry defaults to clearing the transactional memory fields and monitoring a second set of memory locations by continuously polling the shared memory.

[0034] In some examples, in response to a snoop request identifying a given memory location, the monitoring circuitry identifies that data has been modified based on whether the given memory location is indicated in the address storage circuitry as being in a first set of memory locations or whether it is tagged in the cache as being in a second set of memory locations.

[0035] As described above, this utilization of existing cache coherency systems (e.g., snoop requests) allows the present technology to be easily implemented in a typical processing system. Checking whether a given memory location identified by a snoop request is part of the first set of memory locations involves checking the given memory location against the index of the first set of memory locations stored in the address storage circuitry, for example, by accessing the address storage circuitry and checking whether one of the sorted indexes in the address storage circuitry matches the index of the given address. Meanwhile, checking whether a given memory location is within the second set of memory locations involves identifying whether the given memory location is present in (for example) a cache, and if so, determining whether a tag associated with that entry is set.

[0036] In some examples, the cache is a level 1 data cache.

[0037] It will be understood that this is an implementation detail, and in practice any cache may be used for this purpose. The level 1 data cache is the cache closest to the processing circuitry and is therefore typically faster to access than other caches further down the memory hierarchy. Thus, using the level 1 data cache as additional storage circuitry reduces the time it takes to check whether a given memory location is part of the second set of memory locations, leading to improved system performance.

[0038] In some examples, the additional storage circuitry comprises a register.

[0039] Because registers typically do not occupy a large amount of space (a single register is typically configured to store a single operand), using registers as an additional storage structure limits the circuit area required to implement the present techniques. A particularly space-efficient approach is to utilize existing registers in the system. In some exemplary situations (e.g., when the processing circuitry is in a low power state), the processing circuitry does not utilize all of the available registers, but leaves at least one register available to identify the second set of memory locations.

[0040] In some examples, the register is configured to store a Bloom filter that identifies the second set of memory locations.

[0041] A Bloom filter is a probabilistic data structure in which indicator memory locations can be tested to determine, for example, whether the indicator memory location is part of a second set of memory locations identified by the Bloom filter. Typically, testing a value against a Bloom filter can result in a false positive (e.g., an erroneous determination that a memory location is part of the second set) but not a false negative. Bloom filters are a particularly space-efficient format for identifying a set of data values ​​(e.g., a single register can be used to identify multiple memory locations), which makes it possible to limit the increase in circuit area required to implement these examples of the present technology. In practice, it is typical to limit the number of data values ​​added to a Bloom filter because the likelihood of false positives increases as the number of values ​​in the Bloom filter increases, but in fact the number of data values ​​that can be identified by a Bloom filter stored in a single register is theoretically unlimited. The time it takes to determine whether a value is part of the set of values ​​represented by the Bloom filter (e.g., the time it takes to determine whether a memory location is part of the second set of locations) is constant regardless of how many values ​​are represented. This means that there is also a time advantage associated with using Bloom filters, so the amount of processing time spent checking whether a memory location is one of the memory locations in the second set can be done deterministically and is in most cases reduced compared to other techniques. Therefore, using Bloom filters in this way also allows for improved system performance.

[0042] In some examples, the Bloom filter includes a bit array, and during execution of the watch address instruction, the processing circuitry, in response to determining that the capacity of the address storage circuitry has been reached, applies at least one hash function to an index of the new memory location to identify a plurality of bit positions in the Bloom filter, and sets each of the plurality of bit positions to a predetermined value.

[0043] The Bloom filter in such an example is an array (e.g., a set, series) of 1s and 0s stored in a register, and each hash function maps an input value (e.g., an index of a new memory location, such as an address or portion of an address) to a single bit location (bit position) in the array or to multiple bit positions in the array, each of which is set to a predetermined value (e.g., 1 or 0) when the input value is added to the set. Thus, adding a new memory location to a second set of memory locations is a relatively simple operation, requiring only a small number of bits in the register to be updated. As noted above, this approach is also particularly space-efficient due to the fact that a single register can be used to identify multiple memory locations.

[0044] In some examples, the monitoring circuitry determines that the data has been modified in response to at least one of: determining that the first set of memory locations includes the given memory location when an index of the given memory location matches an index stored in the address storage circuitry in response to a snoop request identifying the given memory location; and determining that the second set of memory locations includes the given memory location based on testing the index of the given memory location against a Bloom filter.

[0045] As discussed above, testing a memory location against a Bloom filter allows a determination to be made that the memory location is not or may be within the second set of memory locations; e.g., false positives are possible, but no false negatives. However, false positives are not particularly problematic in these examples because they do not affect the functional correctness of the system. That is, while system performance is slightly affected by false positives due to the processing circuitry unnecessarily accessing memory locations that are not actually modified, this does not prevent the processing circuitry from operating correctly. Checking whether a given memory location identified by a snoop request is part of the first set of memory locations involves checking the given memory location against the indexes of the first set of memory locations stored in the address storage circuitry, for example, by accessing the address storage circuitry and checking whether one of the sorted indexes in the address storage circuitry matches the index of the given address. Checking whether a given memory location is potentially part of the second set of memory locations identified by the Bloom filter involves testing the index of the given memory location against the Bloom filter, for example, by applying the same hash used to add the memory location to the second set, and checking whether the bit position identified by the hash is set to a predetermined value. Thus, the time it takes to check whether a given memory location is potentially part of the second set (and the associated performance impact) is constant regardless of how many memory locations are included in the second set.

[0046] In some examples, the monitoring circuitry is separate from the processing circuitry.

[0047] For example, the monitoring circuitry is a separate hardware structure from the processing circuitry. This allows the processing circuitry to focus on executing instructions rather than monitoring the first and second sets of memory locations, thereby improving system performance. Alternatively, having the monitoring circuitry as a separate piece of hardware allows the processing circuitry to enter a low power mode when it has no instructions to execute, reducing its power consumption while allowing the monitored addresses to continue to be monitored.

[0048] In some examples, the processing circuitry, in response to a wait for event command, enters a low power state until an event indicator is received by the processing circuitry.

[0049] For example, the processing circuitry may enter a low power state (e.g., a standby state, a power saving mode) without the monitoring circuitry entering a low power state, which is possible because the monitoring circuitry is separate from the processing circuitry. By allowing the processing circuitry to enter a low power state while the monitoring circuitry continues to monitor the first and second sets of memory locations, system power consumption may be reduced (e.g., because the monitoring circuitry is dedicated circuitry for monitoring the first and second sets of addresses, its power consumption means that it is likely to be lower than the power consumption of processing circuitry adapted to perform a wider range of operations).

[0050] In some examples, the event indication includes an indication that the data was modified.

[0051] For example, the processing circuitry may be configured to exit the low power state in response to receiving an indication that the data has been modified. This allows for reduced power consumption (by allowing the processing circuitry to enter the low power state) while still allowing the processing circuitry to be notified of any modifications to the data stored in the first and second sets of locations.

[0052] In some examples, the first set of memory locations and the second set of memory locations include memory locations to which the other set of processing circuitry can write messages that are read by the processing circuitry.

[0053] In a system comprising multiple processing units (e.g., multiple processing circuitry, also referred to as processing elements), all having access to a shared memory, the processing units can send messages to each other by writing the messages to particular areas of the shared memory. A receiving processing unit receives the messages by accessing the associated memory location. It is therefore beneficial for the processing circuitry to be notified whenever data in the particular area is modified. Thus, in these examples, the first and second sets of memory locations are memory locations to which other processing elements can write messages to be read by the processing circuitry, and the provision of monitoring circuitry to monitor these memory locations therefore enables the processing circuitry to be notified when a message is written to memory by another processing element.

[0054] In some examples, the first set of memory locations and the second set of memory locations each include non-contiguous memory locations.

[0055] Thus, the first and second sets of memory locations include one or more "gaps" in the memory location addresses, meaning that the memory locations are identified separately (e.g., are not part of a range).

[0056] In a specific example, if a memory region includes address locations A, B, D, E, or D, B, and all of these sets include one or more gaps between the starting and ending addresses, a first set of non-contiguous memory locations can be defined as {A, B, E}, or {B, D, E}, or {A, B, C, E}. Such sets cannot include {A, B, C} or {D, E, F}, because they do not include such gaps. That is, the first and second sets of memory locations cannot be completely defined using a single address range with a starting point and an ending point.

[0057] Because non-contiguous memory locations are independently identified, each new memory location to be monitored by the monitoring circuitry requires the addition of new data to the address storage circuitry or additional storage circuitry (e.g., storing a new index for the new memory location). This technique allows for an increase in the number of independently identified, non-contiguous (e.g., discontinuous, disjoint) memory locations that can be monitored by the monitoring circuitry.

[0058] In some examples, during execution of the watch address instruction, following updating the address storage circuitry to indicate that a new memory location should be monitored by the watch circuitry, the processing circuitry is configured to check whether the capacity of the address storage circuitry has now been reached, and in response to determining that the capacity of the address storage circuitry has been reached, the processing circuitry is configured to update the capacity indicator to indicate that the capacity of the address storage circuitry has been reached.

[0059] For example, each time a new memory location is added to the first set of memory locations, the processing circuitry checks whether the address storage circuitry has consequently reached its capacity and sets the capacity indicator accordingly, which allows the accuracy of the capacity indicator to be maintained.

[0060] Specific embodiments will now be described with reference to the drawings.

[0061] FIG. 1 schematically illustrates one example of a data processing system 2 in which the techniques described herein may be used. The system 2 has multiple processing elements 4, 6 that share access to a memory 8. In this example, the processing elements include two central processing units (CPUs) 4 and a network interface controller (NIC) 6, although it will be understood that this is merely an example and that many other types of processing elements may be provided, such as a graphics processing unit (GPU), a display controller, a direct memory access (DMA) controller, a peripheral input / output (I / O) controller, etc. The CPUs 4, 6 are examples of processing circuitry that receives indications that data has been modified and executes watch address instructions, and main memory 8 is an example of shared memory. A coherent interconnect 10 is provided to manage coherency between the respective processing elements 4, 6 according to a coherency protocol. Some processing elements, such as CPU 4, have one or more caches 12, 13 for caching instructions or data from a memory system (e.g., from main memory 8). 1 illustrates each CPU 4 with a single level 1 data cache 12 and a single level 1 instruction cache 13 for simplicity, although a given processing element may have multiple levels of cache (e.g., a level 1 cache and a level 2 cache). The device also includes at least one system-level cache 14, coupled, for example, to interconnect 10, that is not assigned to a particular processing element but is located closer to the memory system. System cache 14 may be used to speed up accesses to the memory system by uncached processing elements, such as network interface controller 6, that do not have a cache themselves.

[0062] Interconnect 10 has snoop filters 16 that track which caches hold data from a particular address. Snoop filters 16 may be exact or may use a more approximate representation (e.g., a filter representation) that allows for some false-positive detections that a given address is cached in a particular cache, but not false-negatives (when the data is cached but not detected by the filter). Upon detecting a read or write access from a given processing element to a given address, coherent interconnect 10 consults snoop filters 16 for the corresponding address, identifies any caches that may hold the data, and, if necessary, sends snoop requests to the corresponding caches to query the coherency state of the data held by those caches, returning the corresponding data value and / or triggering an invalidation. A coherency protocol defines what response should be taken for a particular type of transaction when the data is held in a cache in a particular coherency state. For example, when data is cached in a shared state indicating that coherency should be maintained with corresponding data in other caches, a write to the shared data by one processing element triggers invalidation of corresponding data in caches elsewhere in the system to prevent other processing elements from accessing potentially out-of-date information. Thus, interconnect 10 can exchange various coherency protocol transactions (such as read, write, or snoop transactions) with each cache or processing element.

[0063] Some software processes running on one of the CPUs 4 need to quickly and efficiently multiplex many communication streams received from other actors. These communication streams may come, for example, from other processing elements 4 updating shared memory, from external sources via network interface controller 6 or peripheral I / O devices, or from another software process (e.g., another virtual machine) running on the same processing element. For example, another processing element 4 may send a message to one of the CPUs by writing data to a specific area of ​​shared memory 8. To avoid software processes having to continuously poll a large number of memory locations (e.g., to check for messages from other processing elements), each CPU 4 of FIG. 1 is provided with address storage circuitry 20 for storing monitoring data defining a first set of memory locations in shared memory 8 that should be monitored for changes, and monitoring circuitry 22 for monitoring accesses to the memory system. When a change to the data in one of the memory locations indicated in address storage circuitry 20 is detected by monitoring circuitry 22, monitoring circuitry 22 sends an interrupt to the corresponding CPU 4 notifying CPU 4 that the data stored at one of the monitored addresses has changed, the interrupt being an example of an indication that the data has been modified. Address storage circuitry 20 is an example of address storage circuitry that stores an index of a first set of memory locations in a shared memory and can store monitoring data that independently define multiple non-contiguous memory locations, allowing multiple memory locations to be monitored for changes in parallel. Monitoring circuitry 22 is an example of monitoring circuitry that monitors the first set of memory locations and a second set of memory locations in the shared memory identified in the further storage circuitry to identify whether data stored in either set of memory locations has been modified.

[0064] At the architectural level, processing circuitry (CPU) 4 supports a number of instructions in the instruction set architecture that control the setting and clearing of watchdog data in address storage circuitry 20 and the reporting of which regions have changed. An instruction decoder in each processor 4 may, for example, detect the opcode of an instruction fetched for processing and, when a watchdog address instruction (discussed below) is encountered, control processing circuitry 4 to trigger an update of data in address storage circuitry 20. The instruction decoder may also control the processing circuitry to request a report from watchdog circuitry 22 of which memory locations have changed.

[0065] Thus, a watch address instruction is provided to enable the CPU 4 to register memory locations in the CPU local watch store (address storage circuitry) 20, and the corresponding watch circuitry 22 can watch for changes to those locations while the CPU is in low power mode and wait to be notified of those changes so as not to miss any changes; this is possible because the watch circuitry 22 is separate from the CPU 4, and therefore can continue to watch memory locations while the CPU is in low power mode.

[0066] Using a wait-for-event (WFE) instruction, the processor can be switched into a power saving state (e.g., low power or standby mode), and the processor 4 then waits for the monitoring circuitry 22 to signal that a change has been detected. When the monitoring circuitry 22 notifies the processor that an event has occurred, an index (e.g., address) of the memory location where the change was detected is added to a buffer or log of addresses to be accessed by the processing circuitry.

[0067] 1, each processing element 4 that can establish a request for monitoring of a memory location is provided with its own separate address storage circuitry 20 and monitoring circuitry 22. This allows the address storage circuitry to be integrated into the coherency scheme managed by coherent interconnect 10, such that entries in address storage circuitry 20, in some examples, are tagged with a coherency state according to an associated coherency protocol and are snooped in response to changes to the data at the corresponding address. Furthermore, in addition to (or instead of) actively monitoring memory locations, monitoring circuitry 22 may also be configured to intercept snoop requests sent by coherent interconnect 12 to identify modified memory locations.

[0068] The inventors have recognized that when the capacity of address storage circuitry 20 is reached, a problem can arise if a watch address instruction is executed by processing circuitry 4 that specifies a new address to be monitored by watch circuitry 22. In this situation, watch circuitry 22 would not be able to monitor the new memory location specified by the watch address instruction without, for example, sacrificing one of the memory locations currently being monitored. Thus, the performance advantage provided by watch circuitry 22 and address storage circuitry 20 is only provided until the capacity of address storage circuitry 20 is exceeded.

[0069] To address this problem, one could increase the size of address storage circuitry 20 or provide additional storage circuitry for storing address watch data, however this would come at the cost of a significant increase in circuit area.

[0070] Instead, the present technology addresses this issue by identifying any additional memory locations to be monitored in a different format in an existing storage structure, such as a cache, or in a register. As explained in the following example, the different format is a different configuration of bits used to identify the memory locations. For example, a first set of memory locations may be identified in the form of full memory addresses, while a second set of memory addresses may be identified in a Bloom filter or as a tag set in a cache. Thus, monitoring circuitry 22 monitors two sets of memory locations: a first set of memory locations identified by address monitoring data stored in address storage circuitry 20 and a second set of addresses identified in additional storage circuitry. For example, the additional storage circuitry may include data cache 12 or a register. This approach allows for a significant increase in the number of memory locations that can be monitored by monitoring circuitry 22 without significantly increasing the circuit area.

[0071] The additional storage circuitry may be implemented in any of several ways. For example, Figure 2 schematically illustrates an example in which the additional storage circuitry comprises a cache 24. For example, this may be the level 1 data cache 12 shown in Figure 1, although it will be understood that other caches within the system may also be used.

[0072] As shown in Figure 2, address storage circuitry 20 is provided to store indices of a first set of memory locations within the shared memory that are monitored by monitoring circuitry 22. The indices may take any form, but in this example are addresses.

[0073] The address storage circuitry 20 has a plurality of entries 30, each entry 30 configured to store the address of a memory location within the first set of memory locations monitored by the monitoring circuitry. These addresses may be physical addresses that directly identify locations within the shared memory, or they may be virtual addresses that need to be translated to a physical address (e.g., in a memory management unit (MMU)) before the corresponding memory location can be accessed.

[0074] The address storage circuitry 20 also includes a capacity indicator 32 that indicates whether the capacity of the address storage circuitry 20 has been reached. In this example, the capacity indicator 32 is a value that is stored in an additional entry (specifically, the last entry) in the address storage circuitry 20 and is set to a predetermined value when the capacity is reached. For example, when the capacity of the address storage circuitry 20 is reached (e.g., when each entry 30 stores a valid address to be monitored), the capacity indicator 32 may be set to 1, and when the capacity has not been reached, the capacity indicator 32 may be set to 0 or may be used to store an entry. However, it will be understood that this is only one example of a value that may be used, and that in practice, any value may be used to indicate whether the capacity of the address storage circuitry 20 has been reached. The capacity indicator 32 is an example of a capacity indicator that indicates whether the capacity of the address storage circuitry 20 has been reached.

[0075] FIG. 2 also illustrates a cache 24. The cache 24 includes a plurality of entries 34, each of which includes an address field 36 representing a memory location in the shared memory and a data field 38 that stores a cached copy of the data stored at the corresponding memory location. It will be appreciated that the cache 24 need not necessarily store full addresses but may instead store an indication of the memory location in another form. While not shown, in some examples, each cache entry 34 also includes one or more coherency fields that indicate the coherency state of each entry 34. The cache 24 shown in the example of FIG. 2 is a set-associative cache with four ways in each set. However, it will be appreciated that this is merely an example, and any type of cache (e.g., a fully associative cache, or a direct-mapped cache, or a cache with another number of ways) may be used. Each entry 34 also includes a monitor field 40 (or monitor bit) that indicates whether the memory location identified by the address stored in the address field of that cache line is one of a second set of memory locations that should be monitored by monitor circuitry. In some examples, monitor field 40 stores a single bit that is set to a first value (e.g., 0) to indicate that the memory location identified in a given entry is not part of the second set of memory locations, or that is set to a second value (e.g., 1) to indicate that the memory location is part of the second set. By adding monitor field 40 in this manner, an existing cache 24 (e.g., a level 1 data cache) in a system can be adapted to indicate the second set of memory locations that are monitored by the monitor circuitry without significantly increasing the circuit area; in this example, the size of the cache only needs to be expanded by a single bit for each entry.

[0076] Monitoring circuitry (not shown) is then configured to monitor both the first set of memory locations (identified by the addresses stored in address storage circuitry 20) and the second set of memory locations (identified by modification field 40 in cache 24) for changes to the data stored in those memory locations.

[0077] 2, the new memory location is at "Address X," it first checks whether capacity indicator 32 indicates that the capacity of address storage circuitry 20 has been reached. If capacity indicator 32 indicates that the capacity of address storage circuitry 20 has not been reached (e.g., capacity indicator 32 is set to 0), the processing circuitry adds the new memory location to the first set of memory locations by storing the address (Address X) in an available entry 30 of address storage circuitry 20. On the other hand, if capacity indicator 32 indicates that the capacity of address storage circuitry 20 has been reached, the processing circuitry instead identifies the new memory location in cache 24 and adds the new memory location to the second set of memory locations by setting the corresponding monitoring field 40 to a predetermined value (e.g., 1).

[0078] In this way, with only a small increase in circuit area (adding a single entry to address storage circuitry 20 to provide capacity indicator 32 and adding a single field 40 to each entry in cache 24), the number of non-contiguous memory locations that can be monitored by the monitoring circuitry can be greatly increased.

[0079] The increase in circuit area required to implement the present technique can be further reduced by reusing existing fields in the cache 24 to provide the monitoring field 40. For example, FIG. 3 shows the cache 24 including one or more transactional memory fields 42, 44. These fields are used to track whether an address is part of a read set or a write set of addresses being tracked by the processing circuitry during the execution of a transaction. A transaction is a block of instructions executed atomically by the processing circuitry, and any updates to memory (e.g., stores) are committed at the end of the transaction only if the other instructions in the transaction have executed successfully. Memory locations accessed by the processing circuitry during the execution of a transaction are tracked to determine whether they were accessed by another process during the execution of the transaction. In this example, the processing circuitry tracks a read set of addresses corresponding to memory locations that received a read access as part of the transaction and a write set of addresses corresponding to memory locations that will be written upon completion of the transaction.

[0080] In some examples of the present technology, one or both of the transactional memory fields 42, 44 are reused for use as monitoring fields, allowing memory locations in the second set to be identified in the cache 12 without increasing the size of the cache.

[0081] It may seem counterintuitive to reuse transactional memory fields in this manner, as it would be expected to have a negative impact on the processing of transactions. However, in some situations, transactions are infrequent, in which case transactional memory fields 42 and 44 are not used often. For example, when processing circuitry is placed in a low power state, the processing circuitry is not processing transactions and therefore will not utilize transactional memory fields 42, 44. Therefore, the fields may be reused at this point with little or no cost.

[0082] When the processing circuitry processes a transaction, it may clear all of the transactional memory fields and default to monitoring memory locations in the second set by continuously polling the shared memory. Alternatively, if only one of the transactional memory fields 42, 44 is used to indicate a memory location in the second set, the processing circuitry may process the transaction using the other transactional memory field. For example, if a memory location in the read set is accessed during a transaction, this indicates that the data read from that location during the transaction was potentially out of date, so it is often more important to monitor addresses in the read set than in the write set. Thus, in some instances, the processing circuitry reuses the write set field 44 to indicate a memory location in the second set and continues to process the transaction using the read set field 42.

[0083] Another example of how the additional storage circuitry for identifying the second set of memory locations may be implemented is through the use of registers. Figure 4 shows an example of this technique in which the second set of memory locations is identified using a Bloom filter 46 stored in a register 48.

[0084] A Bloom filter is a probabilistic data structure that can be used to test whether an element (e.g., a data value) is likely to be part of a set. Typically, false positives are possible, but not false negatives; e.g., testing a value against a Bloom filter determines whether the value is definitely not in the set or potentially in the set. In this example, Bloom filter 46 is a bit array stored in register 48. Processing circuitry adds data values ​​to the set of values ​​represented by Bloom filter 46 by applying multiple different hash functions 47 to the data values, the results of which identify a set of bit positions in the bit array (e.g., each hash function 47 identifies one or more bit positions). Processing circuitry then sets each bit position identified by the hash functions to a set value (e.g., 1). To check whether a value is likely to be part of the set identified by the Bloom filter, processing circuitry applies the same hash function to the value and checks whether the bits identified by the hash functions are set to a predetermined value.

[0085] In the example shown in FIG. 4, when a watch address instruction identifying a given address (address X) is executed by processing circuitry, if capacity indicator 32 indicates that the capacity of address storage circuitry 20 has been reached, the processing circuitry merges the address into Bloom filter 46 stored in register 48 (e.g., by applying a set of hash functions 47 to the address and setting bits identified by hash functions 47 to predetermined values).

[0086] Bloom filters are space-efficient storage structures, capable of storing a large number of data values ​​in a small amount of space. In this example, the second set of memory locations to be monitored by the monitoring circuitry can be indicated using a single register 48. This allows for a significant expansion of the number of memory locations that can be monitored by the monitoring circuitry without a significant increase in circuit area. Furthermore, the time it takes to test whether an element is part of the set of elements represented by the Bloom filter remains constant, no matter how many elements are in the set. Therefore, using Bloom filter 46 to identify the addresses of the second set also saves processing time.

[0087] In some examples, register 48 is one of an existing set of registers accessible to the processing circuitry, which further reduces the circuit area required to implement the present techniques.

[0088] In the examples described so far, the first set of memory locations and the second set of memory locations monitored by the monitoring circuitry are identified using their associated memory addresses, e.g., address storage circuitry 20 and cache 24 store the addresses of the first and second sets of memory locations, and the addresses of the second set of memory locations are input values ​​merged into Bloom and are identified in a different format.

[0089] FIG. 5A is a flow diagram illustrating an example of the response of the processing circuitry of the present technology to a watch address command.

[0090] The method begins at step S60, in which the processing circuitry determines whether a new memory location should be monitored by the monitoring circuitry. For example, the processing circuitry determines whether a monitor address command has been received. When the processing circuitry determines that a new memory location should be monitored, the processing circuitry determines whether the capacity of the address storage circuitry has been reached (S62). For example, the processing circuitry checks whether a capacity indicator is set to a predetermined value. If capacity has been reached, the processing circuitry indicates the new memory location in a cache or Bloom filter (S64), according to the examples described above, before returning to step S60.

[0091] On the other hand, if the capacity of the address storage circuitry has not been reached, the processing circuitry adds an index of the new memory location (e.g., address) to the address storage circuitry (S66). The processing circuitry then checks whether the capacity of the address storage circuitry has been reached (S68) following the addition of the new memory location. If the capacity of the address storage circuitry has not been reached, the method returns to S60. On the other hand, if capacity has been reached, the processing circuitry updates the capacity indicator to indicate that the capacity of the address storage circuitry has been reached (S70) before returning to step S60. Collectively, steps S66, S68 and S70 form step S73 of updating the address storage circuitry.

[0092] 5B is a flow diagram illustrating the removal of a memory location from a first set of memory locations or a second set of memory locations. This may be in response to, for example, a specific end monitoring instruction that specifies a memory location that should no longer be monitored. In this example, the memory address of the second set is represented in the cache.

[0093] The method begins with step S61, which determines whether a memory location should be removed from the first set of memory locations or the second set of memory locations. When it is determined that a memory location should be removed, it is determined whether the memory location in question is in the first set of memory locations (as indicated in the address storage circuitry) or in the second set of memory locations (as indicated in the further storage circuitry) (S63). When the memory location is indicated in the first set, the memory location is removed from the address storage circuitry (S67). It is then determined whether a capacity indicator indicates that the capacity of the address storage structure has been reached (S69). If the capacity indicator does not indicate that capacity has been reached, the method returns to step S61. If the capacity indicator indicates that capacity has been reached, the capacity indicator is updated to indicate that the capacity of the address storage circuitry is no longer reached (due to the removal of the memory location from the address storage circuitry) (S71), and the method returns to step S61.

[0094] Returning to step S63, if it is determined that the memory location is not in the first set (e.g., it is in the second set), the watchdog tag in the cache line corresponding to the memory location to be removed is cleared (S65) before the method returns to step S61. As noted above, this example assumes that a memory location of the second set is represented in the cache. If the second set were instead represented in the Bloom filter, the entry could not be removed from the Bloom filter, so the method returns directly to step S61 when the memory location is determined to be in the second set. In this case, a false positive result would be returned whenever the memory location is tested against the Bloom filter.

[0095] 6 is a flow diagram illustrating a method performed by processing circuitry in accordance with some examples of the present technology. The method begins at step S60, where the processing circuitry determines whether a new memory location should be monitored by the monitoring circuitry. If the processing circuitry determines that there are no new memory locations to monitor (e.g., if a monitor address command is not received), the method proceeds directly to step S74, where the processing circuitry determines whether a wait for event (WFE) command has been received.

[0096] On the other hand, if the processing circuitry determines that there is a new memory location to be monitored (e.g., a monitor address command has been received), the processing circuitry determines whether the capacity of the address storage circuitry has been reached (S62) (e.g., by checking whether a capacity indicator has a predetermined value). If capacity has not been reached, the processing circuitry updates the address storage circuitry (S73) before proceeding to step S74. While steps S668, S68, and S70 are not explicitly shown in Figures 6 and 7, it will be understood that these steps are all present as part of step S73. On the other hand, if the capacity of the address storage circuitry has been reached, the processing circuitry instead merges the indicator of the new memory location into the Bloom filter (S72) before proceeding to step S74.

[0097] In step S74, the processing circuitry determines whether a WFE command has been received. If a WFE command has not been received, the method returns to step S60. On the other hand, if a WFE command has been received, the processing circuitry executes the WFE command by determining (S76) whether an event has already occurred (e.g., data in one of the memory locations monitored by the monitoring circuitry has changed). If an event has already occurred, the method moves to step S84.

[0098] If an event has not yet occurred, the processing circuitry enters a power saving mode (e.g., a low power state or a standby state) while the monitoring circuitry continues to monitor the first and second sets of memory locations (S78). The processing circuitry remains in the power saving mode until it determines that an event notification has been received (S80). The event notification in this example includes an indication generated by the monitoring circuitry that data in one of the memory locations being monitored by the monitoring circuitry has been modified, which may mean, for example, that a message from another processing circuitry has been written to the memory location. The processing circuitry repeats steps S78 and S80 until an event notification is received.

[0099] When an event notification is received, the processing circuitry exits the power saving state (S82). In step S84, the processing circuitry then identifies which, if any, memory regions have been modified. The processing circuitry determines whether any memory regions have been modified (S86), and if no regions have been modified, returns to step S74. On the other hand, if one or more memory regions have changed, the processing circuitry adds the addresses of the changed memory locations to a log of addresses processed by the processing circuitry (S88).

[0100] FIG. 7 is a flow diagram illustrating an alternative method performed by processing circuitry. The method of FIG. 7 is identical to the method of FIG. 6, except that when the processing circuitry determines that the capacity of the storage circuitry has been reached (S62), the processing circuitry tags the memory location as being monitored in the cache (S94) (e.g., by setting a monitor field in the cache to a predetermined value). Optionally, as indicated by the dashed line, the processing circuitry may first check whether the memory location is recorded in the cache (S90) and, if not, replace the entry in the cache according to normal cache eviction policies (S92). However, these steps are optional, since the memory location is expected to be present in the cache; the processing circuitry likely accessed the memory location in response to receiving a monitor address instruction, at which point the memory location is added to the cache. Therefore, these steps need not be included in a system that automatically adds an address specified by an instruction to a cache.

[0101] FIG. 8 illustrates a simulator implementation of the present technology. While the previously described embodiments implement the invention in terms of apparatus and methods for operating specific processing hardware supporting the technology, it is also possible to provide an instruction execution environment according to the embodiments described herein implemented through the use of a computer program. Such computer programs are often referred to as simulators, insofar as they provide a software-based implementation of a hardware architecture. Various simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, simulator implementations run on a host processor 100, optionally running a host operating system 102 that supports a simulator program 104. In some configurations, there are multiple layers of simulation between the hardware and the provided instruction execution environment, and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations that run at reasonable speeds, but such an approach is justified in some situations when it is desirable to execute code native to another processor for compatibility or reuse reasons. For example, a simulator implementation may provide an instruction execution environment that has additional features not supported by the host processor hardware, or that is typically associated with a different hardware architecture. An overview of simulation is given in "Some Efficient Architecture Simulation Techniques," Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0102] While embodiments have been described above with reference to specific hardware components or features, equivalent functionality is provided in the simulated embodiments by suitable software components or features. For example, specific circuitry may be implemented as computer program logic in the simulated embodiments. Similarly, memory hardware such as registers or caches may be implemented as software data structures in the simulated embodiments. In the example of FIG. 8 , these include address storage program logic 108, which maintains a data structure (in the memory or registers of host device 100) that represents (emulates) the address storage circuitry described in the examples above; capacity indicator program 110 logic, which maintains a capacity indicator as described in the examples above; monitor program logic 112, which emulates the monitor circuitry described in the examples above; and instruction decode program logic 114, which emulates the instruction decoder of the processing circuitry described above. In configurations where one or more of the hardware elements referenced in the previously described embodiments are present in host hardware (e.g., host processor 100), some simulated embodiments may use the host hardware where suitable. For example, host processor 130 may include caches in hardware that perform the functions of caches 12 and 13 of Figure 1 and / or cache 24 of Figures 2 and 3. Simulator code 104 may also include register emulation logic (not shown) that maintains data structures (in memory or registers of host device 100) that represent registers of system 2. In some examples, this includes registers 48 that store Bloom filters 46 described in some examples above.

[0103] In response to a watch address instruction in target code 106, instruction decode program logic 114 maps the watch address instruction to a set of instructions in the instruction set and checks the capacity indicator emulated by capacity indicator program logic 110 to determine whether the capacity of the emulated address storage circuitry has been reached. When capacity has not been reached, an index of the new memory location specified by the watch address instruction is added to a data structure maintained by address storage program logic 108, but if capacity has been reached, the new memory location is indicated in a cache (e.g., a cache of host hardware 100, or a data structure maintained in memory or in a register of host processor 100) or in a Bloom filter stored in a data structure maintained by register emulation logic.

[0104] In some examples, simulator program 104 is stored on a computer-readable storage medium (e.g., a non-transitory storage medium) and provides a program interface (instruction execution environment) to target code 106 (which may include applications, an operating system, and a hypervisor) that is the same as the interface of the hardware architecture modeled by simulator program 104. Thus, program instructions of target code 106, including the watch address instruction and WFE instruction described above, can be executed from within an instruction execution environment using simulator program 102, thereby allowing host computer 100, which does not actually have the hardware functions of device 2 discussed above, to emulate these functions.

[0105] In this application, the term "configured to..." is used to mean that an element of an apparatus has a configuration that is capable of performing a defined operation. In this context, "configuration" refers to a hardware or software configuration or method of interconnection. For example, an apparatus may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the operation. "Configured to" does not imply that an apparatus element needs to be modified in any way to provide the defined operation.

[0106] Although illustrative embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to these precise embodiments and that various changes and modifications can be made in these embodiments by those skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims.

Claims

1. 1. An apparatus comprising: address storage circuitry for storing indices of memory locations in the first set of shared memory; a capacity indicator that indicates whether the capacity of the address storage circuitry has been reached; monitoring circuitry for monitoring the first set of memory locations and a second set of memory locations of the shared memory identified in further storage circuitry to identify whether data stored in either set of memory locations has been modified, and in response to determining that the data has been modified, generating an indication that the data has been modified; processing circuitry for executing a watch address instruction to receive the indication that the data has been modified and which specifies the address of a new memory location within the shared memory; determining whether the capacity of the address storage circuitry has been reached based on the capacity indicator; updating the address storage circuitry to indicate that the new memory location should be monitored by the monitoring circuitry in response to determining that the capacity of the address storage circuitry has not been reached; and and processing circuitry for, in response to determining that the capacity of the address storage circuitry has been reached, updating the further storage circuitry to indicate that the new memory location should be monitored by the monitoring circuitry.

2. the address storage circuitry includes a plurality of entries, each entry configured to store one of the indices of the first set of memory locations; 2. The apparatus of claim 1, wherein the capacity indicator is configured to indicate that the capacity of the address storage circuitry has been reached unless the plurality of entries includes at least one available entry for storing an index of the new memory location.

3. 3. The apparatus of claim 1, wherein the capacity indicator indicates whether the capacity of the address storage circuitry has been reached based on a value stored in the address storage circuitry.

4. 4. The apparatus of claim 1, wherein the monitoring circuitry is configured to identify that the data has been modified in response to receiving a snoop request that identifies a memory location in the first set or the second set.

5. 5. The apparatus of claim 1, wherein the further storage circuitry is configured to store the indices of the second set of memory locations in a format that differs from the indices of the first set of memory locations stored in the address storage circuitry.

6. The apparatus of any preceding claim, wherein the further storage circuitry comprises a cache.

7. the cache includes a plurality of entries pointing to the second set of memory locations, each of the entries associated with a tag; 7. The apparatus of claim 6, wherein during execution of the watch address instruction, the processing circuitry is configured to update the cache to indicate that the new memory location should be watched by setting the tag associated with a new entry that indicates the new memory location to a predetermined value.

8. 8. The apparatus of claim 7, wherein the tag is stored in a transactional memory field configured to indicate whether a cached memory location associated with the tag has been accessed by the processing circuitry during execution of a current transaction or will be accessed by the processing circuitry upon completion of execution of the current transaction.

9. 9. The apparatus of claim 7 or 8, wherein the monitoring circuitry, in response to a snoop request identifying a given memory location, identifies that the data has been modified based on whether the given memory location is indicated in the address storage circuitry as being in the first set of memory locations or whether the given memory location is tagged in the cache as being in the second set of memory locations.

10. The apparatus of any one of claims 6 to 9, wherein the cache is a level 1 data cache.

11. Apparatus according to any preceding claim, wherein the further storage circuitry comprises a register.

12. The apparatus of claim 11 , wherein the register is configured to store a Bloom filter that identifies the second set of memory locations.

13. the Bloom filter includes a bit array; During execution of the watch address instruction, the processing circuitry, in response to determining that the capacity of the address storage circuitry has been reached, applying at least one hash function to the index of the new memory location to identify a plurality of bit positions in the Bloom filter; and setting each of the plurality of bit positions to a predetermined value.

14. The monitoring circuitry responds to a snoop request identifying a given memory location by: determining that the first set of memory locations includes the given memory location when an index of the given memory location matches an index stored in the address storage circuitry; and determining that the second set of memory locations includes the given memory location based on testing the index of the given memory location against the Bloom filter.

15. Apparatus according to any preceding claim, wherein the monitoring circuitry is separate from the processing circuitry.

16. 16. The apparatus of claim 15, wherein the processing circuitry, in response to a wait for event command, enters a low power state until an event indicator is received by the processing circuitry.

17. The apparatus of claim 16 , wherein the event indication includes the indication that the data has been modified.

18. 18. The apparatus of claim 1, wherein the first set of memory locations and the second set of memory locations comprise memory locations to which processing circuitry of the other set can write messages to be read by the processing circuitry.

19. 19. The apparatus of any preceding claim, wherein the first set of memory locations and the second set of memory locations each comprise non-contiguous memory locations.

20. during execution of the watch address instruction, following updating the address storage circuitry to indicate that the new memory location should be watched by the watch address circuitry, the processing circuitry is configured to check whether the capacity of the address storage circuitry has been reached; 20. The apparatus of any preceding claim, wherein the processing circuitry is configured to, in response to determining that the capacity of the address storage circuitry has now been reached, update the capacity indicator to indicate that the capacity of the address storage circuitry has been reached.

21. 1. A method comprising: storing in address storage circuitry indexes of the first set of memory locations of the shared memory; providing a capacity indicator for indicating whether the capacity of said address storage circuitry has been reached; monitoring the first set of memory locations and a second set of memory locations of the shared memory identified in the further storage circuitry to identify whether data stored in either set of memory locations has been modified; generating an indication that the data has been modified in response to determining that the data has been modified; receiving, in processing circuitry, the indication that the data has been modified; Executing a watch address instruction that specifies the address of a new memory location within said shared memory; determining whether the capacity of the address storage circuitry has been reached based on the capacity indicator; updating the address storage circuitry to indicate that the new memory location should be monitored by the monitoring in response to determining that the capacity of the address storage circuitry has not been reached; and and in response to determining that the capacity of the address storage circuitry has been reached, updating the further storage circuitry to indicate that the new memory location should be monitored.

22. 1. A computer program for controlling a host data processing apparatus to provide an instruction execution environment for executing target code, comprising: address storage program logic for maintaining an address storage structure in a memory or register of said host data processing apparatus to store indices of memory locations of the first set of shared memory; capacity indicator program logic for maintaining a capacity indicator in said memory or said register to indicate whether the capacity of said address storage structure has been reached; monitor program logic for monitoring the first set of memory locations and a second set of memory locations of the shared memory identified in the memory or a further storage structure maintained in the register to identify whether data stored in either set of memory locations has been modified, the monitor program logic generating an indication that the data has been modified in response to determining that the data has been modified; instruction decoding program logic for decoding instructions of the target code and controlling the host data processing apparatus to perform data processing; The instruction decode program logic responds to a watch address instruction specifying the address of a new memory location within the shared memory by: determining whether the capacity of the address storage structure has been reached based on the capacity indicator; updating the address storage structure to indicate that the new memory location should be monitored by monitoring logic in response to determining that the capacity of the address storage structure has not been reached; and in response to determining that the capacity of the address storage structure has been reached, updating the further storage structure to indicate that the new memory location should be monitored by the monitoring logic.

23. 1. An apparatus comprising: means for storing indices of the first set of memory locations in the shared memory; means for indicating whether the capacity of said means for storing indices of said first set of memory locations has been reached; means for monitoring the first set of memory locations and a second set of memory locations of the shared memory identified by the means for further storing to identify whether data stored in either set of memory locations has been modified; means for generating an indication that the data has been modified in response to determining that the data has been modified; means for receiving the indication that the data has been modified; Executing a watch address instruction that specifies the address of a new memory location within said shared memory; determining whether the capacity of the means for storing indices of the first set of memory locations has been reached based on the means for indicating whether the capacity of the means for storing indices of the first set of memory locations has been reached; in response to determining that the capacity of the means for storing indices of the first set of memory locations has not been reached, updating the means for storing indices of the first set of memory locations to indicate that the new memory locations should be monitored by the means for monitoring; and and means for, in response to determining that the capacity of the means for storing indices of the first set of memory locations has been reached, updating the means for further storing to indicate that the new memory location should be monitored by the means for monitoring.

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