Electronic circuit and method for self-testing data memories

Abstract

User data (D) written in data memory (RAM) IN ) to Error Correcting Code (ECC IN The present invention describes an electronic circuit and method for self-test of a data memory (RAM) comprising / using a first error correction code unit (ECCGEN1) for generating user data and associated error correction codes (ECCs) in the data memory (RAM). IN ) is written into the memory in a write cycle. IN ) and the associated error correction code (ECCCHK / CORR) written into the error check unit (ECC IN ) to provide error correction code (ECC IN ) and the error check unit (ECCCHK / CORR) checks the user data (D IN ) is calculated from the counter check code (CCC IN ) is determined to provide a Latent_Fault flag.

Description

[Technical Field]

[0001] The present invention relates to an electronic circuit for self-testing a data memory, a first error correction code unit for generating an error correction code from user data to be written into the data memory, wherein the electronic circuit is configured to write the user data and the associated error correction code into the data memory; an error checking unit for calculating a counter check code from user data read from the data memory and for comparing the counter check code with an error correction code read from the memory together with the associated user data, wherein the error checking unit is configured to provide an error flag if there is a difference between the error check code and the counter check code; Equipped with.

[0002] The invention further relates to a method for self-testing a data memory, a) a write cycle, - calculating an error correction code from user data provided to be written into a data memory; - storing the calculated error correction code and associated user data in a data memory; a write cycle comprising the steps of: b) a read cycle, - reading user data and associated stored error correction codes from a data memory; - calculating a counter check code from user data read from the data memory; comparing the error correction code read from the data memory with the counter check code and providing an error flag indicating a malfunction of the data memory if there is a mismatch; a read cycle comprising the step of: Equipped with. [Background technology]

[0003] When storing data electronically in a data memory, malfunctions can occur due to several reasons.

[0004] To detect memory data corruption, error correcting codes are used to detect and correct n-bit data corruption occurring in data memory. Such errors can be caused by bit flips due to several reasons.

[0005] It is known to write extra memory bits to record the parity of a data string (e.g., a single byte or multiple bytes), which allows for the detection of all single-bit errors. It is further known to use error correcting codes (ECC), which are calculated from the user data being written into the data memory and stored together with the user data in the data memory. Error correcting codes, such as single-error correcting and double-error correcting Hamming codes, allow single-bit errors to be corrected and double-bit errors to be detected. This can be combined with the use of extra parity bits. Error correcting codes are also known to correct multi-bit errors. The error correcting code function can be implemented in hardware along with the logic of the data memory device.

[0006] G. Tosenovjan: "Error correction codes implemented on MPC55XX and MPC56XX devices," NXP-free scale semiconductor Application note, Document no. AN5200, rev. 1, 12 / 2015, describes error correction code functionality used in data memories in applications where data corruption through soft errors cannot be easily tolerated. For example, single errors are corrected and double errors are detected and indicated by an ECC error interrupt.

[0007] Single-bit errors can be "physically" repaired by reading the data from the data memory and writing them back after correction.

[0008] JP-H-08263391 A discloses a memory device having a method for testing a random access memory (RAM) for storing an error correction code (ECC). The memory device includes an ECC generation circuit and a RAM for storing the ECC in an error correction / detection circuit. In the memory device, the ECC is generated by the ECC generation circuit from write data received from a memory control device. In the error correction / detection circuit, a syndrome is generated from the ECC at an address indicated by a signal line of the RAM. If the error detected by the syndrome results in a single-bit error, the error-corrected data is set in a register and single-bit error information is set in an error flag. If a double-bit error occurs, double-bit error information is set in an error flag, and the content of the error flag is reported to the memory control device via a signal line.

[0009] US 2020 / 0167230 A1 discloses a method and apparatus for self-diagnosis of RAM errors detecting logic in a powertrain controller that includes an error correcting code (ECC) module that includes an ECC comparator.

[0010] A self-test of the RAM error detection logic is provided to diagnose whether an error occurs in the RAM error detection logic or in the error correction code ECC module. A test is performed on the error correction code module corresponding to the RAM operating in conjunction with the second core of the microcontroller unit during a specific test operation in the test mode.

[0011] When testing of each ECC module is performed, the tests performed by each core include checking whether the error detection function is operating properly through a first task for performing an OR input with a specified value so that an error occurs in the test bit input port of the ECC comparator, checking whether the error detection function is operating properly through a second task for correctable error testing in which the input port of the ECC comparator is flipped and input so that one bit of input data is actually input, and checking whether the error detection function is operating properly through a third task for uncorrectable error testing in which the input port of the ECC comparator is flipped and input so that two bits of input data are actually input. Summary of the Invention

[0012] The object of the present invention is to provide an improved electronic circuit and method for easily and safely monitoring malfunctions of an error correction code unit provided for generating an error correction code (ECC) from user data. This object is achieved by an electronic circuit having the features of claim 1 and a method having the features of claim 5.

[0013] Preferred embodiments are set forth in the dependent claims.

[0014] The electronic circuit according to the preamble of claim 1 is further configured to provide the user data written in the data memory and the associated error correction code written in the error check unit in a write cycle of writing the user data and the associated error correction code in the data memory, and to provide a latent fault flag if a difference is determined between the error correction code and the counter check code.

[0015] The latent fault flag indicates an error occurring in the error correcting code unit, so that the functionality of the error correcting code unit can be easily monitored without requiring additional time and with only limited hardware and / or software resources.

[0016] Therefore, according to the invention, the error checking unit designed for the read cycle to check the stored error correction codes and counter check codes calculated from the user data read from the data memory is, according to the invention, also used for the write cycle to check the error correction codes generated by the error correction code unit in the write cycle, which makes it possible to protect the memories and registers in accordance with the ISO standard 26262 against permanent and transient faults, especially in safety-critical applications.

[0017] Error correcting code units and error checking units are security mechanisms within the meaning of this ISO standard 26262.

[0018] By monitoring the error correction code unit by using an error checking unit during the write cycle, both safety mechanisms are monitored for the occurrence of latent failures. ISO standard 26262 speaks of latent failures, for example, when the safety mechanism itself is defective, which means that errors in the functional logic are no longer recognized.

[0019] While prior art safety mechanisms are not only checked for permanent errors when the system is powered up via the logic Bist (LBist), in the present invention the safety mechanisms are monitored frequently by comparing the error correction code with the associated counter check code not only during read cycles of the data memory but also during write cycles.

[0020] The data memory may be any data memory, in particular a random access memory, a register, etc. The data memory may be provided in a separate integrated circuit or may be part of an integrated circuit such as a microprocessor, a microcontroller, an FPGA, an ASIC, etc.

[0021] The electronic circuits can be easily implemented as the present invention monitors each other using existing security mechanisms comprising an error correction code unit (ECCGEN) and an error check unit (ECCCHK / CORR).

[0022] Preferably, the electronic circuit comprises at least one multiplexer unit so that the error correction code (ECC) generated from the error correction code unit and the write user data of the memory are switched to the error check unit (ECCCHK / CORR) by the multiplexer unit in a write cycle.

[0023] For this reason, the electronic circuit preferably comprises: a first multiplexer having first and second inputs and an output, wherein user data to be written into the data memory is provided at the second input of the first multiplexer, and user data provided from the data memory when reading from the data memory is provided at the first input of the first multiplexer, the output of the first multiplexer being connected to the input of the error checking unit when the first multiplexer is controlled by the data memory read / write flag to provide to the input of the error checking unit user data read from the data memory in a read cycle and to provide to the input of the error checking unit user data provided to be written into the data memory in a write cycle; a second multiplexer having first and second inputs and an output, wherein the error correction code generated by the error correction code unit for user data to be written into the data memory is provided at the second input of the second multiplexer, and the error correction code read from the data memory when reading associated user data from the data memory in a read cycle is provided at the first input of the second multiplexer, the output of the second multiplexer being connected to the input of the error check unit, the second multiplexer being controlled by the data memory read / write flag to provide the error check unit with the error correction code obtained directly from the error correction code unit in a write cycle and to provide the error correction code obtained directly from the data memory in a read cycle; Equipped with.

[0024] The first and second multiplexers can be provided as separate electronic circuits, which may be separate electronic components or separate functional units in a common integrated circuit. The first and second multiplexers can also preferably be designed to be integrally formed in a common multiplexer unit. The switching between data from the data memory (stored error correction code and stored user data) in a read cycle and data written into the data memory (generated error correction code and user data) in a write cycle is controlled by read and write commands applied to the data memory, which are available, for example, on signal lines of the electronic circuit. This read / write flag is a 1-bit signal, which is used to control the first and second multiplexers.

[0025] The purpose of the first and second multiplexers is to supply the error checking unit with the error correction code and user data provided at the input of the data memory, which are written into the data memory during a write cycle, and the stored error correction code and stored user data at the output of the data memory, which are read from the data memory during a read cycle.

[0026] Except for the multiplexer unit, no additional hardware is required to achieve the improved electronic circuit. Furthermore, since the functions of the error check unit for writing data into the data memory can be performed in parallel, there is no time delay caused by additional safety checks.

[0027] The output of the error checking unit may be provided to the input of at least one multiplexer, the at least one multiplexer being controlled by the read / write flag to provide a latency flag at the output of the multiplexer in a write cycle and to provide an error flag as a result of a comparison between a stored error correction code (ECC) read from the data memory and a counter check code (CCC) calculated from the user data, which is read from the data memory in a read cycle.

[0028] Preferably, the error check unit of the electronic circuit further comprises a second error code generation unit provided for calculating a counter check code. The check code comparison unit is configured to compare the error correction code with the counter check code, and if there is a mismatch between the compared error correction code and the counter check code, to either set a correctable error flag if a correctable error is detected, or set an uncorrectable error flag if an uncorrectable error is detected. The correctable and uncorrectable flags are set in a read cycle, while the latent fault flag is set in a write cycle.

[0029] These error flags can be signaled externally and also used internally to monitor the functionality of the error code generation unit during write cycles.

[0030] In a further improved embodiment, the error check unit comprises an error location unit configured to locate at least one bit position of the detected failing bit by comparing the error correction code with the respective counter check code. The error check unit is configured to set a latent failure flag when locating at least one bit position of the failing bit, or a correctable error flag or an uncorrectable error flag is set. Thus, the result of monitoring the function of the error code generation unit in a write cycle by using the correctable and uncorrectable error flags is combined with the result of locating the bit positions of the failing bits to provide the latent failure flag.

[0031] This can be implemented by the use of OR gates, where the error checking unit comprises a first OR gate that provides a flag if the bit position of at least one of the faulty bits is indicated by the bit vector at the input of the first OR gate, and a second OR gate that provides a latent fault flag as the output of the second OR gate if at least one of the error flag, correctable error flag, or uncorrectable error flag provided by the first OR gate is set at the input of the second OR gate.

[0032] The error location unit is adapted to function in both write and read cycles.

[0033] In a preferred embodiment, the electronic circuit further comprises an error correction unit designed to provide corrected user data at its output as a function of an error location vector indicating the location of failed bits in the user data at the input of the error correction unit. The error checking unit further comprises a comparator unit designed to compare the user data at the input of the error correction unit with the corrected user data at the output of the error correction unit and to indicate an error flag if there is a mismatch between the compared and corrected user data in a write cycle. This allows an easy safety check of the functionality of the correction unit during data processing without any time delay.

[0034] The method for self-diagnosis of data memory is a) a write cycle, - calculating an error correction code from user data provided to be written into a data memory; - storing the calculated error correction code and associated user data in a data memory; a write cycle comprising the steps of: b) a read cycle, - reading user data and associated stored error correction codes from a data memory; - calculating a counter check code from user data read from the data memory; comparing the error correction code read from the data memory with the counter check code and providing an error flag indicating a malfunction of the data memory if there is a mismatch; a read cycle comprising the step of: Equipped with.

[0035] In the write cycle, - calculating a counter check code from user data provided to be written into a data memory; comparing the calculated error correction code with the calculated counter check code and providing a latent failure flag indicating a latent failure of the function provided for calculating the error correction code to be stored in the data memory during a write cycle if there is a mismatch; An additional step is provided to:

[0036] The method performed in the electronic circuit described above preferably comprises: - transferring to the error checking unit during a write cycle the error correction code provided at the output of the error correction code unit and the associated user data provided at the input of the error correction code unit, and providing a latent fault flag in case of a mismatch during the write cycle; - transferring to an error checking unit, in a read cycle, the stored error correction code and the associated stored user data read from the data memory, and providing an error flag indicating a malfunction of the data memory in the read cycle; The method further comprises the step of:

[0037] The latent failure flag indicates a latent failure of the safety functions provided by the error correction code unit and the error check unit used to control the data memory to indicate any malfunction of the data memory. The use of both the error correction code unit and the error check unit in the write cycle allows for a safety check of these safety functions themselves. This works because the direct input of the error correction code unit, i.e., user data, and the direct output of the error correction code unit, i.e., the calculated error correction code, are fed directly to the error check unit without intermediate storage in the data memory, which could result in a failure. If a latent failure is monitored by a mismatch between the error correction code and the calculated counter check code, the error is caused either by the error correction code unit when calculating the error correction code or by the error check unit when calculating the counter check code. Another latent failure in the error correction code unit or the error check unit can be caused by a bit flip in the registers of the error correction code unit and the error check unit.

[0038] Preferably, a single bit error in the user data is corrected and a correctable error flag is set by the error checking unit, and any error with more than one bit in the user data can be indicated as an uncorrectable error by the error flag without correcting the user data.

[0039] Such correction of a single bit error can be limited to a read cycle that reads data from the memory.

[0040] In a preferred embodiment, the data memory is additionally monitored frequently by performing a read cycle after the write cycle to immediately check the correctness of the write cycle.

[0041] In a write cycle, the method preferably comprises: -User data (D) provided to be written into data memory (RAM) IN ) to Error Correction Code (ECCIN ) and -Error Correction Code (ECC) calculated in data memory (RAM) IN ) and related user data (D IN ) and -User data (D) provided to be written into data memory (RAM) IN ) to counter check code (CCC IN ) and -Calculated Error Correction Code (ECC IN ) is the calculated counter check code (CCC IN ) and if there is a mismatch, the error correction code (ECC) IN ) or in the third step, the counter check code (CCC IN providing at least one error flag (CERR, UNCERR) indicating a malfunction in the calculation of -Counter check code (CCC IN ) caused by a fault when calculating the processed user data (D IN Detecting the bit position of a bit identified as faulty in checking whether at least one of a correctable error flag (CERR), an uncorrectable error flag (UNCERR) is set, or at least one bit position with a faulty bit is detected, and setting a latent fault flag if at least one of a correctable error flag (CERR) or an uncorrectable error flag (UNCERR) is set, or at least one bit position with a faulty bit is detected; The method includes a step of:

[0042] For this reason, the write cycle is also used to monitor the functionality of the error correction code and the calculation of the counter check code.

[0043] In the read cycle, the method preferably comprises: -Data memory (RAM) to user data (DOUT ) and associated stored error correcting codes (ECC OUT ) and -User data (D) read from data memory (RAM) OUT ) to counter check code (CCC OUT ) and -Error Correction Code (ECC) read from data memory (RAM) OUT ) is the calculated counter check code (CCC OUT ) and providing at least one error flag (CERR, UNCERR) indicating malfunction of the data memory (RAM) if there is a mismatch; -User data (D) read from data memory (RAM) OUT Detecting the bit position of the failing bit in - checking whether at least one of a correctable error flag (CERR), an uncorrectable error flag (UNCERR) is set or at least one bit position with a faulty bit is detected, and setting a latent fault signal if at least one of a correctable error flag (CERR) or an uncorrectable error flag (UNCERR) is set or at least one bit position with a faulty bit is detected; The method includes a step of:

[0044] For this reason, the read cycle is also used to monitor the function of detecting the bit location of the failing bit.

[0045] Preferably, the method further comprises: reading user data (D) from a data memory (RAM) in a read cycle at the indicated bit position; OUT ) correcting the failed bit.

[0046] Undetected errors may occur in the detection or correction logic when unintentionally correcting user data, for example by toggling a bit due to a fault in the detection or correction logic. Such errors can be detected in subsequent processing of the corrected user data on the receiver side. OUT ) is read from the data memory (RAM) and sent to the receiver. OUT ) in a read cycle. The user data can be transferred, for example, by using an ECC protected data bus. The received corrected user data (D OUT ) can be detected by the error correction check ECCCHK on the receiver side. The error correction check ECCCHK checks the received corrected user data (D OUT ) and received error correction code (ECC OUT If ECC protected memory is not used at the transmitter side, the transmitter will OUT ) based on error correction code ECC GEN In this case, the data bus generates the corrected user data (D OUT ) and the corresponding error correcting code ECC GEN is protected by

[0047] In another embodiment, the user data (D IN ,D OUT ) is the corrected user data (D OUT, CORR ) and they are compared with the user data (D IN ,D OUT The error flag is corrected in the step of correcting the failed bit in the compared user data (D IN ,D OUT ) and corrected user data (D OUT, CORR) is indicated if there is a mismatch between the bit position of the faulty bit and the bit position of the faulty bit. This allows an easy safety check of the functionality of the correction unit during data processing without any time delay, and also allows the write cycle to be used to monitor the functionality of the detection and correction of the bit position of the faulty bit.

[0048] The invention is disclosed by means of illustrative embodiments in the enclosed drawings. [Brief explanation of the drawings]

[0049] [Figure 1] FIG. 1 is a block diagram of an electronic circuit according to the prior art. [Figure 2] 1 is a block diagram of an illustrative embodiment of an electronic circuit in accordance with the present invention; [Figure 3a)] 3 is a block diagram of an illustrative embodiment of an error checking unit comprising an error correction unit for the electronic circuit in FIG. 2. [Figure 3b)] FIG. 3b is a block diagram of the error checking unit in FIG. 3a with an additional comparator for safety checking of the error correction unit. [Figure 4] FIG. 1 is a flow diagram of a method for self-testing a data memory. [Figure 5a)] 5 is a flow diagram of the improved method of FIG. 4 with a correction step in the write cycle. [Figure 5b] 5 is a flow diagram of the improved method of FIG. 4 with a correction step in the read cycle. [Figure 6] FIG. 1 is a block diagram of the interconnection of the electronic circuit and the receiver by a data bus with an additional error checking unit on the receiver side.

[0050] FIG. 1 presents a block diagram of a prior art electronic circuit for self-testing a data memory RAM according to the prior art. IN (31...0) is provided by the user to be written into the data memory RAM to store data in a specific location. User Data D INis a data packet comprising a number of bits, i.e., one byte, or as shown, a number of bytes each comprising 8 bits (e.g., a 4-byte data packet). The data packet also contains user data D along with a storage address in the data memory RAM. IN It may comprise:

[0051] User data D stored in data memory RAM IN can be read out, which in the following will be referred to as the stored user data D OUT It is called (31...0).

[0052] To continuously check the functionality of the data memory RAM, a first error correction code unit ECCGEN1 is provided, which IN (31...0) to Error Correction Code ECC IN which is provided to be written into a data memory RAM.

[0053] The written user data D IN (31...0) is fed into the first error correction code unit ECCGEN1, which encodes the user data D stored in the data memory RAM. IN Error Correction Code ECC as a function of (31...0) IN The function can be, for example, a Hamming code, an HSIAO code, a Reed-Solomon code, etc. It can be implemented in hardware as a programmable logic unit controlled by a software algorithm, or entirely in software running on a data processor in electronic circuitry.

[0054] The error correcting code ECC calculated by the first error correcting code unit ECCGEN1 IN Then the associated user data D IN (31...0) in the data memory RAM.

[0055] This is controlled by a write flag WR on a signal line which indicates a write cycle for storing data in the data memory RAM.

[0056] Reading data from the data memory RAM is controlled by a read flag, which is, for example, the inversion of the write flag WR on a signal line.

[0057] In a read cycle, the user data D OUT (31...0) is the associated stored error correction code ECC OUT The error check unit checks the user data D read from the data memory RAM. OUT (31...0) to counter check code CCC OUT Calculate the counter check code CCC OUT In the read cycle, the associated user data D OUT Error Correction Code ECC read from data memory RAM with (31...0) OUT It is designed to be compared with

[0058] Therefore, the error check unit ECCCHK outputs a read flag on the signal line

number

[0059] The check and read cycle is performed to check the stored and read error correction code ECC. OUT is the user data D read from the data memory RAM. OUT Calculated counter check code CCC calculated as a function of (31...0) OUT Determine whether it is similar to

[0060] If a malfunction occurs in the data memory RAM, for example, due to at least one bit flip, the error correction code ECC OUT The calculated counter check code CCC OUT The error check unit ECCCHK provides error flags for corrected errors CERR and uncorrectable errors UNCERR.

[0061] In a preferred embodiment, the error check unit ECCCHK checks the user data D if there is an error. OUT It has a correction unit that corrects (31...0). A single bit error can be easily corrected so that the error flag ERR indicates a corrected error CERR. If the error is not correctable, this is indicated by the uncorrectable error flag UNCERR.

[0062] The error flags CERR and UNCERR are read flags.

number

[0063] At the output of the error check unit ECCCHK, the user data D OUT (31...0) is provided, which is read from the data memory RAM and possibly corrected by the correction logic.

[0064] This prior art electronic circuit is designed to protect data memory RAM against transient and permanent errors by protection with error correcting codes.

[0065] The use of an error correcting code ECC makes it possible to detect and correct single bit errors in data memories RAM and to detect more than one bit error, ie two bit errors.

[0066] For example, the corresponding 7-bit error correction code ECC is, for example, 32-bit user data DIN (31...0), which is provided to be written into the data memory RAM by the hardware ECCGEN, and the error correction code ECC is used to correct the user data D IN (31...0) is written into the data memory RAM.

[0067] For example, when reading a memory line from the data memory RAM, the read user data D OUT (31...0) is the error correction code ECC read out in the same way. OUT are checked in another hardware unit, the error checking unit ECCCHK.

[0068] User Data D OUT If there is a 1-bit error in (31...0), it will be recognized via the error checking unit ECCCHK, corrected via the hardware ECCORR, and the correctable error flag CERR will be set.

[0069] User Data D OUT If there is any double bit error in (31...0), it will be recognized via the error checking unit ECCCHK and the uncorrectable error flag UNCERR will be set.

[0070] The first error correction code unit ECCGEN1 and the error check unit ECCCHK are safety mechanisms within the meaning of ISO standard 26262. The function of the error correction unit ECCCORR is safety-critical in read cycles, since unintentional correction of output data would result in the following system functioning with incorrect data. The standard only requires that an error must be reported, but not that it must be corrected, so the correction unit in the electronic circuit and the respective safety monitoring procedures for controlling the function of the correction unit in write cycles are optional.

[0071] According to ISO standard 26262, a latent failure exists, for example, when the safety mechanism itself is defective, such that an error in the functional logic is no longer recognized. The prior art safety mechanism according to Figure 1 does not check the safety mechanism, or only checks the safety mechanism for permanent errors, when the system is activated via the Logic Bist (LBist).

[0072] 2 presents a block diagram of an electronic circuit according to the invention, which comprises a data memory RAM, a first error correcting code unit ECCGEN1 and an error checking unit ECCCHK, together with an AND logic (&_1) according to the prior art electronic circuit according to FIG.

[0073] Additionally, a first multiplexer MUX_1 and a second multiplexer MUX_2 are provided, the outputs of both the first and second multiplexers MUX_1 and MUX_2 being connected to inputs of an error checking unit ECCCHK.

[0074] The first input of the first multiplexer MUX_1 is connected to the data memory RAM, and the read user data D from the data memory RAM is input to the input of the first multiplexer. OUT Provides (31...0).

[0075] The second input of the first multiplexer MUX_1 is the write user data D IN (31...0) which are provided by the user to be written into the data memory RAM.

[0076] The first input of the second multiplexer MUX_2 is connected to the data memory RAM and stores the error correction code ECC OUT which is provided to the second input of the first multiplexer MUX_1, and OUT Related to (31...0).

[0077] A second input of the second multiplexer MUX_2 is connected to the output of the first error correction code unit ECCGEN1 to transmit the calculated error correction code ECC to the input of the second multiplexer. IN to provide.

[0078] The first and second multiplexers MUX_1 and MUX_2 are controlled by write and read flags on signal lines in addition to the chip select CS signal associated with the data memory RAM.

[0079] When a write flag is present on the data memory RAM and the first and second multiplexers MUX_1 and MUX_2 along with the chip select CS command, the second input is selected for the write cycle and is obtained directly from the first error correction code unit ECCGEN1 and is used to store the user data D IN User data D calculated as a function of (31...0) and written into the data memory RAM IN (31...0) and the error correction code ECC are provided to the input of the error check unit ECCCHK. In this write cycle, the error check unit checks the user data D provided to be written in the data memory RAM. IN It calculates a counter check code CCC as a function of (31...0) and checks the error correction code ECC obtained directly from the first error correction code unit ECCGEN1 against this counter check code CCC. The error check unit calculates an error flag, which is treated as a latent fault flag by using a second AND logic &_2, which is controlled by a write flag and a chip select flag (WR and CS) on signal lines, which indicate the actual write cycle to write to the digital memory RAM.

[0080] If a mismatch is detected by the error checking unit ECCCHK, a latent failure flag, i.e. a digital "1" bit, is set indicating a malfunction of the safety mechanism provided by the first error correcting code unit ECCGEN1 and the error checking unit ECCCHK.

[0081] In a read cycle, the second AND logic is disabled due to the read flag (the inverse of the write flag). Hence, the first AND logic &_1 is enabled when the error check unit ECCCHK indicates an uncorrectable error in the error flag at the output of the error check unit. Hence, the output of the first AND logic provides an indication of a correctable error CORR and an uncorrectable error UNCORR. Repeated indications of correctable memory errors indicate a latent fault in the memory with a risk of uncorrectable errors.

[0082] In this read cycle, the stored error correction code ECC read from the data memory (RAM) OUT and stored user data D OUT (31...0) are transferred to the input of the error check unit ECCCHK and stored read user data D OUT Error correction code ECC stored against counter check code CCC calculated as a function of (31...0) OUT Counter check.

[0083] This is the function that corresponds to the prior art solution described in FIG.

[0084] 2 uses the existing safety mechanism established by the first error correction code unit ECCGEN1 and the error check unit ECCCHK to monitor each other during the write cycle. IN (31...0) is switched to the error checking unit ECCCHK in a write cycle by a multiplexer unit comprising a first and a second multiplexer.

[0085] If there is a single bit error or a double bit error in the first error correcting code unit ECCGEN1 or the error checking unit ECCCHK, it will be identified and signaled via a latent fault flag.

[0086] At every write access to the data memory RAM, the safety mechanism is checked without any need for software with high diagnostic coverage (DC). The diagnostic coverage DC is 100%.

[0087] The monitoring of the safety mechanism is simply performed by the error check unit ECCCHK checking the existing error correction code ECC and the user data D IN (31...0) and executes this error check unit ECCCHK in this write cycle, thereby storing the user data D in the data memory. IN This is done in a write cycle in parallel with writing (31...0).

[0088] The electronic circuit can be fully implemented in hardware as part of a data memory RAM integrated circuit or as part of a larger logic structure such as a microcontroller, microprocessor, FPGA, ASIC, or other logic circuit comprising a memory unit. A memory unit within the meaning of the present invention also includes a data register. The electronic circuit can be designed in combination with any kind of memory, including RAM memory, registers, non-volatile memory, etc.

[0089] FIG. 3a) is a block diagram of an exemplary embodiment of an error checking unit ECCCHK / CORR comprising an error correction unit ECCCOR for the electronic circuit in FIG.

[0090] The safety objectives of ISO 26262 do not stipulate that errors signed by error flags (CORR, UNCORR, latent faults) must always be corrected. However, a false correction may not be performed during readout if no error exists.

[0091] An error in the error correction logic ECCCOR or the error checking logic ECCCHK that results in an "unintended" correction on the first day would violate the safety objectives of ISO 26 262, since the system would continue to operate with incorrect data. It is therefore advantageous to monitor a large part of the correction logic ECCCOR already during the write cycle, which can be part of the error checking unit ECCCHK / CORR.

[0092] A simple and fast check for two error cases during a write cycle can be performed by the logic shown illustratively in the block diagram of FIG.

[0093] The error check unit ECCCHK / CORR uses the error correction code ECC shown in Figure 2. IN A counter check code CCC, which is similar to the first error correction code unit ECCGEN1, is provided to calculate OUT This comprises a second error correction code unit ECCGEN2 which calculates, in each cycle, i.e., read and write cycles, the user data D written into the data memory in the write cycle. IN (31...0) and the user data D read from the memory RAM in the read cycle. OUT (31...0) and the error check function ECCCHK is an error correction code ECC IN Counter check code CCC OUT and sets a correctable error flag CERR if a correctable, e.g., single-bit error, is detected, or sets an uncorrectable error flag UNCERR if an uncorrectable, e.g., multi-bit error, is detected.

[0094] The flags may be digital states (0 or 1), where a digital 0 may indicate no error, i.e., no correctable error for the CORR flag or no uncorrectable error for the UNCORR flag, respectively, and a digital 1 may indicate an error, i.e., a correctable error for the CORR flag or an uncorrectable error for the UNCORR flag, respectively.

[0095] On a read cycle, these CORR and UNCORR flags are indicated at the output of the &_1 logic.

[0096] The error checking unit ECCCHK / CORR further comprises an error location unit ERRLOC configured to locate at least one bit position of the failing bit. IN The respective counter check code CCC OUT and provides a bit vector (31...0) indication, e.g., a digital 1 in the bit vector at the failed bit position and a digital 0 at the corrected bit position. The error location unit ERRLOC receives as input data an 8-bit error correction code ECC IN and 8-bit counter check code CCC OUT , as well as a 32-bit vector gate with a 32-bit error locator vector as output.

[0097] The error location vector is transferred to an input of the error correction unit ECCCOR and is used to correct the user data D provided to a second input of the error correction unit ECCCOR. IN The error correction unit ECCCOR can be designed to toggle each bit indicated as faulty by the error location vector. The output of the error correction unit ECCCOR is the corrected user data D. OUT Provides (31...0).

[0098] The (eg, 32-bit) error location vector is forwarded to the input of a first OR gate OR1, which indicates an error flag at its output if at least one bit of the error location vector indicates the presence of a failing bit.

[0099] To monitor the functioning of the error control logic, an error check function is performed for both read and write cycles, providing a CORR / UNCORR flag. The CORR / UNCORR flag is used internally as an input to a second OR gate OR2 to provide a latent fault flag if an error, i.e., a correctable or uncorrectable error, is detected by the error check logic in a read or write cycle indication. Such an error is detected by the first or second error code generation unit ECCGEN. 1 / 2 This indicates a malfunction of one of the following:

[0100] The output of the first OR gate OR1, which indicates an error flag, is also transferred to the input of the second OR gate OR2 to provide a latent fault flag if an error is detected by the error location unit ECCLOC.

[0101] At least the error location unit ERRLOC is executed in the read and write cycles. The error correction unit ECCCOR also corrects the resulting corrected user data D at its output. OUT Even though (31...0) are unused for this write cycle, they can still function in the write cycle.

[0102] Two errors can be distinguished.

[0103] a) Error Correction Code (ECC) for both write and read cycles IN The first error code generation unit ECCGEN1 is provided to generate an error and counter check code CCC OUT The error in the second error code generation unit ECCGEN2 is provided to calculate

[0104] b) first and second error code generation units ECCGEN 1 / 2 is error-free, but the error location unit ECCLOC is faulty, which will lead to incorrect correction of the data.

[0105] For the first error type a), in either case, either a correctable error CORR or an uncorrectable error UNCORR flag will be recognized internally in the ECCCHK / CORR module, which then results in the setting of a latent fault flag due to the second OR gate OR2.

[0106] For the second error type b), a latent fault flag will also be set. IN and counter check code CCC OUT Although the error location unit ERRLOC does not indicate any errors by comparing with the same error correction code ECC IN and counter check code CCC OUT When locating the failing bit location by analyzing the CERR flag, the UNCERR flag, and the error flag at the output of the first OR gate OR1, there is a malfunction in the error location unit ERRLOC, which is detected by the second OR logic OR2 for the CERR flag, the UNCERR flag, and the error flag.

[0107] In general, it can be said that all corrections during a write cycle lead to the setting of a latent fault flag, regardless of whether the error is in the ECCGEN logic, or the ECCCHK logic, or the ERRLOC logic.

[0108] 3b is a block diagram of an exemplary improved embodiment of the error check unit ECCCHK / CORR shown in FIG. 3a). In addition, the error check unit ECCCHK / CORR comprises an optional comparator COMP, which is provided for checking the functionality of the error correction unit ECCCOR in a write cycle. The user data D at the input of the error correction unit ECCCOR IN ,D OUT and the corrected user data D at the output of the error correction unit ECCCOR. OUT, CORR is provided at the input of the comparator, which is the user data D IN ,D OUT Corrected user data D OUT, CORR If there is a mismatch between these two user data in the write cycle WR and the corrected user data, an error flag is indicated, which is transferred to the input of the second OR gate OR2.

[0109] Any malfunction of the error correction logic ECCCOR is detected by a second OR logic OR2 on the CERR flag, the UNCERR flag, the error flag at the output of the first OR gate OR1 as well as on the error flag of the comparator COMP.

[0110] Figure 4 shows the write cycle WR for writing user data to the data memory RAM and the read cycle for reading the output data from the data memory RAM.

number

number

[0111] Figure 5 shows W4) comparing the calculated error correction code ECC with the calculated counter check code CCC and providing, in case of a mismatch, in a write cycle WR, at least one error flag CERR, UNCERR indicating a malfunction in the calculation of the error correction code ECC in step W1) or in the calculation of the counter check code CCC in step W3); W5 / R4) User data D provided to be written into data memory RAM in a write cycleIN (31...0), or user data D read from the data memory RAM in a read cycle OUT Detecting the bit position of the failing bit in (31...0); W6 / R5) checking whether at least one of the correctable error flags CORR and / or the uncorrectable error flag UNCORR has been set in step W4 / R3) or whether at least one bit position with a faulty bit has been detected in step W5 / R5); 5 shows an improved flowchart of the method in FIG. 4 with a corrected additional step of performing

[0112] In step W6 / R5, a latent fault flag is set if at least one of a correctable error flag (CERR) or an uncorrectable error flag (UNCERR) is set, or if at least one bit position with a faulty bit is detected.

[0113] For the read cycle, a further improved method is W7 / R6: User data D read from data memory RAM in a read cycle at the bit positions indicated in steps W5 / R4, for example by toggling the respective bits. OUT Correcting the failed bits in (31...0).

[0114] Step W7 / R6 is not monitored and a malfunction can occur in this step, for example due to a faulty memory or register or due to a toggle error in the correction step W7. This is because the error correction code (ECC) read from the data memory (RAM) OUT ) at the output of step W7 / R6 together with the corrected user data D OUT(31...0). Such a pair of user data and the associated error correction code can be transferred to the receiver, for example, on an ECC-protected data bus, where the receiver performs the ECC check ECCCHK described above. In this case, a faulty connection on the transmitting side will be detected by the receiver system.

[0115] 6 shows a block diagram of a part of an electronic circuit comprising a data memory RAM and the interconnection of an error checking unit ECCCHK including an error correction unit CORR. The output of the error checking unit ECCCHK / CORR is connected to a data bus B, so that the error correction code ECC OUT and related corrected user data D OUT (31...0) are communicated to at least one receiver via data bus B. The receiver is shown with its parts at the bottom of data bus B, which are relevant to the present invention. The receiver comprises an additional error checking unit ECCCHK on the receiver side.

[0116] The error correction code ECC calculated by the error correction code unit ECCGEN of the transmitter as configured by using the configuration signal CONFIG that controls the multiplexer OUT or the generated error correction code ERR GEN or the corrected user data D is provided at the input of the error checking unit ECCCHK. OUT (31...0) is present at the other input of the error check unit ECCCHK. From this, the error check unit ECCCHK OUT and the received corrected user data D OUT It is possible to check the validity of (31...0).

[0117] If additional ECCGEN logic is provided at the input of the data bus to provide an ECC-controlled data bus, for example as an implemented feature in the data memory unit, a pair of corrected user data D is transmitted to the receiver via the data bus. OUT (31...0) and Error Correction Code (ECC OUT It is advisable to disable this ECCGEN logic when communicating with the data bus. The use of additional ECC check logic at the input of the data bus ensures that the corrected user data D OUT and ECC OUT This is counterproductive because the error will always be corrected.

[0118] Unintentional correction of user data can be monitored by an ECC check logic ECCCHK at the receiver side that protects the data bus. OUT will be detected by the destination. If there is no fault in the correction logic, the data bus is protected with the use of the corrected data and the associated corrective error checking code. The inventions described in the claims of the present application as originally filed are set forth below. [C1] An electronic circuit for self-testing a data memory (RAM), comprising: -User data (D) written in the data memory (RAM) IN ) to Error Correction Code (ECC IN a first error correcting code unit (ECCGEN) for generating 1 ), wherein the electronic circuit stores the user data (D IN ) and the associated error correcting code (ECC IN ), -User data (D) read from the data memory (RAM) OUT ) to counter check code (CCC OUT ) and calculate the counter check code (CCC OUT ) to the relevant user data (D OUT ) and the error correction code (ECC) read from the data memory (RAM) OUT an error check unit (ECCCHK / CORR) for comparing the error check code (ECC OUT ) and the counter check code (CCC OUT ) and providing an error flag (CERR / UNCERR) if there is a difference between The electronic circuit stores the user data and the associated error correction code (ECC) in the data memory (RAM). IN The user data (D IN ) and the associated error correction code (ECC) written into the error check unit (ECCCHK / CORR). IN ) to provide the error correction code (ECC IN ) and the error check unit (ECCCHK / CORR) IN ) calculated from the counter check code (CCC IN 1. An electronic circuit configured to provide a Latent_Fault flag when a difference is determined between the reference voltage and the reference current. [C2] The electronic circuit a first multiplexer (MUX_1) with first and second inputs and an output, wherein the user data (D IN ) is provided at the second input of the first multiplexer (MUX_1) and is used to read the user data (D OUT ) is provided at the first input of the first multiplexer (MUX_1), and the output of the first multiplexer (MUX_1) is provided to the input of the error check unit (ECCCHK / CORR) to receive the user data (D OUT ) and provides the input of the error check unit (ECCCHK / CORR) with the user data (D) provided to be written into the data memory (RAM) in the write cycle. IN ) connected to the input of the error check unit (ECCCHK / CORR) when the first multiplexer (MUX_1) is controlled by a data memory read / write flag to provide a second multiplexer (MUX_2) having first and second inputs and an output, wherein the user data (D IN ) for the first error correction code unit (ECCGEN 1 ) generated by the error correction code (ECC IN ) is provided at the second input of the second multiplexer (MUX_2) to transfer the associated user data (D OUT ) read from the data memory (RAM), OUT ) is provided at the first input of the second multiplexer (MUX_2), the output of the second multiplexer (MUX_2) is connected to an input of the error check unit (ECCCHK / CORR), and the second multiplexer (MUX_2) provides the first error correction code unit (ECCGEN) to the error check unit (ECCCHK / CORR) in a write cycle. 1 ) directly derived from the error correcting code (ECC IN ) and in a read cycle, the error correction code (ECC) obtained directly from the data memory (RAM) OUT ) controlled by the data memory read / write flag to provide 10. The electronic circuit of claim 1, comprising: [C3] The electronic circuit of C2, wherein the first and second multiplexers (MUX_1, MUX_2) are integrally formed in a common multiplexer unit. [C4] The output of the error check unit (ECCCHK / CORR) is provided to an input of at least one logic unit (&_1, &_2), which in a write cycle, receives the user data (D IN ) calculated from the error correcting code (ECC IN ) and the user data (D IN ) IN and providing the Latent_Fault flag at the output of the at least one logic unit (&_1, &_2) in the write cycle as a result of a comparison with the stored error correction code (ECC) read from the data memory in the read cycle. OUT ) and the user data (D OUT ) OUT 4. The electronic circuit according to claim 1, wherein the electronic circuit is controlled by the read / write flag to provide an error flag (CERR / UNCERR) as a result of a comparison with the read / write flag. [C5] The error check unit (ECCCHK / CORR) OUT A second error code generation unit (ECCGEN) is provided to calculate 2 ) and the error correction code (ECC IN ) to the counter check code (CCC OUT ) and compare the compared error correction codes (ECC IN ) and counter check code (CCCOUT and a check code comparison unit (ECCCHK) configured to either set a correctable error flag (CERR) if a correctable error is detected or to set an uncorrectable error flag (UNCERR) if an uncorrectable error is detected, when there is a mismatch between the [C6] The error check unit (ECCCHK / CORR) IN ) to the respective counter check codes (CCC OUT ), wherein the error check unit (ECCCHK / CORR) is configured to set a Latent_Fault flag when locating at least one bit position of a faulty bit, or to set a correctable error flag (CERR) or an uncorrectable error flag (UNCERR), and the error location unit (ERRLOC) is adapted to function in both the write cycle and the read cycle. [C7] The error check unit (ECCCHK / CORR) is configured to check whether at least one bit position of the faulty bit is connected to a first OR gate (OR 1 ) provides a flag if indicated by a bit vector at the input of the first OR gate (OR 1 ) and the first OR gate (OR 1 At least one of the error flag provided by the first OR gate (OR), the correctable error flag (CERR), or the uncorrectable error flag (UNCERR) is input to a second OR gate (OR 2 ) is set at the input of the second OR gate (OR 2 the second OR gate (OR ) providing a latent fault signal as an output thereof; 2 ) The electronic circuit according to C6, characterized in that it comprises: [C8] The error check unit (ECCCHK / CORR) detects the user data (D IN ,D OUT ) as a function of the error location vector indicating the location of the failed bit in OUT, CORR ) at the input of the error correction unit (ECCCOR), and the error check unit (ECCCHK / CORR) is designed to provide the user data (D IN ,D OUT ) to the corrected user data (D OUT, CORR ) and the compared user data (D IN ,D OUT ) and the corrected user data (D OUT, CORR 8. The electronic circuit of any one of claims 1 to 7, further comprising a comparator unit designed to indicate an error flag if there is a mismatch between [C9] 1. A method for self-testing a data memory, comprising: a) a write cycle, - user data (D) provided to be written into said data memory (RAM) IN ) to Error Correction Code (ECC IN ) and - the calculated error correction code (ECC) in the data memory (RAM) IN ) and the associated user data (D IN ) and a write cycle comprising the steps of: b) a read cycle, -The data memory (RAM) to the user data (D OUT ) and the associated stored error correcting code (ECC OUT ) and - The user data (D OUT ) to counter check code (CCC OUT ) and - The error correction code (ECC) read from the data memory (RAM) OUT ) to the counter check code (CCC OUT ) and providing an error flag indicating malfunction of said data memory (RAM) if there is a discrepancy. a read cycle comprising the step of: In the write cycle, - the user data (D) provided to be written into the data memory (RAM) IN ) to counter check code (CCC IN ) and - the calculated error correction code (ECC IN ) to the calculated counter check code (CCC IN ), and if there is a mismatch, the error correction code (ECC) stored in the data memory (RAM) in the write cycle. IN providing a Latent_Fault flag indicating a latent fault of said function provided for calculating The method, characterized by the additional step of: [C10] - instructing the error check unit (ECCCHK / CORR) to, during a write cycle, read the error correction code (ECC) provided at the output of the error correction code unit (ECCGEN) IN ) and the associated user data (D) provided at the input of the error correction code unit (ECCGEN). IN ) and providing a Latent_Fault flag if there is a mismatch in the write cycle; - the error check unit (ECCCHK / CORR) checks the stored error correction code (ECC) read from the data memory (RAM) during the read cycle. OUT ) and the associated stored user data (D OUT ) to provide an error flag indicating malfunction of said data memory (RAM) during a read cycle; The method according to C9, which is performed by the electronic circuit according to any one of C1 to C8, characterized in that [C11] The user data (D IN ,D OUT ) is corrected, a correctable error flag is set, and the user data (D IN ,D OUT Any error with more than one bit in the user data (D IN ,D OUT 11. The method of claim 9 or 10, wherein the error flag indicates an uncorrectable error without correcting the error. [C12] The write cycle comprises: - user data (D) provided to be written into said data memory (RAM) IN ) to Error Correction Code (ECC IN ) and - the calculated error correction code (ECC) in the data memory (RAM) IN ) and the associated user data (D IN ) and - the user data (D) provided to be written into the data memory (RAM) IN ) to counter check code (CCC IN ) and - the calculated error correction code (ECC IN ) to the calculated counter check code (CCC IN ), and if there is a mismatch, IN ) or in the third step, the counter check code (CCC IN providing at least one error flag (CERR, UNCERR) indicating a malfunction in said calculation of - the counter check code (CCC IN ) caused by a failure when calculating the processed user data (D IN Detecting the bit positions of bits identified as faulty in checking whether at least one of the correctable error flag (CERR), the uncorrectable error flag (UNCERR) is set, or at least one bit position with a faulty bit is detected, and setting a Latent_Fault flag if at least one of the correctable error flag (CERR) or the uncorrectable error flag (UNCERR) is set, or at least one bit position with a faulty bit is detected; The method according to any one of C9 to C11, comprising the step of: [C13] The read cycle comprises: -The data memory (RAM) to the user data (D OUT ) and the associated stored error correcting code (ECC OUT ) and - The user data (D OUT ) to counter check code (CCC OUT ) and - The error correction code (ECC) read from the data memory (RAM) OUT ) to the calculated counter check code (CCC OUT ) and providing at least one error flag (CERR, UNCERR) indicating a malfunction of said data memory (RAM) in case of a discrepancy; - The user data (D OUT Detecting the bit position of the failing bit in - checking whether at least one of the correctable error flag (CERR), the uncorrectable error flag (UNCERR) is set or at least one bit position with a failed bit is detected, and setting a latent failure signal if at least one of the correctable error flag (CERR) or the uncorrectable error flag (UNCERR) is set or at least one bit position with a failed bit is detected; The method according to any one of C9 to C12, comprising the step of: [C14] The user data (D OUT 14. The method of claim 12 or 13, characterized in that: [C15] The receiver reads the error correction code (ECC) from the data memory (RAM). OUT ) together with the corrected user data (D OUT ) on the receiver side, and OUT 15. The method according to any one of C9 to C14, characterized in that the correctness of [C16] The user data (D IN ,D OUT ) to the corrected user data (DOUT, CORR ) and compare them with the user data (D IN ,D OUT ) and corrects the failed bit in the compared user data (D IN ,D OUT ) and the corrected user data (D OUT, CORR 16. The method according to claim 14 or 15, characterized in that in the step of indicating a potential fault signal if there is a discrepancy between the

Claims

1. An electronic circuit for self-testing a data memory (RAM), comprising: - User data (D) written into the data memory (RAM) IN ) to the associated error correction code (ECC IN a first error correction code unit (ECCGEN) for generating 1 ), wherein the electronic circuit stores the user data (D IN ) and the associated error correction code (ECC IN ) - User data (D) read from the data memory (RAM) OUT ) to counter check code (CCC OUT ) and calculate the counter check code (CCC OUT ) to the user data (D OUT ) and an error correction code (ECC) read from the data memory (RAM) OUT an error check unit (ECCCHK / CORR) for comparing the error check code (ECC OUT ) and the counter check code (CCC OUT ) and providing an error flag (CERR / UNCERR) if there is a difference between the In an electronic circuit comprising: The electronic circuit stores the user data (D IN ) and the associated error correction code (ECC) in the data memory (RAM). IN ) to be written into the memory in a write cycle. IN ) and the associated error correction code (ECC IN ) to the error check unit (ECCCHK / CORR) to check the associated error correction code (ECC IN ) and the error check unit (ECCCHK / CORR) checks the user data (D IN ) is calculated from the counter check code (CCC IN ) and providing a Latent_Fault flag if it is determined that there is a difference between the the error check unit (ECCCHK / CORR) comprises: a second error code generation unit (ECCGEN 2 ) provided for calculating the counter check code (CCC OUT ); and a check code comparison unit (ECCCHK) configured to compare the error correction code (ECC IN ) with the counter check code (CCC OUT ), and, if there is a mismatch between the compared error correction code (ECC IN ) and the counter check code (CCC OUT ), to set a correctable error flag (CERR) if a correctable error is detected, or to set an uncorrectable error flag (UNCERR) if an uncorrectable error is detected; the error check unit (ECCCHK / CORR) comprises an error location unit (ERRLOC) configured to locate at least one bit position of a detected faulty bit by comparing the error correction code (ECC IN ) with the respective counter check code (CCC OUT ), the error check unit (ECCCHK / CORR) is configured to set a Latent_Fault flag when locating at least one bit position of the faulty bit, or to set a correctable error flag (CERR) or an uncorrectable error flag (UNCERR), and the error location unit (ERRLOC) is adapted to function in both the write cycle and the read cycle. An electronic circuit comprising:

2. The electronic circuit a first multiplexer (MUX_1) with first and second inputs and an output, in which the user data (D IN ) is provided at the second input of the first multiplexer (MUX_1) and is used to read the user data (D) provided from the data memory (RAM) when reading from the data memory (RAM). OUT ) is provided at the first input of the first multiplexer (MUX_1), and the output of the first multiplexer (MUX_1) is provided to an input of the error check unit (ECCCHK / CORR) to receive the user data (D) read from the data memory (RAM) in the read cycle. OUT ) and provides the input of the error check unit (ECCCHK / CORR) with the user data (D) provided to be written into the data memory (RAM) in the write cycle. IN ) connected to the input of the error check unit (ECCCHK / CORR) when the first multiplexer (MUX_1) is controlled by a data memory read / write flag to provide a second multiplexer (MUX_2) having first and second inputs and an output, in which the user data (D IN ) for the first error correction code unit (ECCGEN 1 ) generated by the error correction code (ECC IN ) is provided at the second input of the second multiplexer (MUX_2) to receive the associated user data (D OUT ) read from the data memory (RAM) when reading the error correction code (ECC OUT ) is provided at the first input of the second multiplexer (MUX_2), the output of the second multiplexer (MUX_2) is connected to an input of the error check unit (ECCCHK / CORR), and the second multiplexer (MUX_2) provides the first error correction code unit (ECCGEN) to the error check unit (ECCCHK / CORR) during the write cycle. 1 ) obtained directly from the error correction code (ECC IN ) and in the read cycle, the error correction code (ECC) obtained directly from the data memory (RAM) OUT ) controlled by the data memory read / write flag to provide 2. The electronic circuit of claim 1, comprising:

3. 3. The electronic circuit of claim 2, wherein said first and second multiplexers (MUX_1, MUX_2) are integrally formed in a common multiplexer unit.

4. The output of the error check unit (ECCCHK / CORR) is provided to an input of at least one logic unit (&_1, &_2), and the at least one logic unit (&_1, &_2) checks the user data (D) provided to be written into the data memory in the write cycle. IN ) the calculated error correction code (ECC IN ) and the user data (D IN ) the counter check code (CCC IN ) to provide the Latent_Fault flag at the output of the at least one logic unit (&_1, &_2) during the write cycle as a result of a comparison with the stored error correction code (ECC) read from the data memory during the read cycle. OUT ) and the user data (D OUT ) the counter check code (CCC OUT 4. An electronic circuit according to claim 2 or 3, characterized in that it is controlled by said read / write flag to provide an error flag (CERR / UNCERR) as a result of a comparison with said read / write flag.

5. The error check unit (ECCCHK / CORR) is configured to check whether at least one bit position of the failing bit is connected to a first OR gate (OR 1 ) input, which provides a flag if indicated by a bit vector at the input of the first OR gate (OR 1 ) and the first OR gate (OR 1 At least one of the error flags provided by the first OR gate (OR), the correctable error flag (CERR), or the uncorrectable error flag (UNCERR) is input to a second OR gate (OR 2 ) is set at the input of the second OR gate (OR 2 ) providing a latent fault signal as an output of the second OR gate (OR 2 2. The electronic circuit of claim 1, further comprising:

6. The error check unit (ECCCHK / CORR) detects the user data (D IN , D OUT ) corrected user data (D OUT, CORR ) at the input of the error correction unit (ECCCOR), wherein the error check unit (ECCCHK / CORR) is designed to provide the user data (D IN , D OUT ) to the corrected user data (D OUT, CORR ) and the compared user data (D IN , D OUT ) and the corrected user data (D OUT, CORR 6. An electronic circuit according to any one of claims 1 to 5, characterized in that it further comprises a comparator unit designed to indicate an error flag in case of a discrepancy between

7. 1. A method for self-testing a data memory, comprising: a) a write cycle, - user data (D) provided to be written into said data memory (RAM) IN ) to the error correction code (ECC IN ) and - storing the calculated error correction code (ECC) in the data memory (RAM) IN ) and associated user data (D IN ) and a write cycle comprising the steps of: b) a read cycle, - User data (D OUT ) and associated stored error correcting code (ECC OUT ) and - the user data (D OUT ) to counter check code (CCC OUT ) and - the associated stored error correction code (ECC) read from the data memory (RAM) OUT ) to the counter check code (CCC OUT ) and providing an error flag indicating malfunction of said data memory (RAM) if there is a discrepancy; a read cycle comprising the step of: In the write cycle, - the user data (D) provided to be written into the data memory (RAM) IN ) to counter check code (CCC IN ) and - the calculated error correction code (ECC IN ) to the calculated counter check code (CCC IN ), and if there is a mismatch, the error correction code (ECC) stored in the data memory (RAM) in the write cycle. IN providing a Latent_Fault flag indicating a latent failure of the function provided to calculate characterized by the additional step of: The write cycle comprises: a first step of calculating an error correction code (ECC IN ) from user data (D IN ) provided to be written in said data memory (RAM); a second step of storing said calculated error correction code (ECC IN ) and said associated user data (D IN ) in said data memory (RAM); a third step of calculating a counter check code (CCC IN ) from said user data (D IN ) provided to be written in said data memory (RAM); a fourth step of comparing the calculated error correction code (ECC IN ) with the calculated counter check code (CCC IN ), providing, in case of a mismatch, at least one error flag (CERR, UNCERR) indicating a malfunction in the calculation of the error correction code (ECC IN ) in the first step or in the calculation of the counter check code (CCC IN ) in the third step; a fifth step of detecting the bit positions of bits identified as faults in the user data (D IN ) caused by a fault when calculating the counter check code (CCC IN ); a sixth step of checking whether at least one of the correctable error flag (CERR), the uncorrectable error flag (UNCERR) is set or at least one bit position with a faulty bit is detected, setting a Latent_Fault flag if at least one of the correctable error flag (CERR) or the uncorrectable error flag (UNCERR) is set or at least one bit position with a faulty bit is detected; comprising the step of: method.

8. - to the error check unit (ECCCHK / CORR) in the write cycle, the error correction code (ECCGEN) provided at the output of the error correction code unit (ECCGEN) IN ) and the associated user data (D) provided at the input of the error correction code unit (ECCGEN). IN ) to provide a Latent_Fault flag if there is a mismatch in the write cycle; - the error check unit (ECCCHK / CORR) receives the stored error correction code (ECCCHK / CORR) read from the data memory (RAM) during the read cycle; OUT ) and the associated stored user data (D OUT ) to provide an error flag indicating a malfunction of said data memory (RAM) during said read cycle; The method according to claim 7, implemented in an electronic circuit according to any one of claims 1 to 6, characterized in that

9. The user data (D IN , D OUT ) is corrected, a correctable error flag is set, and the user data (D IN , D OUT Any error with more than one bit in the user data (D IN , D OUT 9. The method of claim 7, wherein the error flag indicates an uncorrectable error without correcting the error.

10. The read cycle comprises: - User data (D OUT ) and the associated stored error correction code (ECC OUT ) and - the user data (D OUT ) to counter check code (CCC OUT ) and The error correction code (ECC) read from the data memory (RAM) OUT ) to the calculated counter check code (CCC OUT ) and providing at least one error flag (CERR, UNCERR) indicating a malfunction of said data memory (RAM) in case of a discrepancy; - the user data (D OUT Detecting the bit position of the failing bit in the checking whether at least one of the correctable error flag (CERR), the uncorrectable error flag (UNCERR) is set or at least one bit position with a failed bit is detected, and setting a latent failure signal if at least one of the correctable error flag (CERR) or the uncorrectable error flag (UNCERR) is set or at least one bit position with a failed bit is detected; The method according to any one of claims 7 to 9, characterized in that it comprises the step of:

11. The user data (D OUT 11. The method according to claim 7 or 10, characterized in that:

12. The receiver receives the error correction code (ECC) read from the data memory (RAM). OUT ) together with the corrected user data (D OUT ) on the receiver side, and OUT 12. The method according to claim 7, further comprising checking the correctness of

13. The user data (D IN , D OUT ) into the corrected user data (D OUT, CORR ) and they are compared with the user data (D IN , D OUT ) and corrects the failed bit in the compared user data (D IN , D OUT ) and the corrected user data (D OUT, CORR 13. The method according to claim 11 or 12, characterized in that in the step of indicating a potential fault signal, any discrepancy between the

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