Power Conversion Device

Abstract

To provide a power converter capable of suppressing potential fluctuations in a neutral point.SOLUTION: A power converter includes: a first capacitor and a second capacitor connected in series between a pair of DC terminals; a multiplex inverter circuit that has a plurality of three-level inverters connected to a neutral point between the first capacitor and the second capacitor and the pair of DC terminals, the outputs of the plurality of three-level inverters being serially multiplexed; and a control circuit. The control circuit causes a voltage of one of the first capacitors and the second capacitor to output from the three-level inverter of a first group of the plurality of three-level inverters and causes a voltage of the other capacitor that overlaps a voltage of the one capacitor to output from a three-level inverter of a second group out of the plurality of three-level inverters with the same polarity as a voltage of the one capacitor.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a power conversion device. [Background technology]

[0002] In recent years, renewable energy has become increasingly popular, and large-scale wind farms equipped with many wind turbines have been constructed. A wind turbine is equipped with a converter that converts the generated power to direct current (DC), an inverter that converts the DC to alternating current (AC), and a harmonic filter that removes harmonic currents generated by the inverter. However, when a wind turbine equipped with a harmonic filter is connected to a power grid, resonance occurs between the capacitance of the harmonic filter and the inductance of the power grid or transformer, which can cause the output voltage to become unstable.

[0003] Fig. 1 is a diagram showing the configuration of a resonance suppression device disclosed in Patent Document 1. Patent Document 1 proposes a resonance suppression device (STATCOM: Static Synchronous Compensator) that has a resonance suppression function as one of its harmonic control functions. This resonance suppression device multiplies the harmonic components of the system voltage v and / or the output current i1 of the wind power generator by a gain to obtain a current command value i * is calculated, and the current command value i * The deviation between the inverter output current i and the voltage command value v is detected and input to the current control unit. * The inverter connected in parallel to the power grid outputs the voltage command value v * By supplying a compensation current i according to the above to the power grid, harmonics in the power grid are suppressed.

[0004] On the other hand, high-voltage, large-capacity power conversion devices connected to power grids, such as STATCOMs, often employ a multiplexed configuration in which multiple inverters are connected in series or parallel. This configuration has the advantage of achieving higher output voltages and currents, as well as reducing output harmonics. Of these, the method of connecting inverters in series multiplexes offers a high degree of freedom in the output voltage waveform level, making it suitable for applications that output harmonic currents. In addition, it is possible to lower the carrier frequency depending on the number of inverters connected in series, thereby reducing switching losses generated by semiconductor switches.

[0005] A configuration is known in which a neutral point clamped three-level inverter is used for inverters that are multiplexed in series (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 6164291 [Patent Document 2] Patent No. 6178433 [Non-patent literature]

[0007] [Non-Patent Document 1] Shimamura et al., "Balancing Control of DC Input Capacitor Voltage of NPC Inverter", Institute of Electrical Engineers Semiconductor Power Conversion Study Group Document SPC-91-37 Summary of the Invention [Problem to be solved by the invention]

[0008] However, in a three-level inverter, the neutral point potential fluctuates depending on the operating mode in which current flows through the neutral point of the DC power supply circuit. Fluctuations in the neutral point potential can result in excessive voltage being applied to the semiconductor switches.

[0009] The present disclosure provides a power conversion device capable of suppressing potential fluctuations at the neutral point. [Means for solving the problem]

[0010] In one aspect of the present disclosure, a first capacitor and a second capacitor connected in series between a pair of DC terminals; a multiplexed inverter circuit including a plurality of three-level inverters connected to a neutral point between the first capacitor and the second capacitor and the pair of DC terminals, wherein outputs of the plurality of three-level inverters are multiplexed and connected in series; a control device that outputs the voltage of one of the first capacitor and the second capacitor from a three-level inverter of a first group of the plurality of three-level inverters, and outputs the voltage of the other capacitor, which is superimposed on the voltage of the one capacitor, from a three-level inverter of a second group of the plurality of three-level inverters with the same polarity as the voltage of the one capacitor. [Effects of the Invention]

[0011] According to one aspect of the present disclosure, it is possible to suppress fluctuations in the potential of the neutral point. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a configuration diagram of a resonance suppression device disclosed in Patent Document 1. [Figure 2] 1 is a diagram illustrating a configuration example of a power conversion device according to an embodiment of the present invention. [Figure 3] 10 is a timing chart illustrating a gate command that generates a switching pattern in which a neutral point current flows. [Figure 4] FIG. 10 is a diagram illustrating an example of the configuration of a control block that generates a gate command that generates a switching pattern in which a neutral point current flows. [Figure 5] 1 is a diagram illustrating the relationship between the output power of a three-level inverter, the carrier wave, and the potential fluctuation at the neutral point. [Figure 6] FIG. 10 is a diagram illustrating an example of the configuration of a control block for switching between ±Vp voltages and ±Vn voltages. [Figure 7] 10A and 10B are diagrams illustrating operational waveforms when the pulse switching signal is off or on. [Figure 8] FIG. 10 is a diagram illustrating an example of an operating waveform when there is no inter-multiplex pulse switching during dual multiplexing. [Figure 9] FIG. 10 is a diagram illustrating an example of an operational waveform when there is inter-multiplex pulse switching during dual multiplexing. [Figure 10] FIG. 10 is a diagram illustrating an example of an operating waveform when there is no inter-multiplex pulse switching during triple multiplexing. [Figure 11] FIG. 10 is a diagram illustrating an example of an operational waveform when there is inter-multiplex pulse switching during triple multiplexing. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0014] Fig. 2 is a diagram showing an example of the configuration of a power conversion device according to this embodiment, which shows a power conversion device in which NPC (Neutral Point Clamped) single-phase three-level inverters are connected in series. The power conversion device shown in Fig. 1 is applicable to a STATCOM as disclosed in Patent Document 1, but may also be applied to other uses.

[0015] 2 converts input DC power into three-phase AC power and outputs it to a three-phase power grid 14. The power conversion device 10 includes a plurality of capacitors (a first capacitor C1 and a second capacitor C2), a plurality of single-phase multiplex inverter circuits 11 (11U, 11V, 11W), a plurality of transformers 41 (41U, 41V, 41W), and a control device 30.

[0016] A plurality of capacitors C1, C2 are connected in series between a pair of DC terminals (a first DC terminal P and a second DC terminal N). The low potential side of the first capacitor C1 and the high potential side of the second capacitor C2 are connected at a neutral point M. The first capacitor C1 is connected between the first DC terminal P and the neutral point M, and the second capacitor C2 is connected between the neutral point M and the second DC terminal N.

[0017] The plurality of single-phase multiple inverter circuits 11 are interconnected, and in the example shown in Fig. 2 are star-connected. Each of the plurality of single-phase multiple inverter circuits 11 has a pair of AC terminals c, d and a plurality of single-phase three-level inverters 20. In the example shown in Fig. 2, the plurality of single-phase multiple inverter circuits 11 each have three stages of single-phase three-level inverters 20 with the same configuration, and are connected to the power grid 14 via a plurality of transformers 41.

[0018] The AC terminal c of the U-phase single-phase multiple inverter circuit 11U is connected to the U-phase power line of the power grid 14. The AC terminal c of the V-phase single-phase multiple inverter circuit 11V is connected to the V-phase power line of the power grid 14. The AC terminal c of the W-phase single-phase multiple inverter circuit 11W is connected to the W-phase power line of the power grid 14. The AC terminals d of the single-phase multiple inverter circuits 11 of each phase are connected to each other at the neutral point j.

[0019] The plurality of single-phase three-level inverters 20 for each phase convert DC power input from a common DC path into AC power and output it. Each of the plurality of single-phase three-level inverters 20 for each phase has a pair of DC cell terminals e, f, a neutral terminal m, a pair of AC cell terminals g, h, semiconductor switches Q1 to Q8, and diodes D1 to D4.

[0020] The first DC cell terminals e of the plurality of single-phase three-level inverters 20 for each phase are commonly connected to a first DC terminal P. The second DC cell terminals f of the plurality of single-phase three-level inverters 20 for each phase are commonly connected to a second DC terminal N. The neutral terminals m of the plurality of single-phase three-level inverters 20 for each phase are commonly connected to a neutral point M.

[0021] The plurality of single-phase three-level inverters 20 are each connected in series via a pair of AC cell terminals g, h. More specifically, the pair of AC cell terminals g, h of each of the plurality of single-phase three-level inverters 20 for each phase is connected in series via a transformer between a pair of AC terminals c, d of the single-phase multiplex inverter circuit 11 to which it belongs.

[0022] The single-phase three-level inverter 20 has a u-phase arm connected between a pair of DC terminals P, N, and a v-phase arm connected between a pair of DC terminals P, N.

[0023] The u-phase arm has switch elements Q1, Q2, Q3, and Q4 and clamp diodes D1 and D2. An anti-parallel diode is connected to each of the switch elements Q1 to Q4. The clamp diode D1 has an anode connected to the neutral terminal m and a cathode connected to the connection point between the switch elements Q1 and Q2. The clamp diode D2 has a cathode connected to the neutral terminal m and an anode connected to the connection point between the switch elements Q3 and Q4. The connection point between the switch elements Q2 and Q3 is connected to the AC cell terminal g.

[0024] The v-phase arm has switching elements Q5, Q6, Q7, and Q8 and clamp diodes D3 and D4. An anti-parallel diode is connected to each of switching elements Q5 to Q8. The anode of clamp diode D3 is connected to neutral terminal m, and the cathode is connected to the connection point between switching elements Q5 and Q6. The cathode of clamp diode D4 is connected to neutral terminal m, and the anode is connected to the connection point between switching elements Q7 and Q8. The connection point between switching elements Q6 and Q7 is connected to AC cell terminal h.

[0025] The switch elements Q1 to Q8 are, for example, IGBTs (Insulated Gate Bipolar Transistors), but may also be other semiconductor switches such as GCTs (Gate Commutated Turn-off) thyristors or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0026] The control device 30 is a device that controls the multiple single-phase multiple inverter circuits 11, and includes, for example, a memory and a processor. The functions of the control device 30 are realized by a processor such as a CPU (Central Processing Unit) operating according to a program stored in the memory. The functions of the control device 30 may also be realized by an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0027] The power conversion device 10 can output a multilevel voltage waveform with reduced harmonics and a voltage equal to or higher than the withstand voltage of the switching elements by having the control device 30 cause each of the multiple single-phase three-level inverters 20 to output voltage waveforms with different phases from one another. The voltage across the multiple single-phase three-level inverters 20 connected in series is the sum (superimposition) of the rectangular waveform voltages generated at each pair of AC cell terminals g, h of the multiple single-phase three-level inverters 20. Therefore, by having the single-phase three-level inverters 20 at each stage output voltage waveforms with different phases from one another, a multilevel waveform with reduced harmonics can be synthesized.

[0028] The single-phase three-level inverter 20 has the above-described configuration, which allows for the miniaturization of the LC filter used to convert the output voltage into a sine wave. In addition, the use of a three-level inverter has the advantage that the voltage fluctuation range per switch operation is half that of a two-level inverter, which means that the switching loss generated in the semiconductor switch can be roughly halved.

[0029] In the single-phase three-level inverter 20, the potential of the neutral point M may fluctuate depending on the current (neutral point current) flowing through the neutral point M. Fig. 3 is a timing chart illustrating an example of a gate command that generates a switching pattern in which the neutral point current flows. Fig. 4 is a diagram showing an example of the configuration of a control block that generates a gate command that generates a switching pattern in which the neutral point current flows.

[0030] In Figures 3 and 4, the three-level inverter converts the carrier wave into a modulating wave Vu+ * ,Vu- * ,Vv+ * ,Vv- * The semiconductor switches Q1 to Q8 operate in accordance with the gate commands derived by comparing Vu+ * is a command for generating gate commands for the switch elements Q1 and Q3. * is a command for generating gate commands for the switch elements Q2 and Q4. * is a command for generating gate commands for the switch elements Q5 and Q7. * is a command for generating gate commands for the switch elements Q6 and Q8.

[0031] As shown in Figure 3, the output voltage of the three-level inverter is composed of a combination of ±(Vp+Vn) voltages, ±Vp voltages, ±Vn voltages, and zero voltage. The Vp voltage represents the voltage of the first capacitor C1 (the voltage between the first DC terminal P and the neutral point M), and the Vn voltage represents the voltage of the second capacitor C2 (the voltage between the second DC terminal N and the neutral point M).

[0032] When ±(Vp+Vn) voltages are output, capacitors C1 and C2 are charged and discharged depending on the current polarity. Similarly, when ±Vp voltages are output, capacitor C1 is charged and discharged, when ±Vn voltages are output, capacitor C2 is charged and discharged, and when zero voltage is output, capacitors C1 and C2 are not charged and discharged.

[0033] When the polarity of the carrier wave is positive (0% to 100%), ±(Vp+Vn) voltages and ±Vn voltages are output, and when the polarity of the carrier wave is negative (0% to -100%), ±(Vp+Vn) voltages and ±Vp voltages are output.

[0034] A three-level inverter must be operated so that the Vp voltage and the Vn voltage are the same, but the potential of neutral point M fluctuates depending on the operating mode in which ±Vp voltage or ±Vn voltage is output (current flows through neutral point M). The potential of neutral point M also fluctuates when the frequency of the inverter's output power and the frequency of the carrier wave are the same.

[0035] FIG. 5 illustrates the relationship between the output power of the three-level inverter INV and fluctuations in the carrier and neutral point potentials. As shown in FIG. 5(a), when the carrier wave amplitude is between 0 and -100%, the Vp voltage rises. On the other hand, when the carrier wave amplitude is between 0 and 100%, the Vn voltage drops. This state continues, causing the potential at the neutral point M to fluctuate. However, when the phase of the output power lags behind the phase of the carrier wave by 90 degrees, as shown in FIG. 5(b), the increase and decrease in the Vp and Vn voltages (the charge and discharge amounts of capacitors C1 and C2) are equal, so the potential at the neutral point M hardly fluctuates. Such fluctuations in the neutral point potential may result in excessive voltage being applied to the semiconductor switch.

[0036] When a three-level inverter uses an Nth-order carrier wave to output an (N+1)th-order positive-phase harmonic current or an (N-1)th-order negative-phase harmonic current, the frequency of the output power matches the frequency of the carrier wave.

[0037] The harmonic power Q when the three-level inverter outputs the Mth-order positive-sequence harmonic current is expressed by the following equation 1.

[0038]

number

[0039] On the other hand, when the three-level inverter outputs an M-th order negative-phase harmonic current, the harmonic power Q is expressed by the following equation 2.

[0040]

number

[0041] As described above, in a three-level inverter, the neutral point potential may fluctuate. As a method for suppressing the fluctuation of the neutral point potential, a technique for controlling the fluctuation of the neutral point potential by superimposing a DC component on a voltage command is known (see, for example, Non-Patent Document 1).

[0042] Generally, in an inverter, the carrier frequency is set sufficiently high relative to the output voltage frequency, so the inverter output power (harmonic power) in the carrier frequency band is minute, and the resulting fluctuation in neutral point potential is small. Therefore, conventional control techniques such as those described in Non-Patent Document 1 may be able to suppress fluctuations in neutral point potential.

[0043] However, in devices like resonance suppression devices that have a relatively low carrier frequency and actively output harmonics, the neutral point potential fluctuations due to harmonic power are large. Therefore, to suppress the neutral point fluctuations using conventional control technology, it is necessary to provide sufficient margin in the electrical specifications of the inverter, which may result in an increase in the size of the device. Furthermore, the neutral point potential fluctuations may increase the voltage of one of the capacitors, which may exceed the element's withstand voltage and cause element damage.

[0044] Therefore, the control device 30 (see FIG. 2) according to this embodiment outputs the voltage of one of the first capacitor C1 and the second capacitor C2 from a three-level inverter of a first group (e.g., an odd-numbered stage) among the plurality of three-level inverters 20 connected in series in multiplex. Meanwhile, the control device 30 according to this embodiment outputs the voltage of the other capacitor, which is to be superimposed on the voltage of the one capacitor, from a three-level inverter of a second group (e.g., an even-numbered stage) among the plurality of three-level inverters 20, with the same polarity as the voltage of the one capacitor. The control device 30 controls each of the plurality of single-phase multiplex inverter circuits 11 (11U, 11V, 11W) in this output format.

[0045] For example, the control device 30 causes the three-level inverters of the first group to output the positive voltage (+Vp voltage) of the first capacitor C1, and the three-level inverters of the second group to output the positive voltage (+Vn voltage) of the second capacitor C2 that is superimposed on the positive voltage of the first capacitor C1. The control device 30 causes the three-level inverters of the first group to output the positive voltage (+Vn voltage) of the second capacitor C2, and the three-level inverters of the second group to output the positive voltage (+Vp voltage) of the first capacitor that is superimposed on the positive voltage of the second capacitor C2. The control device 30 causes the three-level inverters of the first group to output the negative voltage (-Vp voltage) of the first capacitor C1, and the three-level inverters of the second group to output the negative voltage (-Vn voltage) of the second capacitor C2 that is superimposed on the negative voltage of the first capacitor C1. The control device 30 causes the three-level inverters of the first group to output the negative voltage (-Vn voltage) of the second capacitor C2, and causes the three-level inverters of the second group to output the negative voltage (-Vp voltage) of the first capacitor C1 to be superimposed on the negative voltage of the second capacitor C2.

[0046] According to this embodiment, in a first half cycle in which a positive voltage is output from each pair of AC cell terminals g, h, if the first multiplex (first stage) inverter outputs a +Vp voltage (or a +Vn voltage), the control device 30 controls the second multiplex (second stage) inverter to output a +Vn voltage (or a +Vp voltage). On the other hand, in a second half cycle in which a negative voltage is output from each pair of AC cell terminals g, h, if the first multiplex (first stage) inverter outputs a -Vp voltage (or a -Vn voltage), the control device 30 controls the second multiplex (second stage) inverter to output a -Vn voltage (or a -Vp voltage). In this way, by exchanging the output voltages between the inverters connected in series, the ±Vp voltages and ±Vn voltages that cause potential fluctuations at the neutral point M can be canceled out between the inverters connected in series. As a result, it is possible to prevent the power conversion device 10 from becoming larger and prevent element damage.

[0047] Next, the power conversion device 10 of this embodiment will be described in more detail.

[0048] Fig. 6 is a diagram showing an example of the configuration of a control block for switching between ±Vp voltages and ±Vn voltages. Fig. 7 is a diagram showing operating waveforms when the pulse switching signal is off or on. The switching control shown in Fig. 6 is realized by control device 30.

[0049] As shown in FIGS. 6 and 7, the control device 30 converts the carrier wave into a modulated wave Vu+ * ,Vu- * ,Vv+ * ,Vv- * The control device 30 then derives gate commands for the semiconductor switches Q1 to Q8 by comparing the carrier wave with the modulating wave Vu+ * ,Vu- * ,Vv+ * ,Vv- * The gate commands for each switch element derived after comparing them are swapped between Q1 and Q8, Q2 and Q7, Q3 and Q6, and Q4 and Q5 according to the pulse switching signal. This allows the output of ±Vp voltages and ±Vn voltages to be switched (see A in Figure 7).

[0050] The control device 30 switches based on the number of multiplexing stages (the number of stages of three-level inverters connected in series). For example, the control device 30 turns off the pulse switching signal of the even-numbered three-level inverters and turns on the pulse switching signal of the odd-numbered three-level inverters. In this case, the switching elements Q1 to Q8 in the even-numbered three-level inverters switch according to the gate command shown in FIG. 7(a), and the switching elements Q1 to Q8 in the odd-numbered three-level inverters switch according to the gate command shown in FIG. 7(b). This switching causes the voltage Vuv output from the pair of AC cell terminals g, h of the even-numbered three-level inverters as shown in FIG. 7(a) and the voltage Vuv output from the pair of AC cell terminals g, h of the odd-numbered three-level inverters as shown in FIG. 7(b) to overlap (be added).

[0051] As a result, the positive voltage (+Vp voltage) of the first capacitor C1 output from the odd-numbered three-level inverter is superimposed on the positive voltage (+Vn voltage) of the second capacitor C2 output from the even-numbered three-level inverter. The positive voltage (+Vn voltage) of the second capacitor C2 output from the odd-numbered three-level inverter is superimposed on the positive voltage (+Vp voltage) of the first capacitor C1 output from the even-numbered three-level inverter. The negative voltage (-Vp voltage) of the first capacitor C1 output from the odd-numbered three-level inverter is superimposed on the negative voltage (-Vn voltage) of the second capacitor C2 output from the even-numbered three-level inverter. The negative voltage (-Vn voltage) of the second capacitor C2 output from the odd-numbered three-level inverter is superimposed on the negative voltage (-Vp voltage) of the first capacitor C1 output from the even-numbered three-level inverter.

[0052] Fig. 8 is a timing chart illustrating the operating waveforms when there is no inter-multiplex pulse switching during dual multiplexing. Fig. 9 is a timing chart illustrating the operating waveforms when there is inter-multiplex pulse switching during dual multiplexing. Figs. 8 and 9 illustrate the case where the number of multiplexes is 2 (even number).

[0053] As shown in Figure 8, when the pulse switching signals of the first multiplex (first stage) and second multiplex (second stage) three-level inverters are off, the ±Vp voltages (or ±Vn voltages) of the first multiplex and the ±Vp voltages (or ±Vn voltages) of the second multiplex overlap. Therefore, the ±Vp voltages and ±Vn voltages that cause potential fluctuations at neutral point M increase by the number of multiplexes, and the potential fluctuations at neutral point M also increase by that amount (see B in Figure 8).

[0054] On the other hand, as shown in FIG. 9, by setting the pulse switching signal of the first multiplex to off and the pulse switching signal of the second multiplex to on, when the first multiplex outputs ±Vp voltages (or ±Vn voltages), the second multiplex outputs ±Vn voltages (or ±Vp voltages). Therefore, the ±Vp voltages and ±Vn voltages that cause potential fluctuations at neutral point M are canceled out between the multiplexes (see C in FIG. 9). This makes it possible to suppress potential fluctuations at neutral point M. Note that FIG. 9 illustrates a configuration in which three-level inverters whose pulse switching signals are off belong to a first group, and three-level inverters whose pulse switching signals are on belong to a second group, and illustrates a case in which the numbers of three-level inverters belonging to both groups are equal.

[0055] Fig. 10 is a timing chart illustrating an example of operating waveforms when there is no inter-multiplex pulse switching during triple multiplexing. Fig. 11 is a timing chart illustrating an example of operating waveforms when there is inter-multiplex pulse switching during triple multiplexing. Figs. 10 and 11 illustrate the case where the number of multiplexes is 3 (odd number).

[0056] As shown in Figure 10, when the pulse switching signals of the first multiplex (first stage), second multiplex (second stage), and third multiplex (third stage) three-level inverters are off, the ±Vp voltages (or ±Vn voltages) of the first multiplex, the ±Vp voltages (or ±Vn voltages) of the second multiplex, and the ±Vp voltages (or ±Vn voltages) of the third multiplex overlap. Therefore, the ±Vp voltages and ±Vn voltages that cause potential fluctuations at neutral point M increase by the number of multiplexes, and the potential fluctuations at neutral point M also increase by that amount (see D in Figure 10).

[0057] On the other hand, as shown in FIG. 11 , by setting the pulse switching signal of the first multiplex to OFF, the pulse switching signal of the second multiplex to ON, and the pulse switching signal of the third multiplex to OFF, when the first multiplex outputs ±Vp voltages (or ±Vn voltages), the second multiplex outputs ±Vn voltages (or ±Vp voltages), and the third multiplex outputs ±Vp voltages (or ±Vn voltages). Therefore, the ±Vp voltages and ±Vn voltages that cause potential fluctuations at neutral point M are canceled out by the first multiplex and the second multiplex, leaving only the ±Vp voltages and ±Vn voltages of the third multiplex. Therefore, the potential fluctuations at neutral point M can be reduced to only that of one multiplex (see E in FIG. 11 ). Note that FIG. 11 illustrates an example in which three-level inverters whose pulse switching signals are OFF belong to the first group, and three-level inverters whose pulse switching signals are ON belong to the second group, with the difference in the number of three-level inverters belonging to both groups being 1.

[0058] The control device 30 may also switch each of the multiple three-level inverters 20 connected in series between the first group and the second group. This allows, for example, when at least one of the multiple three-level inverters 20 connected in series is bypassed due to a failure or the like, to rearrange the groups to which the remaining three-level inverters 20 belong. This allows reselection of whether the remaining three-level inverters 20 should be switched using the command pattern shown in FIG. 7(a) or FIG. 7(b), thereby enabling continued suppression of neutral point potential fluctuations.

[0059] Although the embodiments have been described above, the technology of the present disclosure is not limited to the above-described embodiments, and various modifications and improvements are possible, such as combinations with or substitutions for part or all of other embodiments. [Explanation of symbols]

[0060] 10 Power conversion device 11, 11U, 11V, 11W single-phase multiple inverter circuit 14 Power system 20 3-level inverter 30 Control device 41, 41U, 41V, 41W transformers

Claims

1. a first capacitor and a second capacitor connected in series between a pair of DC terminals; a multiplexed inverter circuit including a plurality of three-level inverters connected to a neutral point between the first capacitor and the second capacitor and to the pair of DC terminals, wherein outputs of the plurality of three-level inverters are multiplexed and connected in series; a control device that outputs a voltage of one of the first capacitor and the second capacitor from a three-level inverter of a first group among the plurality of three-level inverters, and outputs a voltage of the other capacitor, which is superimposed on the voltage of the one capacitor, from a three-level inverter of a second group among the plurality of three-level inverters, with the same polarity as the voltage of the one capacitor; The control device When the number of multiplexed inverters is even, the control is switched to a control in which the number of the three-level inverters in the first group is equal to the number of the three-level inverters in the second group, and when the number of multiplexed inverters is odd, the control is switched to a control in which the difference in number between the three-level inverters in the first group and the three-level inverters in the second group is 1; The positive voltage of the first capacitor is output from the three-level inverter of the first group, and the positive voltage of the second capacitor superimposed on the positive voltage of the first capacitor is output from the three-level inverter of the second group; The positive voltage of the second capacitor is output from the three-level inverter of the first group, and the positive voltage of the first capacitor superimposed on the positive voltage of the second capacitor is output from the three-level inverter of the second group; The negative voltage of the first capacitor is output from the three-level inverter of the first group, and the negative voltage of the second capacitor superimposed on the negative voltage of the first capacitor is output from the three-level inverter of the second group; The negative voltage of the second capacitor is output from the three-level inverter of the first group, and the negative voltage of the first capacitor superimposed on the negative voltage of the second capacitor is output from the three-level inverter of the second group. Power conversion device.

2. the three-level inverters of the first group are three-level inverters in odd-numbered stages among the plurality of three-level inverters, The three-level inverters of the second group are three-level inverters in even-numbered stages among the plurality of three-level inverters. The power conversion device according to claim 1 .

3. 3 . The power conversion device according to claim 1 , wherein the control device switches each of the plurality of three-level inverters between the three-level inverter of the first group and the three-level inverter of the second group.

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