Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of suppressing deterioration in electric characteristics associated with a temperature rise and a method for manufacturing the semiconductor device.SOLUTION: A semiconductor device 100 comprises a substrate 10, a semiconductor layer lamination structure, and a source electrode and a drain electrode. The semiconductor layer lamination structure includes a first channel layer 111, a first barrier layer 121, a second channel layer 112, and a second barrier layer 122. A first recess 81, a second recess 82, and a plurality of third recesses are formed in the semiconductor layer lamination structure. The first recess, the second recess, and the third recess reach the first channel layer. The semiconductor layer lamination structure also includes a source region 21, a drain region 22, and a plurality of gate electrodes 33 embedded in each third recess. Adjacent third recesses constitute a recess pair, and a fourth recess 91 penetrating at least the second barrier layer is formed between two third recesses constituting the recess pair of the semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] 2. Description of the Related Art A field effect transistor (FET) is known which has a plurality of gate electrodes buried down to the channel layer, arranged between a source region and a drain region so as to intersect with the direction of carrier conduction in the channel layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,388,746 [Patent Document 2] US Patent Application Publication No. 2019 / 0267454 [Patent Document 3] Japanese Patent Application Laid-Open No. 2010-135640 [Patent Document 4] Japanese Patent Publication No. 2020-136476 [Non-patent literature]

[0004] [Non-Patent Document 1] K. Miwa, Appl. Phys. Express 13 (2020) Summary of the Invention [Problem to be solved by the invention]

[0005] Conventional FETs are prone to localized temperature rises, which can lead to deterioration of electrical characteristics.

[0006] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress deterioration of electrical characteristics that accompanies an increase in temperature. [Means for solving the problem]

[0007] A semiconductor device according to the present disclosure includes a substrate, a semiconductor layer provided on the substrate, and a source electrode and a drain electrode in ohmic contact with the semiconductor layer. The semiconductor layer includes a first channel layer, a first barrier layer provided on the first channel layer, a second channel layer provided on the first barrier layer, and a second barrier layer provided on the second channel layer. The semiconductor layer is formed with a first recess located on the substrate side of the source electrode, a second recess located on the substrate side of the drain electrode, and a plurality of third recesses located between the first recess and the second recess and arranged in a direction intersecting an arrangement direction of the first recess and the second recess. The first recess, the second recess, and the third recess are formed in the first channel layer. the semiconductor layer has: a source region formed in the first recess and having a lower electrical resistance than the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer; and a drain region formed in the second recess and having a lower electrical resistance than the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer; the source electrode is in contact with the source region, the drain electrode is in contact with the drain region, and the semiconductor layer has a plurality of gate electrodes embedded in each of the third recesses; adjacent third recesses form a recess pair; and in some of the recess pairs, a fourth recess is formed between two of the third recesses that form the recess pair in the semiconductor layer, the fourth recess penetrating at least the second barrier layer. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to suppress the deterioration of electrical characteristics that accompanies an increase in temperature. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a top view showing the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view (part 1) showing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 2) showing the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is a top view showing a semiconductor device according to a reference example. [Figure 13] FIG. 13 is a cross-sectional view showing a semiconductor device according to a reference example. [Figure 14] FIG. 14 is a diagram showing the temperature distribution in the channel region during operation in the reference example. [Figure 15] FIG. 15 is a diagram showing the temperature distribution in the channel region during operation in the first embodiment. [Figure 16] FIG. 16 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 17] FIG. 17 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 18] FIG. 18 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 19]FIG. 19 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 20] FIG. 20 is a diagram (part 1) showing the band structures of the channel layer and the barrier layer in the second embodiment. [Figure 21] FIG. 21 is a diagram (part 2) showing the band structures of the channel layer and the barrier layer in the second embodiment. [Figure 22] FIG. 22 is a diagram (part 3) showing the band structures of the channel layer and the barrier layer in the second embodiment. [Figure 23] FIG. 23 is a perspective view showing a semiconductor device according to the third embodiment. [Figure 24] FIG. 24 is a cross-sectional view showing a semiconductor device according to the third embodiment. [Figure 25] FIG. 25 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 26] FIG. 26 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 27] FIG. 27 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the third embodiment. [Figure 28] FIG. 28 is a diagram (part 1) showing the band structures of the channel layer and the barrier layer in the third embodiment. [Figure 29] FIG. 29 is a diagram (part 2) showing the band structures of the channel layer and the barrier layer in the third embodiment. [Figure 30] FIG. 30 is a diagram (part 3) showing the band structures of the channel layer and the barrier layer in the third embodiment. [Figure 31] FIG. 31 is a diagram showing the temperature distribution in the channel region during operation in the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0011] [1] A semiconductor device according to one aspect of the present disclosure includes a substrate, a semiconductor layer provided on the substrate, and a source electrode and a drain electrode in ohmic contact with the semiconductor layer. The semiconductor layer includes a first channel layer, a first barrier layer provided on the first channel layer, a second channel layer provided on the first barrier layer, and a second barrier layer provided on the second channel layer. The semiconductor layer includes a first recess located on the substrate side of the source electrode, a second recess located on the substrate side of the drain electrode, and a plurality of third recesses located between the first recess and the second recess and arranged in a direction intersecting an arrangement direction of the first recess and the second recess. The first recess, the second recess, and the third recess are formed in the first channel layer. the semiconductor layer has a source region formed in the first recess and having a lower electrical resistance than the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer, and a drain region formed in the second recess and having a lower electrical resistance than the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer, the source electrode is in contact with the source region, the drain electrode is in contact with the drain region, and the semiconductor layer has a plurality of gate electrodes embedded in each of the third recesses, adjacent third recesses form a recess pair, and in some of the recess pairs, a fourth recess is formed between two of the third recesses that form the recess pair in the semiconductor layer, the fourth recess penetrating at least the second barrier layer.

[0012] In some of the recess pairs, a fourth recess is formed between two third recesses constituting the recess pair in the semiconductor layer, so that heat generated in the channel region near the gate electrode located at the center can be released to the outside without accumulating inside, thereby suppressing deterioration of electrical characteristics due to temperature rise.

[0013] [2] In [1], the fourth recesses may be formed in every other pair of recesses. In this case, it is easy to suppress deterioration of electrical characteristics due to an increase in temperature while ensuring the amount of current.

[0014] [3] In [1] or [2], the fourth recess may reach the first channel layer. In this case, the fourth recess can be formed by dry etching.

[0015] [4] In [1] or [2], the bottom surface of the fourth recess may be located within the first barrier layer. In this case, the fourth recess can be formed by photoelectrochemical etching, which makes it easy to suppress etching damage.

[0016] [5] In [1] or [2], the first barrier layer may have a first band gap, the second barrier layer may have a second band gap smaller than the first band gap, and the bottom surface of the fourth recess may be located within the second barrier layer. In this case, a current can flow through the first channel layer even on the substrate side of the fourth recess.

[0017] [6] In [5], the first barrier layer may be a first nitride semiconductor layer containing Al at a first concentration, and the second barrier layer may be a second nitride semiconductor layer containing Al at a second concentration lower than the first concentration. In this case, the second band gap of the second barrier layer is easily made smaller than the first band gap of the first barrier layer.

[0018] [7] In [5] or [6], a plurality of pairs of the second channel layer and the second barrier layer may be provided. In this case, the amount of current can be adjusted according to the number of pairs of the second channel layer and the second barrier layer.

[0019] [8] In any of [5] to [7], the semiconductor layer may have a third channel layer and a third barrier layer provided on the third channel layer, the first channel layer may be provided on the third barrier layer, and the first recess, the second recess, and the third recess may reach the third channel layer. In this case, a current can flow through the third channel layer.

[0020] [9] A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes forming a semiconductor layer on a substrate, and forming a source electrode and a drain electrode in ohmic contact with the semiconductor layer, wherein the forming the semiconductor layer includes forming a first channel layer, forming a first barrier layer on the first channel layer, forming a second channel layer on the first barrier layer, forming a second barrier layer on the second channel layer, forming a first recess located on the substrate side of the source electrode, forming a second recess located on the substrate side of the drain electrode, forming a source region in the first recess, the source region having lower electrical resistance than the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer, and forming a second recess in the second recess. forming a drain region having lower electrical resistance than the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer; forming a plurality of third recesses located between the first recess and the second recess and arranged in a direction intersecting the arrangement direction of the first recess and the second recess; adjacent third recesses constituting recess pairs, and forming fourth recesses penetrating at least the second barrier layer between two of the third recesses constituting the recess pair in the semiconductor layer in some of the recess pairs; and embedding a plurality of gate electrodes in each of the third recesses, wherein the first recess, the second recess, and the third recess reach the first channel layer, the source electrode contacts the source region, and the drain electrode contacts the drain region.

[0021] In some of the recess pairs, a fourth recess is formed between two third recesses constituting the recess pair in the semiconductor layer, so that heat generated in the channel region near the gate electrode located at the center can be released to the outside without accumulating inside, thereby suppressing deterioration of electrical characteristics due to temperature rise.

[0022]

[10] In [9], the first barrier layer may have a first band gap, the second barrier layer may have a second band gap smaller than the first band gap, and the step of forming the fourth recess may include a step of photoelectrochemically etching the semiconductor layer while irradiating the semiconductor layer with light having energy smaller than the first band gap and larger than the second band gap. In this case, the first barrier layer remains on the substrate side of the fourth recess, allowing current to flow through the first channel layer.

[0023] [Details of the embodiments of the present disclosure] Embodiments of the present disclosure will be described in detail below, but the present disclosure is not limited thereto. Note that, in this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description. In this specification and drawings, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction will be referred to as the XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction will be referred to as the YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction will be referred to as the ZX plane. For convenience, the Z1-Z2 direction will be defined as the up-down direction, with the Z1 side referred to as the upper side and the Z2 side referred to as the lower side. Furthermore, a planar view refers to viewing an object from the Z1 side, and a planar shape refers to the shape of an object viewed from the Z1 side.

[0024] (First embodiment) The first embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT) that uses a nitride semiconductor as a main constituent material. FIG. 1 is a perspective view showing the semiconductor device according to the first embodiment. FIG. 2 is a top view showing the semiconductor device according to the first embodiment. FIGS. 3 and 4 are cross-sectional views showing the semiconductor device according to the first embodiment. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIG. 2. Note that the insulating film, source electrode, and drain electrode are omitted in FIG. 1, and the insulating film is omitted in FIG. 2.

[0025] As shown in FIGS. 1 to 4 , the semiconductor device 100 according to the first embodiment includes a substrate 10 and a stacked structure 20 of multiple semiconductor layers provided on the substrate 10. For example, the substrate 10 is a SiC substrate having a (0001) plane on its upper surface, and the stacking direction of the stacked structure 20 is the

[0001] direction. The stacked structure 20 includes, formed in this order from the substrate 10 side, a channel layer 111, a barrier layer 121, a channel layer 112, a barrier layer 122, a channel layer 113, a barrier layer 123, a channel layer 114, and a barrier layer 124. The stacked structure 20 may include a buffer layer provided between the substrate 10 and the channel layer 111, and may include a cap layer provided on the barrier layer 124.

[0026] The channel layer 111 is, for example, an undoped GaN layer having a thickness of 5 nm to 500 nm. The channel layers 112 to 114 are, for example, undoped GaN layers having a thickness of 5 nm to 30 nm. The barrier layers 121 to 124 are, for example, n-type AlN layers having a thickness of 5 nm to 30 nm. x Ga 1-x The channel layer 111 is an N layer. A part of the channel layer 111 may be a buffer layer. The band gaps of the barrier layers 121 to 124 are larger than the band gaps of the channel layers 111 to 114. The channel layer 111 is an example of a first channel layer, and the barrier layer 121 is an example of a first barrier layer. The channel layers 112 to 114 are an example of a second channel layer, and the barrier layers 122 to 124 are an example of a second barrier layer.

[0027] A recess 81 for a source and a recess 82 for a drain are formed in the stacked structure 20. The recesses 81 and 82 reach the channel layer 111. The bottom surfaces of the recesses 81 and 82 are located closer to the substrate 10 than the upper surface of the channel layer 111. The bottom surfaces of the recesses 81 and 82 are located deeper toward the substrate 10 than the upper surface of the channel layer 111. The recess 81 is an example of a first recess, and the recess 82 is an example of a second recess.

[0028] The stacked structure 20 has a source region 21 provided in the recess 81 and a drain region 22 provided in the recess 82. The electrical resistance of each of the source region 21 and the drain region 22 is lower than the electrical resistance of the channel layers 111 to 114 and the barrier layers 121 to 124. The source region 21 and the drain region 22 are, for example, n-type GaN layers. The stacked structure 20 is an example of a semiconductor layer.

[0029] The semiconductor device 100 has a source electrode 31 provided on the source region 21 and a drain electrode 32 provided on the drain region 22. The source electrode 31 contacts the source region 21, and the drain electrode 32 contacts the drain region 22. The source electrode 31 and the drain electrode 32 include, for example, a Ta film and an Al film thereon.

[0030] The semiconductor device 100 has an insulating film 41 that covers a portion of the stacked structure 20 between the source electrode 31 and the drain electrode 32. The insulating film 41 is formed on the stacked structure 20. An opening 61 for a source and an opening 62 for a drain are formed in the insulating film 41. The source electrode 31 is provided inside the opening 61 for the source, and the drain electrode 32 is provided inside the opening 62 for the drain. The insulating film 41 is, for example, a Si nitride film.

[0031] A plurality of recesses 83 for gates are formed in the stacked structure 20. The number of recesses 83 is not limited, but may be, for example, four or more. The recesses 83 are located between the recesses 81 and the recesses 82, and are arranged in a direction intersecting the arrangement direction of the recesses 81 and the recesses 82. The recesses 83 reach the channel layer 111. The bottom surface of each recess 83 is located closer to the substrate 10 than the top surface of the channel layer 111. The bottom surface of each recess 83 is located deeper toward the substrate 10 than the top surface of the channel layer 111. The recesses 83 are an example of a third recess.

[0032] Adjacent recesses 83 form a recess pair. There are a plurality of recess pairs, and in some of the plurality of recess pairs, a current-limiting recess 91 is formed between two recesses 83 that form the recess pair in the stacked structure 20. The recess 91 is formed, for example, in every other recess pair. The recess 91 penetrates the barrier layers 121 to 124 and reaches the channel layer 111. The bottom surface of each recess 91 is located closer to the substrate 10 than the top surface of the channel layer 111. The bottom surface of each recess 91 is located deeper toward the substrate 10 than the top surface of the channel layer 111. The recess 91 may be connected to an adjacent recess 83. When the recess 91 is connected to the adjacent recess 83, the recess 83 and the recess 91 may be considered as a single recess. The recess 91 is an example of a fourth recess.

[0033] An opening 63 located above the recess 83 and an opening 64 located above the recess 91 are formed in the insulating film 41. The openings 63 and 64 may be formed so as to be continuous with each other.

[0034] The semiconductor device 100 has a plurality of gate electrodes 33 embedded in each of the recesses 83. The plurality of gate electrodes 33 may be commonly connected. The gate electrode 33 includes, for example, a Ni film and an Au film thereon.

[0035] The semiconductor device 100 has an insulating film 42 that covers the gate electrode 33. The insulating film 42 is also formed on the insulating film 41. The insulating film 42 may also cover the source electrode 31 and the drain electrode 32.

[0036] 3 and 4, in the semiconductor device 100, a 2DEG 171 exists near the upper surface of the channel layer 111, a 2DEG 172 exists near the upper surface of the channel layer 112, a 2DEG 173 exists near the upper surface of the channel layer 113, and a 2DEG 174 exists near the upper surface of the channel layer 114. Also, as shown in FIG. 2, a depletion layer 35 is formed around the gate electrode 33 in response to the gate voltage applied to the gate electrode 33. When the depletion layer 35 is formed, the 2DEGs 171 to 174 are almost absent from the channel layers 111 to 114 within the depletion layer 35. Therefore, the current I flowing between the source region 21 and the drain region 22 can be controlled in response to the gate voltage applied to the gate electrode 33. In this manner, the region between adjacent gate electrodes 33 in the stacked structure 20 functions as an effective channel region.

[0037] Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Figures 5 to 11 are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment. Figures 5 to 8 show variations of the cross section shown in Figure 3. Figures 9 to 11 show variations of the cross section shown in Figure 4.

[0038] 5, the channel layers 111 to 114 and the barrier layers 121 to 124 are formed on the substrate 10. The channel layers 111 to 114 and the barrier layers 121 to 124 are formed by, for example, metal organic chemical vapor deposition (MOCVD).

[0039] Next, as shown in FIG. 6, a recess 81 for a source and a recess 82 for a drain are formed in the channel layers 111-114 and the barrier layers 121-124. To form the recesses 81 and 82, reactive ion etching (RIE) is performed using an electron beam resist (not shown) as a mask. A reactive gas containing chlorine (Cl) is used to etch the channel layers 111-114 and the barrier layers 121-124. After the recesses 81 and 82 are formed, the mask is removed.

[0040] Next, a source region 21 is formed in the recess 81, and a drain region 22 is formed in the recess 82. For example, an n-type GaN layer is formed as the source region 21 and the drain region 22. The n-type GaN layer can be formed by, for example, a sputtering method, an MOCVD method, or a molecular beam epitaxy (MBE) method. In this way, a stacked structure 20 is formed.

[0041] 7, an insulating film 41 is formed on the barrier layer 124. Next, an opening 61 for a source and an opening 62 for a drain are formed in the insulating film 41. The openings 61 and 62 are formed by RIE using, for example, an electron beam resist (not shown) as a mask. A reactive gas containing fluorine (F) is used to etch the insulating film 41.

[0042] Next, as shown in FIG. 8 , a source electrode 31 is formed inside the opening 61, and a drain electrode 32 is formed inside the opening 62. The source electrode 31 and the drain electrode 32 can be formed by, for example, vapor deposition, lift-off, and alloying heat treatment. The source electrode 31 and the drain electrode 32 include, for example, a Ta film and an Al film thereon. The source electrode 31 and the drain electrode 32 each make ohmic contact with the stacked structure 20.

[0043] 9, an opening 63 for a gate and an opening 64 for a recess 91 are formed in the insulating film 41. The openings 63 and 64 may be formed so as to be continuous with each other. The openings 63 and 64 are formed by RIE using, for example, an electron beam resist (not shown) as a mask. A reactive gas containing F is used to etch the insulating film 41.

[0044] 10, a gate recess 83 and a current limiting recess 91 are formed in the channel layers 111-114 and the barrier layers 121-124. The recesses 83 and 91 are formed by RIE using, for example, the electron beam resist used to form the openings 63 and 64 as a mask. A reactive gas containing Cl is used to etch the channel layers 111-114 and the barrier layers 121-124. After the recesses 83 and 91 are formed, the mask is removed.

[0045] 11, the gate electrode 33 is formed in the opening 63 and the recess 83. The gate electrode 33 can be formed by, for example, evaporation and lift-off. The gate electrode 33 includes, for example, a Ni film and an Au film thereon. Next, an insulating film 42 that covers the gate electrode 33 is formed on the insulating film 41. The insulating film 42 may cover the source electrode 31 and the drain electrode 32.

[0046] Thereafter, wiring and the like are formed as necessary. In this manner, the semiconductor device 100 according to the first embodiment can be manufactured.

[0047] The effects of the first embodiment will now be described with reference to a reference example. Fig. 12 is a top view showing a semiconductor device according to the reference example. Fig. 13 is a cross-sectional view showing a semiconductor device according to the reference example. Fig. 13 corresponds to a cross-sectional view taken along line XIII-XIII in Fig. 12.

[0048] 12 and 13, in the semiconductor device 900 according to the reference example, the current limiting recesses 91 are not formed in the stacked structure 20. Therefore, in all pairs of recesses, the 2DEGs 171-174 are present near the top surfaces of the channel layers 111-114, respectively.

[0049] The other configurations are the same as those in the first embodiment.

[0050] FIG. 14 is a diagram showing the temperature distribution in the channel region during operation in the reference example. FIG. 15 is a diagram showing the temperature distribution in the channel region during operation in the first embodiment. The upper part of FIG. 14 shows a top view, and the lower part shows the temperature distribution along the two-dot chain line B in the top view. The upper part of FIG. 15 shows a top view, and the lower part shows the temperature distribution along the two-dot chain line B in the top view. The thickness of the arrow indicating the current I in FIGS. 14 and 15 reflects the magnitude of the current I.

[0051] As shown in FIG. 14, in the reference example, the temperature of the channel regions located closer to the center tends to be higher. This is because heat generated in the outer channel regions is easily released to the outside, while heat generated in the center tends to accumulate inside. In contrast, in the first embodiment, the current-limiting recess 91 is formed in the stacked structure 20, so that the temperature in the channel regions located closer to the center is approximately the same as the temperature in the channel regions located closer to the outside, as shown in FIG. 15. This is because heat generated in the center is also easily released to the outside before accumulating inside. Therefore, according to the first embodiment, it is possible to suppress deterioration of electrical characteristics due to an increase in temperature.

[0052] By forming the recesses 91 in every other pair of recesses, it is possible to easily suppress the deterioration of electrical characteristics due to an increase in temperature while ensuring the amount of current.

[0053] Since the recess 91 reaches the channel layer 111, the recess 91 can be easily formed by dry etching.

[0054] (Second embodiment) Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the stacked structure 20. Fig. 16 is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0055] In the semiconductor device 200 according to the second embodiment, as shown in FIG. 16 , instead of the recess 91, a recess 92 is formed in the stacked structure 20. The recess 92 penetrates the barrier layers 122 to 124 and reaches the barrier layer 121. The bottom surfaces of the recesses 92 are located closer to the substrate 10 than the top surfaces of the barrier layers 121. The bottom surfaces of the recesses 92 are located deeper toward the substrate 10 than the top surfaces of the barrier layers 121. Furthermore, the bottom surfaces of the recesses 92 are located above (on the side away from the substrate 10) the interface between the channel layer 111 and the barrier layer 122. The recess 92 may be connected to an adjacent recess 83. The recess 92 is an example of a fourth recess.

[0056] 16, in the semiconductor device 200, 2DEGs 171-174 are present near the upper surfaces of the channel layers 111-114, respectively. However, on the substrate 10 side of the bottom surface of the recess 92, the 2DEG 171 is not present in the channel layer 111 when no voltage is applied to the gate electrode 33.

[0057] The other configurations are the same as those in the first embodiment.

[0058] Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described. Figures 17 to 19 are cross-sectional views showing the method for manufacturing the semiconductor device according to the second embodiment.

[0059] First, similarly to the first embodiment, processing is performed up to the formation of the openings 63 and 64 in the insulating film 41 (see FIG. 9). Next, as shown in FIG. 17, using the insulating film 41 with the openings 63 and 64 formed therein as a mask, a part of the recess 83 and a recess 92 are formed in the laminated structure 20 by photoelectrochemical (PEC) etching. In PEC etching, for example, a solution obtained by mixing an aqueous solution of potassium hydroxide (KOH) and an aqueous solution of potassium peroxodisulfate (K2S2O8) is used as an etching solution. This solution contains hydroxide ions (OH - ) and peroxodisulfate ion (SO8 2- ) The laminated structure 20 is irradiated with light having energy greater than the band gap of the barrier layers 121 to 124, such as ultraviolet light. For example, when the band gap of the barrier layers 121 to 124 is 3.97 eV, extreme ultraviolet light having a wavelength of 310 nm is irradiated. The energy E of extreme ultraviolet light having a wavelength of 310 nm is UV is 4.01 eV.

[0060] Here, the progress of PEC etching in the second embodiment will be described. Figs. 20 to 22 are diagrams showing the band structures of the channel layers 111 to 114 and the barrier layers 121 to 124 in the second embodiment. Figs. 20 to 22 show the band structures along the dashed line A in Fig. 17. Fdenotes the Fermi level.

[0061] Immediately after the start of PEC etching, as shown in FIG. 20 , 2DEG 174 is present in channel layer 114 on the substrate 10 side of gate opening 63. When ultraviolet light 65 is incident on barrier layer 124, the barrier layer 124 absorbs the ultraviolet light 65 because the band gap of barrier layer 124 is smaller than the energy of the ultraviolet light 65. Electron-hole pairs are generated in barrier layer 124, and the barrier layer 124 is decomposed. At this time, the holes are consumed on the surface of barrier layer 124. Electrons flow into 2DEG 174, then reach source electrode 31 or drain electrode 32, and are consumed on the surface of source electrode 31 or drain electrode 32.

[0062] Thereafter, as the PEC etching progresses, the recess 92 deepens. As the recess 92 deepens, the portion of the barrier layer 124 closer to the substrate 10 than the bottom of the recess 92 becomes thinner, and the 2DEG 174 in the channel layer 114 on the substrate 10 side of the bottom of the recess 92 decreases. When the thickness of this portion reaches a certain thickness, the 2DEG 174 in the channel layer 114 on the substrate 10 side of the bottom of the recess 92 is depleted.

[0063] The ultraviolet light 65 also enters the barrier layer 123. When the ultraviolet light 65 enters the barrier layer 123, the barrier layer 123 absorbs the ultraviolet light 65 because the band gap of the barrier layer 123 is smaller than the energy of the ultraviolet light 65, generating electron-hole pairs in the barrier layer 123. Therefore, even if the 2DEG 174 in the channel layer 114 is depleted, the 2DEG 173 exists in the channel layer 113. Therefore, as shown in FIG. 21 , electrons flow into the 2DEG 173 in the channel layer 113, and the decomposition of the barrier layer 124 continues. Furthermore, when the recess 92 reaches the channel layer 114, the channel layer 114 is also decomposed by a similar mechanism. In this way, electron-hole pairs are generated and the recess 92 is successively formed in the barrier layer 123, the channel layer 113, the barrier layer 122, the channel layer 112, and the barrier layer 121 by contact with the etching solution.

[0064] Thereafter, when the thickness of the portion of the barrier layer 121 closer to the substrate 10 than the bottom surface of the recess 92 reaches a certain thickness, the 2DEG 171 in the channel layer 111 is depleted on the substrate 10 side of the bottom surface of the recess 92. When the 2DEG 171 in the channel layer 111 is depleted, as shown in FIG. 22 , even if electron-hole pairs are generated in the barrier layer 121, the electrons cannot move, and the PEC etching stops.

[0065] In this manner, the recess 92 can be formed by PEC etching. As the recess 92 is formed, the 2DEG 171 disappears from the channel layer 111 on the substrate 10 side of the bottom surface of the recess 92.

[0066] After forming a portion of the recess 83 and the recess 92, the remainder of the recess 83 is formed as shown in FIG. 18. To form the remainder of the recess 83, RIE is performed using, for example, an electron beam resist (not shown) as a mask. A reactive gas containing Cl is used to etch the channel layer 111 and the barrier layer 121. After forming the remainder of the recess 83, the mask is removed.

[0067] 19, the gate electrode 33 is formed in the opening 63 and the recess 83. Next, the insulating film 42 that covers the gate electrode 33 is formed on the insulating film 41. The insulating film 42 may cover the source electrode 31 and the drain electrode 32.

[0068] Thereafter, wiring and the like are formed as necessary. In this manner, the semiconductor device 200 according to the second embodiment can be manufactured.

[0069] The second embodiment also provides the same effects as the first embodiment. Moreover, in the second embodiment, the recesses 92 can be formed by PEC etching, which can reduce etching damage to the channel layer 111 and the barrier layer 121 compared to when the recesses 91 are formed by RIE.

[0070] (Third embodiment) Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in the configuration of the stacked structure 20. Fig. 23 is a perspective view showing a semiconductor device according to the third embodiment. Fig. 24 is a cross-sectional view showing the semiconductor device according to the third embodiment. Note that the insulating film is omitted in Fig. 23.

[0071] 23 and 24 , in the semiconductor device 300 according to the third embodiment, the stacked structure 20 includes, instead of the channel layers 111 to 114 and the barrier layers 121 to 124, a channel layer 311, a barrier layer 321, a channel layer 312, a barrier layer 322, a channel layer 313, a barrier layer 323, a channel layer 314, and a barrier layer 324, which are formed in this order from the substrate 10 side. The stacked structure 20 may have a buffer layer provided between the substrate 10 and the channel layer 311, and may have a cap layer provided on the barrier layer 324.

[0072] The channel layer 311 is, for example, an undoped GaN layer having a thickness of 5 nm to 500 nm. The channel layers 312 to 314 are, for example, undoped GaN layers having a thickness of 5 nm to 30 nm. The barrier layer 321 is, for example, an n-type AlN layer having a thickness of 5 nm to 30 nm. x3 Ga 1-x3 The barrier layer 322 is an n-type Al layer having a thickness of, for example, 5 nm or more and 30 nm or less. x1 Ga 1-x1 The barrier layers 323 and 324 are n-type AlN layers having a thickness of, for example, 5 nm or more and 30 nm or less. x2 Ga 1-x2 The channel layer 311 may be partially formed as a buffer layer. x1 Ga 1-x1 The N layer is an example of a first nitride semiconductor layer, and is an n-type Al x2 Ga 1-x2 The N layer is an example of a second nitride semiconductor layer.

[0073] The barrier layer 322 has a first band gap Eg1, and the barrier layers 322 and 324 have a second band gap Eg2. The value of x2 is smaller than the value of x1. The second band gap Eg2 is smaller than the first band gap by Eg1. For example, the value of x1 is 0.32, and the value of x2 is 0.28. In this case, the first band gap Eg1 is 4.05 eV, and the second band gap Eg2 is 3.97 eV. The n-type impurities contained in the barrier layers 321 to 324 are, for example, Si or Ge. The barrier layer 321 has a third band gap Eg3. The magnitude relationship of the third band gap Eg3 to the first band gap Eg1 and the second band gap Eg2 is not limited. The value of x3 may be equal to or different from the value of x1 or x2. The first band gap Eg1, the second band gap Eg2, and the third band gap Eg3 are larger than the band gaps of the channel layers 311 to 314. The channel layer 312 is an example of a first channel layer, and the barrier layer 322 is an example of a first barrier layer. The channel layers 313 and 314 are examples of a second channel layer, and the barrier layers 323 and 324 are examples of a 21st barrier layer. The channel layer 311 is an example of a third channel layer, and the barrier layer 321 is an example of a third barrier layer.

[0074] In the semiconductor device 300, as shown in FIGS. 23 and 24, recesses 93 are formed in the stacked structure 20 instead of the recesses 91. The recesses 93 penetrate the barrier layer 324 and reach the barrier layer 323. The bottom surfaces of the recesses 93 are located closer to the substrate 10 than the upper surface of the barrier layer 323. The bottom surfaces of the recesses 93 are located deeper toward the substrate 10 than the upper surface of the barrier layer 323. Furthermore, the bottom surfaces of the recesses 93 are located above (away from the substrate 10) the interface between the channel layer 313 and the barrier layer 323. The recesses 93 may be connected to adjacent recesses 83. The recesses 93 are an example of a fourth recess.

[0075] 23 and 24 , in semiconductor device 300, 2DEG 371 exists near the upper surface of channel layer 311, 2DEG 372 exists near the upper surface of channel layer 312, 2DEG 373 exists near the upper surface of channel layer 313, and 2DEG 374 exists near the upper surface of channel layer 314. However, on the substrate 10 side of the bottom surface of recess 93, 2DEG 373 does not exist in channel layer 313 when no voltage is applied to gate electrode 33.

[0076] The other configurations are the same as those in the first embodiment.

[0077] Next, a method for manufacturing the semiconductor device 300 according to the twenty-third embodiment will be described. Figures 25 to 27 are cross-sectional views showing the method for manufacturing the semiconductor device according to the third embodiment.

[0078] First, similarly to the first embodiment, processing is performed up to the formation of the openings 63 and 64 in the insulating film 41 (see FIG. 9). Next, as shown in FIG. 25, using the insulating film 41 with the openings 63 and 64 formed therein as a mask, a part of the recess 83 and a recess 93 are formed in the laminated structure 20 by PEC etching. In PEC etching, for example, a solution obtained by mixing an aqueous solution of potassium hydroxide (KOH) and an aqueous solution of potassium peroxodisulfate (K2S2O8) is used as an etching solution. This solution contains hydroxide ions (OH - ) and peroxodisulfate ion (SO8 2- ) and the like. The stacked structure 20 is irradiated with light, for example, ultraviolet light, having energy smaller than the first band gap Eg1 of the barrier layer 322 and larger than the second band gap Eg2 of the barrier layers 323 and 324. For example, when the first band gap Eg1 is 4.05 eV and the second band gap Eg2 is 3.97 eV, extreme ultraviolet light with a wavelength of 310 nm is irradiated. As described above, the energy E of the extreme ultraviolet light with a wavelength of 310 nm is UV is 4.01 eV.

[0079] Here, the progress of PEC etching in the third embodiment will be described. Figs. 28 to 30 are diagrams showing the band structures of the channel layers 311 to 314 and the barrier layers 321 to 324 in the third embodiment. Figs. 28 to 30 show the band structures along the dashed line A in Fig. 25. E in Figs. 28 to 30 F denotes the Fermi level.

[0080] Immediately after the start of PEC etching, as shown in FIG. 28, the 2DEG 174 is present in the channel layer 314 on the substrate 10 side of the gate opening 63. When ultraviolet light 65 is incident on the barrier layer 324, the second band gap Eg2 is increased by the energy E of the ultraviolet light 65. UV Since the absorption of the ultraviolet light 65 is smaller than the absorption of the ultraviolet light 65, the barrier layer 324 absorbs the ultraviolet light 65, generating electron-hole pairs in the barrier layer 324 and decomposing the barrier layer 324. At this time, the holes are consumed on the surface of the barrier layer 324. Furthermore, the electrons flow into the 2DEG 374, then reach the source electrode 31 or the drain electrode 32, and are consumed on the surface of the source electrode 31 or the drain electrode 32.

[0081] Thereafter, as the PEC etching progresses, the recess 93 deepens. As the recess 93 deepens, the portion of the barrier layer 324 closer to the substrate 10 than the bottom of the recess 93 becomes thinner, and the 2DEG 374 in the channel layer 314 on the substrate 10 side of the bottom of the recess 93 decreases. When the thickness of this portion reaches a certain thickness, the 2DEG 374 in the channel layer 314 on the substrate 10 side of the bottom of the recess 93 is depleted.

[0082] The ultraviolet light 65 also enters the barrier layer 323. When the ultraviolet light 65 enters the barrier layer 323, the barrier layer 323 absorbs the ultraviolet light 65 because the band gap of the barrier layer 323 is smaller than the energy of the ultraviolet light 65, generating electron-hole pairs in the barrier layer 323. Therefore, even if the 2DEG 374 in the channel layer 314 is depleted, the 2DEG 373 exists in the channel layer 313. Therefore, as shown in FIG. 29, electrons flow into the 2DEG 373 in the channel layer 313, and the decomposition of the barrier layer 324 continues. Furthermore, when the recess 93 reaches the channel layer 314, the channel layer 314 is also decomposed by a similar mechanism. In this way, the generation of electron-hole pairs and the contact with the etching solution form recesses 92 in the barrier layer 323.

[0083] In the third embodiment, the first band gap Eg1 of the barrier layer 322 is set to the energy E UV 30, even if electron-hole pairs are generated in the barrier layer 323, the electrons cannot move to the 2DEG 372. Therefore, when the 2DEG 373 in the channel layer 313 is depleted, the PEC etching stops. Therefore, when the recess 93 is formed by PEC etching, the channel layers 311-313 and the barrier layers 321-322 are not etched.

[0084] In this manner, the recess 93 can be formed by PEC etching. As the recess 93 is formed, the 2DEG 373 disappears from the channel layer 313 on the substrate 10 side of the bottom surface of the recess 93.

[0085] After forming a portion of the recess 83 and the recess 93, the remainder of the recess 83 is formed as shown in FIG. 26. To form the remainder of the recess 83, RIE is performed using, for example, an electron beam resist (not shown) as a mask. A reactive gas containing Cl is used to etch the channel layers 311-313 and the barrier layers 321-323. After forming the remainder of the recess 83, the mask is removed.

[0086] 27, the gate electrode 33 is formed in the opening 63 and the recess 83. Next, the insulating film 42 that covers the gate electrode 33 is formed on the insulating film 41. The insulating film 42 may cover the source electrode 31 and the drain electrode 32.

[0087] Thereafter, wiring and the like are formed as necessary. In this manner, the semiconductor device 300 according to the third embodiment can be manufactured.

[0088] Here, the effects of the third embodiment will be described. Fig. 31 is a diagram showing the temperature distribution in the channel region during operation in the third embodiment. The upper side of Fig. 31 shows a top view, and the lower side shows the temperature distribution along the two-dot chain line B in the top view. The thickness of the arrow indicating the current I in Fig. 31 reflects the magnitude of the current I.

[0089] In the third embodiment, 2DEGs 371 and 372 are present on the substrate 10 side of recess 93. Therefore, as shown in Fig. 31, a larger current can flow through the semiconductor device as a whole than in the first embodiment while suppressing the accumulation of heat generated in the channel region located in the center. Therefore, according to the third embodiment, it is easy to achieve both high output and suppression of heat generation.

[0090] The provision of the pair of the channel layer 313 and the barrier layer 323 and the pair of the channel layer 314 and the barrier layer 324 allows a larger current to flow than when only one of these pairs is provided. Also, the provision of the pair of the channel layer 311 and the barrier layer 321 allows a larger current to flow than when this pair is not provided.

[0091] Note that the material of the barrier layers 321 to 324 is not limited to AlGaN, as long as the first band gap Eg1 of the barrier layer 322 is larger than the second band gap Eg2 of the barrier layers 323 and 324. For example, the material of the barrier layer 322 may be AlN, InAlN, or InAlGaN. Furthermore, the barrier layers 321 to 324 may be undoped layers.

[0092] The number of pairs of second channel layers and second barrier layers is not particularly limited. The amount of current can be adjusted depending on the number of pairs of second channel layers and second barrier layers. Similarly, the number of pairs of third channel layers and third barrier layers is not particularly limited. The amount of current can be adjusted depending on the number of pairs of third channel layers and third barrier layers.

[0093] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0094] 10: Circuit board 20: Laminated structure 21: Source area 22: Drain region 31: Source electrode 32: Drain electrode 33: Gate electrode 35: Depletion layer 41, 42: insulating film 61, 62, 63, 64: Opening 65: Ultraviolet light 81, 82, 83, 91, 92, 93: recesses 100, 200, 300, 900: Semiconductor device 111, 112, 113, 114, 311, 312, 313, 314: Channel layer 121, 122, 123, 124, 321, 322, 323, 324: Barrier layer 171, 172, 173, 174:2DEG

Claims

1. A substrate; a semiconductor layer provided on the substrate; a source electrode and a drain electrode in ohmic contact with the semiconductor layer; and The semiconductor layer is a first channel layer; a first barrier layer provided on the first channel layer; a second channel layer provided on the first barrier layer; a second barrier layer provided on the second channel layer; and The semiconductor layer a first recess located on the substrate side of the source electrode; a second recess located on the substrate side of the drain electrode; a plurality of third recesses positioned between the first recesses and the second recesses and arranged in a direction intersecting the arrangement direction of the first recesses and the second recesses; is formed, the first recess, the second recess, and the third recess reach the first channel layer; The semiconductor layer is a source region formed in the first recess and having an electrical resistance lower than that of the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer; a drain region formed in the second recess and having an electrical resistance lower than that of the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer; and the source electrode contacts the source region; the drain electrode contacts the drain region; a plurality of gate electrodes embedded in each of the third recesses; Adjacent third recesses constitute a recess pair, A semiconductor device in which, in some of the plurality of recess pairs, a fourth recess that penetrates at least the second barrier layer is formed between the two third recesses that constitute the recess pair in the semiconductor layer.

2. The semiconductor device according to claim 1 , wherein the fourth recess is formed in every other pair of recesses.

3. The semiconductor device according to claim 1 , wherein the fourth recess reaches the first channel layer.

4. 3. The semiconductor device according to claim 1, wherein the bottom surface of the fourth recess is located within the first barrier layer.

5. the first barrier layer has a first bandgap; the second barrier layer has a second bandgap smaller than the first bandgap; 3. The semiconductor device according to claim 1, wherein the bottom surface of the fourth recess is located within the second barrier layer.

6. the first barrier layer is a first nitride semiconductor layer containing Al at a first concentration; 6. The semiconductor device according to claim 5, wherein the second barrier layer is a second nitride semiconductor layer containing Al at a second concentration lower than the first concentration.

7. 7. The semiconductor device according to claim 5, further comprising a plurality of pairs of the second channel layer and the second barrier layer.

8. The semiconductor layer is a third channel layer; and a third barrier layer provided on the third channel layer; and the first channel layer is provided on the third barrier layer; 8. The semiconductor device according to claim 5, wherein the first recess, the second recess, and the third recess reach the third channel layer.

9. forming a semiconductor layer on a substrate; forming a source electrode and a drain electrode in ohmic contact with the semiconductor layer; and The step of forming the semiconductor layer includes: forming a first channel layer; forming a first barrier layer on the first channel layer; forming a second channel layer on the first barrier layer; forming a second barrier layer on the second channel layer; forming a first recess located on the substrate side of the source electrode; forming a second recess located on the substrate side of the drain electrode; forming a source region in the first recess, the source region having a lower electrical resistance than the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer; forming a drain region in the second recess, the drain region having an electrical resistance lower than that of the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer; forming a plurality of third recesses positioned between the first recesses and the second recesses and arranged in a direction intersecting the arrangement direction of the first recesses and the second recesses; adjacent third recesses form a recess pair, and in some of the recess pairs, a fourth recess is formed between two of the third recesses that form the recess pair in the semiconductor layer, the fourth recess penetrating at least the second barrier layer; and a step of embedding a plurality of gate electrodes in each of the third recesses; the first recess, the second recess, and the third recess reach the first channel layer; the source electrode contacts the source region; The method for manufacturing a semiconductor device, wherein the drain electrode is in contact with the drain region.

10. the first barrier layer has a first bandgap; the second barrier layer has a second bandgap smaller than the first bandgap; 10. The method for manufacturing a semiconductor device according to claim 9, wherein the step of forming the fourth recess includes a step of photoelectrochemically etching the semiconductor layer while irradiating the semiconductor layer with light having energy smaller than the first band gap and larger than the second band gap.

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