Delta-Sigma Modulator

Abstract

To provide a delta-sigma modulator that has a small circuit area and can reduce errors.SOLUTION: A delta-sigma modulator 10 includes: a first integration unit that integrates an input analog signal; a second integration unit that integrates a signal output by the first integration unit; a selection unit that selects at least one of the signal output by the first integration unit and a signal output by the second integration unit, and outputs a signal corresponding to the selected signal; a quantizer that quantizes the signal output by the selection unit; a DA converter that DA-converts an output of the quantizer and outputs a feedback signal to be fed back to the first integration unit; and a control circuit that controls the first integration unit and the second integration unit to perform different integration operations in a first period and a second period. The control circuit controls the selection unit to change signal selection between the final output of the quantizer in the first period and before the start of the second period.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a delta-sigma modulator. [Background technology]

[0002] Conventionally, as a method for achieving high resolution with low power consumption, an incremental delta-sigma modulator is known, which operates as an integrator with a first-order feedback coefficient of 1 until a predetermined period has elapsed, and then operates as an amplifier with a first-order feedback coefficient greater than 1 after the predetermined period has elapsed (see, for example, Patent Document 1). [Prior art document] [Patent documents] Patent Document 1: JP 2019-118100 A Summary of the Invention

[0003] A first aspect of the present invention provides a delta-sigma modulator. The delta-sigma modulator may include a first integrator unit that integrates an input analog signal. The delta-sigma modulator may include a second integrator unit that integrates a signal output by the first integrator unit. The delta-sigma modulator may include a selector unit 140 that selects at least one of the signal output by the first integrator unit and the signal output by the second integrator unit and outputs a signal corresponding to the selected signal. The delta-sigma modulator may include a quantizer that quantizes the signal output by the selector unit 140. The delta-sigma modulator may include a DA converter that performs DA conversion on the output of the quantizer and outputs a feedback signal that is fed back to the first integrator unit. The delta-sigma modulator may include a controller that controls the first integrator unit and the second integrator unit to perform different integral operations in a first period and a second period. The control unit may control the selection unit 140 to change the signal selection during the period from the final output of the quantizer in the first period to before the start of the second period.

[0004] The control section may control the selection section 140 to change the signal selection at least one clock before the second period.

[0005] The control unit may control the selection unit 140 to select at least one of the signal output by the first integration unit and the signal output by the second integration unit, add the selected signal to the analog signal, and output the signal.

[0006] The control unit may control the selection unit 140 to select the signal output by the first integrator unit and the signal output by the second integrator unit during the first period, add the selected signal to the analog signal, and output the result. The control unit may control the selection unit 140 to select only the signal output by the second integrator unit during the period from the final output of the quantizer during the first period to the start of the second period, add the selected signal to the analog signal, and output the result.

[0007] The control unit may control the first integrating unit to operate as an integrator with a feedback coefficient of 1 in the first period, and to operate as an integrator with a feedback coefficient of 0 in the second period. The control unit may control the second integrating unit to operate as an integrator with a feedback coefficient of 1 in the first period, and to operate as an integrator with a feedback coefficient greater than 1 in the second period.

[0008] The delta-sigma modulator may be an incremental AD converter that is reset after each AD conversion cycle that converts an input analog signal into a digital signal.

[0009] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0010] [Figure 1] 1 shows an example of the configuration of a delta-sigma modulator according to the present embodiment. [Figure 2] 2 shows a more detailed configuration example of the delta-sigma modulator according to the present embodiment. [Figure 3] 3 shows a more detailed configuration example of a selection unit of the delta-sigma modulator according to the present embodiment. [Figure 4] 10 shows a comparative example of a timing chart of a delta-sigma modulator. [Figure 5] 10 shows a comparative example of a timing chart of a delta-sigma modulator. [Figure 6] 1 shows an example of a timing chart for a delta-sigma modulator. [Figure 7] 1 shows an example of a timing chart for a delta-sigma modulator. DETAILED DESCRIPTION OF THE INVENTION

[0011] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0012] 1 shows an example of the configuration of a delta-sigma modulator 10 according to this embodiment. The delta-sigma modulator 10 receives an input analog signal A sig to the digital signal D SIG The delta-sigma modulator 10 is an incremental AD converter that resets after each AD conversion cycle. The delta-sigma modulator 10 may repeat one AD conversion cycle consisting of a first period and a second period and a reset period after the AD conversion.

[0013] The delta-sigma modulator 10 includes an adder / subtractor unit 110, a first integrator unit 120, a second integrator unit 130, a selector unit 140, a quantizer 150, a digital filter 155, a DA converter 170, a control circuit 180, and a reset circuit 190. Note that the control unit of the present application may include the control circuit 180 and the reset circuit 190 of this embodiment.

[0014] The adder-subtractor 110 is connected to the input terminal 100, the first integrator 120, and the DA converter 170. The adder-subtractor 110 converts the analog signal A sig The feedback signal A output from the DA converter 170 FBAnalog signal A subtracted from IN1 is output to the first integrator 120.

[0015] The first integrator 120 is connected to the second integrator 130 and the selector 140, and receives the analog signal A sig The first integrator 120 may be an analog integrator. The first integrator 120 integrates the analog signal A sig and feedback signal A FB Analog signal A, which is the difference between IN1 is integrated and the analog signal A OUT1 to the second integrator 130 and the selector 140.

[0016] The second integrator 130 is connected to the selector 140 and selects the analog signal A output from the first integrator 120. OUT1 The second integrating section 130 may be an analog integrator. The second integrating section 130 integrates the feedback signal A output by the DA converter 170 during the first period and the second period. FB is received via the first integrator 120, integrated, and an analog signal A OUT2 to the selection unit 140.

[0017] The selector 140 is connected to the input terminal 100 and the quantizer 150, and selects the analog signal A sig , the analog signal A output by the first integrator 120 OUT1 , and the analog signal A output by the second integrator 130 OUT2 and generate an analog signal A according to the selected signal. SUM2 The selection section 140 may be configured to perform feedforward control of the delta-sigma modulator 10.

[0018] The quantizer 150 is connected to the digital filter 155 and the DA converter 170, and converts the analog signal A output from the selector 140 into SUM2 The quantized digital signal D outThe quantizer 150 outputs the analog signal A in response to an externally supplied clock signal. SUM2 The quantizer 150 functions as a 1-bit quantizer to quantize the binary digital signal D out Alternatively, the quantizer 150 may function as a multi-bit quantizer to quantize the multi-level digital signal D out may be quantized to

[0019] The digital filter 155 is connected to an output terminal 160 and receives the modulated digital signal D output by the quantizer 150. out is filtered to produce a digital signal D SIG In response to the control signal, the digital filter 155 outputs the digital signal D out In the first period, the digital filter 155 may operate as an integral filter that digitally integrates the bit stream of the digital signal, and in the second period, the digital filter 155 may operate as an integral filter having a feedback coefficient greater than 1. The digital filter 155 may calculate a digital value in synchronization with a clock signal. Furthermore, the digital filter 155 may reset the amount of integration in response to receiving a reset signal from the reset circuit 190.

[0020] The digital filter 155 may also have a low-pass filter to reduce quantization noise generated in the quantizer 150. The digital filter 155 may also have a decimation filter to reduce the sampling frequency. The digital filter 155 outputs a digital signal D SIG is supplied to the output terminal 160.

[0021] The DA converter 170 converts the output D OUT is converted digitally to analogue form and fed back to the first integrator 120. FB The DA converter 170 outputs a digital signal D OUT is an analog feedback signal A FB may be converted to

[0022] The control circuit 180 is connected to the second integrator unit 130, the selector unit 140, and the digital filter 155, and outputs control signals that switch the operations of the second integrator unit 130, the selector unit 140, and the digital filter 155. The control circuit 180 may switch the operations of the second integrator unit 130, the selector unit 140, and the digital filter 155 at predetermined timing. The control circuit 180 may output different control signals to the second integrator unit 130 and the selector unit 140. The control circuit 180 may also notify the reset circuit 190 of the timing at which a reset signal should be supplied.

[0023] The reset circuit 190 is connected to the first integrator section 120, the second integrator section 130, and the digital filter 155, and outputs a reset signal that resets the outputs of the first integrator section 120, the second integrator section 130, and the digital filter 155 at predetermined intervals. The reset circuit 190 may reset the integral values ​​held by the first integrator section 120 and the second integrator section 130 at each conversion period of the incremental delta-sigma modulation. The reset circuit 190 may also reset the first integrator section 120 and the second integrator section 130 within each conversion period of the incremental delta-sigma modulation. The first integrator section 120 and the second integrator section 130 are controlled by a control signal from the control circuit 180 and a reset signal from the reset circuit 190 to perform different integral operations in the first period and the second period.

[0024] Fig. 2 shows a more detailed example of the configuration of the delta-sigma modulator 10 according to this embodiment. Fig. 2 shows in more detail the first integrator section 120 and the second integrator section 130 in the delta-sigma modulator 10 of Fig. 1. These will be described in more detail below.

[0025] The first integrator 120 has a first adder 200 and a first switch 201, and has a feedback path that returns the output of the first switch 201 to the input of the first adder 200. The first adder 200 is connected to the feedback path of the adder / subtractor 110 and the input of the first switch 201, and receives a feedback signal A via the adder / subtractor 110. FBThe first adding unit 200 receives the analog signal A from the adding / subtracting unit 110. IN1 and the analog signal A from the first switching unit 201. OUT1 and outputs the analog signal A to the first switching unit 201. SUM1 Output.

[0026] The first switching unit 201 selects the analog signal A output from the first adding unit 200. SUM1 is output with a gain of 1 in the first period, and alternately output with gains of 1 and 0 in the second period. The first switching unit 201 has a first delay element 205, a first amplifier 210, a first multiplexer 215, a second delay element 220, and a second multiplexer 225.

[0027] The first delay element 205 is connected between the first adder 200 and one input of the first multiplexer 215, and is used to multiplex the signal A SUM1 The first amplifier 210 is connected between the first adder 200 and the other input of the first multiplexer 215, and delays and outputs the signal A SUM1 with a gain of 0 (i.e., 0 V). The output of the first multiplexer 215 is connected to the second delay element 220 and one input of the second multiplexer 225, and the output of the first delay element 205 and the output of the first amplifier 210 are input thereto, and the first multiplexer 215 outputs one of the output of the first delay element 205 and the output of the first amplifier 210 in response to a reset signal. During the reset period, the first multiplexer 215 may output the signal that the first amplifier 210 outputs with a gain of 0 in response to the reset signal.

[0028] The second delay element 220 is connected between the output of the first multiplexer 215 and the other input of the second multiplexer 225, and delays and outputs the signal from the first multiplexer 215. The output of the second multiplexer 225 is connected to the second integrator 130 and the input of the first adder 200. The second multiplexer 225 receives the output of the second delay element 220 and the output of the first multiplexer 215, and outputs one of the output of the second delay element 220 and the output of the first multiplexer 215 in response to a reset signal.

[0029] The reset circuit 190 may control the first integrating section 120 to operate as an integrator with a feedback coefficient of 1 in the first period, and to operate as an integrator with a feedback coefficient that alternates between 0 and 1 in the second period. As a result, the first integrating section 120 operates as an integrator with a feedback coefficient that alternates between 0 and 1 in the first period. IN1 and signal A output in the previous clock cycle OUT1 Signal A obtained by adding OUT1 In the second period, 0V and the input signal A IN1 and are output alternately.

[0030] The second integrator unit 130 has a second switching unit 203, a second adder unit 240, a second amplifier 245, a fourth multiplexer 250, and a fourth delay element 255. The second integrator unit 130 has a feedback path that returns the output of the second adder unit 240 to the input of the second adder unit 240 via the second amplifier 245, the fourth multiplexer 250, and the fourth delay element 255.

[0031] The second switching unit 203 switches the signal A from the first integrating unit 120 during the first period. OUT1 is delayed and output, and in the second period, the signal A from the first integrator 120 is OUT1 The second switching unit 203 has a third delay element 230 and a third multiplexer 235. The third delay element 230 is connected between the first integrating unit 120 and one input of the third multiplexer 235, and outputs the signal A output by the first integrating unit 120 without delay. OUT1The third multiplexer 235 has the other input connected to the first integrator 120 and the output connected to the input of the second adder 240. The third multiplexer 235 outputs one of the output of the third delay element 230 and the output of the first integrator 120 in response to a control signal. The third multiplexer 235 outputs the signal A from the third delay element 230 during the first period, and outputs the signal A from the first integrator 120 during the second period. OUT1 may be output.

[0032] The second adder 240 adds the analog signal A IN2 and the analog signal from the feedback path are added to generate the resulting analog signal A OUT2 The second amplifier 245 is connected between the output of the second adder 240 and one input of the fourth multiplexer 250, and amplifies the analog signal A from the second adder 240 by a factor x (for example, x>1). OUT2 The fourth multiplexer 250 has the other input connected to the output of the second adder 240, and the output connected to a fourth delay element 255. The fourth multiplexer 250 outputs one of the output of the second adder 240 or the output of the second amplifier 245 in response to a control signal. The fourth delay element 255 is connected to the second adder 240, and delays the signal from the fourth multiplexer 250 and outputs the delayed signal to the second adder 240.

[0033] In the first period, the fourth multiplexer 250 receives the signal A from the second adding unit 240. OUT2 and in a second period, the amplified signal from the second amplifier 245 may be output.

[0034] The control circuit 180 may control the second integrating section 130 to operate as an integrator with a feedback coefficient of 1 in the first period, and to operate as an integrator with a feedback coefficient greater than 1 in the second period. As a result, the second integrating section 130 operates as an integrator with a feedback coefficient greater than 1 in the first period. IN2 and signal A output in the previous clock cycle OUT2 Signal A obtained by addingOUT2 In the second period, the input signal A IN2 and signal A output in the previous clock cycle OUT2 Signal A obtained by adding a signal multiplied by x OUT2 Output.

[0035] Here, the feedback coefficient indicates the magnification of the amplifier arranged in the feedback path of each of the first integrator section 120 and the second integrator section 130. For example, in the path from the output to the input of the adder section of the first integrator section 120 and the second integrator section 130, if a signal input to that path passes without passing through an amplifier, the feedback coefficient is 1, and if a signal input to that path passes through an amplifier with a magnification x, the feedback coefficient is x.

[0036] FIG. 3 shows a more detailed example configuration of the selection section 140 of the delta-sigma modulator 10 according to this embodiment.

[0037] The selection section 140 has three input terminals 300 , 310 , and 320 , a third amplifier 330 , a fourth amplifier 340 , a selection switch 360 , a fifth amplifier 350 , a third addition section 370 , and an output terminal 380 .

[0038] The input terminal 300 is connected to the input terminal 100 of the delta-sigma modulator 10, and receives the analog signal A sig The input terminal 310 is connected to the first integrating section 120, and receives the analog signal A OUT1 The input terminal 320 is connected to the second integrating section 130, and receives the analog signal A OUT2 The third amplifier 330 is connected between the input terminal 300 and the third adder 370, and receives the analog signal A sig The fourth amplifier 340 is connected between the input terminal 310 and the selection switch 360, and outputs the analog signal A OUT1The fifth amplifier 350 is connected between the input terminal 320 and the third adder 370, and amplifies the analog signal A by a factor of α1 and outputs the amplified signal. The selection switch 360 is disposed between the fourth amplifier 340 and the third adder 370, and is turned on / off in response to a control signal from the control circuit 180 to connect / disconnect the fourth amplifier 340 and the third adder 370. The fifth amplifier 350 is connected between the input terminal 320 and the third adder 370, and OUT2 is amplified by α2 and output.

[0039] The third adder 370 is connected to the output terminal 380 and receives the analog signal A from the input terminal 100. sig , the analog signal A from the first integrator 120 OUT1 , the analog signal A from the second integrator 130 OUT2 is input, and the analog signal A SUM2 When the selection switch 360 is turned on in response to the control signal, the selection unit 140 outputs the analog signal α0A sig , α1A OUT1 , and α2A OUT2 When the selection switch 360 is turned off in response to the control signal, the analog signal α0A sig and α2A OUT2 may be added and output.

[0040] Note that the magnifications α0, α1, and α2 may be any values. Furthermore, a selection switch 360 may be additionally disposed between the fifth amplifier 350 and the third adder 370. In this case, the selection section 140 may alternately turn on / off the connections between the input terminal 310 and the third adder 370 in response to the control signal by turning off the additional selection switch 360 when the selection switch 360 is on, and by turning off the selection switch 360 when the additional selection switch 360 is on.

[0041] FIG. 4 shows a comparative example of a timing chart of the delta-sigma modulator 10. In FIG. 4, the incremental period indicates the first period, and the exponential period indicates the second period. The horizontal axis in FIG. 4 indicates time. In FIG. 4, RST indicates a reset signal, CLK indicates a clock signal input to each component of the delta-sigma modulator 10, and the "first integrator," "second integrator," and "selector" indicate the operating states of the first integrator 120, the second integrator 130, and the selector 140 during the incremental and exponential periods.

[0042] 4, after the reset circuit 190 causes the RST signal to fall to low, the control circuit 180 inputs control signals to the first integrator unit 120, the second integrator unit 130, and the selector unit 140 to switch to the incremental operation state. After the rising edge of the clock signal j+3 (j>1) at the end of the incremental period, the control circuit 180 and the reset circuit 190 simultaneously input signals to the first integrator unit 120, the second integrator unit 130, and the selector unit 140 to switch to the exponential operation state. As a result, the first integrator unit 120, the second integrator unit 130, and the selector unit 140 simultaneously switch from the incremental operation state to the exponential operation state.

[0043] 5 shows a comparative example of a timing chart of the delta-sigma modulator 10. FIG. 5 shows the correspondence between the outputs of the first integrator 120, the second integrator 130, and the selector 140 and the clock signal in the timing chart of FIG. 4. In the j-th cycle from the end of the reset period of the clock signal, the digital signal D output by the quantizer 150 is out is represented as D(j), and the analog signal A output from the first integrator 120 is obtained by feeding back the D(j). OUT1 I1(j), and the analog signal A output by the second integrator 130 is calculated using I1(j). OUT2 Let I2(j) be denoted as I2(j).

[0044] After the reset period ends and the RST signal falls to low, the delta-sigma modulator 10 starts an AD conversion cycle from the incremental period. SUM2 The first integrator 120 receives the output D(1) of the quantizer 150 at the next CLK 2 as an input and supplies the first output D(1). The first integrator 120 receives the output D(1) of the quantizer 150 at the next CLK 2 as a feedback and supplies the output I1(1). At the same time at this CLK 2, the quantizer 150 supplies the next output D(2). The second integrator 130 receives the output I1(1) of the first integrator 120 at the next CLK 3 and supplies the output I2(1). At this CLK 3, the quantizer 150 and the first integrator 120 both supply the next outputs D(3) and I1(2).

[0045] By repeating this operation, after quantizer 150 supplies output D(j) at the jth CLK, second integrator unit 130 supplies output I2(j) at the j+2th CLK, two clocks later, and the incremental operation state ends. From the next j+3th CLK, the exponential period begins. Before the rising edge of clock signal j+3, selector unit 140 receives signals in the incremental operation state from first integrator unit 120 and second integrator unit 130, and therefore output D(j+3) at clock signal j+3 becomes an output in the incremental operation state.

[0046] Specifically, when the output D(j+3) is supplied, the output A of the selection unit 140 is SUM2 is the formula (A SUM2 =α0A sig +α1A OUT1 +α2A OUT2 ) However, this output A SUM2 is not the output of the quantizer 150 in exponential terms.

[0047] On the other hand, in order for the quantizer 150 to provide the first output of the exponential period, the selector 140 must be in the exponential operating state.SUM2 is the formula (A SUM2 =α0A sig +α2A OUT2 ) Therefore, after the selection unit 140 is operated in the exponential operating state at the j+4th CLK, the quantizer 150 performs quantization and supplies the output D(j+4). During the exponential period, the second integration unit 130 takes in the output D(j+4) and supplies the output I2(j+4). As a result, in the comparative example, the output of the delta-sigma modulator 10 is delayed by at least one clock for the amount of output D(j+3) when switching to the exponential period.

[0048] FIG. 6 shows an example of a timing chart of the delta-sigma modulator 10. In FIG. 6, the incremental period indicates a first period, and the exponential period indicates a second period. The horizontal axis in FIG. 6 indicates time. In FIG. 6, RST indicates a reset signal, CLK indicates a clock signal input to each component of the delta-sigma modulator 10, and the "first integrator," "second integrator," and "selector" indicate the operating states of the first integrator 120, the second integrator 130, and the selector 140 during the incremental and exponential periods.

[0049] In the timing chart of this embodiment, the control circuit 180 controls the selection unit 140 to change the signal selection during the period from the final output of the quantizer 150 in the first period (incremental period) to before the start of the second period (exponential period). In Fig. 6, a pre-period is provided one clock before the rising edge of the clock signal j+3 at the start of the exponential period after the incremental period, and the selection unit 140 is controlled to switch to the exponential operating state during the pre-period.

[0050] 6, after the RST signal falls to low, the control circuit 180 and reset circuit 190 input signals to the first integrator 120, the second integrator 130, and the selector 140 to switch them to an incremental operating state. At the rising edge of the clock signal j+2, the control circuit 180 inputs a signal to the selector 140 to switch them to an exponential operating state (i.e., to turn off the selection switch 360 of the selector 140). Therefore, during the pre period, only the selector 140 is in the exponential operating state, and the first integrator 120 and the second integrator 130 are in the incremental operating state.

[0051] At the rising edge of clock signal j+3, control circuit 180 and reset circuit 190 input signals for switching to the exponential operating state to first integrator 120 and second integrator 130. As a result, first integrator 120 and second integrator 130 simultaneously switch from the incremental operating state to the exponential operating state at the rising edge of clock signal j+3.

[0052] 7 shows an example of a timing chart of the delta-sigma modulator 10. FIG. 7 shows the correspondence between the outputs of the first integrator 120, the second integrator 130, and the selector 140 and the clock signal in the timing chart of FIG. 6. In the j-th cycle from the end of the reset period of the clock signal, the digital signal D output by the quantizer 150 is out is denoted as D(j), and the analog signal A output from the first integrator 120 is calculated by using the D(j) as feedback. OUT1 I1(j), and the analog signal A output by the second integrator 130 is calculated using I1(j). OUT2 is denoted as I2(j). The operation of the delta-sigma modulator 10 during the incremental period is the same as that shown in FIG.

[0053] The selection unit 140 enters the period pre at the j+2th clock, the selection switch 360 turns off, and receives the output I2(j) of the second integrator 130. Therefore, the selection unit 140 receives the output I2(j) of the second integrator 130 in the period pre by the formula (A SUM2 =α0A sig +α2A OUT2 Since the control signal for the incremental operation state is input to the second integrator 130, the second integrator 130 operates in the incremental operation state to obtain I2(j), but since the control signal for the exponential operation state is input to the selector 140, the selector 140 outputs A to the quantizer 150 in the exponential operation state. SUM2 Therefore, quantizer 150 can obtain an output equivalent to D(j+4) in FIG. 5 at the j+3 rising edge of the clock (i.e., at the start of the exponential period), thereby eliminating the delay at the start of the exponential period.

[0054] In this embodiment, the delay is eliminated by changing the control of the selector 140 one clock before the start of the second period. However, depending on the order of the incremental delta-sigma modulator, this is not limited to one clock before the start of the second period. Taking FIG. 7 as an example, the control of the selector 140 may be switched at any timing between the time when the final output D(j) of the quantizer 150 is supplied for the first period and the time when the second period starts (i.e., the two-clock period a in FIG. 7) begins. During the period from the time when the quantizer 150 supplies the output D(j) to the start of the second period, the quantizer 150 operates to feed back the output D(j) to the second integrator 130. Therefore, the outputs D(j+1) and D(j+2) of the quantizer 150 obtained during this period are unnecessary. For example, in the case of an nth-order delta-sigma modulator (n>1), the control of the selection unit 140 may be switched n clocks before. Specifically, in the case of a second-order delta-sigma modulator, the control of the selection unit 140 may be switched two clocks before the start of the second period, and in the case of a third-order delta-sigma modulator, the control of the selection unit 140 may be switched between three clocks before the start of the second period and before the start of the second period.

[0055] Furthermore, the delta-sigma modulator 10 may not include the reset circuit 190, in which case the AD converter may not be an incremental type because it does not perform a reset operation.

[0056] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0057] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0058] 10 Delta-Sigma Modulator 100 Input terminal 110 Addition and subtraction section 120 First integral part 130 Second integral part 140 Selection Section 150 Quantizer 155 Digital Filter 160 output terminal 170 DA converter 180 Control circuit 190 Reset Circuit 200 First Addition Unit 201 First switching section 205 first delay element 210 First Amplifier 215 First Multiplexer 220 second delay element 225 Second Multiplexer 203 Second switching section 240 Second Addition Unit 245 Second Amplifier 250 Fourth Multiplexer 255 4th delay element 300 input terminal 310 Input terminal 320 input terminal 330 Third Amplifier 340 Fourth Amplifier 350 Fifth Amplifier 360 selection switch 370 Third Addition Section 380 output terminal

Claims

1. a first integrating unit that integrates an input analog signal; a second integrator that integrates the signal output by the first integrator; a selection unit that selects either only the signal output by the second integration unit or both the signal output by the first integration unit and the signal output by the second integration unit, and outputs a signal corresponding to the selected signal; a quantizer that quantizes the signal output by the selection unit; a DA converter that performs DA conversion on the output of the quantizer and outputs a feedback signal that is fed back to the first integrating unit; a control unit that controls the first integrating unit and the second integrating unit so that they perform different integral operations in a first period and a second period; The control unit controls the selection unit to change the selection of the signal during a period from the final output of the quantizer in the first period to before the second period starts. Delta-sigma modulator.

2. The control unit controls the selection unit to change the selection of the signal at least one clock before the second period.

2. The delta-sigma modulator of claim 1.

3. The control unit controls the selection unit to select either only the signal output by the second integration unit or both the signal output by the first integration unit and the signal output by the second integration unit, and to add the selected signal to the analog signal and output the result.

3. The delta-sigma modulator according to claim 1.

4. The control unit during the first period, controlling the selection unit to select the signal output by the first integration unit and the signal output by the second integration unit, add the selected signal to the analog signal, and output the result; During the period from the final output of the quantizer in the first period to the start of the second period, the selector is controlled to select only the signal output by the second integrator, add the selected signal to the analog signal, and output the result.

4. The delta-sigma modulator of claim 3.

5. The control unit controlling the first integrating unit to operate as an integrator with a feedback coefficient of 1 during the first period and to operate as an integrator with a feedback coefficient of 0 during the second period; The second integrating unit is controlled so as to operate as an integrator with a feedback coefficient of 1 during the first period and to operate as an integrator with a feedback coefficient greater than 1 during the second period.

5. A delta-sigma modulator according to claim 1.

6. The delta-sigma modulator is an incremental AD converter that is reset after each AD conversion cycle that converts the input analog signal into a digital signal.

6. A delta-sigma modulator according to claim 1.

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