Semiconductor device and manufacturing method thereof

Abstract

To improve reliability of a semiconductor device.SOLUTION: A semiconductor device comprises: an insulation layer IFL which is formed in a semiconductor substrate SUB; a conductive film PL which is formed on the insulation layer IFL; an interlayer insulating film IL which covers the conductive film PL; a contact hole CH1 which is formed on the interlayer insulating film IL, the conductive film PL and the insulation layer IFL; and a plug PG1 which is embedded in the contact hole CH1. A side surface of the interlayer insulating film IL is apart from a side surface of the conductive film PL such that a portion of an upper surface of the conductive film PL is exposed. A side surface of the insulation layer IFL is apart from a side surface of the conductive film PL such that a portion of a lower surface of the conductive film PL is exposed. A distance (L1) from the lower surface of the conductive film PL to a bottom of the contact hole CH1 is longer than a distance (L2) from the side surface of the conductive film PL to the side surface of the interlayer insulating film IL.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a contact hole formed in an interlayer insulating film and a manufacturing method thereof. [Background technology]

[0002] Known power devices include power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), which use a vertical trench gate structure. Some semiconductor devices (semiconductor chips) equipped with power devices include a resistor region and a diode region in addition to a cell region where a main device is formed.

[0003] For example, Patent Document 1 discloses a semiconductor device including a power MOSFET and a protection diode. The protection diode is formed on an element isolation region and covered with an interlayer insulating film. A contact hole is formed in the interlayer insulating film, and a gate wiring and a source electrode are embedded in the contact hole. One end of the protection diode is electrically connected to the gate wiring, and the other end of the protection diode is electrically connected to the source electrode. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-324570 Summary of the Invention [Problem to be solved by the invention]

[0005] 27 to 32, semiconductor devices of study examples 1 to 3 studied by the present inventors will be described below. These semiconductor devices include an IGBT as a power device. FIGS. 27 to 32 show a region in which a resistive element is formed as an example of a semiconductor element other than the IGBT. Here, a conductive film PL constitutes the resistive element.

[0006] FIG. 27 shows a semiconductor device of Study Example 1. As shown in FIG. 27, in Study Example 1, a conductive film PL is formed on the upper surface of a semiconductor substrate SUB via an insulating film IF2. The insulating film IF2 is, for example, a silicon oxide film. The conductive film PL is, for example, a polycrystalline silicon film, and forms a resistance element. In addition, an interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB so as to cover the conductive film PL. The interlayer insulating film IL is, for example, a silicon oxide film formed by a CVD method.

[0007] A contact hole CH1 is formed in the interlayer insulating film IL in the same process as the contact holes that reach the body region and emitter region of the IGBT.

[0008] Here, the contact hole CH1 is formed by etching deeper than the thickness of the interlayer insulating film IL. Therefore, the contact hole CH1 is also formed in a part of the conductive film PL. If the conductive film PL is sufficiently thick, for example, 600 nm, the bottom of the contact hole CH1 is located inside the conductive film PL, and the contact hole CH1 does not reach the semiconductor substrate SUB.

[0009] FIG. 28 shows a semiconductor device of Study Example 2. Study Example 2 is a device with more advanced miniaturization than Study Example 1. Therefore, as shown in FIG. 28, a planarization process is performed on the upper surface of the interlayer insulating film IL by a CMP method for the purpose of improving the processing accuracy of contact holes, etc. In semiconductor devices using fine processes such as SOC (System On Chip), a method is used in which dummy patterns are laid out in empty spaces to further planarize the upper surface of the interlayer insulating film IL. On the other hand, in power devices such as IGBTs, the space available for laying dummy patterns is very small, so using such a method is not very practical.

[0010] Therefore, in Study Example 2, the thickness of the conductive film PL is set to be thinner than that in Study Example 1, for example, 250 nm, thereby reducing the step on the upper surface of the interlayer insulating film IL.

[0011] However, because the thickness of the conductive film PL and the thickness of the interlayer insulating film IL on the conductive film PL are thin, when the contact hole CH1 is formed, the bottom of the contact hole CH1 may penetrate the conductive film PL and reach the insulating film IF2. Furthermore, depending on the amount of etching when the contact hole CH1 is formed, the bottom of the contact hole CH1 may reach the semiconductor substrate SUB, causing a short circuit.

[0012] To avoid such a problem, it is conceivable to form the contact hole CH1 in a manufacturing process separate from the contact holes that reach the body and emitter regions of the IGBT, and to control the depth of the contact hole CH1 separately. However, this would require an additional mask and manufacturing process, which would increase manufacturing costs.

[0013] 29 to 32 show a semiconductor device of Study Example 3. In Study Example 3, as shown in FIG. 29, an insulating film IF1 is formed under an insulating film IF2. The insulating film IF1 is, for example, a silicon oxide film formed by thermal oxidation. By providing an insulating layer IFL, which is a stacked film of such insulating films IF1 and IF2, under the conductive film PL, it is possible to prevent the bottom of the contact hole CH1 from reaching the semiconductor substrate SUB even if the contact hole CH1 penetrates the insulating film IF2.

[0014] In recent processes, a step of isotropic etching the interlayer insulating film IL is performed in order to increase the contact area between the plug embedded in the contact hole of the IGBT and the emitter region, and between the plug PG1 and the conductive film PL. In this isotropic etching, a solution containing hydrofluoric acid is used to selectively etch the silicon oxide film.

[0015] 30 shows the state after the isotropic etching process. The isotropic etching process causes the side surfaces of the interlayer insulating film IL to recede, exposing the upper surface of the conductive film PL. At the same time, the insulating films IF2 and IF1, each made of a silicon oxide film, also partially recede, exposing the lower surface of the conductive film PL.

[0016] Thereafter, as shown in FIG. 31, a barrier metal film BM is formed in the contact hole CH1, and as shown in FIG. 32, a conductive film CF is formed on the barrier metal film BM so as to fill the contact hole CH1. The barrier metal film BM and the conductive film CF form a plug PG1. The barrier metal film BM is formed by the CVD method and is made of, for example, a stacked film of a titanium film and a titanium nitride film. The conductive film CF is formed by the CVD method and is made of, for example, a tungsten film.

[0017] As a result of the above-described isotropic etching process, the distance from the side surface of the conductive film PL to the side surface of the interlayer insulating film IL in the contact hole CH1 is distance L2. The distance from the lower surface of the conductive film PL to the bottom of the contact hole CH1 is distance L3. The etching rate of the insulating film IF1 formed by thermal oxidation is slightly slower than the etching rates of the insulating film IF2 and the interlayer insulating film IL formed by CVD. Therefore, distance L3 is approximately the same as or shorter than distance L2.

[0018] As shown in Figure 31, if the distance L3 is short, the gas used in the CVD method when forming the barrier metal film BM is not sufficiently supplied to the vicinity of the lower surface of the conductive film PL, making it more likely that areas where the thickness of the barrier metal film BM is insufficient will occur.

[0019] The barrier metal film BM also serves as a seed film when the conductive film CF is formed. Therefore, as shown in FIG. 32, in areas where the barrier metal film BM is thin, the conductive film CF does not grow sufficiently, and voids are likely to occur in the contact hole CH1. Furthermore, in areas where the barrier metal film BM is not formed, the WF gas reacts with the conductive film CF (polycrystalline silicon film), causing defects such as partial loss of the conductive film CF. Such areas are shown as defective areas 20 in FIG. 32 and are likely to cause corrosion or deformation in subsequent manufacturing processes.

[0020] Although it is possible to increase the time of the isotropic etching process in order to increase the distance L3, this would also increase the distance L2, widening the opening width of the contact hole CH1. As a result, the opening width of the IGBT contact hole would also become too wide, resulting in the IGBT gate electrode being exposed within the IGBT contact hole. This would result in the problem of the IGBT gate electrode being electrically connected to the emitter electrode.

[0021] A main object of the present invention is to suppress the above-mentioned defects and improve the reliability of semiconductor devices. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0022] A brief summary of a representative embodiment of the present invention will be given below.

[0023] In one embodiment, a semiconductor device includes a semiconductor substrate having an upper surface and a lower surface, an insulating layer formed from the upper surface of the semiconductor substrate to extend into the semiconductor substrate, a first conductive film formed on the insulating layer, an interlayer insulating film formed on the upper surface of the semiconductor substrate to cover the first conductive film, a first contact hole formed in the interlayer insulating film, the first conductive film, and the insulating layer so that its bottom is located in the insulating layer, and a first plug embedded in the first contact hole, wherein a side surface of the interlayer insulating film in the first contact hole is spaced apart from a side surface of the first conductive film so that a portion of the upper surface of the first conductive film is exposed, a side surface of the insulating layer in the first contact hole is spaced apart from a side surface of the first conductive film so that a portion of the lower surface of the first conductive film is exposed, and a first distance from the lower surface of the first conductive film to the bottom of the first contact hole is longer than a second distance from the side surface of the first conductive film to a side surface of the interlayer insulating film.

[0024] In one embodiment, a method for manufacturing a semiconductor device includes: (a) preparing a semiconductor substrate having an upper surface and a lower surface; (b) after the step (a), forming a first insulating film from the upper surface of the semiconductor substrate to the interior of the semiconductor substrate; (c) after the step (b), forming a second insulating film on the first insulating film, the second insulating film having a thickness thinner than the first insulating film; (d) after the step (c), forming a first conductive film on the second insulating film; (e) after the step (d), forming an interlayer insulating film on the upper surface of the semiconductor substrate so as to cover the first conductive film; (f) after the step (e), forming a first contact hole in the interlayer insulating film, the first conductive film, the second insulating film, and the first insulating film so that the bottom of the first contact hole is located in the first insulating film; (g) after the step (f), performing an isotropic etching process on the interlayer insulating film, the second insulating film, and the first insulating film; and (h) after the step (g), embedding a first plug in the first contact hole. Here, by the step (g), within the first contact hole, the side surface of the interlayer insulating film is separated from the side surface of the first conductive film so that a portion of the upper surface of the first conductive film is exposed, and by the step (g), within the first contact hole, the side surface of the first insulating film and the side surface of the second insulating film are separated from the side surface of the first conductive film so that a portion of the lower surface of the first conductive film is exposed, and a first distance from the lower surface of the first conductive film to the bottom of the first contact hole is longer than a second distance from the side surface of the first conductive film to the side surface of the interlayer insulating film.

[0025] A method for manufacturing a semiconductor device in one embodiment is a method for manufacturing a semiconductor device having a first region and a second region different from the first region. (b) after the step (a), forming a first insulating film in the first region from a position higher than the top surface of the semiconductor substrate to the inside of the semiconductor substrate; (c) after the step (b), forming a trench in the semiconductor substrate in the second region on the top surface side of the semiconductor substrate; (d) after the step (c), performing an isotropic etching process on the first insulating film so as to reduce the thickness of the first insulating film; (e) after the step (d), forming a gate insulating film in the trench; (f) after the step (e), forming a gate electrode on the gate insulating film so as to fill the trench; (g) after the step (f), forming a second insulating film having a thickness thinner than the first insulating film on the top surface of the semiconductor substrate in the first region and the second region so as to cover the first insulating film in the first region and the gate electrode in the second region; forming a first conductive film on a second insulating film; (i) after the step (h), removing the first conductive film and the second insulating film so that the first conductive film and the second insulating film are selectively left on the first insulating film; (j) after the step (i), forming a first impurity region of a first conductivity type in the semiconductor substrate in the second region on the upper surface side of the semiconductor substrate so that the bottom of the first impurity region is located above the bottom of the trench; (k) after the step (j), forming a second impurity region of a second conductivity type opposite to the first conductivity type in the first impurity region. (l) after the step (k), forming an interlayer insulating film on the upper surface of the semiconductor substrate in the first region and the second region so as to cover the first conductive film in the first region and to cover the gate electrode, the first impurity region, and the second impurity region in the second region; (m) after the step (l), performing a planarization process on the interlayer insulating film in the first region and the second region by a CMP method in order to planarize the upper surface of the interlayer insulating film; (n) after the step (m),(o) forming a first contact hole in the interlayer insulating film, the first conductive film, the second insulating film and the first insulating film in the first region so that the bottom of the first contact hole is located in the first insulating film, and forming a second contact hole in the interlayer insulating film, the second impurity region and the first impurity region in the second region so that the bottom of the second contact hole is located in the first impurity region; and (o) after step (n), embedding a first plug in the first contact hole and embedding a second plug in the second contact hole. [Effects of the Invention]

[0026] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0027] [Figure 1] 1 is a plan view showing the entire semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 3] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 4] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 5] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 6] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 7] 1 is an enlarged cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 8] 1 is an enlarged cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 9] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 10] 10 is a cross-sectional view showing a manufacturing process following FIG. 9. [Figure 11] 11 is a cross-sectional view showing a manufacturing process following FIG. 10. [Figure 12]12 is a cross-sectional view showing a manufacturing process following FIG. 11. [Figure 13] 13 is a cross-sectional view showing a manufacturing process following FIG. 12. [Figure 14] 14 is a cross-sectional view showing a manufacturing process following FIG. 13. [Figure 15] 15 is a cross-sectional view showing a manufacturing process following FIG. 14. [Figure 16] 16 is a cross-sectional view showing a manufacturing process following FIG. 15. [Figure 17] FIG. 17 is a cross-sectional view showing a manufacturing process following FIG. [Figure 18] 18 is a cross-sectional view showing a manufacturing process following FIG. 17. [Figure 19] FIG. 19 is a cross-sectional view showing a manufacturing process following FIG. [Figure 20] 19A to 19C are cross-sectional views showing the manufacturing process following FIG. [Figure 21] 21 is a cross-sectional view showing a manufacturing process following FIG. 20. [Figure 22] 22 is a cross-sectional view showing a manufacturing process following FIG. 21. [Figure 23] 23 is a cross-sectional view showing a manufacturing process following FIG. 22. [Figure 24] FIG. 24 is a cross-sectional view showing a manufacturing process following FIG. 23. [Figure 25] FIG. 25 is a cross-sectional view showing a manufacturing process following FIG. 24. [Figure 26] FIG. 26 is a cross-sectional view showing a manufacturing process following FIG. 25. [Figure 27] FIG. 1 is a cross-sectional view showing a semiconductor device in Study Example 1. [Figure 28] FIG. 10 is a cross-sectional view showing a semiconductor device in Study Example 2. [Figure 29] FIG. 10 is a cross-sectional view showing a semiconductor device in Study Example 3. [Figure 30] FIG. 30 is a cross-sectional view showing a manufacturing process following FIG. 29. [Figure 31] 31 is a cross-sectional view showing a manufacturing process following FIG. 30. [Figure 32] 32 is a cross-sectional view showing a manufacturing process following FIG. 31. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0029] (Embodiment 1) <Structure of semiconductor device> A semiconductor device 100 according to the first embodiment will be described below with reference to Figures 1 to 8. Figure 1 is a plan view showing a semiconductor chip which is the semiconductor device 100.

[0030] As shown in FIG. 1, most of the semiconductor device 100 is covered with an emitter electrode EE, and a plurality of cells constituting the IGBT are formed below the emitter electrode EE. A gate wiring GW is formed around the emitter electrode EE. The center of the emitter electrode EE serves as an emitter pad, and the center of the gate wiring GW serves as a gate pad. External connection terminals such as wire bonding or clips (copper plates) are connected to the emitter pad and the gate pad, thereby electrically connecting the semiconductor device 100 to other semiconductor chips or wiring boards.

[0031] The semiconductor device 100 includes regions 1A to 3A, which are different from one another. Region 1A in FIG. 1 is a resistor region where resistor elements are formed. The resistor elements are used as gate resistors, etc. Region 2A in FIG. 1 is a cell region where multiple cells constituting the IGBT are formed. Region 3A in FIG. 1 is a diode region where diode elements are formed. The diode elements are used for gate protection, temperature detection, etc.

[0032] Fig. 2 is a plan view of a main part corresponding to region 1A. Fig. 3 is a plan view of a main part corresponding to region 3A. Fig. 4 is a plan view of a main part corresponding to region 2A. Fig. 5 is a cross-sectional view taken along line AA in Fig. 2 and a cross-sectional view taken along line BB in Fig. 4. Fig. 6 is a cross-sectional view taken along line CC in Fig. 3.

[0033] 2 to 4, the contact holes CH1 and CH2 have a slit shape in plan view, with the opening width in a first direction being wider than the opening width in a second direction perpendicular to the first direction. That is, the contact holes CH1 and CH2 have a rectangular shape in plan view.

[0034] However, the planar shape of the contact holes CH1 and CH2 is not limited to a slit shape, and may be a dot shape in which the opening width in the first direction is the same as the opening width in the second direction. That is, the contact holes CH1 and CH2 each having a rectangular shape in plan view may be arranged in plurality in the first direction.

[0035] In many cases, the planar shapes of the contact holes CH1 and CH2 have rounded corners after photolithography resolution, so that the contact holes CH1 and CH2 ultimately have a rectangular shape with rounded corners or a circular shape in plan view.

[0036] 3 and 6 have almost the same main features as the resistor elements shown in Figures 2 and 5, except that a p-type anode region PLP and an n-type cathode region PLN are formed in the conductive film PL. Therefore, the resistor element in region 1A and the IGBT cell in region 2A will be described below.

[0037] 5 and 6, semiconductor device 100 includes a semiconductor substrate SUB having a low-concentration n-type drift region NV. Here, the n-type semiconductor substrate SUB itself constitutes the drift region NV. Note that the drift region NV may be a stacked structure of an n-type silicon substrate and a semiconductor layer grown on the silicon substrate by epitaxial growth while introducing phosphorus (P). In the present application, such a stacked structure will also be described as the semiconductor substrate SUB.

[0038] An n-type field stop region (impurity region) NS is formed in the semiconductor substrate SUB on the lower surface side thereof. The field stop region NS is provided to prevent a depletion layer extending from the pn junction on the upper surface side of the semiconductor substrate SUB from reaching the p-type collector region PC when the IGBT is turned off.

[0039] A p-type collector region (impurity region) PC is formed on the lower surface side of the semiconductor substrate SUB. The collector region PC is located below the field stop region NS.

[0040] A collector electrode CE is formed below the lower surface of the semiconductor substrate SUB. The collector electrode CE is electrically connected to the collector region PC and supplies a collector potential to the collector region PC. The collector electrode CE is made of a metal film such as an AlSi film, a Ti film, a NiV film, or an Au film.

[0041] <Resistance element> The structure of the region 1A will be described below. In the semiconductor device 100, the conductive film PL formed in the region 1A is used as a resistance element.

[0042] 5, a p-type well region PW is formed in the semiconductor substrate SUB on the upper surface side of the semiconductor substrate SUB. The well region PW is formed in the same process as the floating region PF of the region 1A, but is physically separated from the floating region PF.

[0043] An insulating layer IFL is formed from the upper surface of the semiconductor substrate SUB to the inside of the semiconductor substrate SUB. In other words, the insulating layer IFL is formed in the semiconductor substrate SUB, and the lower surface of the insulating layer IFL is located lower than the upper surface of the semiconductor substrate SUB.

[0044] The insulating layer IFL includes insulating films IF1 and IF2. The insulating film IF1 is formed inside the semiconductor substrate SUB and is, for example, a silicon oxide film. The insulating film IF2 is formed on the insulating film IF1 and is, for example, a silicon oxide film. The insulating film IF2 has a thickness thinner than that of the insulating film IF1. The thickness of the insulating film IF1 is, for example, 500 to 600 nm. The thickness of the insulating film IF2 is, for example, 50 to 100 nm.

[0045] A conductive film PL is formed on the insulating layer IFL. The conductive film PL is, for example, a polycrystalline silicon film doped with p-type impurities. The thickness of the conductive film PL is, for example, 150 to 250 nm.

[0046] An interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB so as to cover the conductive film PL. The interlayer insulating film IL is, for example, a silicon oxide film. The interlayer insulating film IL has been subjected to a planarization process to flatten the upper surface of the interlayer insulating film IL. Therefore, the thickness of the interlayer insulating film IL on the upper surface of the semiconductor substrate SUB is, for example, 600 to 800 nm, while the thickness of the interlayer insulating film IL on the upper surface of the conductive film PL is, for example, 300 to 450 nm.

[0047] A contact hole CH1 is formed in the interlayer insulating film IL, the conductive film PL, and the insulating layer IFL. The bottom of the contact hole CH1 is located in the insulating layer IFL (in the insulating film IF1). A plug PG1 is buried in the contact hole CH1. The plug PG1 includes a barrier metal film BM and a conductive film CF formed on the barrier metal film BM. The barrier metal film BM is, for example, a stacked film of a titanium film and a titanium nitride film formed on the titanium film. The conductive film CF is, for example, a tungsten film.

[0048] On the interlayer insulating film IL, a gate wiring GW is formed. The conductive film PL is electrically connected to the gate wiring GW via a plug PG1. By configuring the electrical path in the middle of the gate wiring GW with the conductive film PL, the conductive film PL can be used as a gate resistor.

[0049] The main features of Embodiment 1 are the shape of the contact hole CH1 and the point where the plug PG1 and the conductive film PL are in contact within the contact hole CH1. Such features will be described in detail later.

[0050] <Structure of IGBT cell> The structure of region 2A will be described below. Here, an IGBT to which a vertical trench gate structure is applied is exemplified.

[0051] As shown in FIG. 5, on the upper surface side of the semiconductor substrate SUB, a trench TR is formed in the semiconductor substrate SUB. The depth of the trench TR is, for example, 3 to 4 μm. A gate insulating film GI is formed in the trench TR. The gate electrode GE is formed on the gate insulating film GI so as to fill the trench TR. The gate insulating film GI is, for example, a silicon oxide film, and the gate electrode GE is, for example, a polycrystalline silicon film into which n-type impurities are introduced.

[0052] On the upper surface side of the semiconductor substrate SUB, a hole barrier region (impurity region) NHB is formed in the semiconductor substrate SUB between the pair of gate electrodes GE. A p-type base region (impurity region) PB is formed in the hole barrier region NHB. An n-type emitter region (impurity region) NE is formed in the p-type base region PB. The bottom of the base region PB is located above the bottom of the trench TR, and the bottom of the emitter region NE is located above the bottom of the base region PB.

[0053] Furthermore, on the upper surface side of the semiconductor substrate SUB, a p-type floating region (impurity region) PF is formed in the semiconductor substrate SUB except for the region in which the hole barrier region NHB is formed. A p-type base region PB is formed in the floating region PF. In order to enhance high-voltage resistance characteristics, the floating region PF is formed to a position deeper than the bottom of the trench TR and is formed so as to cover the bottom of the trench TR.

[0054] The interlayer insulating film IL is also formed on the upper surface of the semiconductor substrate SUB in region 2A so as to cover the gate electrode GE, the emitter region NE, and the base region PB. A contact hole CH2 is formed in the interlayer insulating film IL, the emitter region NE, and the base region PB in region 2A. The bottom of the contact hole CH2 is located in the base region PB. A plug PG2 is buried in the contact hole CH2. The plug PG2 has the same configuration as the plug PG1 and includes a barrier metal film BM and a conductive film CF.

[0055] A p-type high-concentration diffusion region (impurity region) PR is formed in the base region PB around the bottom of the contact hole CH2. The high-concentration diffusion region PR is provided to reduce the contact resistance with the plug PG2 and to prevent latch-up.

[0056] In the region 2A, the side surface of the interlayer insulating film IL is recessed because an isotropic etching process is performed on the interlayer insulating film IL in order to increase the contact area between the plug PG2 embedded in the contact hole CH2 and the emitter region NE. That is, in the contact hole CH2, the side surface of the interlayer insulating film IL is spaced apart from the side surface of the emitter region NE so that part of the upper surface of the emitter region NE is exposed.

[0057] An emitter electrode EE is formed on the interlayer insulating film IL. The emitter electrode EE is electrically connected to the emitter region NE, base region PB, and heavily doped diffusion region PR via plugs PG2, and supplies an emitter potential to these regions. Although not shown here, the gate wiring GW is electrically connected to the gate electrode GE via another plug, and supplies a gate potential to the gate electrode GE.

[0058] The emitter electrode EE and the gate wiring GW are each made of, for example, a TiW film and an aluminum film formed on the TiW film. The aluminum film is the main conductor film of the emitter electrode EE and the gate wiring GW and is much thicker than the TiW film.

[0059] <Diode element structure> 6, the structure of region 3A will be described below. In the semiconductor device 100, the conductive film PL formed in region 3A is used as a diode element. The other structures are the same as those in region 1A, so descriptions thereof will be omitted.

[0060] In the diode element shown in Figure 6, ions are implanted into the conductive film PL to form a p-type anode region PLP and an n-type cathode region PLN. Contact holes CH1 are formed in the anode region PLP and the cathode region PLN, respectively, and plugs PG1 are embedded in the contact holes CH1. Although not shown here, an emitter electrode EE and a gate wiring GW are formed on the interlayer insulating film IL in region 3A. The anode region PLP is electrically connected to the emitter electrode EE via the plug PG1, and the cathode region PLN is electrically connected to the gate wiring GW via the plug PG1.

[0061] <Main features of the first embodiment> The main features of the first embodiment will be described below with reference to Figures 7 and 8. Figures 7 and 8 are enlarged cross-sectional views of the periphery of contact hole CH1. Figure 7 also shows the state before plug PG1 is buried in contact hole CH1.

[0062] In region 1A, the interlayer insulating film IL is isotropically etched in the same process as the process of forming contact hole CH2 in region 2A, so that the side surfaces of the interlayer insulating film IL are recessed. In contact hole CH1, the side surfaces of the interlayer insulating film IL are spaced apart from the side surfaces of the conductive film PL so that part of the upper surface of the conductive film PL is exposed. The distance L2 between these side surfaces is, for example, 50 to 100 nm.

[0063] Here, the insulating layer IFL is also recessed by the above-mentioned isotropic etching process. Therefore, in the contact hole CH1, the side surfaces of the insulating layer IFL (side surfaces of the insulating film IF1 and the insulating film IF2) are spaced apart from the side surfaces of the conductive film PL so that part of the lower surface of the conductive film PL is exposed. In other words, the opening width of the contact hole CH1 formed in the interlayer insulating film IL and the opening width of the contact hole CH1 formed in the insulating layer IFL are wider than the opening width of the contact hole CH1 formed in the conductive film PL.

[0064] As will be explained later, in the first embodiment, before the above-described isotropic etching process, the contact hole CH1 is formed in advance so that the bottom of the contact hole CH1 reaches the inside of the insulating layer IFL. Since the above-described isotropic etching process is performed in this state, the distance L1 from the lower surface of the conductive film PL to the bottom of the contact hole CH1 is longer than the distance L3 in the study example 3 and is also longer than the distance L2. The distance L1 is, for example, 150 to 200 nm.

[0065] In the study example 3, the short distance L3 made it easy for the thickness of the barrier metal film BM to be insufficient in some places. Therefore, in the places where the barrier metal film BM was thin, the conductive film CF did not grow sufficiently, which caused problems such as voids being easily generated in the contact hole CH1 and the WF gas reacting with the conductive film CF, resulting in the loss of part of the conductive film CF.

[0066] In the first embodiment, the distance L1 is sufficiently long, so that the gas used in the CVD method when forming the barrier metal film BM is sufficiently supplied to the vicinity of the lower surface of the conductive film PL. Therefore, a barrier metal film BM with a sufficient thickness is secured within the contact hole CH1. The barrier metal film BM also serves as a seed film when forming the conductive film CF, so that the conductive film CF also grows sufficiently. Therefore, in the first embodiment, various problems that occurred in the third study example are resolved, and the reliability of the semiconductor device can be improved.

[0067] Furthermore, the barrier metal film BM is in contact with a part of the upper surface of the conductive film PL, the side surface of the conductive film PL, and a part of the lower surface of the conductive film PL within the contact hole CH1. Therefore, the contact area between the plug PG1 and the conductive film PL can be increased, which reduces the contact resistance between the plug PG1 and the conductive film PL and improves the adhesion between the plug PG1 and the conductive film PL.

[0068] The diode element in region 3A can also provide the same effect as the resistor element in region 1A.

[0069] <Method of manufacturing a semiconductor device> A method for manufacturing the semiconductor device 100 according to the first embodiment will be described below with reference to FIGS.

[0070] First, as shown in FIG. 9, a semiconductor substrate SUB having an n-type drift region NV is prepared. The semiconductor substrate SUB has an upper surface and a lower surface. Next, a silicon oxide film 10 is formed on the upper surface of the semiconductor substrate SUB by, for example, thermal oxidation. Next, a silicon nitride film 11 is formed on the silicon oxide film 10 by, for example, CVD.

[0071] 10, the silicon nitride film 11 and the silicon oxide film 10 in the region 1A are selectively removed by photolithography and dry etching to form openings in the silicon nitride film 11 and the silicon oxide film 10. Next, a dry etching process is further performed to etch a portion of the semiconductor substrate SUB exposed in the opening, thereby forming a groove in the semiconductor substrate SUB.

[0072] 11, the semiconductor substrate SUB is subjected to a thermal oxidation treatment to form an insulating film IF1 from the upper surface of the semiconductor substrate SUB to the inside of the semiconductor substrate SUB. In this state, the insulating film IF1 is formed up to a position higher than the upper surface of the semiconductor substrate SUB. That is, the insulating film IF1 having a LOCOS structure is formed on the semiconductor substrate SUB in the region 1A. In this state, the thickness of the insulating film IF1 is, for example, 700 to 800 nm.

[0073] 12, the silicon nitride film 11 is removed by isotropic etching using a solution containing phosphoric acid. Next, a p-type well region PW is formed in the semiconductor substrate SUB in region 1A by photolithography and ion implantation, and a p-type floating region PF is formed in the semiconductor substrate SUB in region 2A. Next, an n-type hole barrier region NHB is formed in the semiconductor substrate SUB in region 2A by photolithography and ion implantation.

[0074] Next, as shown in FIG. 13, a trench TR is formed in the semiconductor substrate SUB in the region 2A by photolithography and dry etching.

[0075] 14, the silicon oxide film 10 is removed by isotropic etching using a solution containing hydrofluoric acid. At this time, the insulating film IF1 is also exposed to the isotropic etching, so that the upper surface of the insulating film IF1 recedes and the thickness of the insulating film IF1 becomes thinner.

[0076] 15, the semiconductor substrate SUB is subjected to a heat treatment at, for example, 1000 to 1200° C. to diffuse the impurities contained in the hole barrier region NHB, the floating region PF, and the well region PW. This heat treatment causes the hole barrier region NHB to diffuse to near the bottom of the trench TR, and the floating region PF to diffuse to a position deeper than the bottom of the trench TR so as to cover the bottom of the trench TR.

[0077] Although not shown in the drawings, this heat treatment is performed in a state where a sacrificial silicon oxide film is formed on the semiconductor substrate SUB including the inside of the trench TR. After the heat treatment, the sacrificial silicon oxide film is removed by isotropic etching using a solution containing hydrofluoric acid. At this time, the insulating film IF1 is also exposed to the isotropic etching, so that the upper surface of the insulating film IF1 recedes and the thickness of the insulating film IF1 becomes thinner. In this state, the thickness of the insulating film IF1 is, for example, 500 to 600 nm.

[0078] 16, a gate insulating film GI is formed inside the trench TR and on the semiconductor substrate SUB. The gate insulating film GI is formed by thermal oxidation. The thickness of the gate insulating film GI is, for example, 100 nm.

[0079] Next, a gate electrode GE is formed so as to fill the trench TR. To form the gate electrode GE, first, a polycrystalline silicon film doped with n-type impurities is formed on the gate insulating film GI by, for example, a CVD method. Next, the polycrystalline silicon film formed outside the trench TR is removed by a dry etching process. The polycrystalline silicon film formed inside the trench TR is left as the gate electrode GE.

[0080] 17, an insulating film IF2 is formed on the insulating film IF1, on the gate electrode GE, and on the gate insulating film GI formed outside the trench TR, for example, by a CVD method. The thickness of the insulating film IF2 is, for example, 50 to 100 nm. Next, a conductive film PL is formed on the insulating film IF2, for example, by a CVD method. The thickness of the conductive film PL is, for example, 150 to 250 nm.

[0081] Next, p-type impurities are introduced into the conductive film PL by ion implantation. Note that n-type and p-type impurities are introduced into the conductive film PL in region 3A by photolithography and ion implantation, forming an anode region PLP and a cathode region PLN. Next, a resist pattern RP1 is formed on the conductive film PL in region 1A so as to selectively cover the conductive film PL located on the insulating film IF1. Note that the anode region PLP and the cathode region PLN are also covered with the resist pattern RP1.

[0082] Next, as shown in FIG. 18, a dry etching process is performed using the resist pattern RP1 as a mask to pattern the conductive film PL and the insulating film IF2. As a result, a resistor element is formed in region 1A, and a diode element is formed in region 3A. The patterned insulating films IF2 and IF1 form an insulating layer IFL. This dry etching process also removes the gate insulating film GI formed outside the trench TR. Thereafter, the resist pattern RP1 is removed by ashing.

[0083] Next, as shown in FIG. 19, a p-type base region PB is formed in the semiconductor substrate SUB (floating region PF and hole barrier region NHB) on the upper surface side of the semiconductor substrate SUB by photolithography and ion implantation. The bottom of the base region PB is located higher than the bottom of the trench TR. Next, an n-type emitter region NE is formed in the base region PB by photolithography and ion implantation. Thereafter, a heat treatment is performed to activate the impurities contained in each impurity region.

[0084] Next, as shown in FIG. 20, an interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB in the regions 1A and 2A so as to cover the conductive film PL, the gate electrode GE, the base region PB, and the emitter region NE.

[0085] 21, in order to planarize the upper surface of the interlayer insulating film IL, a planarization process is performed on the interlayer insulating film IL in the region 1A and the region 2A by the CMP method. After the planarization process, the thickness of the interlayer insulating film IL on the upper surface of the semiconductor substrate SUB is, for example, 600 to 800 nm, and the thickness of the interlayer insulating film IL on the upper surface of the conductive film PL is, for example, 300 to 450 nm.

[0086] 22, a contact hole CH1 is formed in the interlayer insulating film IL, the conductive film PL, the insulating film IF2, and the insulating film IF1 in region 1A by photolithography and dry etching. At the same time, a contact hole CH2 is formed in the interlayer insulating film IL, the emitter region NE, and the base region PB in region 2A. Next, a p-type high-concentration diffusion region PR is formed in the base region PB located at the bottom of the contact hole CH2 by ion implantation.

[0087] Here, the bottom of contact hole CH1 is located in insulating film IF1, and the bottom of contact hole CH2 is located in base region PB. In study example 3, as shown in FIG. 29, contact hole CH1 penetrates the conductive film PL, and the bottom of contact hole CH1 is located on or in insulating film IF2. In embodiment 1, contact hole CH1 is formed deeper than in study example 3.

[0088] At this point, the distance from the lower surface of the conductive film PL to the bottom of the contact hole CH1 is, for example, 100 to 150 nm. In other words, the amount of etching of the insulating layer IFL in FIG. 22 is set to be larger than the amount of etching of the interlayer insulating film IL and the insulating layer IFL by the isotropic etching process in FIG.

[0089] Next, as shown in FIG. 23, the interlayer insulating film IL and the insulating layer IFL (insulating film IF2 and insulating film IF1) are subjected to an isotropic etching process using a solution containing hydrofluoric acid. This isotropic etching process separates the side surface of the interlayer insulating film IL from the side surface of the conductive film PL in the contact hole CH1 so that a portion of the upper surface of the conductive film PL is exposed. Also, in the contact hole CH1, the side surface of the insulating layer IFL (the side surface of the insulating film IF1 and the side surface of the insulating film IF2) separates from the side surface of the conductive film PL so that a portion of the lower surface of the conductive film PL is exposed. Also, in the contact hole CH2, the side surface of the interlayer insulating film IL separates from the side surface of the emitter region NE so that a portion of the upper surface of the emitter region NE is exposed.

[0090] The above-described isotropic etching process also deepens the depth of the contact hole CH1. That is, as shown in FIG. 7, the distance L1 from the lower surface of the conductive film PL to the bottom of the contact hole CH1 becomes longer than the distance L2.

[0091] 24, a barrier metal film BM is formed by CVD on the interlayer insulating film IL including inside the contact holes CH1 and CH2. The barrier metal film BM is, for example, a stacked film of a titanium film and a titanium nitride film. At this point, the barrier metal film BM contacts part of the upper surface, the side surface, and part of the lower surface of the conductive film PL in the contact hole CH1.

[0092] Next, a conductive film CF is formed on the barrier metal film BM so as to fill the contact holes CH1 and CH2. The conductive film CF is, for example, a tungsten film, and is formed using WF6 gas.

[0093] 25, the conductive film PL and the barrier metal film BM formed outside the contact holes CH1 and CH2 are removed by a polishing process using the CMP method or an anisotropic dry etching process, thereby embedding a plug PG1 including the conductive film PL and the barrier metal film BM in the contact hole CH1, and embedding a plug PG2 including the conductive film PL and the barrier metal film BM in the contact hole CH2.

[0094] 26, a gate wiring GW is formed on the interlayer insulating film IL in region 1A, and an emitter electrode EE is formed on the interlayer insulating film IL in region 2A. First, a TiW film is formed on the interlayer insulating film IL by, for example, sputtering, and then an aluminum film is formed on the TiW film by, for example, sputtering. Next, the TiW film and the aluminum film are patterned by photolithography and dry etching to form the gate wiring GW and the emitter electrode EE.

[0095] Thereafter, a field stop region NS, a collector region PC, and a collector electrode CE are formed on the lower surface side of the semiconductor substrate SUB, thereby obtaining the structure shown in FIG.

[0096] First, a support tape is attached to the upper surface of the semiconductor substrate SUB, and the lower surface of the semiconductor substrate SUB is ground to reduce the thickness of the semiconductor substrate SUB to, for example, 80 to 90 μm. The lower surface of the semiconductor substrate SUB is then etched using a solution containing hydrofluoric acid to remove the grinding-damaged layer. Ion implantation is then performed from the lower surface of the semiconductor substrate SUB to form an n-type field stop region NS and a p-type collector region PC. After these ion implantations, laser annealing is performed to activate the impurities contained in the field stop region NS and the collector region PC. Next, a metal film, such as an AlSi film, Ti film, NiV film, or Au film, is formed below the lower surface of the semiconductor substrate SUB by, for example, sputtering. This metal film becomes the collector electrode CE.

[0097] In this manner, the semiconductor device 100 according to the first embodiment is manufactured.

[0098] The manufacturing method of the first embodiment, like the second embodiment, can be adapted to devices with more advanced miniaturization than the first embodiment. For example, the steps on the upper surface of the interlayer insulating film IL are reduced in order to improve the processing accuracy of contact holes. To achieve this, the upper surface of the interlayer insulating film IL is planarized by the CMP method to thin the conductive film PL. Furthermore, the thickness of the insulating film IF1 is reduced so that the upper surface of the insulating film IF1 is substantially flush with the upper surface of the semiconductor substrate SUB, thereby also reducing the steps on the upper surface of the interlayer insulating film IL.

[0099] Even in this case, by forming the insulating layer IFL under the conductive film PL, it is possible to eliminate the problem that the contact hole CH1 penetrates the conductive film PL and reaches the semiconductor substrate SUB. Furthermore, in order to avoid such a problem, it is not necessary to form the contact hole CH1 in a manufacturing process separate from that for the contact hole CH2, so there is no need to add an additional mask or manufacturing process, and an increase in manufacturing costs can be suppressed.

[0100] Furthermore, after forming the contact hole CH1 deeper than in Study Example 3 in the process of FIG. 22, the depth of the contact hole CH1 is further deepened by the isotropic etching process of FIG. 23. That is, the distance L1 from the lower surface of the conductive film PL to the bottom of the contact hole CH1 is made sufficiently long. This ensures that the barrier metal film BM is formed normally, making it easier for the conductive film CF to grow sufficiently using the barrier metal film BM as a seed film. Furthermore, since there are no areas where the barrier metal film BM is very thin or where no barrier metal film BM is formed, the problem of WF6 gas reacting with the conductive film CF and causing a portion of the conductive film CF to be lost is eliminated. Therefore, a highly reliable semiconductor device 100 can be manufactured.

[0101] Although the present invention has been described above based on the above embodiment, the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention.

[0102] For example, in the above embodiment, an IGBT is exemplified as a device formed in region 2A, but the technology disclosed in the above embodiment is not limited to IGBTs and can also be applied to power MOSFETs having a vertical trench gate structure. [Explanation of symbols]

[0103] 100 Semiconductor device 10 Silicon oxide film 11 Silicon nitride film 20 Defective parts 1A area (resistance element area) 2A area (cell area) 3A area (diode element area) BM Barrier metal film CE collector electrode CF conductive film CH1, CH2 contact holes EE emitter electrode GE gate electrode GI gate insulating film GW Gate wiring IF1, IF2 insulating film IFL insulating layer IL Interlayer insulating film NE emitter region NHB hole barrier region NS field stop region NV drift region PB Base Area PC Collector Area PF floating area PG1, PG2 plugs PL conductive film PR high concentration diffusion region PW well region SUB Semiconductor substrate TR Trench

Claims

1. a semiconductor substrate having an upper surface and a lower surface; an insulating layer formed from the upper surface of the semiconductor substrate to the interior of the semiconductor substrate; a first conductive film formed on the insulating layer; an interlayer insulating film formed on the upper surface of the semiconductor substrate so as to cover the first conductive film; a first contact hole formed in the interlayer insulating film, the first conductive film, and the insulating layer so that the bottom of the first contact hole is located in the insulating layer; a first plug embedded in the first contact hole; Equipped with In the first contact hole, a side surface of the interlayer insulating film is spaced apart from a side surface of the first conductive film so that a part of an upper surface of the first conductive film is exposed; In the first contact hole, a side surface of the insulating layer is spaced apart from a side surface of the first conductive film so that a part of a lower surface of the first conductive film is exposed; a first distance from a lower surface of the first conductive film to a bottom of the first contact hole is longer than a second distance from a side surface of the first conductive film to a side surface of the interlayer insulating film.

2. 2. The semiconductor device according to claim 1, the first plug includes a barrier metal film and a second conductive film formed on the barrier metal film; A semiconductor device, wherein the barrier metal film is in contact with a portion of the upper surface of the first conductive film, a side surface of the first conductive film, and a portion of the lower surface of the first conductive film within the first contact hole.

3. 2. The semiconductor device according to claim 1, the insulating layer includes a first insulating film formed inside the semiconductor substrate, and a second insulating film formed on the first insulating film and having a thickness thinner than that of the first insulating film; The bottom of the first contact hole is located in the first insulating film.

4. 4. The semiconductor device according to claim 3, the interlayer insulating film, the first insulating film, and the second insulating film are silicon oxide films, The semiconductor device, wherein the first conductive film is a polycrystalline silicon film.

5. 2. The semiconductor device according to claim 1, a first region in which the first conductive film is formed; a second region different from the first region; a trench formed in the semiconductor substrate in the second region on the upper surface side of the semiconductor substrate; a gate insulating film formed in the trench; a gate electrode formed on the gate insulating film so as to fill the trench; a first impurity region of a first conductivity type formed in the semiconductor substrate in the second region on the upper surface side of the semiconductor substrate so that the bottom of the first impurity region is located above the bottom of the trench; a second impurity region formed in the first impurity region and having a second conductivity type opposite to the first conductivity type; Further provided with the interlayer insulating film is also formed on the upper surface of the semiconductor substrate in the second region so as to cover the gate electrode, the first impurity region, and the second impurity region; a second contact hole is formed in the interlayer insulating film, the second impurity region, and the first impurity region of the second region so that the bottom of the second contact hole is located in the first impurity region; In the second contact hole, a side surface of the interlayer insulating film is spaced apart from a side surface of the second impurity region so that a part of an upper surface of the second impurity region is exposed; a second plug embedded in the second contact hole;

6. 6. The semiconductor device according to claim 5, the interlayer insulating film in the first region and the second region is subjected to a planarization process for planarizing an upper surface of the interlayer insulating film.

7. 6. The semiconductor device according to claim 5, a gate wiring formed on the interlayer insulating film in the first region and electrically connected to the gate electrode; an emitter electrode formed on the interlayer insulating film in the second region; Further provided with the first impurity region and the second impurity region are electrically connected to the emitter electrode via the second plug; the first conductive film is electrically connected to the gate wiring via the first plug, and is used as a resistor element or a diode element.

8. (a) providing a semiconductor substrate having an upper surface and a lower surface; (b) after the step (a), forming a first insulating film from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate; (c) after the step (b), forming a second insulating film on the first insulating film, the second insulating film having a thickness thinner than that of the first insulating film; (d) after the step (c), forming a first conductive film on the second insulating film; (e) after the step (d), forming an interlayer insulating film on the upper surface of the semiconductor substrate so as to cover the first conductive film; (f) after the step (e), forming a first contact hole in the interlayer insulating film, the first conductive film, the second insulating film, and the first insulating film so that the bottom of the first contact hole is located in the first insulating film; (g) after the step (f), performing an isotropic etching process on the interlayer insulating film, the second insulating film, and the first insulating film; (h) after the step (g), burying a first plug in the first contact hole; Equipped with In the step (g), a side surface of the interlayer insulating film is separated from a side surface of the first conductive film in the first contact hole so that a part of an upper surface of the first conductive film is exposed; by the step (g), in the first contact hole, the side surfaces of the first insulating film and the second insulating film are separated from the side surfaces of the first conductive film so that a part of the lower surface of the first conductive film is exposed; A method for manufacturing a semiconductor device, wherein a first distance from a lower surface of the first conductive film to a bottom of the first contact hole is longer than a second distance from a side surface of the first conductive film to a side surface of the interlayer insulating film.

9. 9. The method for manufacturing a semiconductor device according to claim 8, the first plug includes a barrier metal film and a second conductive film; The step (h) (h1) forming the barrier metal film in the first contact hole by a CVD method; (h2) forming the second conductive film on the barrier metal film so as to fill the first contact hole; and A method for manufacturing a semiconductor device, wherein the barrier metal film contacts a portion of the upper surface of the first conductive film, a side surface of the first conductive film, and a portion of the lower surface of the first conductive film within the first contact hole.

10. 9. The method for manufacturing a semiconductor device according to claim 8, the first insulating film is a silicon oxide film formed by thermal oxidation, the second insulating film is a silicon oxide film formed by a CVD method, The method for manufacturing a semiconductor device, wherein the first conductive film is a polycrystalline silicon film formed by a CVD method.

11. 11. The method for manufacturing a semiconductor device according to claim 10, In the step (b), the first insulating film is formed to a position higher than an upper surface of the semiconductor substrate; a step of isotropically etching the first insulating film between the steps (b) and (c) to reduce the thickness of the first insulating film;

12. 9. The method for manufacturing a semiconductor device according to claim 8, (i) after the step (b) and before the step (c), forming a trench in a second region of the semiconductor substrate on the upper surface side of the semiconductor substrate, the second region being different from a first region in which the first conductive film is formed; (j) forming a gate insulating film in the trench after the step (i) and before the step (c); (k) forming a gate electrode on the gate insulating film so as to fill the trench after the step (j) and before the step (c); (l) after the step (d) and before the step (e), forming a first impurity region of a first conductivity type in the semiconductor substrate in the second region on the upper surface side of the semiconductor substrate so that the bottom of the first impurity region is located above the bottom of the trench; (m) forming a second impurity region of a second conductivity type opposite to the first conductivity type in the first impurity region after the step (l) and before the step (e); Further provided with In the step (e), the interlayer insulating film is also formed on the upper surface of the semiconductor substrate in the second region so as to cover the gate electrode, the first impurity region, and the second impurity region; In the step (f), a second contact hole is formed in the interlayer insulating film, the second impurity region, and the first impurity region of the second region so that the bottom of the second contact hole is located in the first impurity region; In the step (g), a side surface of the interlayer insulating film is separated from a side surface of the second impurity region in the second contact hole so that a part of an upper surface of the second impurity region is exposed; In the step (h), a second plug is buried in the second contact hole.

13. 13. The method for manufacturing a semiconductor device according to claim 12, (n) after the step (e) and before the step (f), performing a planarization process on the interlayer insulating film in the first region and the second region by a CMP method in order to planarize an upper surface of the interlayer insulating film; The method for manufacturing a semiconductor device further comprises:

14. 13. The method for manufacturing a semiconductor device according to claim 12, (o) after the step (h), forming a gate wiring electrically connected to the gate electrode on the interlayer insulating film in the first region, and forming an emitter electrode on the interlayer insulating film in the second region; Further provided with the first impurity region and the second impurity region are electrically connected to the emitter electrode via the second plug; The method for manufacturing a semiconductor device, wherein the first conductive film is electrically connected to the gate wiring via the first plug and is used as a resistor element or a diode element.

15. 1. A method for manufacturing a semiconductor device having a first region and a second region different from the first region, comprising: (a) providing a semiconductor substrate having an upper surface and a lower surface; (b) after the step (a), forming a first insulating film in the first region from a position higher than the upper surface of the semiconductor substrate to the inside of the semiconductor substrate; (c) after the step (b), forming a trench in the semiconductor substrate in the second region on the upper surface side of the semiconductor substrate; (d) after the step (c), performing an isotropic etching process on the first insulating film so as to reduce the thickness of the first insulating film; (e) after the step (d), forming a gate insulating film in the trench; (f) after the step (e), forming a gate electrode on the gate insulating film so as to fill the trench; (g) after the step (f), forming a second insulating film having a thickness thinner than that of the first insulating film on the upper surface of the semiconductor substrate in the first region and the second region so as to cover the first insulating film in the first region and to cover the gate electrode in the second region; (h) after the step (g), forming a first conductive film on the second insulating film in the first region and the second region; (i) after the step (h), removing the first conductive film and the second insulating film so that the first conductive film and the second insulating film are selectively left on the first insulating film; (j) after the step (i), forming a first impurity region of a first conductivity type in the semiconductor substrate in the second region on the upper surface side of the semiconductor substrate so that the bottom of the first impurity region is located above the bottom of the trench; (k) after the step (j), forming a second impurity region of a second conductivity type opposite to the first conductivity type in the first impurity region; (l) after the step (k), forming an interlayer insulating film on the upper surface of the semiconductor substrate in the first region and the second region so as to cover the first conductive film in the first region and to cover the gate electrode, the first impurity region, and the second impurity region in the second region; (m) after the step (l), performing a planarization process on the interlayer insulating film in the first region and the second region by a CMP method in order to planarize an upper surface of the interlayer insulating film; (n) after the step (m), forming a first contact hole in the interlayer insulating film, the first conductive film, the second insulating film, and the first insulating film in the first region so that the bottom of the first contact hole is located in the first insulating film, and forming a second contact hole in the interlayer insulating film, the second impurity region, and the first impurity region in the second region so that the bottom of the second contact hole is located in the first impurity region; (o) after the step (n), a step of burying a first plug in the first contact hole and a second plug in the second contact hole; A method for manufacturing a semiconductor device, comprising:

16. 16. The method for manufacturing a semiconductor device according to claim 15, (p) after the step (n), performing an isotropic etching process on the interlayer insulating film, the second insulating film, and the first insulating film; Further provided with In the step (p), a side surface of the interlayer insulating film is separated from a side surface of the first conductive film in the first contact hole so that a part of an upper surface of the first conductive film is exposed; In the step (p), in the first contact hole, the side surfaces of the first insulating film and the second insulating film are separated from the side surface of the first conductive film so that a part of the lower surface of the first conductive film is exposed; In the step (p), a side surface of the interlayer insulating film is separated from a side surface of the second impurity region in the second contact hole so that a part of an upper surface of the second impurity region is exposed; A method for manufacturing a semiconductor device, wherein a first distance from a lower surface of the first conductive film to a bottom of the first contact hole is longer than a second distance from a side surface of the first conductive film to a side surface of the interlayer insulating film.

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