Semiconductor device and manufacturing method thereof

Abstract

To improve reliability of a semiconductor device.SOLUTION: A gate electrode GE2 is adjacent to a tip end SLb of a semiconductor layer SL of an active region AcN1 in a Y direction so that a projection distance L1 of a tip end GE2b, projected from the semiconductor layer SL of the active region AcN1 in an X direction, becomes 0 or more. The tip end SLb of the gate electrode GE2 is covered with a side wall spacer SW. An epitaxial layer EP and a gate electrode GE2 are connected to each other by a shared contact plug (SPG1) formed over the epitaxial layer EP, the side wall spacer SW, and the gate electrode GE2.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, for example, a semiconductor device using an SOI substrate and a manufacturing method thereof. [Background technology]

[0002] One technology for low-power semiconductor devices is to form a metal-insulator semiconductor field-effect transistor (MISFET) on a silicon-on-insulator (SOI) substrate, which has a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer. A MISFET formed on this SOI substrate can reduce the parasitic capacitance caused by the diffusion region formed in the semiconductor layer. This can improve the operating speed of the MISFET and reduce power consumption.

[0003] For example, Patent Document 1 discloses a technique in which a plurality of MISFETs are formed on an SOI substrate and an SRAM (Static Random Access Memory) circuit is configured using these MISFETs. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-236097 Summary of the Invention [Problem to be solved by the invention]

[0005] One problem with SOI substrates is that when a plug is formed on the semiconductor layer, it may end up on the boundary between the semiconductor layer and the isolation region. In this case, the plug penetrates the insulating layer, reaches the inside of the isolation region, and comes into contact with the semiconductor substrate. This causes a leakage defect, where the semiconductor layer and the semiconductor substrate become electrically connected.

[0006] To prevent such leakage defects, Patent Document 1 discloses a technique for forming an epitaxial layer on a semiconductor layer so that it protrudes from the side surfaces of the semiconductor layer, thereby preventing the plug from contacting the semiconductor substrate even if the plug reaches the inside of the isolation region.

[0007] However, the ease of growth of an epitaxial layer is affected by the crystal orientation of the underlying semiconductor layer. Therefore, it is difficult to form an epitaxial layer with a uniform width over the entire side surface of the semiconductor layer. That is, there is a risk that the plug will come into contact with the semiconductor substrate in areas where the epitaxial layer is thin. The main objective of this application is to provide a technology that can prevent the plug from coming into contact with the semiconductor substrate, even if such a problem occurs, thereby improving the reliability of semiconductor devices.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] A brief summary of a representative embodiment of the present invention will be given below.

[0010] A semiconductor device according to one embodiment includes an SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer; an element isolation portion that penetrates the semiconductor layer and the insulating layer and has a bottom located inside the semiconductor substrate; a first active region in the SOI substrate that is partitioned by the element isolation portion and extends in a first direction in a planar view; a second active region in the SOI substrate that is partitioned by the element isolation portion, extends in the first direction, and is adjacent to the first active region via the element isolation portion in a second direction perpendicular to the first direction in a planar view; a first MISFET formed in the first active region; and a second MISFET formed in the second active region. The first MISFET includes a first gate insulating film formed on the semiconductor layer in the first active region, a first gate electrode formed on the first gate insulating film and on the element isolation portion so as to extend in the second direction, first sidewall spacers formed on side surfaces of the first gate electrode, a first channel region in the semiconductor layer in the first active region located below the first gate electrode, and a first epitaxial layer formed on the semiconductor layer located adjacent to the first channel region. The second MISFET includes a second gate insulating film formed on the semiconductor layer in the second active region, a second gate electrode formed on the second gate insulating film and on the element isolation portion so as to extend in the second direction, second sidewall spacers formed on side surfaces of the second gate electrode, a second channel region in the semiconductor layer in the second active region located below the second gate electrode, and a second epitaxial layer formed on the semiconductor layer located adjacent to the second channel region.Furthermore, the semiconductor layer of the first active region has a first end including a first tip farthest from the first gate electrode in a third direction from the first gate electrode to the second gate electrode in the first direction, the second gate electrode has a second end including a second tip farthest from the second active region in a fourth direction from the second active region to the first active region in the second direction, the second gate electrode is adjacent to the first tip of the semiconductor layer of the first active region in the first direction so that a protrusion distance of the second tip protruding from the semiconductor layer of the first active region in the second direction is 0 or more, the first tip of the semiconductor layer of the first active region is covered by the second sidewall spacer, and the first epitaxial layer and the second gate electrode are connected to each other by a first shared contact plug formed across the first epitaxial layer, the second sidewall spacer, and the second gate electrode.

[0011] A semiconductor device according to one embodiment includes an SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer; an element isolation portion that penetrates the semiconductor layer and the insulating layer and has a bottom located inside the semiconductor substrate; a first active region in the SOI substrate that is partitioned by the element isolation portion and extends in a first direction in a planar view; a second active region in the SOI substrate that is partitioned by the element isolation portion, extends in the first direction, and is adjacent to the first active region via the element isolation portion in a second direction perpendicular to the first direction in a planar view; a first MISFET formed in the first active region; and a second MISFET formed in the second active region. The first MISFET includes a first gate insulating film formed on the semiconductor layer in the first active region, a first gate electrode formed on the first gate insulating film and on the element isolation portion so as to extend in the second direction, first sidewall spacers formed on side surfaces of the first gate electrode, a first channel region in the semiconductor layer in the first active region located below the first gate electrode, and a first epitaxial layer formed on the semiconductor layer located adjacent to the first channel region. The second MISFET includes a second gate insulating film formed on the semiconductor layer in the second active region, a second gate electrode formed on the second gate insulating film and on the element isolation portion so as to extend in the second direction, second sidewall spacers formed on side surfaces of the second gate electrode, a second channel region in the semiconductor layer in the second active region located below the second gate electrode, and a second epitaxial layer formed on the semiconductor layer located adjacent to the second channel region. Furthermore, the second gate electrode and the second sidewall spacer are further located on the semiconductor layer of the first active region, and the first epitaxial layer and the second gate electrode are connected to each other by a first shared contact plug formed across the first epitaxial layer, the second sidewall spacer, and the second gate electrode.

[0012] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: (a) preparing an SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer; (b) forming an isolation portion that penetrates the semiconductor layer and the insulating layer and has a bottom located inside the semiconductor substrate, thereby forming a first active region in the SOI substrate that is partitioned by the isolation portion and extends in a first direction in a planar view; and (c) forming a first gate insulating film of a first MISFET on the semiconductor layer of the first active region and a second gate insulating film of a second MISFET on the semiconductor layer of the second active region; (d) forming a first conductive film on the first gate insulating film, the second gate insulating film, and the device isolation portion; (e) forming a first insulating film on the first conductive film; and (f) patterning the first insulating film and the first conductive film. (g) forming first dummy sidewall spacers on side surfaces of the first gate electrode and forming second dummy sidewall spacers on side surfaces of the second gate electrode; (h) forming a first epitaxial layer on the semiconductor layer of the first active region exposed from the first dummy sidewall spacers and forming a second epitaxial layer on the semiconductor layer of the second active region exposed from the second dummy sidewall spacers; (i) after the step (h), removing the first cap film, the second cap film, the first dummy sidewall spacers and the second dummy sidewall spacers; (j) after the step (i), forming first sidewall spacers on side surfaces of the first gate electrode and forming a second dummy sidewall spacer on the semiconductor layer of the second active region exposed from the second dummy sidewall spacers;(k) forming an interlayer insulating film on the first epitaxial layer, the second epitaxial layer, and the element isolation portion so as to cover the first gate electrode, the first sidewall spacer, the second gate electrode, and the second sidewall spacer; (l) forming a first shared contact hole in the interlayer insulating film, the first shared contact hole reaching the first epitaxial layer and the second gate electrode, and a second shared contact hole reaching the second epitaxial layer and the first gate electrode; and (m) forming a first shared contact plug in the first shared contact hole and a second shared contact plug in the second shared contact hole. Here, the first gate electrode is formed on the first gate insulating film and the element isolation portion so as to extend in the second direction, the second gate electrode is formed on the second gate insulating film and the element isolation portion so as to extend in the second direction, the semiconductor layer in the first active region has a first end including a first tip farthest from the first gate electrode in a third direction from the first gate electrode to the second gate electrode in the first direction, the semiconductor layer in the second active region has a third end including a third tip farthest from the second gate electrode in a fifth direction from the second gate electrode to the first gate electrode in the first direction, the first gate electrode has a fourth end including a fourth tip farthest from the first active region in a sixth direction from the first active region to the second active region in the second direction, and the second gate electrode has a second end including a second tip farthest from the second active region in a fourth direction from the second active region to the first active region in the second direction. the second gate electrode is adjacent to the first tip of the semiconductor layer of the first active region in the first direction so that a protrusion distance of the second tip protruding from the semiconductor layer of the first active region in the second direction is 0 or more, the first tip of the semiconductor layer of the first active region is covered by the second sidewall spacer, and the first gate electrodethe fourth tip of the second active region is adjacent to the third tip of the semiconductor layer of the second active region in the first direction so that a protrusion distance of the fourth tip protruding from the semiconductor layer of the second active region in the second direction is 0 or more, the third tip of the semiconductor layer of the second active region is covered by the first sidewall spacer, the first shared contact plug is formed across the first epitaxial layer, the second sidewall spacer and the second gate electrode, and the second shared contact plug is formed across the second epitaxial layer, the first sidewall spacer and the first gate electrode. [Effects of the Invention]

[0013] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a circuit diagram showing a memory cell of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view showing a memory cell of a semiconductor device according to a first embodiment. [Figure 3] 1 is a plan view showing a part of a memory cell of a semiconductor device according to a first embodiment. [Figure 4] 1 is a cross-sectional view showing a part of a memory cell of a semiconductor device in a first embodiment. [Figure 5] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 6] 6A to 6C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. 5. [Figure 7] 7A to 7C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. 6. [Figure 8] 8 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 7. [Figure 9] 9 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 8. [Figure 10] 10A to 10C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. [Figure 11] 11A to 11C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. [Figure 12] 12 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 11. [Figure 13] FIG. 10 is a plan view showing a part of a memory cell of a semiconductor device according to a second embodiment. [Figure 14] FIG. 10 is a cross-sectional view showing a part of a memory cell of a semiconductor device in a second embodiment. [Figure 15] 10 is a plan view showing a part of a memory cell of a semiconductor device according to Modification 1. FIG. [Figure 16] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to Modification 2. [Figure 17] 17A to 17C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. 16. [Figure 18] 18 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 17. [Figure 19] 19 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 18. [Figure 20] 19A to 19C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. [Figure 21] 21 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 20. [Figure 22] 1 is a plan view showing a part of a memory cell of a semiconductor device in Study Example 1. FIG. [Figure 23] 1 is a cross-sectional view showing a part of a memory cell of a semiconductor device in Study Example 1. FIG. [Figure 24] 10 is a plan view showing a part of a memory cell of a semiconductor device in study example 2. FIG. [Figure 25] 10 is a cross-sectional view showing a part of a memory cell of a semiconductor device in Study Example 2. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0016] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the vertical, height, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that the surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0017] (Embodiment 1) <Structure of semiconductor device> A semiconductor device according to a first embodiment will be described below with reference to FIGS. 1 to 4. The semiconductor device includes an SRAM circuit. The SRAM circuit is configured to include a plurality of memory cells MC as shown in FIGS. 1 and 2. FIG. 1 is a circuit diagram showing a memory cell MC. FIG. 2 is a plan view showing a memory cell MC.

[0018] 1, a memory cell MC is arranged at the intersection of a pair of bit lines BL, / (bar)BL and a word line WL. This memory cell MC has a pair of load transistors (load MISFETs) Lo1, Lo2, a pair of access transistors (transfer MISFETs) Acc1, Acc2, and a pair of driver transistors (drive MISFETs) Dr1, Dr2. The load transistors Lo1, Lo2 are p-channel MISFETs, and the access transistors Acc1, Acc2 and driver transistors Dr1, Dr2 are n-channel MISFETs.

[0019] Of the six MISFETs that make up the memory cell MC, the load transistor Lo1 and driver transistor Dr1 form a CMOS inverter, and the load transistor Lo2 and driver transistor Dr2 form another CMOS inverter. Nodes N1 and N2, which are the mutual input / output terminals of this pair of CMOS inverters, are cross-coupled to form a flip-flop circuit that serves as an information storage unit for storing one bit of information.

[0020] The connections of the six MISFETs will be explained below.

[0021] A load transistor Lo1 is connected between a power supply voltage Vdd and a node N1, a driver transistor Dr1 is connected between the node N1 and a reference voltage Vss, and the gate electrodes of the load transistor Lo1 and the driver transistor Dr1 are connected to a node N2. A load transistor Lo2 is connected between a power supply voltage Vdd and a node N2, and a driver transistor Dr2 is connected between the node N2 and a reference voltage Vss, and the gate electrodes of the load transistor Lo2 and the driver transistor Dr2 are connected to the node N1.

[0022] An access transistor Acc1 is connected between a bit line BL and a node N1, and an access transistor Acc2 is connected between a bit line / BL and a node N2. The gate electrodes of the access transistors Acc1 and Acc2 are connected to a word line WL.

[0023] The relationship between the circuit diagram of FIG. 1 and each plug shown in FIG. 2 will be explained.

[0024] The plug PGa is provided between the driver transistor Dr1 and the reference voltage Vss, the plug PGb is provided between the driver transistor Dr1 and the access transistor Acc1, the plug PGc is provided between the access transistor Acc1 and the bit line BL, and the plug PGd is provided between the load transistor Lo1 and the power supply voltage Vdd.

[0025] The plug PGh is provided between the driver transistor Dr2 and the reference voltage Vss, the plug PGg is provided between the driver transistor Dr2 and the access transistor Acc2, the plug PGf is provided between the access transistor Acc2 and the bit line / BL, and the plug PGe is provided between the load transistor Lo2 and the power supply voltage Vdd.

[0026] The shared contact plug (plug) SPG1 is formed across the gate electrodes GE2 of the load transistor Lo2 and the driver transistor Dr2 and the drain region of the load transistor Lo1, and is electrically connected to the plug PGb by a wiring (not shown). The shared contact plug (plug) SPG2 is formed across the gate electrodes GE1 of the load transistor Lo1 and the driver transistor Dr1 and the drain region of the load transistor Lo2, and is electrically connected to the plug PGg by a wiring (not shown).

[0027] One plug PGw is connected to the gate electrode GE3 of the access transistor Acc1 and is provided between the access transistor Acc1 and the word line WL, while the other plug PGw is connected to the gate electrode GE4 of the access transistor Acc2 and is provided between the access transistor Acc2 and the word line WL.

[0028] The six MISFETs are formed on an SOI substrate 10 having a semiconductor substrate SUB, an insulating layer BOX, and a semiconductor layer SL. The SOI substrate 10 is partitioned into a plurality of active regions by element isolation portions STI. In the memory cell MC, the SOI substrate 10 is partitioned into active regions AcP1, AcP2, AcN1, and AcN2. The active regions AcP1, AcP2, AcN1, and AcN2 each extend in the Y direction and are adjacent to each other in the X direction via the element isolation portions STI. In the X direction, the active region AcN1 is adjacent to the active region AcN2 and the active region AcP1, and the active region AcN2 is adjacent to the active region AcN1 and the active region AcP2. These active regions AcP1, AcP2, AcN1, and AcN2 are folded back to form a memory cell array consisting of a plurality of memory cells MC.

[0029] In addition, since the thickness of the semiconductor layer SL is thin, approximately 10 nm, an epitaxial layer EP is formed on the semiconductor layer SL. A p-type well region is formed in the semiconductor substrate SUB in the active regions AcP1 and AcP2, and an n-type well region NW (described later) is formed in the semiconductor substrate SUB in the active regions AcN1 and AcN2.

[0030] The load transistor Lo1 is formed in the active region AcN1, the load transistor Lo2 is formed in the active region AcN2, the access transistor Acc1 and the driver transistor Dr1 are formed in the active region AcP1, and the access transistor Acc2 and the driver transistor Dr2 are formed in the active region AcP2.

[0031] A back gate voltage Vbg1 is applied to the n-type well regions NW in the active regions AcN1 and AcN2, and a back gate voltage Vbg2 different from the back gate voltage Vbg1 is applied to the p-type well regions in the active regions AcP1 and AcP2.

[0032] The threshold of the load transistor Lo1 is controlled by the voltage applied to the gate electrode GE1 and the back gate voltage Vbg1. The threshold of the load transistor Lo2 is controlled by the voltage applied to the gate electrode GE2 and the back gate voltage Vbg1. The threshold of the access transistor Acc1 is controlled by the voltage applied to the gate electrode GE3 and the back gate voltage Vbg2. The threshold of the access transistor Acc2 is controlled by the voltage applied to the gate electrode GE4 and the back gate voltage Vbg2. The threshold of the driver transistor Dr1 is controlled by the voltage applied to the gate electrode GE1 and the back gate voltage Vbg2. The threshold of the driver transistor Dr2 is controlled by the voltage applied to the gate electrode GE2 and the back gate voltage Vbg2.

[0033] <Memory cell MC structure> Fig. 3 is an enlarged plan view of the main part around the load transistors Lo1 and Lo2 shown in Fig. 2. Fig. 4 is a cross-sectional view taken along line AA shown in Fig. 3. Note that the cross-sectional view taken along line BB shown in Fig. 3 is almost the same as Fig. 4, so hereinafter, only the cross-sectional view taken along line AA will be described.

[0034] 4 will mainly describe the cross-sectional structure around the load transistor Lo1 and shared contact plug SPG1, but the cross-sectional structure around the load transistor Lo2 and shared contact plug SPG2 is the same as that in FIG. 4 except for different reference numerals. The load transistors Lo1 and Lo2 are p-type MISFETs, while the access transistors Acc1 and Acc2 and the driver transistors Dr1 and Dr2 are n-type MISFETs. Therefore, the cross-sectional structures of the access transistors Acc1 and Acc2 and the driver transistors Dr1 and Dr2 have the opposite conductivity types to those shown in FIG. 4.

[0035] As shown in FIG. 4, the SOI substrate 10 has a semiconductor substrate SUB which is a support substrate, an insulating layer BOX formed on the semiconductor substrate SUB, and a semiconductor layer SL formed on the insulating layer BOX.

[0036] The semiconductor substrate SUB is made of, for example, p-type single crystal silicon. The insulating layer BOX is made of, for example, silicon oxide. The insulating layer BOX has a thickness of, for example, 10 nm to 20 nm. The semiconductor layer SL is made of, for example, single crystal silicon. The semiconductor layer SL has a thickness of, for example, 10 nm to 20 nm. The semiconductor layer SL is an intrinsic semiconductor layer into which no n-type or p-type impurities have been introduced by ion implantation or the like. Even if p-type impurities have been introduced into the semiconductor layer SL, the impurity concentration is 1×10 13 / cm 3 The following is the result.

[0037] A plurality of element isolation portions STI are formed in the SOI substrate 10. The element isolation portions STI penetrate the semiconductor layer SL and the insulating layer BOX. The bottoms of the element isolation portions STI are located inside the semiconductor substrate SUB. The element isolation portions STI are composed of trenches formed in the SOI substrate 10 and insulating films embedded in the trenches. The insulating films are, for example, silicon oxide films.

[0038] An n-type well region DNW is formed in the semiconductor substrate SUB. An n-type well region NW is formed in the well region DNW. Although not shown, a well region DNW is also formed in the semiconductor substrate SUB in the active regions AcP1 and AcP2, and a p-type well region is formed in the well region DNW. The well region DNW electrically separates the well region NW from other well regions.

[0039] A gate insulating film GI1 is formed on the semiconductor layer SL. A gate electrode GE1 is formed on the gate insulating film GI1. The gate insulating film GI1 is, for example, a silicon oxide film. The gate electrode GE1 is a conductive film, for example, a polycrystalline silicon film doped with p-type impurities. A portion of the semiconductor layer SL in the active region AcN1 that is located below the gate electrode GE1 becomes a channel region CN1 of the load transistor Lo1.

[0040] Sidewall spacers SW are formed on the side surfaces of the gate electrode GE1. The sidewall spacers SW are made of an insulating film, such as a stacked film of a silicon oxide film and a silicon nitride film formed on the silicon oxide film. Extension regions EX, which are low-concentration p-type impurity regions, are formed in the semiconductor layer SL below the sidewall spacers SW.

[0041] 3, the gate electrodes GE1 and GE2 are also formed on the element isolation parts STI so as to extend in the X direction. In addition, sidewall spacers SW formed on the respective side surfaces of the gate electrodes GE1 and GE2 also extend in the X direction.

[0042] The semiconductor layer SL of the active regions AcN1 and AcN2 each has an end SLa including a tip SLb. The end SLa of the semiconductor layer SL is rounded like a semicircle and tapers toward the tip SLb. That is, the width of the end SLa (i.e., the length of the end SLa in the X direction) is narrower than the width of the channel region CN1 (the width of the semiconductor layer SL located under the gate electrode GE1 or GE2).

[0043] In the first embodiment, the gate electrode GE2 is adjacent to the tip SLb of the semiconductor layer SL of the active region AcN1 in the Y direction, and the gate electrode GE1 is adjacent to the tip SLb of the semiconductor layer SL of the active region AcN2 in the Y direction.

[0044] An epitaxial layer EP is formed on the semiconductor layer SL located adjacent to the channel region CN1. A diffusion region PD, which is a p-type impurity region with a higher concentration than the extension region EX, is formed in the epitaxial layer EP and the semiconductor layer SL. The extension region EX and the diffusion region PD form the source region or drain region of the load transistor Lo1. Note that although the semiconductor layer SL and the epitaxial layer EP are actually integrated, they are shown separately here for ease of understanding.

[0045] A silicide layer SI is formed on the gate electrode GE1 and the epitaxial layer EP. The silicide layer SI is made of, for example, nickel silicide or cobalt silicide.

[0046] An interlayer insulating film IL is formed on the epitaxial layer EP and the element isolation parts STI so as to cover the gate electrode GE1 and the sidewall spacers SW. The interlayer insulating film IL is, for example, a silicon oxide film.

[0047] A shared contact hole SCH1 is formed in the interlayer insulating film IL, reaching the epitaxial layer EP and gate electrode GE2 of the active region AcN1. A shared contact plug SPG1 is formed in the shared contact hole SCH1. A shared contact hole is also formed in the active region AcN2, reaching the epitaxial layer EP and gate electrode GE1, and a shared contact plug SPG2 is formed in the shared contact hole of the active region AcN2.

[0048] The shared contact plugs SPG1 and SPG2 are formed of the same material and in the same manufacturing process as the plugs PGa to PGh and PGw shown in Fig. 2, and are, for example, a laminated film of a barrier metal film and a tungsten film formed on the barrier metal film. The barrier metal film is, for example, a titanium film or a titanium nitride film, or a laminated film thereof.

[0049] The shared contact plug SPG1 is formed across the epitaxial layer EP, sidewall spacer SW, and gate electrode GE2 of the active region AcN1, and the epitaxial layer EP of the active region AcN1 and the gate electrode GE2 are connected by the shared contact plug SPG1. The shared contact plug SPG2 is formed across the epitaxial layer EP, sidewall spacer SW, and gate electrode GE1 of the active region AcN2, and the epitaxial layer EP of the active region AcN2 and the gate electrode GE1 are connected by the shared contact plug SPG2.

[0050] <Problems in the study example and main features of the first embodiment> 22 to 25, the memory cells MC in Study Examples 1 and 2 studied by the inventors of the present application and their problems will be described below. Fig. 22 and Fig. 23 show the memory cells MC in Study Example 1, and Fig. 24 and Fig. 25 show the memory cells MC in Study Example 2.

[0051] 22 and 23, in Study Example 1, the epitaxial layer EP is formed so as to protrude from the boundary (see FIG. 23) between the semiconductor layer SL and the element isolation part STI toward the element isolation part STI. In other words, a part of the epitaxial layer EP is formed also on the element isolation part STI, and a part of the epitaxial layer EP overlaps the element isolation part STI in plan view. The protrusion amount is, for example, 5 nm to 10 nm. Such a configuration is also the same in Embodiment 1.

[0052] In order to form the epitaxial layer EP in this manner, the technique disclosed in Patent Document 1 can be used. The plane orientation of the semiconductor layer SL is (100), and the channel orientation is <100> This makes it easier to grow the epitaxial layer EP toward the element isolation part STI side.

[0053] In Study Example 1, since the epitaxial layer EP is formed as described above, the epitaxial layer EP can fulfill the role of an overhang. For example, as shown in FIG. 23, even when the shared contact plug SPG1 is located on the boundary between the semiconductor layer SL and the element isolation part STI with a certain distance between the semiconductor layer SL and the gate electrode GE2 in the active region AcN1, this boundary is covered with a part (the overhang-shaped part) of the epitaxial layer EP. Therefore, the shared contact plug SPG1 does not contact the semiconductor substrate SUB. This makes it possible to suppress a leakage defect in which the semiconductor layer SL and the semiconductor substrate SUB are brought into a conductive state.

[0054] However, according to the study of the present inventors, it has been found that when the end of the semiconductor layer SL is rounded, the epitaxial layer EP does not grow sufficiently at the rounded portion, resulting in a narrow width of the epitaxial layer EP or no epitaxial layer EP being formed. In FIG. 22 , such a portion is illustrated as a thin-film portion 20. If a shared contact plug SPG1 is formed above the thin-film portion 20, the above-mentioned leakage defect is likely to occur.

[0055] In Study Example 2 shown in FIGS. 24 and 25 , the gate electrode GE2 is positioned closer to the semiconductor layer SL in the active region AcN1 than in Study Example 1, and sidewall spacers SW formed on the side surfaces of the gate electrode GE2 attempt to cover the boundary between the semiconductor layer SL and the element isolation portion STI. Here, the end portion SLa of the semiconductor layer SL is rounded, and therefore, as described as the thin-film portion 20, the width of the epitaxial layer EP at the end portion SLa is narrowed. Also, as shown in FIG. 24 , in Study Example 2, the tip GE2b of the gate electrode GE2 is recessed from the semiconductor layer SL in the active region AcN1 in the X direction from the active region AcN1 to the active region AcN2. Also, the tip GE1b of the gate electrode GE1 is recessed from the semiconductor layer SL in the active region AcN2 in the X direction from the active region AcN2 to the active region AcN1. In FIG. 24 , these recession amounts are illustrated as recession distances L0, and when defined using a protrusion distance L1 (described later), the relationship "L1<0" is satisfied.

[0056] On the other hand, the ends GE1a and GE2a of the gate electrodes GE1 and GE2 are also rounded, like semicircles. The semiconductor layer SL and the gate electrodes GE1 and GE2 are rectangular in design, but it is known that when patterning is performed using photolithography during the manufacturing process, the corners of the workpiece tend to be rounded. The roundness of the semiconductor layer SL and the gate electrodes GE1 and GE2 results from this manufacturing process.

[0057] The sidewall spacers SW are formed with a substantially uniform width along the side surfaces of the gate electrodes GE1 and GE2. Therefore, at the ends GE1a and GE2a, the sidewall spacers SW are gradually separated from the semiconductor layer SL. That is, there are portions of the end SLa of the semiconductor layer SL that are exposed from the sidewall spacers SW.

[0058] Due to these circumstances, when the end SLa of the semiconductor layer SL and the ends GE1a and GE2a of the gate electrodes GE1 and GE2 approach each other, there are likely to be portions where the width of the epitaxial layer EP is very narrow and where the boundary between the semiconductor layer SL and the element isolation portion STI is not covered by the sidewall spacer SW. The line BB in Figure 24 illustrates such a portion. Figure 25 is a cross-sectional view taken along the line BB in Figure 24.

[0059] As shown in FIG. 25, when the shared contact plug SPG1 is formed, the shared contact plug SPG1 contacts both the epitaxial layer EP and the semiconductor substrate SUB, causing a leakage defect.

[0060] In the first embodiment, measures are taken to solve the problems of the study examples 1 and 2. The main features of the first embodiment will be described below with reference to FIG.

[0061] 3, the gate electrode GE1 has an end GE1a including a tip GE1b, and the gate electrode GE2 has an end GE2a including a tip GE2b. Also in the first embodiment, due to reasons arising from the manufacturing process described above, the end GE1a of the gate electrode GE1 is rounded like a semicircle and tapers toward the tip GE1b. That is, the width of the end GE1a (i.e., the length of the end GE1a in the Y direction) is narrower than the width of the gate electrode GE1 located on the channel region CN1 (the width of the gate electrode GE1 located on the semiconductor layer SL of the active region AcN1). Similarly, the end GE2a of the gate electrode GE2 is rounded like a semicircle and tapers toward the tip GE2b. That is, the width of the end GE2a (i.e., the length of the end GE2a in the Y direction) is narrower than the width of the gate electrode GE2 located on the channel region CN1 (the width of the gate electrode GE2 located on the semiconductor layer SL of the active region AcN2).

[0062] In the first embodiment, the tip GE2b of the gate electrode GE2 protrudes from the semiconductor layer SL of the active region AcN1 in the X direction from the active region AcN2 to the active region AcN1. That is, the relationship "L1>0" is satisfied. Also, the tip GE1b of the gate electrode GE1 protrudes from the semiconductor layer SL of the active region AcN2 in the X direction from the active region AcN1 to the active region AcN2. That is, the relationship "L1>0" is satisfied. In FIG. 3, the amount of protrusion is illustrated as a protrusion distance L1.

[0063] Hereinafter, the structures related to the shared contact plug SPG1 (semiconductor layer SL of the active region AcN1, gate electrode GE2, etc.) will be described as a representative, but the same applies to the structures related to the shared contact plug SPG2 (semiconductor layer SL of the active region AcN2, gate electrode GE1, etc.).

[0064] The longer (larger) the protrusion distance L1, the farther the rounded end GE2a of the gate electrode GE2 is from the end SLa of the semiconductor layer SL. Therefore, the tip SLb of the semiconductor layer SL is covered by the sidewall spacer SW formed on the side surface of the gate electrode GE2, and the end SLa of the semiconductor layer SL is also covered by this sidewall spacer SW. Therefore, the cross-sectional view taken along line BB in FIG. 3 is substantially the same as the cross-sectional view taken along line AA in FIG. 3 (FIG. 4).

[0065] Therefore, even if there is a portion where the width of the epitaxial layer EP is very narrow, such as the thin-film portion 20, that portion can be easily covered with the sidewall spacer SW. The boundary between the end portion SLa of the semiconductor layer SL and the element isolation portion STI is covered with the overhanging epitaxial layer EP or the sidewall spacer SW. Moreover, as described above, even in portions other than the end portion SLa, a portion of the epitaxial layer EP is also formed on the element isolation portion STI. That is, the entire boundary between the semiconductor layer SL and the element isolation portion STI is covered with at least one of the epitaxial layer EP or the sidewall spacer SW.

[0066] For this reason, even if the formation position of the shared contact plug SPG1 is misaligned, the shared contact plug SPG1 will not come into contact with the semiconductor substrate SUB. Therefore, leakage defects in which the semiconductor layer SL and the semiconductor substrate SUB are brought into a conductive state can be suppressed, thereby improving the reliability of the semiconductor device.

[0067] The gate electrode GE2 may be formed so that the tip GE2b of the gate electrode GE2 is located in the same position in the X direction as the edge ED farthest from the active region AcN2 (i.e., the edge ED located on the left side in FIG. 3) of the two edges (sides) ED of the semiconductor layer SL of the active region AcN1. That is, the relationship "L1=0" may be satisfied. However, from the viewpoint of reliably covering the end SLa of the semiconductor layer SL, it is preferable that the protrusion distance L1 is set so that the entire end GE2a of the gate electrode GE2 protrudes in the X direction from the semiconductor layer SL of the active region AcN1, as shown in FIG. 3. That is, it is preferable to satisfy the relationship "L1>0".

[0068] On the other hand, referring to FIG. 2, if the protrusion distance L1 is made too long, it will affect the distance L2 between the gate electrode GE2 and the gate electrode GE3. Increasing the protrusion distance L1 to maintain the distance L2 will impair the miniaturization of the memory cell MC. Therefore, the distance L2 must be maintained at at least the minimum processing dimension or longer. For example, if the minimum processing dimension is 40 nm to 70 nm, the distance L2 is set to 40 nm to 70 nm or longer.

[0069] Therefore, it is preferable to set the protruding distance L1 as long as possible, provided that the distance L2 is within the above range.

[0070] <Method of manufacturing a semiconductor device> A method for manufacturing the semiconductor device according to the first embodiment will be described below with reference to FIGS.

[0071] First, as shown in FIG. 5, an SOI substrate 10 is prepared, which has a semiconductor substrate SUB, an insulating layer BOX formed on the semiconductor substrate SUB, and a semiconductor layer SL formed on the insulating layer BOX.

[0072] An example of a process for preparing such an SOI substrate is described below. The SOI substrate can be manufactured, for example, by a bonding method. In the bonding method, for example, the surface of a first semiconductor substrate made of silicon is oxidized to form an insulating layer BOX, and then a second semiconductor substrate made of silicon is bonded to the first semiconductor substrate by pressure bonding at high temperature, and then the second semiconductor substrate is thinned. In this case, the thin film of the second semiconductor substrate remaining on the insulating layer BOX becomes the semiconductor layer SL, and the first semiconductor substrate below the insulating layer BOX becomes the semiconductor substrate SUB.

[0073] Next, an insulating film IF1 made of, for example, silicon oxide is formed on the semiconductor layer SL by, for example, a CVD (Chemical Vapor Deposition) method. The thickness of the insulating film IF1 is, for example, 10 nm to 20 nm.

[0074] Next, an element isolation portion STI is formed, which penetrates the semiconductor layer SL and the insulating layer BOX and has its bottom located inside the semiconductor substrate SUB. Specifically, first, a trench is formed that penetrates the insulating film IF1, the semiconductor layer SL, and the insulating layer BOX and reaches the semiconductor substrate SUB. Next, an insulating film such as a silicon oxide film is formed on the insulating film IF1 including the trench. Next, the insulating film located outside the trench is removed by a polishing process using a CMP (Chemical Mechanical Polishing) method. This forms an element isolation portion STI having the trench and the insulating film remaining inside the trench. Furthermore, by forming the element isolation portion STI, active regions AcP1, AcP2, AcN1, and AcN2 of the SOI substrate 10 are partitioned by the element isolation portion STI.

[0075] Thereafter, although not shown, the insulating film IF1, the semiconductor layer SL, and the insulating layer BOX are sequentially removed in regions other than the memory cells MC. In this process, the insulating film IF1 is removed in the region where the memory cells MC are to be formed.

[0076] 6, first, a gate insulating film GI1 of the load transistor Lo1 is formed on the semiconductor layer SL of the active region AcN1 by, for example, thermal oxidation. Note that, by the same manufacturing process, gate insulating films of the access transistor Acc1 and the driver transistor Dr1 are formed on the semiconductor layer SL of the active region AcP1, gate insulating films of the access transistor Acc2 and the driver transistor Dr2 are formed on the semiconductor layer SL of the active region AcP2, and a gate insulating film of the load transistor Lo2 is formed on the semiconductor layer SL of the active region AcN2.

[0077] Next, a conductive film CF1, such as a polycrystalline silicon film, is formed on the gate insulating film GI1, the other gate insulating films, and the element isolation region STI by, for example, CVD. Next, n-type or p-type impurities are introduced into the conductive film CF1 using photolithography and ion implantation. P-type impurities are introduced into the conductive film CF1 that will later become the load transistors Lo1 and Lo2, while n-type impurities are introduced into the conductive film CF1 that will later become the access transistors Acc1 and Acc2 and the driver transistors Dr1 and Dr2.

[0078] Next, the insulating film IF2 is formed on the conductive film CF1 by, for example, a CVD method. The insulating film IF2 is, for example, a silicon nitride film or a silicon oxide film.

[0079] 7, the insulating film IF2 and the conductive film CF1 are patterned. As a result, a gate electrode GE1 and a cap film CP1 located on the gate electrode GE1 are formed on the gate insulating film GI1 and the element isolation part STI. Note that the gate electrodes GE2 to GE4 and the respective cap films located on the gate electrodes GE2 to GE4 are formed by the same manufacturing process.

[0080] As shown in FIG. 8, dummy sidewall spacers DSW are formed on the side surfaces of the gate electrode GE1. Note that dummy sidewall spacers DSW are also formed on the side surfaces of the gate electrodes GE2 to GE4 by the same manufacturing process. First, a silicon nitride film, for example, is formed by, for example, a CVD method so as to cover the gate electrode GE1 and the cap film CP1. Next, the silicon nitride film is processed by performing an anisotropic etching process on the silicon nitride film, and dummy sidewall spacers DSW are formed on the side surfaces of the gate electrode GE1.

[0081] 9, an epitaxial layer EP made of, for example, single crystal silicon is formed by epitaxial growth on the semiconductor layer SL of the active region AcN1 exposed from the dummy sidewall spacer DSW. Note that, by the same manufacturing process, epitaxial layers EP are also formed on the semiconductor layer SL of the active regions AcP1, AcP2, and AcN2.

[0082] As shown in FIG. 10, first, the cap film CP1 and the dummy sidewall spacers DSW are removed by anisotropic etching. Next, p-type extension regions EX are formed in the semiconductor layer SL and epitaxial layer EP of the active region AcN1 by photolithography and ion implantation. Note that, by the same manufacturing process, p-type extension regions are formed in the semiconductor layer SL and epitaxial layer EP of the active region AcN2. Furthermore, n-type extension regions are formed in the semiconductor layer SL and epitaxial layer EP of the active regions AcP1 and AcP2.

[0083] As shown in FIG. 11, sidewall spacers SW are formed on the side surfaces of the gate electrode GE1. Note that sidewall spacers SW are also formed on the side surfaces of the gate electrodes GE2 to GE4 by the same manufacturing process. First, a silicon nitride film, for example, is formed by, for example, a CVD method so as to cover the gate electrode GE1. Next, the silicon nitride film is processed by performing an anisotropic etching process on the silicon nitride film, and sidewall spacers SW are formed on the side surfaces of the gate electrode GE1.

[0084] Here, the sidewall spacers SW are formed so as to overlap the epitaxial layer EP. Therefore, the boundary between the semiconductor layer SL and the element isolation part STI is covered by the sidewall spacers SW. By making the thickness of the silicon nitride film that becomes the sidewall spacers SW sufficiently thick, it becomes easy to position the ends of the sidewall spacers SW on the epitaxial layer EP.

[0085] As shown in Figure 12, first, a p-type diffusion region PD is formed in the semiconductor layer SL and epitaxial layer EP of the active region AcN1 using photolithography and ion implantation. The diffusion region PD is connected to the extension region EX, and the diffusion region PD and the extension region EX form the source region or drain region of the load transistor Lo1. Note that, by the same manufacturing process, a p-type diffusion region is formed in the semiconductor layer SL and epitaxial layer EP of the active region AcN2. Furthermore, n-type diffusion regions are formed in the semiconductor layer SL and epitaxial layer EP of the active regions AcP1 and AcP2.

[0086] Next, a metal film is formed to cover the gate electrode GE1 and the epitaxial layer EP. This metal film is made of, for example, cobalt, nickel, or a nickel-platinum alloy. Next, the semiconductor substrate SUB is subjected to a first heat treatment at approximately 300°C to 400°C, and then a second heat treatment at approximately 600°C to 700°C, thereby reacting the material contained in the diffusion region PD and the gate electrode GE1 with the metal film. As a result, a silicide layer SI is formed on the diffusion region PD and the gate electrode GE1. Thereafter, the unreacted metal film is removed. Note that, by the same manufacturing process, a silicide layer SI is also formed on the gate electrodes GE2 to GE4 and on the diffusion regions of the active regions AcP1, AcP2, and AcN2.

[0087] 4 is then formed through the following steps: First, an interlayer insulating film IL is formed by, for example, a CVD method on the epitaxial layer EP and the element isolation parts STI so as to cover the gate electrodes GE1 to GE4 and the sidewall spacers SW.

[0088] Next, a shared contact hole SCH1 is formed in the interlayer insulating film IL, reaching the epitaxial layer EP of the active region AcN1 and the gate electrode GE2. By the same manufacturing process, a shared contact hole is formed in the interlayer insulating film IL, reaching the epitaxial layer EP of the active region AcN2 and the gate electrode GE1. Other contact holes for burying plugs PGa-PGh and PGw are also formed in the interlayer insulating film IL.

[0089] Next, a shared contact plug SPG1 is formed in the shared contact hole SCH1. Note that by the same manufacturing process, a shared contact plug SPG2 is formed in another shared contact hole, and plugs PGa to PGh and PGw are formed in the other contact holes.

[0090] First, a barrier metal film is formed on the interlayer insulating film IL, including inside each contact hole, by, for example, sputtering or CVD. The barrier metal film is, for example, a titanium film or a titanium nitride film, or a laminate film of these. Next, a tungsten film is formed on the barrier metal film by, for example, CVD. Next, the barrier metal film and the tungsten film located outside each contact hole are removed by anisotropic etching or polishing by CMP. The barrier metal film and the tungsten film remaining in each contact hole become shared contact plugs SPG1 and SPG2 and plugs PGa to PGh and PGw.

[0091] (Embodiment 2) The semiconductor device according to the second embodiment will be described below with reference to Figures 13 and 14. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0092] In the second embodiment, an end GE2a of the gate electrode GE2 does not protrude from the semiconductor layer SL of the active region AcN1. Instead, as shown in FIGS. 13 and 14, the semiconductor layer SL, insulating layer BOX, and semiconductor substrate SUB of the active region AcN1 are extended in the Y direction more than in the first embodiment, and the gate electrode GE2 and sidewall spacers SW are also located on the semiconductor layer SL of the active region AcN1. Note that a gate insulating film GI2 of the load transistor Lo2 is formed between the gate electrode GE2 and the semiconductor layer SL of the active region AcN1.

[0093] Furthermore, the semiconductor layer SL, insulating layer BOX, and semiconductor substrate SUB of the active region AcN2 are extended in the Y direction more than in the first embodiment, and the gate electrode GE1 and sidewall spacers SW are also located on the semiconductor layer SL of the active region AcN2. Note that the gate insulating film GI1 of the load transistor Lo1 is formed between the gate electrode GE1 and the semiconductor layer SL of the active region AcN2.

[0094] In the second embodiment, the rounded end portions SLa of the semiconductor layer SL are covered by the gate electrodes GE1, GE2 or the sidewall spacers SW. Since portions where the width of the epitaxial layer EP is very narrow, such as the thin-film portions 20, are covered, the shared contact plugs SPG1, SPG2 do not come into contact with the semiconductor substrate SUB. This makes it possible to suppress leakage defects in which the semiconductor layer SL and the semiconductor substrate SUB are brought into a conductive state, thereby improving the reliability of the semiconductor device.

[0095] (Variation 1) The semiconductor device according to the first modification will be described below with reference to Fig. 15. In the first modification, the technique described in the first embodiment is applied to the technique described in the second embodiment.

[0096] As shown in FIG. 15, in the first modification, the rounded end portions SLa of the semiconductor layer SL are also covered with the gate electrodes GE1, GE2 or the sidewall spacers SW.

[0097] Furthermore, by making the gate electrode GE2 protrude from the semiconductor layer SL of the active region AcN1 ("L1>0"), the rounded end GE2a of the gate electrode GE2 can be spaced apart from the end SLa of the semiconductor layer SL. Also, by making the gate electrode GE1 protrude from the semiconductor layer SL of the active region AcN2 ("L1>0"), the rounded end GE1a of the gate electrode GE1 can be spaced apart from the end SLa of the semiconductor layer SL.

[0098] Therefore, the risk of the shared contact plugs SPG1 and SPG2 coming into contact with the semiconductor substrate SUB can be further reduced.

[0099] (Variation 2) 16 to 21, a method for manufacturing a semiconductor device according to Modification 2 will be described below. In the manufacturing method according to Modification 2, dummy sidewall spacers DSW are not used.

[0100] 16 shows a manufacturing process following that shown in FIG. 6. The insulating film IF2 and the conductive film CF1 are patterned. As a result, a gate electrode GE1 and a cap film CP1 located on the gate electrode GE1 are formed on the gate insulating film GI1 and the element isolation part STI. Note that the same manufacturing process is used to form gate electrodes GE2 to GE4 and the respective cap films located on the gate electrodes GE2 to GE4.

[0101] 17, p-type extension regions EX are formed in the semiconductor layer SL of the active region AcN1 by photolithography and ion implantation. By the same manufacturing process, p-type extension regions are formed in the semiconductor layer SL of the active region AcN2. Furthermore, n-type extension regions are formed in the semiconductor layer SL of the active regions AcP1 and AcP2.

[0102] As shown in FIG. 18, sidewall spacers SW are formed on the side surfaces of the gate electrode GE1. Note that sidewall spacers SW are also formed on the side surfaces of the gate electrodes GE2 to GE4 by the same manufacturing process. First, a silicon nitride film, for example, is formed by, for example, a CVD method so as to cover the gate electrode GE1. Next, the silicon nitride film is processed by performing an anisotropic etching process on the silicon nitride film, and sidewall spacers SW are formed on the side surfaces of the gate electrode GE1.

[0103] Here, the sidewall spacers SW are formed so as to overlap the semiconductor layers SL. Therefore, the sidewall spacers SW cover the tips SLb of the semiconductor layers SL and the ends SLa around the tips SLb. By making the thickness of the silicon nitride film that becomes the sidewall spacers SW sufficiently thick, it becomes easier to position the ends of the sidewall spacers SW on the semiconductor layers SL.

[0104] 19, an epitaxial layer EP made of, for example, single crystal silicon is formed by epitaxial growth on the semiconductor layer SL of the active region AcN1 exposed from the sidewall spacer SW. Note that, by the same manufacturing process, epitaxial layers EP are also formed on the semiconductor layer SL of the active regions AcP1, AcP2, and AcN2.

[0105] 20, a p-type diffusion region PD is formed in the semiconductor layer SL and epitaxial layer EP of the active region AcN1 by photolithography and ion implantation. By the same manufacturing process, a p-type diffusion region is formed in the semiconductor layer SL and epitaxial layer EP of the active region AcN2. Furthermore, an n-type diffusion region is formed in the semiconductor layer SL and epitaxial layer EP of the active regions AcP1 and AcP2.

[0106] Next, cap films such as the cap films CP1 and CP2 formed on the gate electrodes GE1 to GE4 are removed by anisotropic etching. Next, a silicide layer SI is formed on the gate electrodes GE1 to GE4, the diffusion region PD, and other diffusion regions in the same manner as in the first embodiment.

[0107] 21, first, an interlayer insulating film IL is formed on the epitaxial layer EP and the element isolation parts STI so as to cover the gate electrodes GE1 to GE4 and the sidewall spacers SW. Next, shared contact holes SCH1 and SCH2 and other contact holes are formed in the interlayer insulating film IL.

[0108] Next, a shared contact plug SPG1 is formed in the shared contact hole SCH1, a shared contact plug SPG2 is formed in the shared contact hole SCH2, and plugs PGa to PGh and PGw are formed in the other contact holes.

[0109] Even when the memory cell MC is formed as in Modification 2, the positional relationship between the end SLa and tip SLb of the semiconductor layer SL and the end GE1a and tip GE1b of the gate electrode GE1 is as described in Fig. 3. The manufacturing method of Modification 2 may also be applied to the second embodiment and Modification 1.

[0110] The present invention has been specifically described above based on the above embodiment, but the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0111] 10 SOI substrate 20 Thin film area Acc1, Acc2 access transistors AcN1, AcN2 active region AcP1, AcP2 active region BL, / BL bit lines BOX insulation layer CF1 conductive film CN1 channel region CP1, CP2 cap membrane Dr1, Dr2 driver transistors DNW well region DSW Dummy Sidewall Spacer ED Edge EP epitaxial layer EX Extension area GE1~GE4 gate electrodes GE1a, GE2a Ends of gate electrodes GE1b, GE2b Tip of gate electrode GI1, GI2 gate insulating film IF1, IF2 insulating film Lo1, Lo2 load transistors MC memory cell N1, N2 nodes NW well region PD diffusion area PGa~PGh, PGw plugs SCH1 Shared Contact Hole SI silicide layer SL Semiconductor layer Edge of SLa semiconductor layer SLb Semiconductor layer tip SPG1, SPG2 shared contact plug STI element isolation section SUB Semiconductor substrate SW Sidewall Spacer Vbg1, Vbg2 back gate voltage Vdd power supply voltage Vss reference voltage WL Word Line

Claims

1. an SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer; an isolation portion that penetrates the semiconductor layer and the insulating layer and has a bottom portion located inside the semiconductor substrate; a first active region in the SOI substrate, the first active region being partitioned by the element isolation portion and extending in a first direction in plan view; a second active region of the SOI substrate that is partitioned by the element isolation portion, extends in the first direction, and is adjacent to the first active region via the element isolation portion in a second direction that is orthogonal to the first direction in a plan view; a first MISFET formed in the first active region; a second MISFET formed in the second active region; Equipped with The first MISFET is a first gate insulating film formed on the semiconductor layer in the first active region; a first gate electrode formed on the first gate insulating film and the element isolation portion so as to extend in the second direction; a first sidewall spacer formed on a side surface of the first gate electrode; a first channel region located under the first gate electrode in the semiconductor layer of the first active region; a first epitaxial layer formed on the semiconductor layer adjacent to the first channel region; and The second MISFET is a second gate insulating film formed on the semiconductor layer in the second active region; a second gate electrode formed on the second gate insulating film and the element isolation portion so as to extend in the second direction; a second sidewall spacer formed on a side surface of the second gate electrode; a second channel region located under the second gate electrode in the semiconductor layer of the second active region; a second epitaxial layer formed on the semiconductor layer adjacent to the second channel region; and the semiconductor layer of the first active region has a first end portion including a first tip farthest from the first gate electrode in a third direction from the first gate electrode to the second gate electrode in the first direction; the second gate electrode has a second end including a second tip farthest from the second active region in a fourth direction from the second active region to the first active region in the second direction; a width of the first end of the semiconductor layer in the first active region is narrower than a width of the first channel region; a width of the second end of the second gate electrode is narrower than a width of the second gate electrode located on the second channel region; the second gate electrode is adjacent to the first tip of the semiconductor layer of the first active region in the first direction such that a protrusion distance of the second tip protruding from the semiconductor layer of the first active region in the second direction is equal to or greater than 0; the first tip of the semiconductor layer of the first active region is covered by the second sidewall spacer; the boundary between the first end and the element isolation portion is covered by the second sidewall spacer; the first epitaxial layer and the second gate electrode are connected to each other by a first shared contact plug formed across the first epitaxial layer, the second sidewall spacer, and the second gate electrode.

2. 2. The semiconductor device according to claim 1, a portion of each of the first epitaxial layer and the second epitaxial layer also formed on the element isolation portion;

3. 2. The semiconductor device according to claim 1, the semiconductor layer of the second active region has a third end portion including a third tip farthest from the second gate electrode in a fifth direction from the second gate electrode to the first gate electrode in the first direction, the first gate electrode has a fourth end including a fourth tip farthest from the first active region in a sixth direction from the first active region to the second active region in the second direction; the first gate electrode is adjacent to the third tip of the semiconductor layer of the second active region in the first direction such that a protrusion distance of the fourth tip protruding from the semiconductor layer of the second active region in the second direction is equal to or greater than 0; the third tip of the semiconductor layer in the second active region is covered by the first sidewall spacer; the second epitaxial layer and the first gate electrode are connected to each other by a second shared contact plug formed across the second epitaxial layer, the first sidewall spacer, and the first gate electrode.

4. 4. The semiconductor device according to claim 3, The first MISFET and the second MISFET constitute a part of an SRAM circuit.

5. 4. The semiconductor device according to claim 3, the first gate electrode is adjacent to the third end of the semiconductor layer of the second active region in the first direction such that the protrusion distance of the fourth tip protruding from the semiconductor layer of the second active region in the second direction is greater than 0; the second gate electrode is adjacent to the first end of the semiconductor layer of the first active region in the first direction so that the protrusion distance of the second tip protruding from the semiconductor layer of the first active region in the second direction is greater than 0.

6. an SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer; an isolation portion that penetrates the semiconductor layer and the insulating layer and has a bottom portion located inside the semiconductor substrate; a first active region in the SOI substrate, the first active region being partitioned by the element isolation portion and extending in a first direction in plan view; a second active region of the SOI substrate that is partitioned by the element isolation portion, extends in the first direction, and is adjacent to the first active region via the element isolation portion in a second direction that is orthogonal to the first direction in a plan view; a first MISFET formed in the first active region; a second MISFET formed in the second active region; Equipped with The first MISFET is a first gate insulating film formed on the semiconductor layer in the first active region; a first gate electrode formed on the first gate insulating film and the element isolation portion so as to extend in the second direction; a first sidewall spacer formed on a side surface of the first gate electrode; a first channel region located under the first gate electrode in the semiconductor layer of the first active region; a first epitaxial layer formed on the semiconductor layer adjacent to the first channel region; and The second MISFET is a second gate insulating film formed on the semiconductor layer in the second active region; a second gate electrode formed on the second gate insulating film and the element isolation portion so as to extend in the second direction; a second sidewall spacer formed on a side surface of the second gate electrode; a second channel region located under the second gate electrode in the semiconductor layer of the second active region; a second epitaxial layer formed on the semiconductor layer adjacent to the second channel region; and the semiconductor layer of the first active region has a first end including a first tip; the second gate electrode has a second end including a second tip; a width of the first end of the semiconductor layer in the first active region is narrower than a width of the first channel region; a width of the second end of the second gate electrode is narrower than a width of the second gate electrode located on the second channel region; the second gate electrode and the second sidewall spacer are further located on the semiconductor layer in the first active region; the first end is covered by the second gate electrode or the second sidewall spacer; the first epitaxial layer and the second gate electrode are connected to each other by a first shared contact plug formed across the first epitaxial layer, the second sidewall spacer, and the second gate electrode.

7. 7. The semiconductor device according to claim 6, a portion of each of the first epitaxial layer and the second epitaxial layer also formed on the element isolation portion;

8. 7. The semiconductor device according to claim 6, the second tip protrudes from the semiconductor layer of the first active region in the second direction, that is, in a direction from the second active region to the first active region.

9. 7. The semiconductor device according to claim 6, the first gate electrode and the first sidewall spacer are further located on the semiconductor layer in the second active region; the second epitaxial layer and the first gate electrode are connected to each other by a second shared contact plug formed across the second epitaxial layer, the first sidewall spacer, and the first gate electrode.

10. 10. The semiconductor device according to claim 9, The first MISFET and the second MISFET constitute a part of an SRAM circuit.

11. (a) preparing an SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer; (b) forming an isolation portion that penetrates the semiconductor layer and the insulating layer and has a bottom portion located inside the semiconductor substrate, thereby forming a first active region in the SOI substrate that is partitioned by the isolation portion and extends in a first direction in a plan view, and a second active region in the SOI substrate that is partitioned by the isolation portion, extends in the first direction, and is adjacent to the first active region via the isolation portion in a second direction orthogonal to the first direction in a plan view; (c) forming a first gate insulating film of a first MISFET on the semiconductor layer of the first active region and forming a second gate insulating film of a second MISFET on the semiconductor layer of the second active region; (d) forming a first conductive film on the first gate insulating film, the second gate insulating film, and the element isolation portion; (e) forming a first insulating film on the first conductive film; (f) patterning the first insulating film and the first conductive film to form a first gate electrode of the first MISFET and a first cap film located on the first gate electrode on the first gate insulating film and on the element isolation portion, and to form a second gate electrode of the second MISFET and a second cap film located on the second gate electrode on the second gate insulating film and on the element isolation portion; (g) forming first dummy sidewall spacers on side surfaces of the first gate electrode and forming second dummy sidewall spacers on side surfaces of the second gate electrode; (h) forming a first epitaxial layer on the semiconductor layer of the first active region exposed by the first dummy sidewall spacer, and forming a second epitaxial layer on the semiconductor layer of the second active region exposed by the second dummy sidewall spacer; (i) after the step (h), removing the first cap film, the second cap film, the first dummy sidewall spacer, and the second dummy sidewall spacer; (j) after the step (i), forming a first sidewall spacer on a side surface of the first gate electrode and forming a second sidewall spacer on a side surface of the second gate electrode; (k) forming an interlayer insulating film on the first epitaxial layer, the second epitaxial layer, and the element isolation portion so as to cover the first gate electrode, the first sidewall spacer, the second gate electrode, and the second sidewall spacer; (l) forming a first shared contact hole in the interlayer insulating film, the first shared contact hole reaching the first epitaxial layer and the second gate electrode, and a second shared contact hole in the interlayer insulating film, the second shared contact hole reaching the second epitaxial layer and the first gate electrode; (m) forming a first shared contact plug in the first shared contact hole and a second shared contact plug in the second shared contact hole; Equipped with the first gate electrode is formed on the first gate insulating film and the element isolation portion so as to extend in the second direction; the second gate electrode is formed on the second gate insulating film and the element isolation portion so as to extend in the second direction; the semiconductor layer of the first active region has a first end portion including a first tip farthest from the first gate electrode in a third direction from the first gate electrode to the second gate electrode in the first direction; the semiconductor layer of the second active region has a third end portion including a third tip farthest from the second gate electrode in a fifth direction from the second gate electrode to the first gate electrode in the first direction, the first gate electrode has a fourth end including a fourth tip farthest from the first active region in a sixth direction from the first active region to the second active region in the second direction; the second gate electrode has a second end including a second tip farthest from the second active region in a fourth direction from the second active region to the first active region in the second direction; a width of the first end of the semiconductor layer in the first active region is narrower than a width of the semiconductor layer in the first active region located under the first gate electrode; a width of the third end of the semiconductor layer in the second active region is narrower than a width of the semiconductor layer in the second active region located under the second gate electrode; a width of the fourth end of the first gate electrode is narrower than a width of the first gate electrode located on the semiconductor layer in the first active region; a width of the second end of the second gate electrode is narrower than a width of the second gate electrode located on the semiconductor layer in the second active region; the second gate electrode is adjacent to the first tip of the semiconductor layer of the first active region in the first direction such that a protrusion distance of the second tip protruding from the semiconductor layer of the first active region in the second direction is equal to or greater than 0; the first tip of the semiconductor layer of the first active region is covered by the second sidewall spacer; the boundary between the first end and the element isolation portion is covered by the second sidewall spacer; the first gate electrode is adjacent to the third tip of the semiconductor layer of the second active region in the first direction such that a protrusion distance of the fourth tip protruding from the semiconductor layer of the second active region in the second direction is equal to or greater than 0; the third tip of the semiconductor layer in the second active region is covered by the first sidewall spacer; a boundary between the third end and the element isolation portion is covered by the first sidewall spacer; the first shared contact plug is formed across the first epitaxial layer, the second sidewall spacer, and the second gate electrode; the second shared contact plug is formed across the second epitaxial layer, the first sidewall spacer, and the first gate electrode.

12. 12. The method for manufacturing a semiconductor device according to claim 11, a first epitaxial layer and a second epitaxial layer each partially formed on the element isolation portion;

13. 12. The method for manufacturing a semiconductor device according to claim 11, The first MISFET and the second MISFET constitute a part of an SRAM circuit.

14. 12. The method for manufacturing a semiconductor device according to claim 11, the first gate electrode is adjacent to the third end of the semiconductor layer of the second active region in the first direction such that the protrusion distance of the fourth tip protruding from the semiconductor layer of the second active region in the second direction is greater than 0; the second gate electrode is adjacent to the first end of the semiconductor layer of the first active region in the first direction so that the protrusion distance of the second tip protruding from the semiconductor layer of the first active region in the second direction is greater than 0.

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