Optical communication device

Abstract

This optical communication device comprises: a semiconductor chip (2) including an optical waveguide (8) formed in the semiconductor chip (2), and G pads (22, 26), a P pad (24), and S pads (23, 25) for outputting electric signals indicating the intensity of light propagating through the optical waveguide (8); and a semiconductor chip (3) including G pads (32, 36) and S pads (33, 35) electrically connected to the G pads (22, 26), the P pad (24), and the S pads (23, 25), the semiconductor chip (3) being connected to the semiconductor chip (2). The center point of at least some of the S pads (23, 25, 33, 35) is positioned over a straight line (L2, L3) on at least one of the chip (2) and the chip (3) parallel to a side (E1, E2) facing the other chip, and the center points of the other electrode pads are positioned over another straight line (L1, L4) farther from the side (E1, E2) than the straight line (L2, L3).

Description

[Technical Field]

[0001] The present invention relates to an optical communication device. [Background technology]

[0002] With the development of various applications such as social media and video distribution, and the construction of data centers and 5G infrastructure, the global Internet continues to expand, and the capacity of optical communication backbone lines is also steadily increasing. As a result, there is a need for optical communication devices that are capable of high-capacity transmission not only over long distances such as between regions, but also over medium distances and even short distances such as within data centers, and that are capable of high-speed optical transmission and reception at low cost.

[0003] In short-distance communications, not only optical communication devices using simple intensity direct modulation methods but also digital coherent optical communication devices are gradually coming into use. Digital coherent optical communication devices modulate both the phase and intensity of light using an optical modulator, and can significantly increase transmission capacity by also performing polarization multiplexing. Digital coherent optical communication devices enable high-capacity communications that transmit and receive data at speeds of 400 Gbps or more using a single wavelength. Such technology is described, for example, in Patent Document 1. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6740206 Summary of the Invention

[0005] FIG. 11 is a diagram showing the top surface of an optical receiver 100 described in Patent Document 1. As shown in FIG. 11, the optical receiver 100 is configured by connecting an optical semiconductor chip 110 and a semiconductor chip 130 to a package substrate 140. The optical semiconductor chip 110 includes a dual-polarization optical hybrid 111 and a dual photodiode 112, and includes anodes S1 and S2 and cathodes CA1 and CA2 as terminals. The semiconductor chip 130 includes a transimpedance amplifier 131 and includes differential input terminals T1 and T2 as terminals. In FIG. 11, electrode pads (hereinafter simply referred to as "pads") are indicated by symbols such as "S1." The optical receiver 100 includes channels C1 to C4, each including a photodiode 112 and a transimpedance amplifier 131. For ease of explanation, FIG. 11 shows the configuration of only channel C1, and does not illustrate channels C2, C3, and C4.

[0006] As shown in FIG. 11, the semiconductor chip 110 and the semiconductor chip 130 are spaced apart from each other by a side E A , E B are arranged side by side on the package substrate 140 so as to be close to each other. In order to prevent deterioration of high frequency signals between the semiconductor chip 110 and the semiconductor chip 130, the anodes S1 and S2, the cathodes CA1 and CA2, and the differential input terminals T1 and T2 are arranged on the side E A , E B It is located relatively close to

[0007] Incidentally, semiconductor chips 110 and 130 are inspected using probes before being made into chips, i.e., while they are still in the wafer state. The inspection equipment is equipped with multiple probes so that many pads can be inspected at once. Probes for multiple signals, grounds, etc., that measure high-frequency signals are often configured so that the tips of the probe needles are aligned in a straight line when they contact the pads. This configuration is widely adopted because it keeps the distance between the signal and ground of the probe constant regardless of the pad position and is easy to manufacture, maintaining the line impedance at a constant value at each pad.

[0008] From the above, in the optical receiver 100, as shown in FIG. 11, the anodes S1 and S2 and the cathodes CA1 and CA2 are arranged along a line L A The differential input terminals T1 and T2 are arranged on the semiconductor chip 110 so as to pass through the line L B The pads formed on the anodes S1 and S2 and the cathodes CA1 and CA2 are arranged so that their center points are aligned with the line L A The differential input terminals T1 and T2 are located on the line L B It is located at the top.

[0009] However, when connecting a semiconductor chip to a package substrate using a flip-chip technique, the pads must be approximately 100 μm in size. In the case of a coherent optical receiver, as shown in FIG. 11, one receiver 100 includes a four-channel dual photodiode 112 and a transimpedance amplifier 131. As devices become smaller, the spacing between channels C1, C2, etc. becomes narrower, resulting in shorter pad-to-pad distances. This can lead to problems such as parasitic capacitance being easily introduced to the signal line 121, anodes S1, S2, and differential terminals T1, T2. For example, if pads measuring 100 μm are provided on a chip with a signal and ground pitch (center-to-center spacing) of 150 μm, the pad spacing will be 50 μm. Pads spaced at such intervals will have capacitance between them. This inter-pad capacitance is added to the capacitance the pads have with respect to the substrate, affecting high-frequency characteristics. As miniaturization progresses and channel spacing becomes narrower, the demand for narrower pad spacing increases, resulting in a relative increase in the proportion of pad capacitance.

[0010] 11 is connected to the semiconductor chips 110 and 130 from above, with their principal surfaces facing each other, and an underfill having a dielectric constant of, for example, 4 is filled between the semiconductor chips 110 and 130. For this reason, flip-chip connections are particularly prone to generating capacitance, and when the transmission rate becomes 64 Gbaud or higher, the capacitance may affect the photoelectric characteristics in an optical receiver and the electro-optical frequency characteristics in an optical transmitter, potentially degrading signal quality.

[0011] The present disclosure has been made in consideration of the above points, and relates to an optical communication device that is advantageous for miniaturization because it is less likely to generate parasitic capacitance even when multiple channels on a semiconductor chip are arranged close to each other and can suppress quality degradation of high-speed signals.

[0012] In order to achieve the above object, an optical communication device according to one embodiment of the present disclosure includes: a first chip having an optical waveguide and a plurality of first electrode pads for outputting an electrical signal indicating the intensity of light propagating through the optical waveguide; and a second chip having a plurality of second electrode pads electrically connected to the first electrode pads directly or via another substrate; the first electrode pads and the second electrode pads include a plurality of signal pads for transmitting the electrical signals, and the center points of at least some of the signal pads are located on a straight line that is parallel to a side of at least one of the first chip and the second chip facing the other chip, and the center points of other first electrode pads and other second electrode pads are located on another straight line that is farther from the facing side than the straight line; In the first chip, a plurality of first electrode pads Part of teeth, the center point of the other first electrode pad is located on the straight line, and the center point of the other first electrode pad is located on another straight line parallel to the straight line; The plurality of first electrode pads whose center points are located on the straight line and the plurality of second electrode pads whose center points are located on the other straight line are The other The first electrode pads are characterized by being arranged so as to be alternately adjacent to each other.

[0013] According to the above aspects, even if multiple channels on a semiconductor chip are arranged close to each other, parasitic capacitance is unlikely to occur, and degradation of the quality of high-speed signals can be suppressed, making it possible to provide an optical communication device that is advantageous for miniaturization. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1A is a top view of the optical communication device according to the first embodiment, and FIG. 1B is a schematic cross-sectional view taken along the arrows Ib and Ib in FIG. [Figure 2] 1(a) is a top view of a partial region of the semiconductor chip shown in FIG. 1(a), and FIG. 1(b) is a top view of a partial region of the package substrate. [Figure 3] 10(a) and 10(b) are diagrams for explaining the effects of the first embodiment. [Figure 4] FIG. 10 is a top view of the optical communication device according to the second embodiment. [Figure 5] 10A is a top view of a partial region of a semiconductor chip according to the second embodiment, and FIG. 10B is a top view of a partial region A4 of a package substrate according to the second embodiment. [Figure 6] FIG. 10 is a diagram for explaining a state of on-wafer measurement according to the second embodiment. [Figure 7] 10A is a top view of a partial region of a semiconductor chip according to a third embodiment, and FIG. 10B is a top view of a partial region of a package substrate. [Figure 8] 10A is a top view of a partial region of a semiconductor chip according to another example of the third embodiment, and FIG. 10B is a top view of a partial region of a package substrate according to another example. [Figure 9] 9A is a top view of the optical communication device according to the fourth embodiment, and FIG. 9B is a schematic cross-sectional view taken along the arrows IXb and IXb in FIG. [Figure 10] 10(a) and 10(b) are top views showing the state before two semiconductor chips are overlapped in two cases of the fifth embodiment. [Figure 11] FIG. 1 is a diagram illustrating a known optical receiver. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, first to fifth embodiments of the present invention (hereinafter, the first to fifth embodiments will also be collectively referred to as "the present embodiment") will be described. The drawings used in the description of the present embodiment are intended to explain the function, configuration, arrangement of each part, and concept of the present disclosure, and do not limit the specific shape or design. Therefore, at least some of the drawings are schematic diagrams, and the aspect ratio, thickness, etc. of the configuration may not be accurately represented. Furthermore, the term "optical communication device" described below refers to having at least one function of transmitting or receiving an optical signal.

[0016] [First embodiment] FIGS. 1(a), 1(b), 2(a), and 2(b) are diagrams illustrating an optical communication device 101 according to a first embodiment of the present disclosure. FIG. 1(a) is a top view of the optical communication device 101, and FIG. 1(b) is a schematic cross-sectional view taken along the arrows Ib and Ib in FIG. 1(a), showing the cross-section and a partial end face. FIG. 2(a) is a top view of a partial region A2 of the semiconductor chip 2 and a partial region A3 of the semiconductor chip 3 shown in FIG. 1(a), and FIG. 2(b) is a top view of a partial region A4 of the package substrate 4. In this embodiment, the package substrate 4 is used as a reference, and the semiconductor chips 2 and 3 are positioned above the package substrate 4. In the optical communication device 101, the sides of the semiconductor chips 2 and 3 are considered to be the top, and the side of the package substrate 4 is considered to be the bottom.

[0017] In this embodiment, the main surface of the package substrate 4 facing the semiconductor chips 2 and 3 is referred to as the upper surface of the package substrate 4, and the back surface thereof is referred to as the lower surface. Of the main surfaces of the semiconductor chips 2 and 3, the main surface facing the package substrate 4 is referred to as the lower surface, and the back surface thereof is referred to as the upper surface. This determination of top and bottom does not depend on the mounting direction of the optical communication device 101. Furthermore, the "main surface" refers to the surface of the semiconductor chips 2 and 3 and the package substrate 4 that is clearly larger in area than the other surfaces. In FIG. 2(a), G pads and the like formed on the undersides of the semiconductor chips 2 and 3 are indicated by dashed lines, and in FIG. 2(b), the line portions formed inside the package substrate 4 are indicated by dashed lines.

[0018] The optical communication device 101 of the first embodiment is configured as an optical receiver. The optical communication device 101 is configured by connecting a plurality of pad electrodes formed on a semiconductor chip 2, which is a first chip, to a plurality of pad electrodes formed on a semiconductor chip 3, which is a second chip. The semiconductor chips 2 and 3 of the first embodiment are connected to one surface of a package substrate 4 by a flip-chip method, with metal formed between the pads of the two chips.

[0019] The semiconductor chip 2 includes an optical waveguide 8 formed therein and a plurality of first electrode pads for outputting an electrical signal indicating the intensity of light propagating through the optical waveguide 8. As shown in FIGS. 1(a) and 2(a), the first electrode pads of the first embodiment include ground pads (hereinafter referred to as "G pads") 22 and 26, signal (hereinafter referred to as "S pads") pads 23 and 25, and a power supply pad (hereinafter referred to as "P pad") 24 for supplying drive power to the dual photodiode 21. The semiconductor chip 2 further includes a dual photodiode 21 having photodiodes 21a and 21b. The dual photodiode 21 has the function of converting light input via the optical waveguide 8 into an electrical signal. The G pads 22 and 26, S pads 23 and 25, and P pad 24 function in cooperation to output an electrical signal.

[0020] As shown in FIG. 2(b), the package substrate 4 includes electrical signal lines 41, 42, 43, 44, and 45 that connect to the G pads 22 and 26, the S pads 23 and 25, and the P pad 24. The lines 41 to 45 are formed on the surface of the package substrate 40 or inside the package substrate 40. As shown in FIG. 2(b), the lines 41 and 45 that connect to the G pads 22 and 26 are provided inside the package substrate 4, while the other lines 42 and 44 are provided on the upper surface of the package substrate 4. The line 43 that connects to the P pad 24 is partially provided on the upper surface of the package substrate 4 and partially provided inside. As shown in FIG. 2(b), the upper surface of the package substrate 4 includes G pads 12a, 12b, 16a, and 16b, S pads 13a, 13b, 15a, and 15b, and P pads 16a and 16b on the package substrate 4 side.

[0021] 2(b), G pads 12a, 12b, 16a, 16b, S pads 13a, 13b, 15a, 15b, and P pads 14a, 14b are formed on the upper surface of the package substrate 4. The G pads 12a, 12b, 16a, 16b come into contact with metal or the like exposed on the upper surface of the package substrate 4.

[0022] As shown in FIGS. 1(a) and 2(a), the semiconductor chip 3, which is the second chip, has G pads 32 and 36 and S pads 33 and 35, which are second electrode pads electrically connected to the G pads 22 and 26 and the S pads 23 and 25 of the semiconductor chip 2. Furthermore, as shown in FIGS. 1(a) and 2(a), the semiconductor chip 3 has a core circuit 7 on its bottom surface. The core circuit 7 is a circuit including elements that process the signal generated by the dual photodiode 21, and may be any circuit depending on the function and specifications of the optical communication device 101. An example of the core circuit 7 is a circuit including a transimpedance amplifier that amplifies the signal.

[0023] As shown in FIG. 1(a), the semiconductor chip 3 is connected to the lines 41 and the like of the package substrate 4 together with the semiconductor chip 2 via the G pads 32 and the like. At this time, the semiconductor chips 2 and 3 are connected to the package substrate 4 so that the bottom surfaces of the regions A2 and A3 shown in FIG. 2(a) overlap the top surface of the region A4 shown in FIG. 2(b). As a result, electrical paths are formed among the G pads 22 and 12a, the lines 41, and the G pads 12b and 32. Similarly, paths are formed among the S pads 23 and 13a, the lines 42, and the S pads 13b and 33; among the P pads 24 and 14a, the lines 43, and the P pad 14b; among the S pads 25 and 15a, the lines 44, and the S pads 15b and 35; and among the G pads 26 and 16a, the lines 45, and the G pads 16b and 36.

[0024] The optical communication device 101 has a plurality of channels, each of which is configured as described above.

[0025] 1(a), in the first embodiment, the center points of the signal pads 23 and 25 among the electrode pads of the semiconductor chip 2 are located on a straight line L2 that is parallel to the side E1 of the semiconductor chip 2 that faces the semiconductor chip 3. The center points of the other first electrode pads, the G pads 22 and 26 and the P pad 24, are located on a straight line L1 that is farther from the side E1 than the straight line L2.

[0026] In this embodiment, the straight lines parallel to side E1 need only be parallel as far as they can be visually observed. Two semiconductor chips connected to one package substrate often have parallel opposing sides to shorten signal lines or to miniaturize the device. In the first embodiment, lines L1 to L4 are lines parallel to side E1, which faces the other chip, and side E2 of semiconductor chip 3. Furthermore, lines L1 to L4 are lines that lie on at least one of semiconductor chips 2 and 3.

[0027] Similarly, in the first embodiment, the center points of the signal pads 33 and 35 among the electrode pads in the semiconductor chip 3 are located on a line L3 parallel to the side E1. The center points of the G pads 32 and 36, which are the other second electrode pads, are located on a line L4 that is farther from the side E1 than the line L3. That is, in the first embodiment, the S pads are arranged closer to the side E1 than the other electrode pads in both the semiconductor chip 2 and the semiconductor chip 3. However, the first embodiment is not limited to this configuration, and the S pads may be arranged closer to the side E1 than the other electrode pads in either the semiconductor chip 2 or the semiconductor chip 3. Also, in the first embodiment, the center points of all the S pads in the semiconductor chips 2 and 3 are located on a line closer to the side E1 than the other G pads, etc. However, in the first embodiment, the center points of some of the S pads may be located on a line closer to the side E1 than the G pads, etc.

[0028] FIG. 3(a) is a diagram illustrating the effects of the above configuration, showing pads P1, P2, and P3. Pad P1 is arranged so that its center point O1 is located on line L1. Pad P3 is a virtual electrode pad arranged so that its center point O3 is located on line L1, similar to pad P1. Pad P2 is an electrode pad arranged so that its center point O2 is located on line L2, which is different from line L1. Dotted lines e1 and e2 are lines that are collinear with the opposing sides of pads P1 and P2, and the distance d1 between dotted lines e1 and e2 indicates the shortest distance between pads P1 and P3. Below, we will explain the effects of arranging virtual pad P3 by sliding it in a direction perpendicular to lines L1 and L2.

[0029] As shown in FIG. 3(a), the shortest distance d2 between the vertices v1 and v2 where pads P1 and P2 are closest to each other is the distance between the intersections of the dotted lines e1 and e2, which are diagonally intersecting the dotted lines e1 and e2. Therefore, it is clear that the shortest distance d2 is longer than the shortest distance d1, which is the distance between the intersections of the dotted lines e1 and e2 and the lines perpendicularly intersecting the dotted lines e1 and e2. Furthermore, the first embodiment is not limited to this arrangement. By arranging the center points of the electrode pads on two or more different lines parallel to side E1, the restriction on the length of the channels in the arrangement direction can be relaxed, and the distance between electrode pads whose center points are located on a single line can be increased. According to this first embodiment, the distance between the electrode pads can be increased without changing the number or size of the electrode pads arranged on the semiconductor chips 2 and 3, thereby reducing the parasitic capacitance of the electrode pads and suppressing degradation of high-speed signal quality, thereby realizing an optical communication device that is advantageous for miniaturization.

[0030] In addition to the above configuration, in the first embodiment, as shown in Figures 1(a), 2(a), and 2(b), the shape of the electrode pads in a top view is an octagon, which is an even-numbered polygon with a larger number of vertices than a rectangle. This configuration allows the first embodiment to further increase the shortest distance between electrode pads. However, the shape of the electrode pads in the first embodiment is not limited to an octagon, and the electrode pads may have a polygonal shape with more vertices.

[0031] FIG. 3(b) is a diagram illustrating the above configuration, showing the top views of an octagonal electrode pad P4 and an electrode pad P5 whose center point is located on a different line from that of the electrode pad P4. The vertices v3 and v4 in FIG. 3(b) are imaginary vertices when the electrode pads P4 and P5 are each rectangular. If the electrode pads P4 and P5 are rectangular in top view, the shortest distance between the electrode pads P4 and P5 is the distance d3 between the opposing vertices v3 and v4. However, if the electrode pads P4 and P5 are octagonal in top view, the shortest distance between the electrode pads P4 and P5 is the distance d4 between the lines closer to the center points of the electrode pads P4 and P5 than the vertices v3 and v4. In other words, electrode pads whose centers are located on different lines and whose shape is octagonal in top view can increase the spacing between the electrode pads without changing the number of electrode pads arranged on the semiconductor chips 2 and 3 or reducing the effective area of ​​the electrode pads connected to the terminals. Therefore, the first embodiment can reduce the parasitic capacitance on the electrode pads and suppress deterioration in the quality of high-speed signals, thereby realizing an optical communication device that is advantageous for miniaturization.

[0032] In particular, ultra-high-speed modulation technologies such as 100 Gbaud and 128 Gbaud are being considered for the next generation of 64 Gbaud and 16QAM systems that achieve 400 Gbps. At such high transmission rates, impedance disturbances are more likely to adversely affect signal quality. Therefore, particularly near pads, which are larger than the signal lines, the gap between the signal and ground becomes narrower, making it more likely for parasitic capacitance to occur. The first embodiment described above can be applied to such ultra-high-speed modulation technologies, reducing the effects of parasitic capacitance.

[0033] 1, in the first embodiment, the S pads 23, 33 and S pads 25, 35 that transmit and receive electrical signals are positioned closer to sides E1, E2 than the G pads 22, 32, 26, 36 and P pad 24. This configuration shortens the signal lines and increases the communication speed. Generally, in the first embodiment, it is preferable to position the G pad 22, etc. or the P pad 24 at a distance of 50 μm or more from side E1. .

[0034] [Second embodiment] Next, a second embodiment of the present disclosure will be described. An optical communication device 201 of the second embodiment aims to ensure ease of on-wafer high-frequency measurement in addition to the effect of reducing parasitic capacitance of the first embodiment.

[0035] 4, 5(a), and 5(b) are diagrams illustrating an optical communication device according to the second embodiment. FIG. 4 is a top view of an optical communication device 201 according to the second embodiment. FIG. 5(a) is a top view of a partial region A5 of a semiconductor chip 5 and a partial region A6 of a semiconductor chip 6 according to the second embodiment, respectively. FIG. 5(b) is a top view of a partial region A4 of a package substrate 4 according to the second embodiment. The semiconductor chip 5 differs from the semiconductor chip 2 only in the shape of the S-pad, and the semiconductor chip 6 differs from the semiconductor chip 3 only in the shape of the S-pad. As shown in FIGS. 4, 5(a), and 5(b), in the second embodiment, S-pads 73a and 75a, which are part of the electrode pads of the semiconductor chip 5, include measurement convex portions 73b and 75b. In the second embodiment, the measurement convex portion 73b and the S-pad 73a are collectively referred to as a convex S-pad 73. Similarly, the S pads having protrusions for measurement will be referred to as S pads with protrusions 75, 83, and 85.

[0036] Similarly, in the second embodiment, the convex S-pad 83, which is part of the electrode pad, on the semiconductor chip 6 includes an S-pad 83a and a measurement convex portion 83b, and the convex S-pad 85 includes an S-pad 85a and a measurement convex portion 85b. However, the second embodiment is not limited to providing electrode pads with measurement convex portions on both semiconductor chips 5 and 6, and either one may have an electrode pad with a measurement convex portion. Also, the second embodiment is not limited to using electrode pads with measurement convex portions only on the S-pads, as on the semiconductor chips 5 and 6, and may use electrode pads with measurement convex portions on all electrode pads or only on electrode pads related to power supply. The use of electrode pads with measurement convex portions can be determined arbitrarily depending on the specifications for on-wafer testing of semiconductor chips.

[0037] 6 is a diagram for explaining the state of on-wafer measurement, taking a semiconductor chip 6 as an example. P is a straight line connecting the tips (points) of a plurality of probe needles in contact with the electrode pads of the semiconductor chip 6. In the second embodiment, the straight line L P The lines L1 and L2 coincide with the lines parallel to the sides E1 and E2. As shown in FIG. 4, the G pads 32 and 36 and the S pads 83a and 85a are arranged so that their centers are located on different lines L3 and L4, respectively. The measuring device measures the line L P At this time, the protruding portions 83b and 85b of the S-pads 83 and 85 are aligned with the straight line L passing through the G-pads 32 and 36. P Since the G pads 32 and 36 and the measurement protrusions 83b and 85b extend upward, the G pads 32 and 36 and the measurement protrusions 83b and 85b are aligned along a straight line L P Therefore, in the second embodiment, a plurality of probe needles whose tips are arranged in a straight line are lowered onto the semiconductor chip 6, and electrical signals can be obtained from all of the G pads 32, 36 and the convex S pads 83, 85. As a result, in the second embodiment, it is possible to use ultra-high frequency probes arranged in a straight line, which are easy to design and manufacture with constant impedance, while avoiding the center points of all the electrode pads being positioned in a straight line and reducing parasitic capacitance.

[0038] The above configuration can be similarly realized in the semiconductor chip 5. That is, as shown in Fig. 4, in the semiconductor chip 5, the G pads 22, 26, the P pad 24 and the convex S pads 73, 75 are on different straight lines L1, L2, and the measurement convex portions 73b, 75b protrude from the S pads 73a, 75a toward the line L1. Therefore, a probe that lowers its probe needle on a straight line can bring the probe needle into contact with the G pads 22, 26, the P pad 24, and the measurement convex portions 73b, 75b at the same time.

[0039] [Third embodiment] Next, a third embodiment will be described. The optical transmitter of the third embodiment, like the first embodiment, is configured by connecting both semiconductor chips 2 and 3 to a package substrate 4. However, the third embodiment aims to match the delay times of the signal lines when the lengths of the signal paths differ between the S-pads 23 and 25 of the semiconductor chip 2 or between the S-pads 33 and 35 of the semiconductor chip 3. To this end, in the third embodiment, the semiconductor chip 2 has two photodiodes 21a and 21b that convert light propagating through the optical waveguide 8 into an electrical signal, and the semiconductor chip 3 has a core circuit 7 that is a circuit supplied with the electrical signals. The length of the signal path from one of the photodiodes (e.g., photodiode 21a) to the core circuit 7 via the line 42 is set equal to the length of the signal path from another of the photodiodes (e.g., photodiode 21b) to the core circuit 7 via the other line 44.

[0040] 7(a) and 7(b) are diagrams illustrating an optical communication device according to a third embodiment. FIG. 7(a) is a top view of a region A2 of a semiconductor chip 2 and a region A3 of a semiconductor chip 3 according to the third embodiment, and FIG. 7(b) is a top view of a region A4 of a package substrate 4. In the third embodiment, a P-pad is provided outside the region A2. The S-pads 23 and 25 are not aligned in a straight line. The S-pad 23 is located close to the photodiode 21a and farther from the semiconductor chip 3 than the S-pad 25. On the other hand, in the semiconductor chip 3, the S-pad 33 is located closer to the core circuit 7 than the S-pad 35. In this case, the third embodiment makes the signal path from the photodiode 21a to the core circuit 7 and the signal path from the photodiode 21b to the core circuit 7 equal in length. That is, in the examples shown in Figures 7(a) and 7(b), the lengths of the signal paths between S pads 23 and 33 and between S pad 33 and core circuit 77 are made equal to the lengths of the signal paths between S pads 25 and 35 and between S pad 35 and core circuit 77, and an equal length design is performed so that the delay times of both signals are equal.

[0041] In the example shown in FIG. 7(b), the lengths of the lines 42 and 44, which are part of the signal path, are changed based on the positions of the S-pads 23, 25, 33, and 35 on the semiconductor chips 2 and 3, resulting in an equal length design. In the example shown in FIG. 7(b), both the lines 42 and 44 have a straight shape. However, in the third embodiment, if the lines need to be extended, they may be bent, for example. Furthermore, when the lines are bent, the third embodiment may take into consideration reflection or induction of electrical signals that occur at the bent portion. In this way, the timing at which the two electrical signals generated by the photodiodes 21a and 21b are input to the core circuit 7 can be matched, thereby improving the operating accuracy of the optical communication device.

[0042] 8(a) and 8(b) are diagrams illustrating another example of the optical communication device according to the third embodiment. Fig. 8(a) is a top view of a partial region A2 of the semiconductor chip 2 and a partial region A3 of the semiconductor chip 3 according to the third embodiment, and Fig. 8(b) is a top view of a partial region A4 of the package substrate 4. In the example shown in Figs. 8(a) and 8(b), the lengths of the lines 41, 42, 43, and 44 formed on the package substrate 4 are all made equal, and the positions of the S-pads 23, 25, 33, and 35 on the semiconductor chips 2 and 3 are adjusted to make the lengths of the two signal lines equal, thereby making the delay times of both signals equal.

[0043] That is, in the third embodiment shown in FIGS. 8(a) and 8(b), the lengths of the lines 42 and 43 are made equal to make the signal delay times on the lines 42 and 43 equal. For this reason, in the third embodiment, the S-pad 23 is arranged closer to the photodiode than the S-pad 25 in the semiconductor chip 2. In addition, in the third embodiment, the S-pad 33 is arranged farther from the core circuit 7 than the S-pad 35 in the semiconductor chip 3. The electrical signal generated by the photodiode 21a is input to the core circuit 7 via the S-pad 23 and the S-pad 33. The electrical signal generated by the photodiode 21b is input to the core circuit 7 via the S-pad 25 and the S-pad 35. For this reason, with the above configuration, the length of the signal path from the photodiode 21a to the core circuit 7 and the length of the signal path from the photodiode 21b to the core circuit 7 can be designed to be equal in length.

[0044] In particular, the electrical reflection characteristics of a photodiode and a transimpedance amplifier, or an optical modulator and an open-collector modulator driver, are not low-reflection but total-reflection. Therefore, the wiring connecting these elements is susceptible to the frequency characteristics being affected by multiple electrical high-frequency reflections, and it is necessary to appropriately design the impedance and length. The third embodiment described above can also be applied to fields that require such high-precision design.

[0045] [Fourth embodiment] Next, a fourth embodiment will be described. FIG. 9(a) is a top view of an optical communication device 301 of the fourth embodiment, and FIG. 9(b) is a cross-sectional view taken along the arrows IXb and IXb. While the optical communication devices of the first to third embodiments all function as receivers, the optical communication device 301 of the fourth embodiment has multiple channels each including a Mach-Zehnder optical modulator 91 and a modulator driver chip, and functions as a transmitter. In the fourth embodiment, the core circuit 7 functions as a modulator driver. The optical communication device 301 is configured by connecting a semiconductor chip 9 including a Mach-Zehnder optical modulator 91 and a semiconductor chip 3 to a package substrate 4.

[0046] 9(a), the optical communication device 301 uses convex S-pads 73, 75, 83, and 85 equipped with measurement convex portions, as in the second embodiment. G-pads 22 and 26 are arranged so that their centers are located on a line L1. G-pads 32 and 36 are arranged so that their centers are located on a line L4.

[0047] [Fifth embodiment] Next, a fifth embodiment will be described. In contrast to the first to fourth embodiments, which all use lines to connect electrode pads, the fifth embodiment has a configuration in which semiconductor chip 2 and semiconductor chip 3 are overlapped and directly connected.

[0048] 10(a) and 10(b) are diagrams for explaining the fifth embodiment. FIGS. 10(a) and 10(b) show the top view of the semiconductor chip 2 and the semiconductor chip 3 before the regions 2A and 3A of the semiconductor chip 2 and 3 are overlapped. FIG. 10(a) shows the semiconductor chips 2 and 3 configured similarly to the first embodiment, while FIG. 10(b) shows an example in which the signal paths of the S-pads 23 and 25 in the semiconductor chip 2 are different in length, and the signal paths of the S-pads 33 and 35 in the semiconductor chip 3 are different in length, as in the third embodiment. In the fifth embodiment, one of the semiconductor chips 2 and 3 shown in FIGS. 10(a) and 10(b) is flipped around a rotation axis R parallel to a line such as the line L1 shown in FIG. 1 and is then placed on top of the other chip for connection. 10(a), the G pads 22 and 32 are connected directly (without via a line), the convex S pads 73 and 83 are connected directly, the P pads 24 and 14b are connected via a line 34, the convex S pads 75 and 85 are connected directly, and the G pads 26 and 36 are connected directly. Also, in the fifth embodiment of FIG. 10(b), the G pads 22 and 32 are connected directly, the S pads 23 and 33 are connected directly, the S pads 25 and 35 are connected directly, and the G pads 26 and 36 are connected directly.

[0049] The above configuration can be realized by arranging the G pads, S pads, and P pads in line symmetry with each other on the semiconductor chips 2 and 3 with respect to the rotation axis R as shown in Figures 10(a) and 10(b). Note that this arrangement of the electrode pads is realized on the surfaces of the semiconductor chips 2 and 3 on which the electrode pads are formed, or on the back surfaces of these surfaces, as shown in Figures 10(a) and 10(b). Note that, of the fifth embodiment, the example shown in Figure 10(b) requires an equal length design of the wiring, as in the third embodiment.

[0050] Note that the fifth embodiment does not specify that in the process of connecting the semiconductor chips 2 and 3, one of the semiconductor chips 2 and 3 is rotated around the rotation axis R, flipped over, and connected to the other, but specifies that in a configuration in which the semiconductor chips 2 and 3 are directly connected, the semiconductor chips 2 and 3 are ultimately arranged in this manner.

[0051] The first to fifth embodiments described above have been described assuming a digital coherent optical receiver with four channels as an example. However, the present disclosure can be applied to any differential optical receiver with a smaller number of channels, and can also be applied to optical receiving methods such as DPSK (Differential Phase Shift Keying) and DQPSK (Differential Quadrature Phase Shift Keying). [Explanation of symbols]

[0052] 2,3,5,6,9 semiconductor chips 4 Package substrate 7 Core Circuit 8 Optical waveguide 21 Dual Photodiode 21a, 21b Photodiode 12a, 12b, 16a, 16b, 22, 26, 32, 36 G Pad 13a, 13b, 15a, 15b, 23, 25, 33, 35, 73a, 75a, 83a, 85a S Pad 14a, 14b, 24, 34 P Pad 41,42,43,44,45 track 56 Beer 73,75,83,85 Convex S-pad 73b, 75b, 83b, 85b Measuring protrusions 91 Mach-Zehnder Optical Modulator 101,201,301 Optical communication device

Claims

1. a first chip having an optical waveguide and a plurality of first electrode pads for outputting an electrical signal indicating the intensity of light propagating through the optical waveguide; a second chip having a plurality of second electrode pads electrically connected to the first electrode pads directly or via another substrate; the first electrode pads and the second electrode pads include a plurality of signal pads that transmit the electrical signals; the center points of at least some of the signal pads among the plurality of signal pads are located on a straight line that is a line parallel to a side of at least one of the first chip and the second chip that faces the other chip, and the center points of other first electrode pads and other second electrode pads are located on another straight line that is farther from the facing side than the straight line; an optical communication device, characterized in that in the first chip, some of the multiple first electrode pads have their center points located on the straight line, and other of the first electrode pads have their center points located on another straight line parallel to the straight line, and the multiple first electrode pads whose center points are located on the straight line and the multiple other first electrode pads whose center points are located on the other straight line are arranged alternately adjacent to each other.

2. 2. The optical communication device according to claim 1, wherein at least some of the first electrode pads have measurement convex portions connected to the first electrode pads, and the measurement convex portions are arranged on the straight line.

3. 3. The optical communication device according to claim 1, wherein at least a portion of the second electrode pads has a measurement convex portion connected to the second electrode pad, and the measurement convex portion is arranged on the straight line.

4. 4. The optical communication device according to claim 1, wherein at least some of the first electrode pads or the second electrode pads have a polygonal shape in top view that has an even number of vertices, more than a rectangle.

5. the first chip has at least two photodiodes that convert light propagating through the optical waveguide into the electrical signal, and the second chip has a supplied circuit that receives the electrical signal; 5. The optical communication device according to claim 1, wherein a delay time of a signal path from one of the photodiodes to the powered circuit is equal to a delay time of a signal path from another of the photodiodes to the powered circuit.

6. 6. The optical communication device according to claim 1, wherein the optical communication device has a plurality of channels each including a photodiode and a transimpedance amplifier, and functions as an optical receiver, or a plurality of channels each including a modulator driver and a Mach-Zehnder optical modulator, and functions as an optical transmitter.

7. 7. The optical communication device according to claim 1, wherein one of the first chip and the second chip is rotated around the straight line as an axis, flipped upside down, and arranged so as to be superimposed on the other chip.

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