Semiconductor Devices

Abstract

This semiconductor device comprises: a semiconductor layer having a first main surface and a second main surface opposite the first main surface; an electron transit layer formed on the first main surface of the semiconductor layer; an electron supply layer formed on the electron transit layer; a gate conduction layer formed on the electron supply layer; a source conduction layer and a drain conduction layer formed on the electron supply layer so as to sandwich the gate conduction layer; an anode conduction layer formed on the second main surface of the semiconductor layer and electrically connected to the source conduction layer; a cathode conduction layer formed on the first main surface of the semiconductor layer and electrically connected to the drain conduction layer; and a rectification element formed using the semiconductor layer so as to be electrically connected to the anode conduction layer and the cathode conduction layer.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device in which a GaN layer is formed on a nitride semiconductor growth substrate that includes an Al2O3 layer made of aluminum oxide, an AlOxNy layer made of aluminum oxynitride, an AlN layer made of aluminum nitride, and an Al2O3 cap layer made of aluminum oxide, all on a silicon substrate made of single crystal silicon. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-38395 Summary of the Invention [Means for solving the problem]

[0004] A semiconductor device according to an embodiment of the present disclosure includes: a semiconductor layer having a first main surface and a second main surface opposite to the first main surface; an electron transit layer formed on the first main surface of the semiconductor layer; an electron supply layer formed on the electron supply layer; a gate conductive layer formed on the electron supply layer; a source conductive layer and a drain conductive layer formed on the electron supply layer so as to sandwich the gate conductive layer; an anode conductive layer formed on the second main surface of the semiconductor layer and electrically connected to the source conductive layer; a cathode conductive layer formed on the first main surface of the semiconductor layer and electrically connected to the drain conductive layer; and a rectifying element formed using the semiconductor layer so as to be electrically connected to the anode conductive layer and the cathode conductive layer. [Brief explanation of the drawings]

[0005] [Figure 1]FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view of a semiconductor element in the first embodiment of the semiconductor device of FIG. [Figure 3] FIG. 3 is a cross-sectional view of a semiconductor element in the first embodiment of the semiconductor device of FIG. [Figure 4] FIG. 4 is a diagram showing a part of the manufacturing process of the semiconductor device of FIG. [Figure 5] FIG. 5 is a diagram showing the next step of FIG. [Figure 6] FIG. 6 is a diagram showing the next step of FIG. [Figure 7] FIG. 7 is a diagram showing the next step of FIG. [Figure 8] FIG. 8 is a diagram showing the next step of FIG. [Figure 9] FIG. 9 is a diagram showing the next step of FIG. [Figure 10] FIG. 10 is a diagram showing the reverse current characteristics of the semiconductor device and the Si diode. [Figure 11A] FIG. 11A is a diagram showing a schematic current path in the semiconductor element. [Figure 11B] FIG. 11B is a diagram showing a schematic current path in the semiconductor element. [Figure 11C] FIG. 11C is a diagram showing a schematic current path in the semiconductor element. [Figure 12] FIG. 12 is a schematic plan view of a semiconductor element according to the second embodiment of the present disclosure. [Figure 13] FIG. 13 is a schematic cross-sectional view of a semiconductor element according to the second embodiment of the present disclosure. [Figure 14] FIG. 14 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present disclosure. [Figure 15] FIG. 15 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 16] FIG. 16 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 17]FIG. 17 is a schematic cross-sectional view of a semiconductor device according to a sixth embodiment of the present disclosure. [Figure 18] FIG. 18 is a schematic cross-sectional view of a semiconductor device according to the seventh embodiment of the present disclosure. [Figure 19] FIG. 19 is a schematic plan view of a semiconductor element according to the eighth embodiment of the present disclosure. [Figure 20] FIG. 20 is a schematic cross-sectional view of a semiconductor element according to a ninth embodiment of the present disclosure. [Figure 21] FIG. 21 is a schematic cross-sectional view of a semiconductor element according to a tenth embodiment of the present disclosure. [Figure 22] FIG. 22 is a schematic cross-sectional view of a semiconductor element according to an eleventh embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0006] <Embodiments of the present disclosure> First, embodiments of the present disclosure will be listed and described.

[0007] A semiconductor device according to an embodiment of the present disclosure includes: a semiconductor layer having a first main surface and a second main surface opposite to the first main surface; an electron transit layer formed on the first main surface of the semiconductor layer; an electron supply layer formed on the electron supply layer; a gate conductive layer formed on the electron supply layer; a source conductive layer and a drain conductive layer formed on the electron supply layer so as to sandwich the gate conductive layer; an anode conductive layer formed on the second main surface of the semiconductor layer and electrically connected to the source conductive layer; a cathode conductive layer formed on the first main surface of the semiconductor layer and electrically connected to the drain conductive layer; and a rectifying element formed using the semiconductor layer so as to be electrically connected to the anode conductive layer and the cathode conductive layer.

[0008] According to this configuration, a rectifying element that allows a current to flow in the reverse direction is formed between the source conductive layer and the drain conductive layer, independently of the electron transit layer and the electron supply layer. This makes it possible to ensure a path for a current to flow from the source conductive layer to the drain conductive layer regardless of the voltage applied to the gate conductive layer. As a result, a semiconductor device with excellent source-drain current conduction characteristics can be provided.

[0009] Furthermore, since the rectifying element is formed using the semiconductor layer, it is possible to form a rectifying element with a low forward voltage, and a semiconductor device with good source-drain current conduction characteristics can be provided.

[0010] Furthermore, since the anode conductive layer formed on the second main surface of the semiconductor layer and the source conductive layer are electrically connected, current collapse in the semiconductor device can be effectively suppressed.

[0011] The semiconductor device according to an embodiment of the present disclosure may include a first through-wire that penetrates the electron supply layer, the electron transit layer, and the semiconductor layer and connects the source conductive layer and the anode conductive layer.

[0012] This makes it possible to reduce the wiring resistance between the source conductive layer and the anode conductive layer, thereby providing a semiconductor device with good conduction characteristics.

[0013] In a semiconductor device according to an embodiment of the present disclosure, the cathode conductive layer may include a second through-wire that penetrates from the drain conductive layer through the electron supply layer and the electron transit layer and contacts the first main surface of the semiconductor layer.

[0014] This reduces the wiring resistance between the drain conductive layer and the cathode conductive layer, thereby providing a semiconductor device with good conduction characteristics. In addition, the drain conductive layer and the cathode conductive layer can be made common, thereby simplifying the structure of the semiconductor device.

[0015] In a semiconductor device according to an embodiment of the present disclosure, the semiconductor layer includes a silicon semiconductor layer, the electron traveling layer includes a nitride semiconductor layer, and may further include a buffer layer formed between the semiconductor layer and the electron traveling layer.

[0016] In a semiconductor device according to an embodiment of the present disclosure, it may further include an insulating layer formed between the electron supply layer and the gate conductive layer.

[0017] In a semiconductor device according to an embodiment of the present disclosure, the rectifying element may include a p-type region formed in the semiconductor layer and electrically connected to the anode conductive layer, and an n-type region formed in the semiconductor layer and electrically connected to the cathode conductive layer.

[0018] In a semiconductor device according to an embodiment of the present disclosure, the rectifying element may include a Schottky junction portion formed in the semiconductor layer and Schottky-junctioned with the cathode conductive layer.

[0019] In a semiconductor device according to an embodiment of the present disclosure, the electron supply layer may include a nitride semiconductor layer having a different Al composition from that of the electron traveling layer.

[0020] A semiconductor device according to an embodiment of the present disclosure, wherein the electron traveling layer is Al 1-X Ga X N (0 < X ≦ 1) layer, and the electron supply layer may include Al 1-X Ga X N (0 ≦ X < 1) layer.

[0021] In a semiconductor device according to an embodiment of the present disclosure, the semiconductor layer includes a first region in which the electron traveling layer and the electron supply layer are formed in a thickness direction view of the semiconductor layer, and a second region in which the rectifying element is formed in the thickness direction view, and the second region may be formed adjacent to the first region.

[0022] In the semiconductor device according to the embodiment of the present disclosure, the second region may be formed along the outer periphery of the first region.

[0023] In a semiconductor device according to an embodiment of the present disclosure, the electron transit layer and the electron supply layer may be stacked in a partial region of the first main surface of the semiconductor layer to form a laminated structure, the semiconductor layer may include a rectifying element formation region formed outside the laminated structure in a direction perpendicular to a thickness direction of the semiconductor layer, and the rectifying element may include a pn junction formed in the rectifying element formation region.

[0024] In the semiconductor device according to the embodiment of the present disclosure, the semiconductor layer may include a semiconductor substrate in which regions of the same conductivity type are exposed on the first main surface and the second main surface. Detailed Description of Embodiments of the Present Disclosure Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following detailed description, there are a plurality of components with names each having an ordinal number, but the ordinal numbers do not necessarily match the ordinal numbers of the components described in the claims. [First embodiment] Fig. 1 is a schematic cross-sectional view of a semiconductor device 1 according to a first embodiment of the present disclosure. The structure of the semiconductor device 1 will be described with reference to Fig. 1. The semiconductor device 1 includes a semiconductor element 2, a package 3, and a lead frame 4.

[0025] The lead frame 4 is formed in the shape of a metal plate. The lead frame 4 is formed by punching, cutting, bending, or the like from a thin metal plate such as Cu. Therefore, the main component of the material of the lead frame 4 is Cu. However, the material of the lead frame 4 is not limited to this.

[0026] The lead frame 4 may include a die pad portion 5 and lead portions 6. The die pad portion 5 supports the semiconductor element 2, and the lead portions 6 are arranged around the die pad portion 5. The lead portions 6 are formed apart from the die pad portion 5. The die pad portion 5 and the lead portions 6 are exposed from the package 3. In this embodiment, the lower surfaces of the die pad portion 5 and the lead portions 6 are selectively exposed from the package 3. The lead portions 6 have portions that are connected to an external circuit of the semiconductor device 1, and may therefore be referred to as terminals.

[0027] The semiconductor element 2 includes a conductive layer 7. The conductive layer 7 is a member that is connected to an external circuit when connecting the semiconductor element 2 to the external circuit. Therefore, the conductive layer 7 may also be referred to as an electrode layer. The semiconductor element 2 is supported by a die pad portion 5 of the lead frame 4 and is mounted on the die pad portion 5 with a bonding material such as solder. The semiconductor element 2 is electrically connected to the lead portions 6 by a conductive member 8. More specifically, the conductive layer 7 formed on the semiconductor element 2 is connected to the lead portions 6 by the conductive member 8, thereby electrically connecting the semiconductor element 2 to the lead portions 6. In this embodiment, the conductive member 8 is a metal wire. Therefore, the semiconductor element 2 is electrically connected to the lead portions 6 by wire bonding.

[0028] The package 3 covers the semiconductor element 2, the conductive member 8, and part of the lead frame 4, and may also be called a sealing resin. The package 3 is made of an insulating material. In this embodiment, the package 3 is made of, for example, black epoxy resin.

[0029] The structure of the semiconductor element 2 packaged in the semiconductor device 1 will be described with reference to Figures 2 and 3. Figures 2 and 3 are diagrams showing a schematic planar structure and a schematic cross-sectional structure of the semiconductor element 2, respectively.

[0030] The semiconductor element 2 is formed in a chip shape and has a rectangular shape in a plan view. The semiconductor element 2 includes a semiconductor chip 50, an insulating layer 16, and a conductive layer .

[0031] The semiconductor chip 50 has a two-tier structure including a base portion 51 and a mesa structure portion 52 selectively formed on the base portion 51. Both the base portion 51 and the mesa structure portion 52 may be rectangular parallelepiped-shaped (rectangular-shaped in plan view).

[0032] The base portion 51 has a first main surface 53, a second main surface 54 opposite the first main surface 53, and first to fourth side surfaces 55A to 55D surrounding the first main surface 53 in a plan view. The second main surface 54 of the base portion 51 may form the back surface of the semiconductor element 2. Meanwhile, the mesa structure 52 has a first main surface 56, a second main surface 57 opposite the first main surface 56, and first to fourth side surfaces 58A to 58D surrounding the first main surface 56 in a plan view. The first to fourth side surfaces 58A to 58D of the mesa structure 52 are formed inside the first to fourth side surfaces 55A to 55D of the base portion 51. As a result, a step 59 is formed between the first to fourth side surfaces 58A to 58D of the mesa structure 52 and the first to fourth side surfaces 55A to 55D of the base portion 51.

[0033] A part of the step 59 may form a lead-out portion 19 in which a part of the base portion 51 is led out laterally relative to the mesa structure 52. This lead-out portion 19 may occupy approximately half the area of ​​the semiconductor element 2 in a plan view. Furthermore, a part of the first main surface 53 of the base portion 51 is exposed by the lead-out portion 19. Meanwhile, the mesa structure 52 may be an element body portion 18 in which a HEMT structure is formed in the semiconductor element 2. In a plan view, the element body portion 18 excluding the lead-out portion 19 may also occupy approximately half the area of ​​the semiconductor element 2, similar to the lead-out portion 19.

[0034] In this embodiment, the base portion 51 may be a silicon semiconductor layer 13, and the mesa structure portion 52 may be a nitride semiconductor layer 12. The silicon semiconductor layer 13 is made of a Si-based semiconductor material such as Si or SiC. In this embodiment, a first impurity region 22 containing p-type impurities is formed over almost the entire silicon semiconductor layer 13. A second impurity region 23 containing n-type impurities is selectively formed in the surface layer of the lead-out portion 19. The silicon semiconductor layer 13 forms a pn junction with the first impurity region 22 and the second impurity region 23. As a result, a diode 17 is formed in the lead-out portion 19 of the silicon semiconductor layer 13.

[0035] The nitride semiconductor layer 12 includes a buffer layer 14, a first nitride semiconductor layer 24 as an example of an electron transit layer of the present disclosure, and a second nitride semiconductor layer 25 as an example of an electron supply layer of the present disclosure.

[0036] The buffer layer 14 is a layer for reducing the defect density of the nitride semiconductor layer 12 formed on the silicon semiconductor layer 13, for example. For example, due to the difference in lattice constant between Si and GaN, dislocation defects may occur in the nitride semiconductor layer 12 grown on the silicon semiconductor layer 13. The inclusion of the buffer layer 14 can suppress the occurrence of dislocation defects in the nitride semiconductor layer 12. The buffer layer 14 may be formed of a single AlN film or may be formed by stacking multiple nitride semiconductor films. When the buffer layer 14 is formed by stacking multiple nitride semiconductor films, it may be composed of an AlN layer in contact with the silicon semiconductor layer 13 as a first buffer layer and an AlGaN layer stacked on the first buffer layer as a second buffer layer. The first buffer layer may also be called a seed layer because it functions to grow an AlGaN layer with a low Al level. The second buffer layer may include a first AlGaN layer in contact with the first buffer layer, and a second AlGaN layer formed on the first AlGaN layer and having a smaller Al composition than the first AlGaN layer.

[0037] If only a single layer of AlGaN is simply provided between the first buffer layer and the nitride semiconductor layer 12, since the difference in lattice constants between AlGaN and GaN is large, when a nitride semiconductor layer 12 having a large thickness is stacked, lattice relaxation of GaN may occur. Therefore, it becomes difficult to impart sufficient breakdown voltage to the semiconductor device 2. As a result, the thickness of the nitride semiconductor layer 12 is limited, and the degree of freedom in device design is reduced. By determining the respective compositions such that the Al composition becomes smaller in the layer closer to the nitride semiconductor layer 12, the lattice constant of the second buffer layer can be gradually increased from a value close to the lattice constant of AlN to a value close to the lattice constant of GaN. As a result, the thickness of the nitride semiconductor layer 12 can be freely designed. Therefore, by designing the nitride semiconductor layer 12 to be thick, the device breakdown voltage can be improved.

[0038] The first nitride semiconductor layer 24 is formed on the buffer layer 14. The first nitride semiconductor layer 24 contains a semiconductor material having a composition of Al 1-X Ga X N (0 < X ≦ 1). The first nitride semiconductor layer 24 may contain a large amount of acceptor impurities and may include a first GaN layer in contact with the buffer layer 14 and a second GaN layer formed on the first GaN layer and containing almost no acceptor impurities. In this case, the first nitride semiconductor layer 24 may contain C (carbon) as an acceptor impurity. Since the second GaN layer is a layer in which a two-dimensional electron gas 100 is formed, it may also be called a conduction path forming layer.

[0039] The second nitride semiconductor layer 25 has a composition of Al 1-X Ga XIt includes a semiconductor material with N (0 < X ≤ 1). The second nitride semiconductor layer 25 is composed of a nitride semiconductor having a larger bandgap than the first nitride semiconductor layer 24. Specifically, the second nitride semiconductor layer 25 is composed of a nitride semiconductor with a higher Al composition than the first nitride semiconductor layer 24. Since the first nitride semiconductor layer 24 and the second nitride semiconductor layer 25 are nitride semiconductors with different bandgaps, lattice mismatch occurs. As a result, in the first nitride semiconductor layer 24, a two-dimensional electron gas 100 spreads at a position close to the interface between the first nitride semiconductor layer 24 and the second nitride semiconductor layer 25 (the second GaN layer).

[0040] The insulating layer 16 is formed in contact with the first main surface 56 of the mesa structure portion 52. The insulating layer 16 may be composed of a material having insulating properties such as SiO2, SiN, SiON, Al2O3, AlN, AlON, HfO, HfN, HfON, HfSiON, AlON, etc. Also, since the insulating layer 16 serves to insulate between the gate 28 described later and the nitride semiconductor layer 12, it may be referred to as a gate insulating layer.

[0041] The conductive layer 7 is electrically connected to the lead portion 6. The conductive layer 7 may include a source 26, a drain 27, a gate 28, an anode 29, and a cathode 30.

[0042] The source 26 and the drain 27 are formed on the element main body portion 18 through source contact holes 31 and drain contact holes 32 provided in the insulating layer 16. The gate 28 is formed on the insulating layer 16. The cathode 30 is formed on the lead-out portion 19. The source 26, the drain 27, the gate 28, and the cathode 30 are separated from each other.

[0043] The source 26 may include a source body 33 and a source extension 34. The source 26 is formed into a comb-like shape by the source body 33 and the source extension 34. The source body 33 is a region that is rectangular in plan view and extends in a direction along the third side surface 58C of the element body 18 in a planar view. The source extension 34 is rectangular in plan view and extends from the source body 33 in a direction along the second side surface 58B and the fourth side surface 58D of the element body 18. A plurality of source extensions 34 are formed at regular intervals. The source 26 is formed in direct contact with the second nitride semiconductor layer 25.

[0044] The drain 27 may include a drain body portion 35 and a drain extension portion 36. The drain 27 is formed into a comb-like shape by the drain body portion 35 and the drain extension portion 36. The drain 27 is arranged so that the comb-like teeth of the drain 27 interdigitate with those of the source 26. The drain body portion 35 is a region having a rectangular shape in a planar view extending in a direction along the first side surface 58A of the element body portion 18 in a planar view. The drain extension portion 36 has a rectangular shape in a planar view extending from the drain body portion 35 in a direction along the second side surface 58B and the fourth side surface 58D of the element body portion 18. A plurality of drain extension portions 36 are formed at regular intervals. The source extension portion 34 and the drain extension portion 36 are adjacent to each other in a direction along the first side surface 58A of the semiconductor element 2. The drain 27 is formed in direct contact with the second nitride semiconductor layer 25.

[0045] The gate 28 is a region that is rectangular in plan view and is formed at one corner of the element body 18 in plan view. The gate 28 is formed on an extension of the source body 33 and on an extension of the drain extension 36. The gate 28 is formed on the insulating layer 16. When the gate 28 is formed on the insulating layer 16, a higher voltage can be applied to the gate 28 compared to when the gate 28 is in direct contact with the nitride semiconductor layer 12.

[0046] The anode 29 is formed to cover the second main surface 54 of the base portion 51. Therefore, the anode 29 is formed on the surface of the silicon semiconductor layer 13 where the p-type first impurity region 22 is formed. In this embodiment, the anode 29 is electrically connected to the source 26 via a through-electrode 37 that penetrates the mesa structure 52 and the base portion 51 from the first main surface 56 of the mesa structure 52 to the second main surface 54 of the base portion 51. When the anode 29 is electrically connected to the source 26, the source 26 and the die pad portion 5 are electrically connected by surface contact with each other via the anode 29, thereby reducing parasitic inductance. This reduces gate voltage oscillations caused by parasitic inductance, reducing problems such as malfunctions and breakdowns, and providing a highly reliable semiconductor device. Furthermore, when the anode 29 is electrically connected to the source 26, the anode 29 and the source 26 of the semiconductor device 1 can be integrated, preventing unnecessary increases in the number of external terminals.

[0047] The cathode 30 is formed on the first main surface 53 of the lead-out portion 19 . The diode 17 is formed by a pn junction formed by the first impurity region 22 and the second impurity region 23 of the lead-out portion 19, an anode 29, and a cathode 30.

[0048] Next, a method for manufacturing the semiconductor device 1 will be described with reference to Figures 4 to 9. Figures 4 to 9 are vertical cross-sectional views showing some of the manufacturing steps of the semiconductor device 1 in the order of steps.

[0049] 4, in manufacturing the semiconductor device 1, first, a silicon semiconductor layer 13 having a p-type first impurity region 22 is prepared. The silicon semiconductor layer 13 is formed, for example, by doping a Si wafer with an acceptor impurity of a trivalent element such as B (boron). Next, a donor impurity of a pentavalent element such as P (phosphorus) is doped on the first main surface 53 side of the silicon semiconductor layer 13 by an impurity diffusion method, an ion implantation method, or the like, thereby forming a second impurity region 23 having n-type conductivity. As a result, a pn junction is formed in the silicon semiconductor layer 13.

[0050] 5, a buffer layer 14 is formed in a region where the device body 18 is to be formed on the silicon semiconductor layer 13. For example, the buffer layer 14 is epitaxially grown on the device body 18 side by MOCVD (Metal Organic Chemical Vapor Deposition).

[0051] 6 and 7, nitride semiconductor layer 12 is then formed. Nitride semiconductor layer 12 is formed by epitaxially growing first nitride semiconductor layer 24 on buffer layer 14 by, for example, MOCVD. Furthermore, second nitride semiconductor layer 25 is formed on first nitride semiconductor layer 24 by MOCVD.

[0052] 8, insulating layer 16 is formed. For example, insulating layer 16 is formed on second nitride semiconductor layer 25 by a plasma CVD (Chemical Vapor Deposition) method, an LPCVD (Low Pressure CVD) method, an ALD (Atomic Layer Deposition) method, or the like. Thereafter, a resist (not shown) is formed on insulating layer 16 in areas excluding areas where source contact holes 31 and drain contact holes 32 are to be formed, and unnecessary portions of insulating layer 16 are removed by etching, thereby forming source contact holes 31 and drain contact holes 32. Source contact holes 31 and drain contact holes 32 penetrate insulating layer 16 and reach second nitride semiconductor layer 25.

[0053] Next, referring to FIG. 9 , the conductive layer 7 is formed. For example, a material for the conductive layer 7 is deposited on the insulating layer 16 by vapor deposition, sputtering, or the like, and then the conductive material is patterned to separate the conductive layer 7 into the source 26, the drain 27, the gate 28, and the cathode 30. Furthermore, for example, the insulating layer 16 and the nitride semiconductor layer 12 are partially covered with a resist and selectively etched to form a through-hole 38, and then a through-electrode 37 is formed in the through-hole 38 by vapor deposition, sputtering, or the like. Furthermore, for example, an anode 29 is formed on the second main surface 54 of the base portion 51 by vapor deposition, sputtering, or the like, and then a plurality of semiconductor devices 1 are cut out from the silicon semiconductor layer 13. The semiconductor device 1 is manufactured through the processes including those described above.

[0054] The semiconductor device 1 according to the first embodiment of the present disclosure includes a normally-off GaN-HEMT (High Electron Mobility Transistor). In a normally-off GaN-HEMT, when no voltage is applied to the gate 28, the entire energy band is elevated, the boundary between the electron transit layer and the electron supply layer becomes higher than the Fermi level, and the two-dimensional electron gas 100 (2DEG) disappears. When a positive voltage is applied to the gate 28, the entire energy band is pulled downward, generating the two-dimensional electron gas 100 and forming a channel between the source and drain.

[0055] Figure 10 shows an example of the drain voltage-drain current characteristics of a normally-off GaN-HEMT device and a Si diode for various gate-source voltages. A normally-off GaN-HEMT device can pass a negative drain current (reverse current) at a low source-drain voltage when the gate-source voltage is the on-voltage (Vgs = 6 V in the figure). However, when the gate-source voltage is the off-voltage (Vgs ≦ 0 V in the figure), the source-drain voltage required to pass the reverse current increases. Thus, the reverse current conduction characteristics of a normally-off GaN-HEMT device are affected by the state of the applied gate voltage. A Si diode can pass a reverse current with better characteristics than a normally-off GaN-HEMT device when an off-voltage is applied.

[0056] 11A to 11C are schematic diagrams illustrating current paths in the semiconductor device 1 according to this embodiment when the gate is on and off. FIG. 11A shows the path of a forward drain current (forward current) flowing through the semiconductor device 1 when an on-voltage is applied to the gate 28. In a normally-off GaN-HEMT device, when an on-voltage is applied to the gate 28, a forward current flows through the two-dimensional electron gas 100, with the channel formed in the first nitride semiconductor layer 24 serving as the main current path (arrow A). At this time, the forward current flows from the cathode 30 to the anode 29 of the diode 17, so no current flows through the diode 17. Furthermore, although not shown, when an off-voltage is applied to the gate 28, no current flows through the normally-off GaN-HEMT device because no channel is formed in the first nitride semiconductor layer 24. Furthermore, as in the case of FIG. 11A, the forward current flows from the cathode 30 to the anode 29 of the diode 17, so no current flows through the diode 17.

[0057] 11B shows the path of a reverse current flowing through semiconductor device 1 when an on-voltage is applied to gate 28. As shown in FIG. 10, a normally-off GaN-HEMT device has better reverse current conduction characteristics than a Si diode when an on-voltage is applied to gate 28. Therefore, when an on-voltage is applied to gate 28, a reverse current flows through two-dimensional electron gas 100, with the channel formed in first nitride semiconductor layer 24 serving as the main current path (arrow B). At this time, the reverse current flows from anode 29 to cathode 30 of diode 17, and diode 17 becomes a secondary current path, resulting in a smaller current flow than in a normally-off GaN-HEMT (arrow C).

[0058] FIG. 11C shows the path of a reverse current flowing through the semiconductor device 1 when an off-state voltage is applied to the gate 28. As shown in FIG. 10, the Si diode has better conduction characteristics for reverse current than the normally-off GaN-HEMT device when an off-state voltage is applied to the gate 28. Because the reverse current flows from the anode 29 to the cathode 30 of the diode 17, when an off-state voltage is applied to the gate 28, the reverse current flows through the diode 17 as the main current path (arrow D). At this time, the normally-off GaN-HEMT device serves as a secondary current path, and a smaller current flows through it than through the diode 17 (arrow E). Therefore, a semiconductor device 1 can be provided that can properly pass a reverse current even when an off-state voltage is applied to the normally-off GaN-HEMT device. [Second embodiment] 12 and 13 are a schematic plan view and a schematic cross-sectional view of a semiconductor element 2 according to the second embodiment.

[0059] The cross-sectional structure of the semiconductor element 2 of this embodiment differs from that of the semiconductor element 2 of the first embodiment in that the drain 27 and cathode 30 are replaced by a common electrode 39, but since the other aspects are the same, only the structure of the common electrode 39 will be described.

[0060] The common electrode 39 is an electrode in which the drain 27 and the cathode 30 are integrally formed.

[0061] The common electrode 39 is formed across the element body 18 and the lead-out portion 19. In the case of a configuration having the common electrode 39, the drain 27 and cathode 30 of the semiconductor element 2 can be integrated, thereby preventing an unnecessary increase in external terminals. [Third embodiment] FIG. 14 is a schematic cross-sectional view of a semiconductor device 1 according to a third embodiment of the present disclosure.

[0062] The semiconductor device 1 according to the third embodiment has the same basic structure as the semiconductor device 1 according to the first embodiment, but differs in the configuration of the conductive member 8. Therefore, only the conductive member 8 will be described.

[0063] The semiconductor element 2 is electrically connected to the lead portions 6 by a conductive member 8. More specifically, the semiconductor element 2 is electrically connected to the lead portions 6 by connecting the conductive layer 7 formed on the semiconductor element 2 to the lead portions 6 by the conductive member 8. In this embodiment, the conductive member 8 is electrically connected to the lead portions 6 by clip bonding using a metal clip. [Fourth embodiment] FIG. 15 is a schematic cross-sectional view of a semiconductor device 1 according to the fourth embodiment of the present disclosure.

[0064] The semiconductor device 1 according to the fourth embodiment differs from the semiconductor device 1 according to the first embodiment in that it does not have a lead frame 4. In the fourth embodiment, the semiconductor device 1 has Cu wiring 40 instead of the lead frame 4.

[0065] The Cu wiring 40 includes a first Cu wiring 41 and a second Cu wiring 42. The semiconductor element 2 is supported by the first Cu wiring 41. The conductive member 8 is formed by the second Cu wiring 42. Therefore, the conductive layer 7 formed on the semiconductor element 2 is connected to the second Cu wiring 42. The second Cu wiring 42 is exposed to the outside of the package 3, and serves as a member that is connected to an external circuit when the semiconductor element 2 is connected to the external circuit. [Fifth embodiment] FIG. 16 is a schematic cross-sectional view of a semiconductor device 1 according to a fifth embodiment of the present disclosure.

[0066] The semiconductor device 1 according to the fifth embodiment has the same basic structure as the semiconductor device 1 according to the first embodiment, but differs in the configuration of the lead frame 4. Therefore, only the lead frame 4 will be described.

[0067] The lead portion 6 includes a source lead 43 connected to the source 26 (conductive layer 7) of the semiconductor element 2 by a conductive member 8. In the fifth embodiment, the die pad portion 5 is formed integrally with the source lead 43. [Sixth embodiment] FIG. 17 is a schematic cross-sectional view of a semiconductor device 1 according to the sixth embodiment of the present disclosure.

[0068] The semiconductor device 1 according to the sixth embodiment has the same basic structure as the semiconductor device 1 according to the third embodiment, but differs in the configuration of the lead frame 4. Therefore, only the lead frame 4 will be described.

[0069] The lead portion 6 includes a source lead 43 connected to the source 26 (conductive layer 7) of the semiconductor element 2 by a conductive member 8. In the sixth embodiment, the die pad portion 5 is formed integrally with the source lead 43. [Seventh embodiment] FIG. 18 is a schematic cross-sectional view of a semiconductor device 1 according to the seventh embodiment of the present disclosure.

[0070] The semiconductor device 1 according to the seventh embodiment has the same basic structure as the semiconductor device 1 according to the fourth embodiment, but differs in the configuration of the Cu wiring 40. Therefore, only the Cu wiring 40 will be described.

[0071] The Cu wiring 40 includes a source wiring 44 connected to the source 26 of the semiconductor element. In the fourth embodiment, the first Cu wiring 41 is formed integrally with the source wiring 44. [Eighth embodiment] Next, with reference to FIG. 19, a planar structure of the semiconductor element 2 according to the eighth embodiment of the present disclosure will be described.

[0072] The planar structure of the semiconductor element 2 of this embodiment differs from that of the semiconductor element 2 of the first embodiment in the form of the element body portion 18, the lead-out portion 19, and the cathode 30, but other aspects are the same, so only the element body portion 18, the lead-out portion 19, and the cathode 30 will be described.

[0073] In this embodiment, the lead portion 19 is formed on the outer periphery of the element body portion 18. Therefore, the element body portion 18 is configured to be surrounded by the lead portion 19. In addition, the second impurity region 23 is formed in a ring shape that surrounds the element body portion 18 in a plan view. The cathode 30 is formed on the lead portion 19 so as to surround the drain 27. In addition, the cathode 30 is formed so as to surround a portion of the element body portion 18. [Ninth embodiment] Next, with reference to FIG. 20, a cross-sectional structure of a semiconductor element 2 according to a ninth embodiment of the present disclosure will be described.

[0074] The cross-sectional structure of the semiconductor element 2 according to this embodiment differs from that of the semiconductor element 2 according to the first embodiment in the manner in which the source 26 and the anode 29 are connected, but the other points are the same, so only the source 26 and the anode 29 will be described. In this embodiment, the source 26 is connected to the anode 29 along the third side surface 58C of the element body 18 and the third side surface 55C of the silicon semiconductor layer 13. [Tenth embodiment] Next, with reference to FIG. 21, a cross-sectional structure of the semiconductor element 2 according to the tenth embodiment of the present disclosure will be described.

[0075] The cross-sectional structure of the semiconductor element 2 according to this embodiment differs from that of the semiconductor element 2 according to the first embodiment in the structures of the insulating layer 16, source 26, and gate 28, but is otherwise identical, so only the structures of the insulating layer 16, source 26, and gate 28 will be described.

[0076] In this embodiment, the gate 28 includes a nitride semiconductor portion 45 and a gate conductive portion 46. The nitride semiconductor portion 45 is formed in contact with the second nitride semiconductor layer 25. The nitride semiconductor portion 45 includes GaN doped with acceptor-type impurities. When the gate 28 includes the nitride semiconductor portion 45, it is possible to cancel out the two-dimensional electron gas 100 generated at the interface between the first nitride semiconductor layer 24 and the second nitride semiconductor layer 25 in the region directly below the gate 28. The gate conductive portion 46 is formed on the nitride semiconductor portion 45.

[0077] The insulating layer 16 is in contact with the upper surface of the second nitride semiconductor layer 25, and covers the side surface of the nitride semiconductor portion 45 and the side surface and surface of the gate conductive portion 46. The insulating layer 16 may be made of an insulating material such as SiO, SiN, SiON, AlO, AlN, AlON, HfO, HfN, HfON, HfSiON, or AlON.

[0078] The source 26 includes a source body portion 47 and a source field plate portion 48. The source body portion 47 is formed in contact with the nitride semiconductor layer 12. The source field plate portion 48 extends from the source body portion 47 and covers the gate 28 via the insulating layer 16. The configuration including the source field plate portion 48 makes it possible to reduce electric field concentration at the end of the source 26, thereby providing a highly reliable semiconductor device. [Eleventh embodiment] Next, with reference to FIG. 22, a cross-sectional structure of the semiconductor element 2 according to the eleventh embodiment of the present disclosure will be described.

[0079] The semiconductor device 2 according to the eleventh embodiment differs from the semiconductor device 2 according to the first embodiment in that the second impurity region 23 is not formed. In this embodiment, the diode 17 may be a Schottky barrier diode 9 formed by a Schottky junction between the silicon semiconductor layer 13 and the cathode 30.

[0080] Although one embodiment of the present disclosure has been described above, the present disclosure can be embodied in other forms.

[0081] For example, in the above-described embodiment, the element body 18 of the semiconductor chip 50 is formed only from the nitride semiconductor layer 12, but a part of the element body 18 may be formed from the silicon semiconductor layer 13. In other words, the boundary between the nitride semiconductor layer 12 and the silicon semiconductor layer 13 may not coincide with the boundary between the base portion 51 and the mesa structure portion 52, and may be located midway in the thickness direction of the element body 18 (mesa structure portion 52).

[0082] Furthermore, it is possible to combine elements of each embodiment within the scope of the claims.

[0083] In addition, various design modifications can be made within the scope of the claims.

[0084] This application corresponds to Patent Application No. 2020-150774 filed with the Japan Patent Office on September 8, 2020, the entire disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0085] 1: Semiconductor device 2: Semiconductor elements 3: Package 4: Lead frame 5: Die pad section 6: Lead section 7: Conductive layer 8: Conductive material 9: Schottky barrier diode 12: Nitride semiconductor layer 13: Silicon semiconductor layer 14: Buffer layer 15: Conductive layer 16: Insulating layer 17: Diode 18: Element body 19:Drawer part 22:First impurity region 23:Second impurity region 24: First nitride semiconductor layer 25: Second nitride semiconductor layer 26: Source 27: Drain 28: Gate 29: Anode 30: Cathode 31: Source contact hole 32: Drain contact hole 33: Source body 34: Source extension 35: Drain body 36: Drain extension 37: Through electrode 38:Through hole 39: Common electrode 40:Cu wiring 41:1st Cu wiring 42: 2nd Cu wiring 43: Source Read 44: Source wiring 45: Nitride semiconductor section 46: Gate conductive part 47: Source body 48: Source field plate section 50: Semiconductor chips 51: Base part 52: Mesa structure 53: (base portion) first main surface 54: (Base part) Second main surface 55A: (Base part) First side 55B: (Base part) Second side 55C: (Base) Third side 55D: (Base) 4th side 56: (Mesa structure) First main surface 57: (Mesa structure) Second main surface 58A: (Mesa structure) First side 58B: (Mesa structure) Second side 58C: (Mesa structure) Third side 58D: (Mesa structure) 4th side 59: Step 100: Two-dimensional electron gas

Claims

1. a semiconductor layer having a first major surface and a second major surface opposite to the first major surface; an electron transit layer formed on the first main surface of the semiconductor layer; an electron supply layer formed on the electron transit layer; a gate conductive layer formed on the electron supply layer; a source conductive layer and a drain conductive layer formed on the electron supply layer so as to sandwich the gate conductive layer; an anode conductive layer formed on the second main surface of the semiconductor layer and electrically connected to the source conductive layer; a cathode conductive layer formed on the first main surface of the semiconductor layer and electrically connected to the drain conductive layer; a rectifying element formed by utilizing the semiconductor layer and electrically connected to the anode conductive layer and the cathode conductive layer, the electron transit layer and the electron supply layer are stacked on a partial region of the first main surface of the semiconductor layer to form a stacked structure, the semiconductor layer includes a rectifying element formation region formed outside the stacked structure in a direction perpendicular to a thickness direction of the semiconductor layer, The rectifying element includes a pn junction formed in the rectifying element forming region.

2. The semiconductor device according to claim 1 , further comprising a first through-wire that penetrates said electron supply layer, said electron transit layer, and said semiconductor layer and connects said source conductive layer and said anode conductive layer.

3. 3 . The semiconductor device according to claim 2 , wherein the cathode conductive layer includes a second through-wire that passes through the electron supply layer and the electron transit layer from the drain conductive layer and is in contact with the first main surface of the semiconductor layer.

4. the semiconductor layer includes a silicon semiconductor layer; the electron transit layer includes a nitride semiconductor layer, 4. The semiconductor device according to claim 1, further comprising a buffer layer formed between the semiconductor layer and the electron transit layer.

5. 5. The semiconductor device according to claim 1, further comprising an insulating layer formed between said electron supply layer and said gate conductive layer.

6. 6. The semiconductor device according to claim 1, wherein the rectifying element includes a p-type region formed in the semiconductor layer and electrically connected to the anode conductive layer, and an n-type region formed in the semiconductor layer and electrically connected to the cathode conductive layer.

7. 7. The semiconductor device according to claim 1, wherein the electron supply layer includes a nitride semiconductor layer having an Al composition different from that of the electron transit layer.

8. the electron transit layer includes an AlGaN (0<X≦1) layer, 8. The semiconductor device according to claim 7, wherein said electron supply layer includes an Al1-XGaXN (0≦X<1) layer.

9. The semiconductor layer is a first region in which the electron transit layer and the electron supply layer are formed as viewed in the thickness direction of the semiconductor layer; a second region as the rectifying element formation region as viewed in the thickness direction, 9. The semiconductor device according to claim 1, wherein the second region is formed adjacent to the first region.

10. 10. The semiconductor device according to claim 9, wherein said second region is formed along an outer periphery of said first region.

11. 11. The semiconductor device according to claim 1, wherein the semiconductor layer includes a semiconductor substrate having exposed regions of the same conductivity type on the first main surface and the second main surface.

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