Image pickup device and method for manufacturing the same

Abstract

An imaging element according to one embodiment of the present disclosure is provided with: a wiring layer which comprises a plurality of wiring lines that extend in one direction; a first barrier film which is superposed on the wiring layer so as to have a first end face positioned above one of the plurality of wiring lines; a first insulating film which is superposed on the wiring layer and the first barrier film; a first void which is formed between the wiring layer and the first insulating film so as to be positioned between a plurality of wiring lines adjacent to each other; and a second void that is formed above the wiring line, above which the first end face is positioned, so as to be positioned in the vicinity of the first end face.

Description

[Technical Field]

[0001] The present disclosure relates to, for example, an imaging element having gaps between wirings and a method for manufacturing the imaging element. [Background technology]

[0002] In semiconductor devices, as semiconductor integrated circuit elements become smaller, the spacing between elements and the wiring connecting elements within an element becomes narrower. In response to this, for example, Patent Document 1 discloses a semiconductor device in which an air gap is formed between the wiring to reduce the capacitance between the wiring. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-193104 Summary of the Invention

[0004] In recent years, stacked image sensors have become commonplace, and there is a demand for a reduction in wiring capacitance.

[0005] It is desirable to provide an imaging device that can reduce wiring capacitance and a method for manufacturing the same.

[0006] An imaging element according to one embodiment of the present disclosure includes a wiring layer having a plurality of wirings extending in one direction, a first barrier film stacked on the wiring layer and having a first end face above one of the plurality of wirings, a first insulating film stacked on the wiring layer and the first barrier film, a first void provided between the wiring layer and the first insulating film and between adjacent plurality of wirings, and a second void provided above the wiring having the first end face and in the vicinity of the first end face.

[0007] A method for manufacturing an imaging element according to one embodiment of the present disclosure includes forming a wiring layer having a plurality of wirings extending in one direction, depositing a first barrier film on the wiring layer, forming a first opening between the first barrier film and adjacent wirings in a predetermined region of the wiring layer, and depositing a first insulating film to form a first gap between the adjacent wirings and a second gap near a first end face formed by the first opening in the first barrier film.

[0008] In an image sensor according to an embodiment of the present disclosure and a manufacturing method of the image sensor according to the embodiment, a first barrier film having a first end face is formed on a wiring layer having a plurality of wirings extending in one direction, above one of the plurality of wirings, and a first insulating film is further formed to cover the wiring layer and the first barrier film, and a first gap is formed between adjacent wirings, and a second gap is formed above the wiring where the first end face of the first barrier film is provided and in the vicinity of the first end face, thereby reducing the capacitance between the wirings extending in one direction. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram illustrating an example of a vertical cross-sectional configuration of a wiring structure according to an embodiment of the present disclosure. [Figure 2] 2 is a schematic diagram illustrating an example of a horizontal cross-sectional configuration of the wiring structure illustrated in FIG. 1. FIG. [Figure 3] 2. FIG. 4 is a schematic diagram illustrating an example of a cross-sectional configuration of the wiring structure shown in FIG. 1 in a vertical direction taken along line II-II shown in FIG. [Figure 4A] 2A to 2C are cross-sectional views illustrating an example of a manufacturing process for the wiring structure shown in FIG. [Figure 4B] FIG. 4B is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 4A. [Figure 4C] FIG. 4C is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 4B. [Figure 4D] FIG. 4D is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 4C. [Figure 4E] FIG. 4E is a schematic cross-sectional view illustrating an example of the manufacturing process following FIG. 4D. [Figure 4F]FIG. 4F is a schematic cross-sectional view showing an example of the manufacturing process subsequent to FIG. 4E. [Figure 4G] FIG. 4C is a schematic cross-sectional view showing an example of the manufacturing process subsequent to FIG. 4F. [Figure 5] 1 is a diagram illustrating an example of a vertical cross-sectional configuration of an imaging element according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram illustrating an example of a schematic configuration of the imaging element illustrated in FIG. 5. [Figure 7] 6 is a diagram in which the wiring structure shown in FIG. 1 is applied to the imaging element shown in FIG. 5. [Figure 8] 7 is a diagram illustrating an example of a sensor pixel and a readout circuit illustrated in FIG. 6. FIG. [Figure 9] 7 is a diagram illustrating an example of a sensor pixel and a readout circuit illustrated in FIG. 6. FIG. [Figure 10] 7 is a diagram illustrating an example of a sensor pixel and a readout circuit illustrated in FIG. 6. FIG. [Figure 11] 7 is a diagram illustrating an example of a sensor pixel and a readout circuit illustrated in FIG. 6. FIG. [Figure 12] FIG. 10 is a diagram illustrating an example of a connection mode between a plurality of readout circuits and a plurality of vertical signal lines. [Figure 13] 6 is a diagram illustrating an example of a cross-sectional configuration in the horizontal direction of the imaging element illustrated in FIG. 5. [Figure 14] 6 is a diagram illustrating an example of a cross-sectional configuration in the horizontal direction of the imaging element illustrated in FIG. 5. [Figure 15] 6 is a diagram illustrating an example of a wiring layout in a horizontal plane of the image sensor illustrated in FIG. 5. [Figure 16] 6 is a diagram illustrating an example of a wiring layout in a horizontal plane of the image sensor illustrated in FIG. 5. [Figure 17] 6 is a diagram illustrating an example of a wiring layout in a horizontal plane of the image sensor illustrated in FIG. 5. [Figure 18] 6 is a diagram illustrating an example of a wiring layout in a horizontal plane of the image sensor illustrated in FIG. 5. [Figure 19A] 6A to 6C are diagrams illustrating an example of a manufacturing process for the imaging element shown in FIG. 5. [Figure 19B] FIG. 19B is a diagram illustrating an example of the manufacturing process following FIG. 19A. [Figure 19C] FIG. 19C is a diagram illustrating an example of the manufacturing process following FIG. 19B. [Figure 19D] FIG. 19D is a diagram illustrating an example of a manufacturing process following FIG. 19C. [Figure 19E] FIG. 19D illustrates an example of the manufacturing process. [Figure 19F] FIG. 19B is a diagram illustrating an example of the manufacturing process following FIG. 19E. [Figure 19G] FIG. 19C is a diagram showing an example of the manufacturing process following FIG. 19F. [Figure 20] FIG. 10 is a schematic diagram illustrating an example of a vertical cross-sectional configuration of a wiring structure according to Modification 1 of the present disclosure. [Figure 21] FIG. 10 is a schematic diagram illustrating an example of a vertical cross-sectional configuration of a wiring structure according to a second modification of the present disclosure. [Figure 22A] 10A to 10C are cross-sectional views illustrating an example of a manufacturing process for a wiring structure according to Modification 2 of the present disclosure. [Figure 22B] FIG. 22B is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 22A. [Figure 22C] FIG. 22C is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 22B. [Figure 22D] FIG. 22D is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 22C. [Figure 22E] FIG. 22E is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 22D. [Figure 23A] FIG. 10 is a schematic diagram illustrating an example of a vertical cross-sectional configuration of a wiring structure according to a third modification of the present disclosure. [Figure 23B] FIG. 10 is a schematic diagram illustrating another example of the vertical cross-sectional configuration of the wiring structure according to the third modification of the present disclosure. [Figure 24] FIG. 2 is a schematic diagram illustrating the shape of a gap. [Figure 25] FIG. 10 is a schematic diagram illustrating another example of the vertical cross-sectional configuration of the wiring structure according to the third modification of the present disclosure. [Figure 26] FIG. 10 is a schematic diagram illustrating another example of the vertical cross-sectional configuration of the wiring structure according to the third modification of the present disclosure. [Figure 27] FIG. 11 is a schematic diagram illustrating an example of a vertical cross-sectional configuration of a wiring structure according to a fourth modification of the present disclosure. [Figure 28A] 28A to 28D are cross-sectional views illustrating an example of a manufacturing process for the wiring structure shown in FIG. 27. [Figure 28B] FIG. 28B is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 28A. [Figure 28C] FIG. 28C is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 28B. [Figure 28D] FIG. 28D is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 28C. [Figure 28E] FIG. 28D is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 28D. [Figure 29] FIG. 11 is a schematic diagram illustrating another example of the vertical cross-sectional configuration of the wiring structure according to the fourth modification of the present disclosure. [Figure 30] FIG. 11 is a schematic diagram illustrating another example of the vertical cross-sectional configuration of the wiring structure according to the fourth modification of the present disclosure. [Figure 31] FIG. 11 is a schematic diagram illustrating another example of the vertical cross-sectional configuration of the wiring structure according to the fourth modification of the present disclosure. [Figure 32] FIG. 11 is a schematic diagram illustrating an example of a vertical cross-sectional configuration of a wiring structure according to a fourth modification of the present disclosure. [Figure 33] FIG. 11 is a schematic diagram illustrating another example of the vertical cross-sectional configuration of the wiring structure according to the fourth modification of the present disclosure. [Figure 34] FIG. 13 is a schematic diagram illustrating another example of the vertical cross-sectional configuration of the wiring structure according to the fifth modification of the present disclosure. [Figure 35A] 35A to 35C are cross-sectional views illustrating an example of a manufacturing process for the wiring structure shown in FIG. 34. [Figure 35B] FIG. 35B is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 35A. [Figure 35C] FIG. 35C is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 35B. [Figure 35D] FIG. 35D is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 35C. [Figure 35E] FIG. 35B is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 35D. [Figure 35F] FIG. 35B is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 35E. [Figure 35G]FIG. 35C is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 35F. [Figure 35H] FIG. 35B is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 35G. [Figure 35I] FIG. 35C is a schematic cross-sectional view showing an example of the manufacturing process following FIG. 35H. [Figure 36] FIG. 13 is a diagram illustrating an example of a vertical cross-sectional configuration of an imaging element according to a sixth modification of the present disclosure. [Figure 37] FIG. 13 is a diagram illustrating an example of a vertical cross-sectional configuration of an imaging element according to a seventh modification of the present disclosure. [Figure 38] FIG. 13 is a diagram illustrating an example of a horizontal cross-sectional configuration of an imaging element according to Modification 8 of the present disclosure. [Figure 39] FIG. 20 is a diagram illustrating another example of the horizontal cross-sectional configuration of an imaging element according to Modification 8 of the present disclosure. [Figure 40] FIG. 13 is a diagram illustrating an example of a horizontal cross-sectional configuration of an imaging element according to a ninth modification of the present disclosure. [Figure 41] FIG. 23 is a diagram illustrating an example of a horizontal cross-sectional configuration of an imaging element according to a tenth modification of the present disclosure. [Figure 42] FIG. 23 is a diagram illustrating an example of a horizontal cross-sectional configuration of an imaging element according to an eleventh modification of the present disclosure. [Figure 43] FIG. 23 is a diagram illustrating another example of the horizontal cross-sectional configuration of an imaging element according to the eleventh modification of the present disclosure. [Figure 44] FIG. 23 is a diagram illustrating another example of the horizontal cross-sectional configuration of an imaging element according to the eleventh modification of the present disclosure. [Figure 45] FIG. 23 is a diagram illustrating an example of a circuit configuration of an image sensor according to a twelfth modification of the present disclosure. [Figure 46] FIG. 46 is a diagram illustrating an example in which the imaging element of FIG. 45 according to Modification 13 of the present disclosure is configured by stacking three substrates. [Figure 47] FIG. 23 is a diagram illustrating an example in which a logic circuit according to a fourteenth modification of the present disclosure is formed separately on a substrate on which sensor pixels are provided and a substrate on which a readout circuit is provided. [Figure 48] FIG. 23 is a diagram illustrating an example in which a logic circuit according to a fifteenth modification of the present disclosure is formed on a third substrate. [Figure 49] FIG. 1 is a diagram illustrating an example of a schematic configuration of an imaging system including an imaging element according to the above embodiment and its modified example. [Figure 50] 50 is a diagram showing an example of an imaging procedure in the imaging system of FIG. 49. [Figure 51] 1A and 1B are diagrams illustrating an outline of exemplary configurations of a non-stacked solid-state imaging element and a stacked solid-state imaging element to which the technology according to the present disclosure can be applied. [Figure 52] 1 is a cross-sectional view showing a first configuration example of a stacked solid-state imaging element. [Figure 53] FIG. 10 is a cross-sectional view showing a second configuration example of a stacked solid-state imaging element. [Figure 54] FIG. 10 is a cross-sectional view showing a third configuration example of a stacked solid-state imaging element. [Figure 55] FIG. 10 is a cross-sectional view showing another example of the configuration of a stacked solid-state imaging element to which the technology according to the present disclosure can be applied. [Figure 56] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 57] FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. [Figure 58] FIG. 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 59] FIG. 2 is a block diagram showing an example of the functional configuration of a camera head and a CCU. DETAILED DESCRIPTION OF THE INVENTION

[0010] An embodiment of the present disclosure will be described in detail below with reference to the drawings. The following description is a specific example of the present disclosure, and the present disclosure is not limited to the following aspects. Furthermore, the present disclosure is not limited to the arrangement, dimensions, dimensional ratios, etc. of each component shown in each drawing. The order of description is as follows. 1. Embodiment (Example of a wiring structure extending in one direction and having gaps between adjacent wirings and near the end faces of barrier films provided on the wirings) 1-1. Wiring structure configuration 1-2. Manufacturing method of wiring structure 1-3. Image sensor configuration 1-4. Manufacturing method of image sensor 1-5. Actions and Effects 2. Variations 2-1. Modification 1 (another example of wiring structure) 2-2. Modification 2 (another example of wiring structure) 2-3. Modification 3 (another example of wiring structure) 2-4. Modification 4 (another example of wiring structure) 2-5. Modification 5 (another example of wiring structure) 2-6. Variation 6 (Example using a planar TG) 2-7. Variation 7 (Example of Cu-Cu bonding at the outer edge of the panel) 2-8. Modification 8 (Example of providing an offset between sensor pixels and readout circuit) 2-9. Modification 9 (Example in which the silicon substrate on which the readout circuit is provided is island-shaped) 2-10. Modification 10 (Example in which the silicon substrate on which the readout circuit is provided is island-shaped) 2-11. Modification 11 (Example of FD shared by eight sensor pixels) 2-12. Modification 12 (Example in which the column signal processing circuit is configured with a general column ADC circuit) 2-13. Modification 13 (imaging device, Three (Example of a structure in which the above substrates are stacked) 2-14. Modification 14 (Example in which logic circuits are provided on the first and second substrates) 2-15. Variation 15 (Logic circuit Third board (Example provided in 3. Application Examples 4. Application Examples

[0011] <1. Embodiment> FIG. 1 is a schematic diagram illustrating an example of a vertical cross-sectional configuration of a wiring structure (wiring structure 100) according to an embodiment of the present disclosure. FIG. 2 is a schematic diagram illustrating an example of a horizontal cross-sectional configuration of the wiring structure 100 shown in FIG. 1. FIG. 1 corresponds to a cross section taken along line II in FIG. 2. FIG. 3 is a schematic diagram illustrating an example of a cross-sectional configuration of the wiring structure 100 shown in FIG. 1, for example, taken along line II-II in FIG. 2. The wiring structure 100 has, for example, a multilayer wiring structure in which multiple wiring layers are stacked, and is applicable, for example, to an image sensor 1 described below.

[0012] The wiring structure 100 includes a wiring layer 112 having a plurality of wirings (e.g., wirings 112X1 to 112X6) extending in one direction (e.g., the Y-axis direction), and a barrier film 121 and an insulating film 123 stacked in this order on the wiring layer 112. The barrier film 121 extends, for example, on the wiring layer 112 and has end faces S121 on the wirings 112X2 and 112X5, for example. The insulating film 123 is stacked above the barrier film 121 and is provided so as to fill openings H2 provided between adjacent wirings (e.g., between adjacent wirings 112X2 and 112X3, between wirings 112X3 and 112X4, and between wirings 112X4 and 112X5). In the present embodiment, gaps G1 are provided within the opening H2 between adjacent wirings 112X2 and 112X3, between wirings 112X3 and 112X4, and between wirings 112X4 and 112X5. Furthermore, end faces S121 of the barrier film 121 are formed, and gaps G2 are provided above the wirings 112X2 and 112X5 and near the end faces S121. The multiple wirings 112X1 to 112X6 and the wiring layer 112 correspond to specific examples of "first wirings" and "first wiring layer" in the present disclosure. The barrier film 121 corresponds to a specific example of a "first barrier film" in the present disclosure, and the insulating film 123 corresponds to a specific example of a "first insulating film" in the present disclosure. The gap G1 corresponds to a specific example of a "first gap" in the present disclosure, and the gap G2 corresponds to a specific example of a "second gap" in the present disclosure.

[0013] (1-1. Wiring structure configuration) The wiring structure 100 has a configuration in which a first layer 110 and a second layer 120 are laminated in this order on, for example, a silicon substrate (not shown).

[0014] The first layer 110 is formed by embedding a plurality of wirings (for example, wirings 112X1 to 112X6) in an insulating film 111.

[0015] The insulating film 111 is formed using, for example, a low-dielectric-constant material (low-k material) having a relative dielectric constant (k) of 3.0 or less. Specifically, examples of the material for the insulating film 111 include carbon-containing silicon dioxide (SiOC), SiOCH, porous silica, fluorine-doped silicon dioxide (SiOF), inorganic SOG, organic SOG, and organic polymers such as polyallyl ether.

[0016] The wiring layer 112 includes, for example, a plurality of wirings extending in one direction, such as wirings 112X1 to 112X6 extending in the Y-axis direction. The wirings 112X1 to 112X6 are formed in parallel with a line (L) / space (S) ratio of 40 to 200 nm / 40 to 200 nm, for example. The wirings 112X1 to 112X6 are embedded in an opening H1 provided in the insulating film 111, and are composed of, for example, a barrier metal 112A formed on the side and bottom surfaces of the opening H1 and a metal film 112B filling the opening H1. Examples of materials for the barrier metal 112A include simple substances such as Ti (titanium) or Ta (tantalum), or nitrides or alloys thereof. Examples of materials for the metal film 112B include metal materials mainly composed of low-resistance metals such as Cu (copper), W (tungsten), or aluminum (Al).

[0017] The first layer 110 further includes a gap between adjacent wirings, specifically, for example, between the wiring 112X2 and the wiring 112X3, between the wiring 112X3 and the wiring 112X4, and between the wiring 112X5 and the wiring 112X6. Wiring 112X4 An opening H2 is provided in the insulating film 111 between the wiring 112X5 and the wiring 112X6.

[0018] The second layer 120 is formed by laminating a barrier film 121 and a plurality of insulating films (insulating films 122 to 126), and for example, a conductive film 127 is embedded in the uppermost insulating film 126. Specifically, from the first layer 110 side, the barrier film 121, insulating film 122, insulating film 123, insulating film 124, insulating film 125, and insulating film 126 are laminated in this order. Wiring 112X4 The opening H2 provided between the wiring 112X2 and the wiring 112X3, the wiring 112X3 and the wiring 112X4, and the wiring 112X5 are closed by the insulating film 123 that constitutes the second layer 120. Wiring 112X4 and the wiring 112X5, a gap G1 is formed between the wiring 112X2 and the wiring 112X3, between the wiring 112X3 and the wiring 112X4, and between the wiring 112X5 and the wiring 112X6, as shown in FIG. Wiring 112X4 The gap G1 is formed in a partial region or over the entire area between the wiring 112X2 and the wiring 112X3, between the wiring 112X3 and the wiring 112X4, and between the wiring 112X5 and the wiring 112X6. Wiring 112X4 and the wiring 112X5, as shown in FIG. 2, they can also be formed between other wirings extending in the Y-axis direction together with the wirings 112X1 to 112X6 (gap forming region 100X).

[0019] The barrier film 121 is intended to prevent diffusion of copper (Cu) and infiltration of moisture when, for example, the interconnects 112X1 to 112X6 are formed using copper (Cu). The barrier film 121 extends over the interconnect layer 112, with the exception of a portion thereof. Specifically, the barrier film 121 is provided so as to cover, except for the opening H2, the insulating film 111, the embedded interconnects 112X1 and 112X6, and portions of the interconnects 112X2 and 112X5 having the opening H2 between them. In other words, the barrier film 121 is formed outside the opening H2 and has an end face S121 above the interconnects 112X2 and 112X5. As a result, above the wiring 112X2 and the wiring 112X5, a step is formed by the upper surfaces of the wirings 112X2 and 112X5 and the end face S121 and upper surface of the barrier film 121, respectively, and when the step is covered with the insulating film 123, a gap G2 that reduces the capacitance near the parallel wirings is formed in a self-aligned manner near the step, specifically above the wiring 112X2 and the wiring 112X5 and near the end face S121. The barrier film 121 is made of, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), SiC x N y The insulating film is formed using silicon carbide (SiC), silicon oxynitride (SiON, SiNO), aluminum oxynitride (AlNO), aluminum nitride (AlN), or the like.

[0020] The insulating film 122, like the barrier film 121, serves to prevent diffusion of copper (Cu) and infiltration of moisture when the wirings 112X1 to 112X6 are formed using copper (Cu), for example. The insulating film 122 corresponds to a specific example of a "second insulating film" in the present disclosure, and is provided on the barrier film 121 and further extends to cover the side and bottom surfaces of the opening H2. As described above, the insulating film 122 is formed of an insulating material that prevents diffusion of copper (Cu) and infiltration of moisture, using, for example, a manufacturing method with low step coverage. Specifically, the insulating film 122 is formed of, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON, SiNO) or SiC x Ny The above are formed by using, for example, a CVD method or a coating method using a spin coater.

[0021] The insulating film 123 is provided on the insulating film 122 and is also provided between the wirings in the opening H2 (specifically, between the wiring 112X2 and the wiring 112X3, between the wiring 112X3 and the wiring 112X4, and Wiring 112X4 and the wiring 112X5) and above the wiring 112X2 and the wiring 112X5, and in the vicinity of the end face S121 of the barrier film 121. The insulating film 123 has low coverage and is formed using, for example, a low-k material with a relative dielectric constant (k) of 3.0 or less. Specifically, examples of the material for the insulating film 123 include carbon-containing silicon dioxide (SiOC), SiOCH, porous silica, fluorine-doped silicon dioxide (SiOF), inorganic SOG, organic SOG, and organic polymers such as polyallyl ether.

[0022] The insulating film 124 corresponds to a specific example of a "third insulating film" of the present disclosure. The insulating film 124 is provided on the insulating film 123 and is formed between the gaps G1 and G2 of the insulating film 123. 2 Fill the unevenness above and fill the gaps G1 and G 2 The insulating film 124 is formed on the upper surface to form a flat surface on which devices can be stacked using hybrid bonding such as Cu-Cu bonding, as will be described in detail later. The insulating film 124 is preferably made of a material that has a higher polishing rate than the insulating film 123 and a relative dielectric constant (k) of approximately 4.0. Examples of such materials include silicon oxide (SiO x ), carbon-containing silicon oxide (SiOC), fluorine-doped silicon oxide (SiOF), silicon oxynitride (SiON), etc. The insulating film 124 may be a single layer film made of one of the above materials, or may be formed as a laminated film made of two or more of them.

[0023] The insulating film 125 is intended to reduce warpage due to stress that occurs when a conductive film 127, which will be described later, is formed. The insulating film 125 is formed by, for example, a CVD (Chemical Vapor Deposition) method, and is made of, for example, silicon oxide (SiO x ), silicon nitride (SiN x ) or the like.

[0024] The insulating film 126 is provided on the insulating film 125, and forms, for example, a bonding surface between the second substrate 20 and the third substrate 30 of the image sensor 1, which will be described later. As a material for the insulating film 126, it is preferable to use a material that has a higher polishing rate than the insulating film 123 and a relative dielectric constant (k) of, for example, about 4.0, so that the bonding surface can be flattened. Such a material can be, for example, silicon oxide (SiO x ), SiOC, SiOF, SiON, etc. The insulating film 126 may be a single layer film made of one of the above materials, or may be formed as a laminated film made of two or more of them.

[0025] The conductive film 127 corresponds to the "first conductive film" of the present disclosure. The conductive film 127 is, for example, a wiring layer provided directly on the wiring layer 112 having the wirings 112X1 to 112X6 extending in one direction. For example, the conductive film 127 is formed by filling an opening H3 provided in a part of the insulating film 126 and the insulating film 125, and is flush with the insulating film 126. The conductive film 127 has a plurality of conductive films (for example, the conductive film 127X1 and the conductive film 127X2), and at least a part of the conductive films 127 extend in one direction and are provided so as to face at least a part of the wirings 112X1 to 112X6. As an example, in FIG. 1, the conductive film 127X1 is formed in a position facing the wirings 112X2, 112X3, and 112X4 having the gap G1 between them, and extends in the Y-axis direction, similar to the wirings 112X2 and 112X3. An opening H4 is provided in the opening H3, penetrating through the barrier film 121 to the insulating film 125 and reaching the wiring 112X1. The conductive film 127X1 is also embedded in this opening H4 and is electrically connected to the wiring 112X1. Note that the conductive film 127 may be formed above a wiring (e.g., wiring 112X6) that does not have a gap G1 formed therebetween, like the conductive film 127X2 (not shown in FIG. 2) shown in FIGS. 1 and 3.

[0026] Conductive film 127 is composed of barrier metal 127A formed on the side and bottom surfaces of openings H3 and H4, and metal film 127B filling openings H3 and H4. Examples of materials for barrier metal 127A include simple substances such as Ti (titanium) or Ta (tantalum), or nitrides or alloys thereof. Examples of materials for metal film 127B include metal materials primarily composed of low-resistance metals such as Cu (copper), W (tungsten), or aluminum (Al).

[0027] (1-2. Manufacturing method of wiring structure) First, the wiring layer 112 including the wirings 112X1 to 112X6 is embedded in the insulating film 111, and then the surface is polished using, for example, CMP (Chemical Mechanical Polishing) to form the first layer 110. Next, as shown in Fig. 4A, a barrier film 121 is formed on the first layer 110 using, for example, PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition) to a thickness of, for example, 10 nm to 50 nm.

[0028] 4B, photolithography is used to pattern a resist film 131 having openings at positions corresponding to the wirings 121X2 to 112X5 on the barrier film 121. Subsequently, as shown in FIG. 4C, the barrier film 121, parts of the wirings 112X2 to 112X5, and the insulating film 111 exposed from the resist film 131 are subjected to, for example, dry etching to form openings H2.

[0029] At this time, it is preferable to process the end surface S121 of the barrier film 121 formed by the opening H2 so that the upper part of the end surface does not have a forward tapered shape that is inclined outward from the opening H2. Specifically, it is preferable to process the end surface S121 of the barrier film 121 so that it is perpendicular to the surface of the wiring layer 112, for example. As a processing condition for this, for example, in dry etching, reaction products generated during etching tend to adhere to the sidewalls and form a tapered shape, so that the pressure and process gas are adjusted to promote the removal of the reaction products. As a result, the end surface S121 of the barrier film 121 is processed into a desired shape (vertical), and a gap G2 can be formed near the end surface S121 of the barrier film 121 when the insulating film 123 described below is formed.

[0030] Next, after removing the resist film 131, as shown in FIG. 4D, an insulating film 122 is formed to a thickness of, for example, 5 nm to 50 nm by using, for example, a CVD method, covering the barrier film 121 and the side and bottom surfaces of the opening H2. Subsequently, as shown in FIG. 4E, an insulating film 123 made of, for example, SiOC or silicon nitride and having a thickness of, for example, 100 nm to 500 nm is formed by using, for example, a CVD method. This closes the opening H2, and the gaps between the wiring 112X2 and the wiring 112X3, between the wiring 112X3 and the wiring 112X4, and between the wiring 112X4 and the wiring 112X5 are formed. Wiring 112X5 Gaps G1 and G2 are formed between the wiring 112X1 and the wiring 112X2 and above the wiring 112X5 and in the vicinity of the end surface S121 of the barrier film 121, respectively.

[0031] Next, as shown in FIG. 4F, a film such as SiO 2 is deposited on the insulating film 123 by using, for example, a CVD method. x 4G, the insulating film 124 is polished by, for example, CMP to flatten the surface.

[0032] Next, insulating film 125 is formed on insulating film 124 using, for example, a CVD method to a thickness of, for example, 50 nm to 500 nm, and then insulating film 126 is formed on insulating film 125 using, for example, a CVD method to a thickness of, for example, 100 nm to 2 μm. Subsequently, using the same method as for opening H2, insulating films 126 and a portion of insulating film 125 are dry-etched to form opening H3, and then opening H4 is formed in opening H3, penetrating barrier film 121 through insulating film 125 and reaching interconnect 112X1. Next, barrier metal 127A is formed on the side and bottom surfaces of openings H3 and H4 using, for example, sputtering, and then metal film 127B is formed in openings H3 and H4 using, for example, plating. Finally, barrier metal 127A and metal film 127B formed on insulating film 126 are polished and removed to form a flat surface where insulating film 126 and conductive film 127 form the same plane. Through the above steps, the wiring structure 100 shown in FIG. 1 is completed.

[0033] (1-3. Image sensor configuration) FIG. 5 illustrates an example of a vertical cross-sectional configuration of an image sensor (image sensor 1) according to an embodiment of the present disclosure. FIG. 6 illustrates an example of a schematic configuration of the image sensor 1 illustrated in FIG. 5. The image sensor 1 is an image sensor having a three-dimensional structure in which a first substrate 10 having sensor pixels 12 that perform photoelectric conversion on a semiconductor substrate 11, a second substrate 20 having readout circuits 22 that output image signals based on charges output from the sensor pixels 12 on a semiconductor substrate 21, and a third substrate 30 having logic circuits 32 that process the pixel signals on a semiconductor substrate 31 are stacked. The wiring structure 100 described above is applied to, for example, a wiring structure near the bonding surface of the second substrate 20 that is bonded to the third substrate 30, as illustrated in FIG. 7.

[0034] As described above, the first substrate 10 has, on its semiconductor substrate 11, a plurality of sensor pixels 12 that perform photoelectric conversion. The plurality of sensor pixels 12 are arranged in a matrix within the pixel region 13 of the first substrate 10. The second substrate 20 has, on its semiconductor substrate 21, readout circuits 22 that output pixel signals based on the charges output from the sensor pixels 12, one for every four sensor pixels 12. The second substrate 20 has, on its semiconductor substrate 21, a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. The third substrate 30 has, on its semiconductor substrate 31, a logic circuit 32 that processes pixel signals. The logic circuit 32 has, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 (specifically, the horizontal drive circuit 35) outputs an output voltage Vout for each sensor pixel 12 to the outside. In the logic circuit 32, for example, a low-resistance region made of silicide formed using a salicide (self-aligned silicide) process using CoSi2, NiSi, or the like may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode. In this embodiment, the semiconductor substrate 11 corresponds to a specific example of a "first semiconductor substrate" in the present disclosure, and the first substrate 10 corresponds to a specific example of a "first substrate" in the present disclosure. The semiconductor substrate 31 corresponds to a specific example of a "second semiconductor substrate" in the present disclosure, and the third substrate 30 corresponds to a specific example of a "second substrate" in the present disclosure. Note that the second substrate 20 including the semiconductor substrate 21 can be considered to be included in the "first substrate" and "second substrate" in the present disclosure.

[0035] The vertical drive circuit 33, for example, sequentially selects a plurality of sensor pixels 12 row by row. The column signal processing circuit 34, for example, performs correlated double sampling (CDS) processing on pixel signals output from each sensor pixel 12 in the row selected by the vertical drive circuit 33. The column signal processing circuit 34 extracts signal levels of the pixel signals by performing CDS processing, for example, and holds pixel data corresponding to the amount of light received by each sensor pixel 12. The horizontal drive circuit 35, for example, sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside. The system control circuit 36, for example, controls the driving of each block (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35) in the logic circuit 32.

[0036] Fig. 8 shows an example of the sensor pixels 12 and the readout circuit 22. Below, a case will be described in which four sensor pixels 12 share one readout circuit 22, as shown in Fig. 8. Here, "shared" means that the outputs of the four sensor pixels 12 are input to a common readout circuit 22.

[0037] The sensor pixels 12 have common components. In Fig. 8, in order to distinguish the components of the sensor pixels 12 from one another, identification numbers (1, 2, 3, 4) are added to the end of the reference numerals of the components of the sensor pixels 12. Hereinafter, when it is necessary to distinguish the components of the sensor pixels 12 from one another, identification numbers are added to the end of the reference numerals of the components of the sensor pixels 12. However, when it is not necessary to distinguish the components of the sensor pixels 12 from one another, the identification numbers at the end of the reference numerals of the components of the sensor pixels 12 are omitted.

[0038] Each sensor pixel 12 includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD performs photoelectric conversion to generate a charge according to the amount of received light. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to a pixel drive line 23. The transfer transistor TR is, for example, a CMOS (Complementary Metal Oxide Semiconductor) transistor.

[0039] The floating diffusions FD of the sensor pixels 12 that share one readout circuit 22 are electrically connected to each other and to an input terminal of the common readout circuit 22. The readout circuit 22 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. The selection transistor SEL may be omitted if necessary. The source of the reset transistor RST (the input terminal of the readout circuit 22) is electrically connected to the floating diffusion FD, and the drain of the reset transistor RST is electrically connected to a power supply line VDD and the drain of the amplification transistor AMP. The gate of the reset transistor RST is electrically connected to a pixel drive line 23. The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the readout circuit 22) is electrically connected to a vertical signal line 24, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23.

[0040] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD. The gate (transfer gate TG) of the transfer transistor TR extends from the surface of the semiconductor substrate 11 through the p-well layer 42 to a depth reaching the PD 41, as shown in FIG. 5 , for example. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 22. The amplification transistor AMP generates a pixel signal with a voltage corresponding to the level of the charge held in the floating diffusion FD. The amplification transistor AMP constitutes a source-follower amplifier and outputs a pixel signal with a voltage corresponding to the level of the charge generated in the photodiode PD. When the select transistor SEL is turned on, the amplifier transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the column signal processing circuit 34 via the vertical signal line 24. The reset transistor RST, the amplifier transistor AMP, and the select transistor SEL are, for example, CMOS transistors.

[0041] As shown in FIG. 9, the select transistor SEL may be provided between the power supply line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the select transistor SEL. The source of the select transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the select transistor SEL is electrically connected to the pixel drive line 23. The source of the amplifier transistor AMP (the output terminal of the readout circuit 22) is electrically connected to the vertical signal line 24, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST. Furthermore, as shown in FIGS. 10 and 11, an FD transfer transistor FDG may be provided between the source of the reset transistor RST and the gate of the amplifier transistor AMP.

[0042] The FD transfer transistor FDG is used to change the conversion efficiency. Generally, pixel signals are small when shooting in dark locations. Based on Q = CV, when performing charge-to-voltage conversion, if the capacitance of the floating diffusion FD (FD capacitance C) is large, the V when converted to voltage by the amplifier transistor AMP will be small. On the other hand, in bright locations, pixel signals are large, so if the FD capacitance C is not large, the floating diffusion FD cannot fully absorb the charge from the photodiode PD. Furthermore, the FD capacitance C must be large so that the V when converted to voltage by the amplifier transistor AMP does not become too large (in other words, to reduce it). Considering these factors, when the FD transfer transistor FDG is turned on, the gate capacitance of the FD transfer transistor FDG increases, increasing the overall FD capacitance C. On the other hand, when the FD transfer transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the FD transfer transistor FDG on and off, the FD capacitance C can be varied, thereby changing the conversion efficiency.

[0043] 12 shows an example of a connection between a plurality of readout circuits 22 and a plurality of vertical signal lines 24. When a plurality of readout circuits 22 are arranged side by side in the extension direction of the vertical signal lines 24 (e.g., the column direction), a plurality of vertical signal lines 24 may be assigned to each readout circuit 22. For example, as shown in FIG. 12, when four readout circuits 22 are arranged side by side in the extension direction of the vertical signal lines 24 (e.g., the column direction), a plurality of vertical signal lines 24 may be assigned to each readout circuit 22. Note that in FIG. 12, identification numbers (1, 2, 3, 4) are added to the end of the reference numerals of the vertical signal lines 24 to distinguish them from one another.

[0044] Next, the vertical cross-sectional configuration of the image sensor 1 will be described with reference to Fig. 5. As described above, the image sensor 1 has a configuration in which the first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order, and further includes a color filter 40 and a light-receiving lens 50 on the back surface (light incident surface) side of the first substrate 10. For example, one color filter 40 and one light-receiving lens 50 are each provided for each sensor pixel 12. In other words, the image sensor 1 is a back-illuminated image sensor.

[0045] The first substrate 10 is formed by laminating an insulating layer 46 on the surface (surface 11S1) of the semiconductor substrate 11. The first substrate 10 has the insulating layer 46 as part of an interlayer insulating film 51. The insulating layer 46 is provided between the semiconductor substrate 11 and a semiconductor substrate 21, which will be described later. The semiconductor substrate 11 is formed of a silicon substrate. The semiconductor substrate 11 has, for example, a p-well layer 42 in and near a part of the surface, and has a PD 41 of a different conductivity type from the p-well layer 42 in the other region (a region deeper than the p-well layer 42). The p-well layer 42 is formed of a p-type semiconductor region. The PD 41 is formed of a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42. The semiconductor substrate 11 has a floating diffusion FD in the p-well layer 42 as a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42.

[0046] The first substrate 10 has a photodiode PD, a transfer transistor TR, and a floating diffusion FD for each sensor pixel 12. The first substrate 10 is configured such that the transfer transistor TR and the floating diffusion FD are provided on a part of the surface 11S1 side of the semiconductor substrate 11 (the side opposite to the light incident surface, the second substrate 20 side). The first substrate 10 has an element isolation portion 43 that isolates each sensor pixel 12. The element isolation portion 43 is formed to extend in the normal direction of the semiconductor substrate 11 (a direction perpendicular to the surface of the semiconductor substrate 11). The element isolation portion 43 is provided between two adjacent sensor pixels 12. The element isolation portion 43 electrically isolates the adjacent sensor pixels 12 from each other. The element isolation portion 43 is made of, for example, silicon oxide. The element isolation portion 43 penetrates, for example, the semiconductor substrate 11. The first substrate 10 further includes, for example, a p-well layer 44 that is a side surface of the element isolation portion 43 and is in contact with the surface on the photodiode PD side. The p-well layer 44 is composed of a semiconductor region of a different conductivity type (specifically, p-type) from the photodiode PD. The first substrate 10 further includes, for example, a fixed charge film 45 that is in contact with the back surface (surface 11S2, other surface) of the semiconductor substrate 11. The fixed charge film 45 is negatively charged to suppress the generation of dark current due to interface states on the light-receiving surface side of the semiconductor substrate 11. The fixed charge film 45 is formed, for example, of an insulating film having a negative fixed charge. Examples of materials for such an insulating film include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. An electric field induced by the fixed charge film 45 forms a hole accumulation layer at the interface on the light-receiving surface side of the semiconductor substrate 11. This hole accumulation layer suppresses the generation of electrons from the interface. The color filter 40 is provided on the back surface side of the semiconductor substrate 11. The color filter 40 is provided, for example, in contact with the fixed charge film 45, and is provided at a position facing the sensor pixel 12 across the fixed charge film 45. The light receiving lens 50 is provided, for example, in contact with the color filter 40, and is provided at a position facing the sensor pixel 12 across the color filter 40 and the fixed charge film 45.

[0047] The second substrate 20 is configured by laminating an insulating layer 52 on the semiconductor substrate 21. The second substrate 20 has the insulating layer 52 as part of an interlayer insulating film 51. The insulating layer 52 is provided between the semiconductor substrate 21 and the semiconductor substrate 31. The semiconductor substrate 21 is configured as a silicon substrate. The second substrate 20 has one readout circuit 22 for every four sensor pixels 12. The second substrate 20 is configured such that the readout circuit 22 is provided on a part of the front surface (the surface 21S1, one surface, facing the third substrate 30) of the semiconductor substrate 21. The second substrate 20 is bonded to the first substrate 10 with the back surface (surface 21S2) of the semiconductor substrate 21 facing the front surface (surface 11S1) of the semiconductor substrate 11. In other words, the second substrate 20 is bonded to the first substrate 10 face-to-back. The second substrate 20 further includes an insulating layer 53 that penetrates the semiconductor substrate 21 in the same layer as the semiconductor substrate 21. The second substrate 20 includes the insulating layer 53 as part of the interlayer insulating film 51. The insulating layer 53 is provided so as to cover the side surfaces of the through wiring 54 described below.

[0048] The stacked body made up of the first substrate 10 and the second substrate 20 has an interlayer insulating film 51 and through-wiring 54 provided in the interlayer insulating film 51. The stacked body has one through-wiring 54 for each sensor pixel 12. The through-wiring 54 extends in the normal direction of the semiconductor substrate 21 and is provided so as to penetrate a portion of the interlayer insulating film 51 that includes the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other by the through-wiring 54. Specifically, the through-wiring 54 is electrically connected to the floating diffusion FD and a connection wiring 55, which will be described later.

[0049] The stacked body made up of the first substrate 10 and the second substrate 20 further has through-hole wires 47, 48 (see FIG. 13 described later) provided in the interlayer insulating film 51. The stacked body has one through-hole wire 47 and one through-hole wire 48 for each sensor pixel 12. The through-hole wires 47, 48 each extend in the normal direction of the semiconductor substrate 21 and penetrate a portion of the interlayer insulating film 51 that includes the insulating layer 53. The first substrate 10 and the second substrate 20 are electrically connected to each other by the through-hole wires 47, 48. Specifically, the through-hole wire 47 is electrically connected to the p-well layer 42 of the semiconductor substrate 11 and the wiring in the second substrate 20. The through-hole wire 48 is electrically connected to the transfer gate TG and the pixel drive line 23.

[0050] The second substrate 20 has, for example, a plurality of connection portions 59 electrically connected to the readout circuit 22 and the semiconductor substrate 21 within the insulating layer 52. The second substrate 20 further has, for example, a wiring layer 56 on the insulating layer 52. The wiring layer 56 has, for example, an insulating layer 57 and a plurality of pixel drive lines 23 and a plurality of vertical signal lines 24 provided within the insulating layer 57. The wiring layer 56 further has, for example, a plurality of connection wires 55 within the insulating layer 57, one for each of four sensor pixels 12. The connection wires 55 electrically connect the through wires 54 electrically connected to the floating diffusions FD included in the four sensor pixels 12 that share the readout circuit 22. Here, the total number of the through wires 54, 48 is greater than the total number of sensor pixels 12 included in the first substrate 10 and is twice the total number of sensor pixels 12 included in the first substrate 10. Furthermore, the total number of the through wires 54, 48, and 47 is greater than the total number of the sensor pixels 12 included in the first substrate 10, and is three times the total number of the sensor pixels 12 included in the first substrate 10.

[0051] The wiring layer 56 further includes, for example, a plurality of pad electrodes 58 in the insulating layer 57. Each pad electrode 58 is formed of a metal such as copper (Cu), tungsten (W), or aluminum (Al). Each pad electrode 58 is exposed on the surface of the wiring layer 56. Each pad electrode 58 is used for electrically connecting the second substrate 20 and the third substrate 30 and for bonding the second substrate 20 and the third substrate 30 together. The plurality of pad electrodes 58 are provided, for example, one for each pixel driving line 23 and vertical signal line 24. Here, the total number of pad electrodes 58 (or the total number of junctions between pad electrodes 58 and pad electrodes 64 (described later)) is, for example, smaller than the total number of sensor pixels 12 included in the first substrate 10.

[0052] FIG. 7 is a schematic diagram illustrating a cross-sectional configuration when the wiring structure 100 is applied to the image sensor 1. In this embodiment, for example, the vertical signal lines 24 correspond to the lines 112X3 and 112X4 in the wiring structure 100, and the power supply lines VSS correspond to the lines 112X2 and 112X5 in the wiring structure 100. Although not shown in FIG. 5, the insulating layer 57 includes a plurality of insulating films 151 to 157, including a barrier film 152, as shown in FIG. 7. The insulating film 154 among them forms gaps G1 and G2 between the parallel-running power supply lines VSS and the vertical signal lines 24, between the parallel-running vertical signal lines 24, above the vertical signal lines 24, and near the end faces of the barrier film 152. The pad electrodes 58 exposed on the surface of the wiring layer 56 correspond to the conductive films 127X1 and 127X2 in the wiring structure 100.

[0053] Some (pad electrodes 58X1) of the pad electrodes 58 are electrically connected to a ground line (wiring 112X1). The ground line is connected to, for example, a p-well or ground (GND) of the semiconductor substrate 11, although not shown. This allows the pad electrodes 58X1 to be used as shield wiring in the stacking direction of the vertical signal lines 24, making it possible to reduce noise generation in the vertical signal lines 24.

[0054] Furthermore, the pad electrode 58X1 functioning as the shield wiring is joined to a pad electrode 64X1 on the third substrate 30, which will be described later. This allows the impedance of the shield wiring to be reduced compared to when the shield wiring is formed by the pad electrode 58X1 alone. Furthermore, the pad electrode 58X1 functioning as the shield wiring is provided so as to traverse the pixel region 13, similar to the vertical signal line 24, for example, and terminates near the periphery beyond the edge of the pixel region 13.

[0055] The third substrate 30 is configured, for example, by laminating an interlayer insulating film 61 on a semiconductor substrate 31. As described below, the third substrate 30 is bonded to the second substrate 20 with their front surfaces facing each other. Therefore, when describing the internal configuration of the third substrate 30, the up-down direction is reversed from the up-down direction in the drawings. The semiconductor substrate 31 is configured as a silicon substrate. The third substrate 30 is configured such that a logic circuit 32 is provided on a portion of the front surface (surface 31S1) of the semiconductor substrate 31. The third substrate 30 further includes, for example, a wiring layer 62 on the interlayer insulating film 61. The wiring layer 62 includes, for example, an insulating layer 63 and a plurality of pad electrodes 64 (e.g., pad electrodes 64X1 and 64X2) provided in the insulating layer 63. The plurality of pad electrodes 64 are electrically connected to the logic circuit 32. Each pad electrode 64 is formed of, for example, Cu (copper). Each pad electrode 64 is exposed on the surface of the wiring layer 62. Each pad electrode 64 is used to electrically connect the second substrate 20 and the third substrate 30 and to bond the second substrate 20 and the third substrate 30 together. The number of pad electrodes 64 does not necessarily need to be multiple; even one pad electrode 64 can be electrically connected to the logic circuit 32. The second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58 and 64 together. That is, the gate (transfer gate TG) of the transfer transistor TR is electrically connected to the logic circuit 32 via the through wiring 54 and the pad electrodes 58 and 64. The third substrate 30 is bonded to the second substrate 20 with the surface (surface 31S1) of the semiconductor substrate 31 facing the surface (surface 21S1) of the semiconductor substrate 21. That is, the third substrate 30 is bonded to the second substrate 20 face-to-face.

[0056] 13 and 14 illustrate an example of a horizontal cross-sectional configuration of the image sensor 1. The upper views of FIGS. 13 and 14 illustrate an example of a cross-sectional configuration at cross section Sec1 in FIG. 1, and the lower views of FIGS. 13 and 14 illustrate an example of a cross-sectional configuration at cross section Sec2 in FIG. 1. FIG. 13 illustrates a configuration in which two sets of four 2×2 sensor pixels 12 are arranged in the second direction H, and FIG. 14 illustrates a configuration in which four sets of four 2×2 sensor pixels 12 are arranged in the first direction V and the second direction H. Note that in the upper cross-sectional views of FIGS. 13 and 14, a diagram illustrating an example of a surface configuration of the semiconductor substrate 11 is superimposed on a diagram illustrating an example of the cross-sectional configuration at cross section Sec1 in FIG. 1, and the insulating layer 46 is omitted. In the lower cross-sectional views of FIGS. 13 and 14, a diagram illustrating an example of a surface configuration of the semiconductor substrate 21 is superimposed on a diagram illustrating an example of the cross-sectional configuration at cross section Sec2 in FIG. 1.

[0057] As shown in FIGS. 13 and 14 , the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in a strip shape in a first direction V (the vertical direction in FIG. 13 , the horizontal direction in FIG. 14 ) within the plane of the first substrate 10. Note that FIGS. 13 and 14 illustrate an example in which the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in two columns in the first direction V. The first direction V is parallel to one of two arrangement directions (e.g., the row direction and the column direction) of the plurality of sensor pixels 12 arranged in a matrix (e.g., the column direction). In the four sensor pixels 12 sharing the readout circuit 22, the four floating diffusions FD are arranged close to each other, for example, via the element isolation portion 43. In the four sensor pixels 12 sharing the readout circuit 22, the four transfer gates TG are arranged to surround the four floating diffusions FD, and for example, the four transfer gates TG form a ring shape.

[0058] The insulating layer 53 is composed of multiple blocks extending in a first direction V. The semiconductor substrate 21 is composed of multiple island-shaped blocks 21A extending in the first direction V and arranged side by side in a second direction H perpendicular to the first direction V, with the insulating layer 53 interposed therebetween. Each block 21A is provided with, for example, multiple sets of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One readout circuit 22 shared by four sensor pixels 12 is composed of, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL located in a region facing the four sensor pixels 12. One readout circuit 22 shared by the four sensor pixels 12 is composed of, for example, an amplification transistor AMP in the block 21A located to the left of the insulating layer 53, and a reset transistor RST and a selection transistor SEL in the block 21A located to the right of the insulating layer 53.

[0059] 15, 16, 17, and 18 show examples of wiring layouts in the horizontal plane of the image sensor 1. Figures 15 to 18 illustrate a case in which one readout circuit 22 shared by four sensor pixels 12 is provided in a region facing the four sensor pixels 12. The wirings shown in Figures 15 to 18 are provided in different layers of the wiring layer 56, for example.

[0060] 15, the four adjacent through-wires 54 are electrically connected to a connection wire 55. The four adjacent through-wires 54 are further electrically connected to the gate of the amplification transistor AMP included in the block 21A adjacent to the left of the insulating layer 53 and the gate of the reset transistor RST included in the block 21A adjacent to the right of the insulating layer 53 via the connection wire 55 and a connection portion 59, for example, as shown in FIG.

[0061] The power supply line VDD is disposed at a position facing the readout circuits 22 arranged side by side in the second direction H, as shown in FIG. 16, for example. The power supply line VDD is electrically connected to the drain of the amplification transistor AMP and the drain of the reset transistor RST of each readout circuit 22 arranged side by side in the second direction H via a connection portion 59, as shown in FIG. 16, for example. Two pixel drive lines 23 are disposed at a position facing the readout circuits 22 arranged side by side in the second direction H, as shown in FIG. 16, for example. One pixel drive line 23 (second control line) is a line RSTG electrically connected to the gate of the reset transistor RST of each readout circuit 22 arranged side by side in the second direction H, as shown in FIG. 16, for example. The other pixel drive line 23 (third control line) is a line SELG electrically connected to the gate of the selection transistor SEL of each readout circuit 22 arranged side by side in the second direction H, as shown in FIG. 16, for example. In each read circuit 22, the source of the amplification transistor AMP and the drain of the selection transistor SEL are electrically connected to each other via a wiring 25, for example, as shown in FIG.

[0062] Two power supply lines VSS are arranged at positions facing the readout circuits 22 arranged side by side in the second direction H, as shown in FIG. 17, for example. Each power supply line VSS is electrically connected to a plurality of through wires 47 at a position facing the sensor pixels 12 arranged side by side in the second direction H, as shown in FIG. 17, for example. Four pixel drive lines 23 are arranged at positions facing the readout circuits 22 arranged side by side in the second direction H, as shown in FIG. 17, for example. Each of the four pixel drive lines 23 is a line TRG electrically connected to the through wire 48 of one of the four sensor pixels 12 corresponding to each readout circuit 22 arranged side by side in the second direction H, as shown in FIG. 17, for example. In other words, the four pixel drive lines 23 (first control lines) are electrically connected to the gates (transfer gates TG) of the transfer transistors TR of the sensor pixels 12 arranged side by side in the second direction H. In FIG. 17, in order to distinguish each wiring TRG, an identifier (1, 2, 3, 4) is added to the end of each wiring TRG.

[0063] 18, the vertical signal line 24 is disposed at a position facing each readout circuit 22 arranged side by side in the first direction V. For example, as shown in FIG. 18, the vertical signal line 24 (output line) is electrically connected to the output terminal (source of the amplification transistor AMP) of each readout circuit 22 arranged side by side in the first direction V.

[0064] (1-4. Manufacturing method of image sensor) Next, a description will be given of a method for manufacturing the imaging device 1. Figures 19A to 19G show an example of the manufacturing process for the imaging device 1.

[0065] First, a p-well layer 42, an element isolation portion 43, and a p-well layer 44 are formed on the semiconductor substrate 11. Next, a photodiode PD, a transfer transistor TR, and a floating diffusion FD are formed on the semiconductor substrate 11 (FIG. 19A). As a result, the sensor pixels 12 are formed on the semiconductor substrate 11. At this time, it is preferable not to use a material with low heat resistance, such as CoSi2 or NiSi formed by a salicide process, as the electrode material used for the sensor pixels 12. Rather, it is preferable to use a material with high heat resistance as the electrode material used for the sensor pixels 12. An example of a material with high heat resistance is polysilicon. Thereafter, an insulating layer 46 is formed on the semiconductor substrate 11 (FIG. 19A). In this manner, the first substrate 10 is formed.

[0066] Next, the first substrate 10 (insulating layer 4 6) A semiconductor substrate 21 is bonded on top of the readout circuit 22 (FIG. 19B). Thereafter, the semiconductor substrate 21 is thinned as necessary. At this time, the thickness of the semiconductor substrate 21 is set to a film thickness necessary for forming the readout circuit 22. The thickness of the semiconductor substrate 21 is generally about several hundred nm. However, depending on the concept of the readout circuit 22, an FD (Fully Depletion) type may also be possible, in which case the thickness of the semiconductor substrate 21 may be in the range of several nm to several μm.

[0067] Next, an insulating layer 53 is formed in the same layer as the semiconductor substrate 21 (FIG. 19C). The insulating layer 53 is formed, for example, in a location facing the floating diffusion FD. For example, slits (openings 21H) penetrating the semiconductor substrate 21 are formed in the semiconductor substrate 21 to separate the semiconductor substrate 21 into a plurality of blocks 21A. Then, the insulating layer 53 is formed so as to fill the slits. Then, a readout circuit 22 including an amplifying transistor AMP and the like is formed in each block 21A of the semiconductor substrate 21 (FIG. 19C). At this time, if a metal material with high heat resistance is used as the electrode material of the sensor pixel 12, the gate insulating film of the readout circuit 22 can be formed by thermal oxidation.

[0068] Next, an insulating layer 52 is formed on the semiconductor substrate 21. In this manner, an interlayer insulating film 51 consisting of insulating layers 46, 52, and 53 is formed. Subsequently, through holes 51A and 51B are formed in the interlayer insulating film 51 (FIG. 19D). Specifically, a through hole 51B that penetrates the insulating layer 52 is formed in a portion of the insulating layer 52 that faces the readout circuit 22. Furthermore, a through hole 51A that penetrates the interlayer insulating film 51 is formed in a portion of the interlayer insulating film 51 that faces the floating diffusion FD (i.e., a portion that faces the insulating layer 53).

[0069] Next, a conductive material is filled into through holes 51A and 51B to form through wiring 54 in through hole 51A and to form connection portion 59 in through hole 51B (FIG. 19E). Furthermore, connection wiring 55 that electrically connects through wiring 54 and connection portion 59 to each other is formed on insulating layer 52 (FIG. 19E). Thereafter, wiring layer 56 is formed on insulating layer 52 (FIG. 19F). In this manner, second substrate 20 is formed.

[0070] Next, the second substrate 20 is attached to the third substrate 30, on which the logic circuit 32 and the wiring layer 62 are formed, with the surface of the semiconductor substrate 21 facing the surface of the semiconductor substrate 31 (FIG. 19G). At this time, the pad electrodes 58 of the second substrate 20 and the pad electrodes 64 of the third substrate 30 are joined to each other, thereby electrically connecting the second substrate 20 and the third substrate 30 to each other. In this manner, the image sensor 1 is manufactured.

[0071] (1-5. Actions and Effects) In the wiring structure 100 of this embodiment and the image sensor 1 to which this structure is applied, gaps G1 and G2 are provided between multiple wirings extending in one direction (e.g., the Y-axis direction) and near some of the wirings. For example, among the wirings 112X1 to 112X6 extending in the Y-axis direction and buried in the insulating film 123, gaps G1 are formed between adjacent wirings 112X2 and 112X3, between wirings 112X3 and 112X4, and between wirings 112X4 and 112X5. Gap G2 is formed near an end face S121 of the barrier film 121 extending on the wiring layer 112 including the wirings 112X1 to 112X6, the end face S121 being formed above the wirings 112X2 and 112X5. This reduces the capacitance between the wirings extending in one direction. This will be described below.

[0072] As mentioned above, in recent years, with the miniaturization of semiconductor integrated circuit elements in semiconductor devices, the spacing between elements and the wiring connecting elements within elements has become narrower, leading to an increase in the capacitance between wiring (parasitic capacitance). The increase in capacitance between wiring delays wiring signals, resulting in a problem of reduced device operating speed. For this reason, in general semiconductor devices, low-k materials are used to electrically insulate wiring in the stacking direction and gaps are provided between parallel wiring to reduce the parasitic capacitance between wiring.

[0073] In the semiconductor device described above, when a via is formed between wirings with a gap between them to connect them to upper wiring layers, a restriction is imposed that no gap is formed next to the wiring where the via is formed in order to prevent unintended short circuits caused by the gap, which poses a problem that the capacitance of the entire wiring layer cannot be sufficiently reduced.

[0074] Furthermore, when wiring is made of copper (Cu), a barrier film with a high dielectric constant (k) is generally laminated on the Cu wiring, which poses the problem of higher capacitance in the lamination direction in the wiring portion where no voids are formed.

[0075] In contrast, in this embodiment, for example, a film formation method with low step coverage is used to form the insulating film 123 between the multiple wirings (e.g., between adjacent wirings 112X2 and 112X3, between adjacent wirings 112X3 and 112X4, and between adjacent wirings 112X4 and 112X5) extending in the Y-axis direction exposed by the opening H2 and on the insulating film (e.g., insulating film 122) around the wirings. As a result, gaps G1 and G2 are formed, for example, between adjacent wirings 112X2 and 112X3, between adjacent wirings 112X3 and 112X4, between adjacent wirings 112X4 and 112X5, and near end faces S121 formed above the wirings 112X2 and 112X5 of the barrier film 121 extending on the wiring layer 112. This reduces the capacitance between the wirings and their vicinity compared to when gaps are formed only between the wirings.

[0076] As described above, the wiring structure 100 of this embodiment can reduce the wiring capacitance of the entire structure. Furthermore, in the image sensor 1 to which the wiring structure 100 of this embodiment is applied, it can reduce the wiring capacitance between and near the wiring of the multiple vertical signal lines 24 that run vertically through the pixel region 13, for example.

[0077] In this embodiment, the insulating film 122 is formed on the barrier film 121 and covers the end surface S121 of the barrier film 121 exposed in the opening H2, the top and side surfaces of the wirings 112X2 and 112X3 extending in the Y-axis direction, the wirings 112X4 and 112X5, and the bottom surface of the opening H2. This film is formed using a film formation method with low step coverage. This reduces the step coverage of the insulating film 123, which can accelerate the closure of the opening H2. This makes it possible to form larger gaps G1 and G2.

[0078] The following describes Modifications 1 to 15. In the following description, the same components as those in the above embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0079] <2. Modifications> (2-1. Variation 1) 20 is a schematic diagram illustrating an example of a vertical cross-sectional configuration of a wiring structure (wiring structure 100A) according to a modified example (modification 1) of the present disclosure. The wiring structure 100A of this modification differs from the above embodiment in that the barrier film 121 is formed to a thickness of, for example, 50 nm to 150 nm.

[0080] In this way, by forming the barrier film 121 thick, the step formed by the upper surfaces of the interconnects 112X2 and 112X5 and the end surface S121 and upper surface of the barrier film 121 becomes larger, so that the gap G2 formed above the interconnects 112X2 and 112X5 and near the end surface S121 can be made larger. Therefore, compared to the interconnect structure 100 of the above embodiment, the interconnect structure 100A of this modification can further reduce the interconnect capacitance between the interconnects and in their vicinity.

[0081] (2-2. Variation 2) 21 is a schematic diagram illustrating an example of a vertical cross-sectional configuration of a wiring structure (wiring structure 100B) according to a modified example (modification 2) of the present disclosure. The wiring structure 100B of this modified example differs from the above-described modification 1 in that the end surface S121 of the barrier film 121 has a so-called inverse tapered shape in which the end on the lower surface (wiring side) is recessed further outside the opening H2 than the end on the upper surface.

[0082] 22A to 22E show an example of a manufacturing process for the wiring structure 100B shown in FIG.

[0083] First, the first layer 110 is formed in the same manner as in the above embodiment, and then, as shown in Fig. 22A, a barrier film 121 is formed on the first layer 110 by, for example, PVD or CVD to a thickness of 50 nm to 150 nm. Next, as shown in Fig. 22B, a resist film 131 having openings at positions corresponding to the wirings 121X2 to 112X5 is patterned on the barrier film 121 by photolithography.

[0084] 22C, the barrier film 121 exposed from the resist film 131, parts of the wirings 112X2 to 112X5, and the insulating film 111 are subjected to, for example, dry etching to form an opening H2. At this time, by adjusting the pressure during etching or adding oxygen (O2) gas as a process gas, for example, the end surface S121 of the barrier film 121 is processed into an inverse tapered shape as shown in FIG.

[0085] Next, after removing the resist film 131, as shown in FIG. 22D, an insulating film 122 is formed to a thickness of, for example, 5 nm to 50 nm by using, for example, a CVD method, covering the barrier film 121 and the side and bottom surfaces of the opening H2. Subsequently, as shown in FIG. 22E, an insulating film 123 made of, for example, SiOC or silicon nitride and having a thickness of, for example, 100 nm to 500 nm is formed by using, for example, a CVD method. This closes the opening H2, and the gaps between the wiring 112X2 and the wiring 112X3, between the wiring 112X3 and the wiring 112X4, and between the wiring 112X4 and the wiring 112X5 are formed. Wiring 112X5 Gaps G1 and G2 are formed between the wiring 112X1 and the wiring 112X2 and above the wiring 112X5 and in the vicinity of the end surface S121 of the barrier film 121, respectively.

[0086] Thereafter, in the same manner as in the above embodiment, insulating films 124, 125, and 126 and a conductive film 127 are formed in this order, completing the wiring structure 100B shown in FIG.

[0087] As described above, in this modification, for example, the end surface S121 of the barrier film 121 formed above the wiring 112X2 and the wiring 112X5 is formed in an inverse tapered shape. This prevents the insulating film 123 from following the end surface S121 of the barrier film 121 when the insulating film 123 is formed using a film formation method with low step coverage, such as a CVD method. This further accelerates the blocking of the opening H2, making it possible to form larger gaps G1 and G2.

[0088] (2-3. Variation 3) 23A is a schematic diagram showing an example of a vertical cross-sectional configuration (wiring structure 100C) of a wiring structure according to a modification (modification 3) of the present disclosure. FIG. 23B is a schematic diagram showing another example of a vertical cross-sectional configuration (wiring structure 100D) of a wiring structure according to modification 3 of the present disclosure. The shapes of the gaps G1 and G2 can also be controlled by changing the materials of the insulating films 122 and 123, for example.

[0089] For example, when phosphate silicate glass (PSG), which is generally considered to have excellent step coverage, is used as the material for insulating film 123, gaps G1 and G2 have a rounded shape as shown in Fig. 23A. On the other hand, when SiOC or silicon nitride, which has poor step coverage, is used as in the above embodiment, actual gaps G1 and G2 have a shape as shown in Fig. 23B.

[0090] For example, as shown in FIG. 24, the distance h1 between the bottom surface of the opening H2 and the gap G1 is smaller in the wiring structure 100D than in the wiring structure 100D. 100C The height h2 of the closed portion of the gap G1 and the width W of the gap G1 are narrower in the wiring structure 100D than in the wiring structure 100A. 100C It will be longer (wider) than

[0091] In addition, for example, when the flow rate of O2 gas is increased during deposition of carbon-containing silicon oxide (SiOC) and the ratio of the flow rate of OMCTS gas to O2 gas is changed from approximately 20:1 to 3:1 (to form a composition close to that of an oxide film) to deposit the insulating film 123, the lower part of the gap G1 facing the bottom surface of the opening H2 becomes flat, for example, as in the wiring structure 100F shown in Fig. 25. Also, for example, when the insulating film 123 is deposited using a Si-rich oxide film such as SiH4 gas, the gap G1 becomes gourd-shaped due to the influence of the step coverage of the insulating film 122, as in the wiring structure 100G shown in Fig. 26.

[0092] (2-4. Variation 4) 27 is a schematic diagram illustrating an example of a vertical cross-sectional configuration of a wiring structure (wiring structure 100G) according to a modification (modification 4) of the present disclosure. The wiring structure 100G of this modification differs from the embodiment in that a barrier film 121 and a barrier film 128 are stacked on the wiring layer 112, and a gap G3 is further formed near an end surface S128 of the barrier film 128. This barrier film 128 corresponds to a specific example of a "second barrier film" of the present disclosure.

[0093] The barrier film 128, like the barrier film 121, is intended to prevent diffusion of copper (Cu) and intrusion of moisture when the wirings 112X1 to 112X6 are formed using copper (Cu), for example. The barrier film 128 extends over the barrier film 121, with the exception of a portion. Specifically, the barrier film 128 extends over the barrier film 121, and has an end face S128 outside the end face S121 of the barrier film 121, for example. The material of the barrier film 128 can be, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), SiC x N y Examples of the material include silicon carbide (SiC), silicon oxynitride (SiON, SiNO), aluminum oxynitride (AlNO), and aluminum nitride (AlN), and among these, a material having an etching rate different from that of the barrier film 121 is selected.

[0094] 28A to 28E show an example of a manufacturing process for the wiring structure 100G shown in FIG.

[0095] First, the first layer 110 is formed in the same manner as in the above embodiment. Then, as shown in FIG. 28A, a barrier film 121 is formed on the first layer 110 by, for example, PVD or CVD to a thickness of, for example, 50 to 150 nm. Next, a barrier film 128 is formed on the barrier film 121 by, for example, PVD or CVD to a thickness of, for example, 100 to 200 nm. Furthermore, a silicon nitride film is formed as the protective film 132 to a thickness of, for example, 50 to 100 nm. In this modification, the barrier film 121 may be formed using tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or the like. Next, as shown in FIG. 28B, a resist film 131 having openings at positions corresponding to the wirings 121X2 to 112X5 is patterned on the protective film 132 by photolithography.

[0096] 28C, the protective film 132 and the barrier film 128 exposed from the resist film 131 are, for example, dry-etched to form an opening H2', and then the resist film 131 is removed. Subsequently, as shown in FIG. 28D, the end surface S128 of the exposed barrier film 128 is recessed, for example, by approximately 30 nm to 50 nm, for example, by dry etching or wafer etching. The barrier film 128 can be isotropically etched, for example, by dry etching using a fluorine-based gas.

[0097] 28E, openings H2 are formed by, for example, dry etching the barrier film 121, parts of the wirings 112X2 to 112X5, and the insulating film 111. At this time, the protective film 132 is also etched and removed together with the barrier film 121, etc.

[0098] Thereafter, as in the embodiment, an insulating film 122 is formed by, for example, CVD to cover the top surfaces of the barrier films 121 and 128 and the side and bottom surfaces of the opening H2, and then an insulating film 123 made of, for example, SiOC or silicon nitride and having a thickness of, for example, 100 nm to 500 nm is formed by, for example, CVD. This closes the opening H2, and the gaps between the wiring 112X2 and the wiring 112X3, between the wiring 112X3 and the wiring 112X4, and between the wiring 112X4 and the wiring 112X5 are closed. Wiring 112X5 Gaps G1, G2, and G3 are formed between the wirings 112X1 and 112X2 and above the wirings 112X5 and in the vicinity of the end face S121 of the barrier film 121 and the side face S128 of the barrier film 128, respectively.

[0099] In this manner, in this modification, for example, the barrier film is a laminated film (barrier films 121 and 128), and further, a step is provided between the barrier film 121 and the barrier film 128. As a result, when the insulating film 123 is formed using a film formation method with low step coverage, such as a CVD method, the insulating film 123 cannot conform to the step between the barrier film 121 and the barrier film 128, and gaps G2 and G3 are formed near the end face S121 of the barrier film 121 and the end face S128 of the barrier film 128, respectively. Therefore, compared to the wiring structure 100 of the above embodiment, the wiring structure 100G of this modification can further reduce the wiring capacitance between the wirings and in their vicinity.

[0100] 27 shows an example in which independent voids G2 and G3 are formed near the end surface S121 of the barrier film 121 and the end surface S128 of the barrier film 128, respectively. However, the voids G2 and G3 may be combined, for example, as in a wiring structure 10H shown in FIG. 29. Furthermore, the end surface S128 of the barrier film 28 may have an inverse tapered shape as in the above-described second modification, for example, as in a wiring structure 10I shown in FIG. 30. Alternatively, both end surfaces S121 and S128 of the barrier films 121 and 128 may have an inverse tapered shape, for example, as in a wiring structure 10J shown in FIG. 31. This allows larger voids G2 and G3 to be formed.

[0101] Furthermore, for example, as in the wiring structure 10K shown in Fig. 32, the barrier film 121 may be set back from the barrier film 128. Furthermore, in this modification, the example in which the barrier film 121 and the barrier film 128 are stacked to provide a step has been shown, but for example, as in the wiring structure 10L shown in Fig. 33, a step may be provided at the end surface S121 by using a single layer of the barrier film 121.

[0102] (2-5. Variation 5) 34 is a schematic diagram showing an example of a vertical cross-sectional configuration (wiring structure 100M) of a wiring structure according to a modification (modification 5) of the present disclosure. In the above-described embodiment and modifications 1 to 4, the barrier film 121 is formed using an insulating material, but this is not limiting. For example, the barrier film 121 may be formed using a metal material for each of a plurality of wirings extending in the Y-axis direction.

[0103] 35A to 35I show an example of a manufacturing process for the wiring structure 100M shown in FIG.

[0104] First, an opening H5 having an expanded upper portion is formed in the insulating film 111. For example, after forming an opening H1 having a uniform width, the upper portion of the opening H1 can be expanded by etching using oxygen (O2) gas, as shown in FIG. 35A. Next, for example, as shown in FIG. 35B, a barrier metal 112A is formed on the side and bottom surfaces of the opening H5, and then a metal film 112B is formed. Thereafter, the surface is polished using, for example, a CMP method, to form a wiring layer 112 embedded in the insulating film 111.

[0105] 35C, the metal film 112B is recessed by, for example, about 10 to 50 nm by wet etching. Subsequently, as shown in FIG. 35D, a barrier film 121 is formed on the wiring layer 112 by, for example, a CVD method to a thickness of, for example, 10 to 50 nm. Here, examples of materials for the barrier film 121 include metal materials such as tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and titanium nitride (TiN).

[0106] Next, as shown in Fig. 35E, the barrier film 121 provided on the insulating film 111 is removed by, for example, CMP to flatten the surface. Subsequently, as shown in Fig. 35F, a resist film 131 having openings at positions corresponding to the wirings 121X2 to 112X5 is patterned by photolithography. Subsequently, as shown in Figs. 35F and 35G, the barrier film 121 and insulating film 111 exposed from the resist film 131 are sequentially processed by, for example, dry etching or wet etching to form openings H2.

[0107] Next, after removing the resist film 131, as shown in FIG. 35H, an insulating film 122 is formed to a thickness of, for example, 5 nm to 50 nm by using, for example, a CVD method, covering the barrier film 121 and the side and bottom surfaces of the opening H2. Subsequently, as shown in FIG. 35I, an insulating film 123 made of, for example, SiOC or silicon nitride and having a thickness of, for example, 100 nm to 500 nm is formed by using, for example, a CVD method. This closes the opening H2, and the gaps between the wiring 112X2 and the wiring 112X3, between the wiring 112X3 and the wiring 112X4, and between the wiring 112X4 and the wiring 112X5 are formed. Wiring 112X5 Gaps G1 and G2 are formed between the wiring 112X1 and the wiring 112X2 and above the wiring 112X5 and in the vicinity of the end surface S121 of the barrier film 121, respectively.

[0108] Thereafter, in the same manner as in the above embodiment, insulating films 124, 125, and 126 and a conductive film 127 are formed in this order, thereby completing the wiring structure 100M shown in FIG.

[0109] In this way, even when the barrier film 121 is formed using a metal material, gaps G1 and G2 can be formed between a plurality of wirings extending in the Y-axis direction (for example, between adjacent wirings 112X2 and 112X3, between wirings 112X3 and 112X4, and between wirings 112X4 and 112X5) and near the end faces of the barrier film 121 formed on the wirings 112X2 and 112X5. This provides the same effects as those of the above-described embodiment.

[0110] Also in this modification, the size of the gap G2 can be controlled by adjusting the thickness of the barrier film 121 or changing the shape of the end portion.

[0111] (2-6. Variation 6) FIG. 36 shows an example of the vertical cross-sectional configuration of an image sensor (image sensor 1) according to a modification (modification 6) of the above-described embodiment. In this modification, the transfer transistor TR has a planar transfer gate TG. Therefore, the transfer gate TG does not penetrate the p-well layer 42, but is formed only on the surface of the semiconductor substrate 11. Even when a planar transfer gate TG is used for the transfer transistor TR, the image sensor 1 has the same effects as the above-described embodiment.

[0112] (2-7. Variation 7) FIG. 37 shows an example of the vertical cross-sectional configuration of an image sensor (image sensor 1) according to a modification (modification 7) of the above-described embodiment. In this modification, the second substrate 20 and the third substrate 30 are electrically connected in a region of the first substrate 10 facing the peripheral region 14. The peripheral region 14 corresponds to the frame region of the first substrate 10 and is provided on the periphery of the pixel region 13. In this modification, the second substrate 20 has a plurality of pad electrodes 58 in a region facing the peripheral region 14, and the third substrate 30 has a plurality of pad electrodes 64 in a region facing the peripheral region 14. The second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58, 64 provided in the region facing the peripheral region 14.

[0113] As described above, in this modification, the second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58, 64 provided in the region facing the peripheral region 14. This reduces the risk of hindering miniaturization of the area per pixel compared to when the pad electrodes 58, 64 are bonded to each other in the region facing the pixel region 13. Therefore, in addition to the effects of the above embodiment, it is possible to provide an image sensor 1 with a three-layer structure that does not hinder miniaturization of the area per pixel, with a chip size equivalent to that of conventional embodiments.

[0114] (2-8. Variation 8) FIG. 38 illustrates an example of a vertical cross-sectional configuration of an imaging element (imaging element 1) according to a modified example (modification 8) of the embodiment. FIG. 39 illustrates another example of a vertical cross-sectional configuration of an imaging element (imaging element 1) according to a modified example (modification 8) of the embodiment. The upper views of FIGS. 38 and 39 illustrate a modified cross-sectional configuration at cross section Sec1 of FIG. 1, and the lower views of FIG. 38 illustrate a modified cross-sectional configuration at cross section Sec2 of FIG. 1. Note that in the upper cross-sectional views of FIGS. 38 and 39, a diagram illustrating a modified surface configuration of semiconductor substrate 11 of FIG. 1 is superimposed on the diagram illustrating the modified cross-sectional configuration at cross section Sec1 of FIG. 1, and insulating layer 46 is omitted. Furthermore, in the lower cross-sectional views of FIGS. 38 and 39, a diagram illustrating a modified surface configuration of semiconductor substrate 21 is superimposed on the diagram illustrating the modified cross-sectional configuration at cross section Sec2 of FIG. 1.

[0115] 38 and 39, the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 (the plurality of dots arranged in a matrix in the figures) are arranged in a strip shape in the first direction V (the left-right direction in FIGS. 38 and 39) within the plane of the first substrate 10. Note that FIGS. 38 and 39 illustrate a case in which the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in two rows in the first direction V. In the four sensor pixels 12 that share the readout circuit 22, the four floating diffusions FD are arranged close to each other, for example, via the element isolation portion 43. In the four sensor pixels 12 that share the readout circuit 22, the four transfer gates TG (TG1, TG2, TG3, TG4) are arranged to surround the four floating diffusions FD, and for example, the four transfer gates TG form a ring shape.

[0116] The insulating layer 53 is composed of a plurality of blocks extending in a first direction V. The semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A extending in the first direction V and arranged side by side in a second direction H perpendicular to the first direction V, with the insulating layer 53 interposed therebetween. Each block 21A is provided with, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One readout circuit 22 shared by four sensor pixels 12 is, for example, not arranged directly opposite the four sensor pixels 12, but arranged offset in the second direction H.

[0117] 38, one readout circuit 22 shared by four sensor pixels 12 is configured with a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL located in an area of ​​the second substrate 20 that is shifted in the second direction H from an area facing the four sensor pixels 12. One readout circuit 22 shared by the four sensor pixels 12 is configured with, for example, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL in one block 21A.

[0118] 39, one readout circuit 22 shared by four sensor pixels 12 is configured by a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and an FD transfer transistor FDG located in an area on the second substrate 20 that is shifted in the second direction H from an area facing the four sensor pixels 12. One readout circuit 22 shared by the four sensor pixels 12 is configured by, for example, the amplification transistor AMP, the reset transistor RST, the selection transistor SEL, and the FD transfer transistor FDG in one block 21A.

[0119] In this modification, the single readout circuit 22 shared by the four sensor pixels 12 is not disposed directly opposite the four sensor pixels 12, but is disposed offset in the second direction H from a position directly opposite the four sensor pixels 12. In this case, the wiring 25 can be shortened, or the wiring 25 can be omitted and the source of the amplification transistor AMP and the drain of the selection transistor SEL can be configured using a common impurity region. As a result, the size of the readout circuit 22 can be reduced, or the size of other parts within the readout circuit 22 can be increased.

[0120] (2-9. Variation 9) Fig. 40 shows an example of a horizontal cross-sectional configuration of an image sensor (image sensor 1) according to a modification (modification 9) of the above embodiment. Fig. 40 shows a modification of the cross-sectional configuration of Fig. 15.

[0121] In this modification, the semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A arranged side by side in the first direction V and the second direction H with an insulating layer 53 interposed therebetween. Each block 21A is provided with, for example, a set of reset transistor RST, amplification transistor AMP, and selection transistor SEL. In this case, crosstalk between adjacent readout circuits 22 can be suppressed by the insulating layer 53, and degradation of image quality due to reduced resolution and color mixing on a reproduced image can be suppressed.

[0122] (2-10. Variation 10) Fig. 41 shows an example of a horizontal cross-sectional configuration of an image sensor (image sensor 1) according to a modification (modification 10) of the above embodiment. Fig. 41 shows a modification of the cross-sectional configuration of Fig. 40.

[0123] In this modification, one readout circuit 22 shared by four sensor pixels 12 is not disposed directly opposite the four sensor pixels 12, but is disposed offset in the first direction V. In this modification, similar to the ninth modification, the semiconductor substrate 21 is further configured with a plurality of island-shaped blocks 21A arranged side by side in the first direction V and the second direction H with an insulating layer 53 interposed therebetween. Each block 21A includes, for example, a set of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. In this modification, a plurality of through wires 47 and a plurality of through wires 54 are also arranged in the second direction H. Specifically, the plurality of through wires 47 are disposed between four through wires 54 sharing a certain readout circuit 22 and four through wires 54 sharing another readout circuit 22 adjacent to the readout circuit 22 in the second direction H. In this configuration, crosstalk between adjacent readout circuits 22 can be suppressed by the insulating layer 53 and the through wires 47, thereby suppressing image quality degradation due to reduced resolution and color mixing in a reproduced image.

[0124] (2-11. Variation 11) Fig. 42 shows an example of a horizontal cross-sectional configuration of an image sensor (image sensor 1) according to a modification (modification 11) of the above embodiment. Fig. 42 shows a modification of the cross-sectional configuration of Fig. 13.

[0125] In this modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD is shared by every four sensor pixels 12. Therefore, in this modification, one through wiring 54 is provided for every four sensor pixels 12.

[0126] Among the plurality of sensor pixels 12 arranged in a matrix, four sensor pixels 12 that share one floating diffusion FD are shifted in the first direction V by the amount of one sensor pixel 12, and the four sensor pixels 12 that correspond to the area are referred to as four sensor pixels 12A for convenience. In this modification, the first substrate 10 shares a through wiring 47 with each of the four sensor pixels 12A. Therefore, in this modification, one through wiring 47 is provided for each of the four sensor pixels 12A.

[0127] In this modification, the first substrate 10 has an element isolation portion 43 that isolates the photodiode PD and the transfer transistor TR for each sensor pixel 12. When viewed from the normal direction of the semiconductor substrate 11, the element isolation portion 43 does not completely surround the sensor pixel 12, and has gaps (unformed regions) near the floating diffusion FD (through wiring 54) and near the through wiring 47. These gaps enable four sensor pixels 12 to share one through wiring 54, or four sensor pixels 12A to share one through wiring 47. In this modification, the second substrate 20 has a readout circuit 22 for each of the four sensor pixels 12 that share the floating diffusion FD.

[0128] Fig. 43 shows another example of the horizontal cross-sectional configuration of the image sensor 1 according to this modification. Fig. 43 shows a modification of the cross-sectional configuration of Fig. 40. In this modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD is shared by every four sensor pixels 12. Furthermore, the first substrate 10 has an element isolation portion 43 that isolates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0129] Fig. 44 shows another example of the horizontal cross-sectional configuration of the image sensor 1 according to this modification. Fig. 44 shows a modification of the cross-sectional configuration of Fig. 41. In this modification, the first substrate 10 has a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD is shared by every four sensor pixels 12. Furthermore, the first substrate 10 has an element isolation portion 43 that isolates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0130] (2-12. Variation 12) FIG. 45 shows the above embodiment and Variations 6 to 11 12 illustrates an example of a circuit configuration of an image sensor (image sensor 1) according to a modified example (modification 12) of the present embodiment. The image sensor 1 according to this modified example is a CMOS image sensor equipped with a column-parallel ADC.

[0131] As shown in Figure 45, the imaging element 1 of this modified example is configured to have a pixel area 13 in which a plurality of sensor pixels 12, each including a photoelectric conversion unit, are arranged two-dimensionally in a matrix, as well as a vertical driving circuit 33, a column signal processing circuit 34, a reference voltage supply unit 38, a horizontal driving circuit 35, a horizontal output line 37, and a system control circuit 36.

[0132] In this system configuration, the system control circuit 36 ​​generates clock signals and control signals, etc., which serve as the basis for the operation of the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc., based on the master clock MCK, and provides these signals to the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, etc.

[0133] The vertical drive circuit 33 is formed on the first substrate 10 together with each sensor pixel 12 in the pixel region 13, and is also formed on the second substrate 20 on which the readout circuit 22 is formed. The column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, the horizontal output line 37, and the system control circuit 36 ​​are formed on the third substrate 30.

[0134] Although not shown here, the sensor pixel 12 may have, for example, a configuration including a photodiode PD and a transfer transistor TR that transfers the charge obtained by photoelectric conversion in the photodiode PD to the floating diffusion FD. Also, although not shown here, the readout circuit 22 may have, for example, a three-transistor configuration including a reset transistor RST that controls the potential of the floating diffusion FD, an amplification transistor AMP that outputs a signal according to the potential of the floating diffusion FD, and a selection transistor SEL that selects pixels.

[0135] In the pixel region 13, the sensor pixels 12 are arranged two-dimensionally, and pixel drive lines 23 are wired for each row of this m-row by n-column pixel arrangement, and vertical signal lines 24 are wired for each column. One end of each of the pixel drive lines 23 is connected to an output terminal of a vertical drive circuit 33 corresponding to each row. The vertical drive circuit 33 is configured with a shift register or the like, and controls row addresses and row scanning of the pixel region 13 via the pixel drive lines 23.

[0136] The column signal processing circuit 34 has, for example, ADCs (analog-to-digital conversion circuits) 34-1 to 34-m provided for each pixel column in the pixel region 13, i.e., for each vertical signal line 24, and converts the analog signals output from each sensor pixel 12 in the pixel region 13 for each column into digital signals and outputs them.

[0137] The reference voltage supply unit 38 has, for example, a DAC (digital-analog conversion circuit) 38A as means for generating a reference voltage Vref having a so-called ramp waveform, the level of which changes in a sloping manner as time passes. However, the means for generating the reference voltage Vref having a ramp waveform is not limited to the DAC 38A.

[0138] The DAC 38A generates a reference voltage Vref having a ramp waveform based on a clock CK given from the system control circuit 36 ​​under the control of a control signal CS1 given from the system control circuit 36, and supplies the reference voltage Vref to the ADCs 34-1 to 34-m of the column signal processing circuit 34.

[0139] Each of the ADCs 34-1 to 34-m is configured to selectively perform AD conversion operations corresponding to an operation mode between a normal frame rate mode using a progressive scan method in which information from all of the sensor pixels 12 is read out, and a high-speed frame rate mode in which the exposure time of the sensor pixels 12 is set to 1 / N and the frame rate is increased by N times, for example, twice, compared to the normal frame rate mode. This operation mode switching is performed under control of control signals CS2 and CS3 provided by the system control circuit 36. An external system controller (not shown) also provides the system control circuit 36 ​​with instruction information for switching between the normal frame rate mode and the high-speed frame rate mode.

[0140] The ADCs 34-1 to 34-m all have the same configuration, and the following description will be given taking the ADC 34-m as an example. The ADC 34-m includes a comparator 34A, a counting means such as an up / down counter (denoted as U / DCNT in the drawing) 34B, a transfer switch 34C, and a memory device 34D.

[0141] The comparator 34A compares the signal voltage Vx of the vertical signal line 24 corresponding to the signal output from each sensor pixel 12 in the nth column of the pixel area 13 with the reference voltage Vref of a ramp waveform supplied from the reference voltage supply unit 38, and, for example, when the reference voltage Vref is greater than the signal voltage Vx, the output Vco becomes an “H” level, and when the reference voltage Vref is equal to or less than the signal voltage Vx, the output Vco becomes an “L” level.

[0142] The up / down counter 34B is an asynchronous counter, and under the control of a control signal CS2 given from the system control circuit 36, a clock CK is given from the system control circuit 36 ​​simultaneously with the DAC 18A, and by counting down (DOWN) or up (UP) in synchronization with the clock CK, the up / down counter 34B measures the comparison period from the start of the comparison operation in the comparator 34A to the end of the comparison operation.

[0143] Specifically, in the normal frame rate mode, when reading out a signal from one sensor pixel 12, the comparison time during the first readout operation is measured by counting down during the first readout operation, and the comparison time during the second readout operation is measured by counting up during the second readout operation.

[0144] On the other hand, in the high-speed frame rate mode, the count result for the sensor pixels 12 in a certain row is retained as is, and then, for the sensor pixels 12 in the next row, the comparison time for the first readout is measured by counting down from the previous count result during the first readout operation, and the comparison time for the second readout is measured by counting up during the second readout operation.

[0145] In the normal frame rate mode, under the control of a control signal CS3 provided from the system control circuit 36, the transfer switch 34C turns on (closed) when the counting operation of the up / down counter 34B for a certain row of sensor pixels 12 is completed, and transfers the counting result of the up / down counter 34B to the memory device 34D.

[0146] On the other hand, at a high frame rate of, for example, N=2, the up / down counter 34B remains in the off (open) state when it completes its counting operation for the sensor pixels 12 in a certain row, and then turns on when it completes its counting operation for the sensor pixels 12 in the next row, and transfers the count results of the up / down counter 34B for two vertical pixels to the memory device 34D.

[0147] In this way, the analog signals supplied for each column from each sensor pixel 12 in the pixel area 13 via the vertical signal line 24 are converted into N-bit digital signals by the operations of the comparators 34A and the up / down counters 34B in the ADCs 34-1 to 34-m and stored in the memory device 34D.

[0148] The horizontal drive circuit 35 is configured with a shift register and the like, and controls the column addresses and column scanning of the ADCs 34-1 to 34-m in the column signal processing circuit 34. Under the control of this horizontal drive circuit 35, the N-bit digital signals AD converted by each of the ADCs 34-1 to 34-m are read out in order to a horizontal output line 37 and output via the horizontal output line 37 as imaging data.

[0149] Although not specifically shown because it is not directly related to the present disclosure, it is also possible to provide circuits other than the above components that perform various signal processing on the imaging data output via the horizontal output line 37.

[0150] In the image sensor 1 equipped with a column-parallel ADC according to this modified example of the above configuration, the count result of the up / down counter 34B can be selectively transferred to the memory device 34D via the transfer switch 34C, so that the count operation of the up / down counter 34B and the read operation of the count result of the up / down counter 34B to the horizontal output line 37 can be controlled independently.

[0151] (2-13. Variation 13) FIG. 46 shows an example of the image sensor of FIG. 45 configured by stacking three substrates (first substrate 10, second substrate 20, and third substrate 30). In this modification, a pixel region 13 including a plurality of sensor pixels 12 is formed in the center of the first substrate 10, and a vertical drive circuit 33 is formed around the pixel region 13. A readout circuit region 15 including a plurality of readout circuits 22 is formed in the center of the second substrate 20, and the vertical drive circuit 33 is formed around the readout circuit region 15. A column signal processing circuit 34, a horizontal drive circuit 35, a system control circuit 36, a horizontal output line 37, and a reference voltage supply unit 38 are formed on the third substrate 30. As a result, as with the above embodiment and its modifications, the structure electrically connecting the substrates does not increase the chip size or hinder miniaturization of the area per pixel. As a result, it is possible to provide an image sensor 1 with a three-layer structure that does not hinder miniaturization of the area per pixel while maintaining the same chip size as before. The vertical drive circuit 33 may be formed only on the first substrate 10 or only on the second substrate 20.

[0152] (2-14. Variation 14) FIG. 47 shows an example of a cross-sectional configuration of an imaging element (imaging element 1) according to a modification (modification 14) of the above-described embodiment and modifications 6 to 12. In the above-described embodiment and modifications 6 to 12, the imaging element 1 is configured by stacking three substrates (first substrate 10, second substrate 20, and third substrate 30). However, 、2The logic circuit 32 may be configured by stacking two substrates (a first substrate 10 and a second substrate 20). In this case, the logic circuit 32 may be formed, for example, on the first substrate 10 and the second substrate 20, as shown in FIG. 47. Here, the circuit 32A of the logic circuit 32 provided on the first substrate 10 side includes a transistor having a gate structure in which a high-dielectric-constant film made of a material (e.g., high-k) that can withstand high-temperature processes and a metal gate electrode are stacked. On the other hand, the circuit 32B provided on the second substrate 20 side includes a low-resistance region 26 made of silicide formed using a salicide (self-aligned silicide) process such as CoSi2 or NiSi on the surface of an impurity diffusion region in contact with the source electrode and the drain electrode. The low-resistance region made of silicide is formed of a compound of the material of the semiconductor substrate and a metal. This allows a high-temperature process such as thermal oxidation to be used when forming the sensor pixels 12. Furthermore, in the circuit 32B of the logic circuit 32 provided on the second substrate 20 side, if the low-resistance region 26 made of silicide is provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode, the contact resistance can be reduced, and as a result, the operation speed of the logic circuit 32 can be increased.

[0153] (2-15. Variation 15) FIG. 48 shows a modified cross-sectional configuration of the image sensor 1 according to a modification (modification 15) of the above-described embodiment and modifications 6 to 12. In the logic circuit 32 of the third substrate 30 according to the above-described embodiment and modifications 6 to 12, low-resistance regions 39 made of silicide, such as CoSi2 or NiSi, may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode using a salicide (self-aligned silicide) process. This allows a high-temperature process, such as thermal oxidation, to be used when forming the sensor pixels 12. Furthermore, if the low-resistance regions 39 made of silicide are provided on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode in the logic circuit 32, contact resistance can be reduced. As a result, the operation speed of the logic circuit 32 can be increased.

[0154] In addition, the above embodiment and Variations 6 to 15 For example, the conductivity types of the above-described embodiments and Variations 6 to 15 In the above description, p-type may be read as n-type, and n-type may be read as p-type. Even in this case, the same effects as those of the above embodiment and its modifications 6 to 17 can be obtained.

[0155] <3. Application Examples> FIG. 49 shows the above embodiment and its Variations 6 to 15 1 shows an example of a schematic configuration of an imaging system 7 including an imaging element (imaging element 1) according to the present invention.

[0156] The imaging system 7 is, for example, an electronic device such as an imaging element of a digital still camera or video camera, or a portable terminal device such as a smartphone or tablet terminal. The imaging system 7 includes, for example, an optical system 241, a shutter device 242, the imaging element 1, a DSP circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248. In the imaging system 7, the shutter device 242, the imaging element 1, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, the operation unit 247, and the power supply unit 248 are connected to each other via a bus line 249.

[0157] The image sensor 1 outputs image data corresponding to incident light. The optical system 241 includes one or more lenses and guides light (incident light) from a subject to the image sensor 1, forming an image on the light-receiving surface of the image sensor 1. The shutter device 242 is disposed between the optical system 241 and the image sensor 1 and controls the light irradiation period and light blocking period of the image sensor 1 under the control of the operation unit 247. The DSP circuit 243 is a signal processing circuit that processes the signal (image data) output from the image sensor 1. The frame memory 244 temporarily stores the image data processed by the DSP circuit 243 on a frame-by-frame basis. The display unit 245 is a panel-type display device, such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays moving or still images captured by the image sensor 1. The storage unit 246 stores image data of moving or still images captured by the image sensor 1 in a recording medium, such as a semiconductor memory or a hard disk. The operation unit 247 issues operation commands for various functions of the image capture system 7 in accordance with user operations. The power supply unit 248 supplies various types of power to the imaging device 1, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, and the operation unit 247 as appropriate.

[0158] Next, the imaging procedure in the imaging system 7 will be described.

[0159] 50 shows an example of a flowchart of the imaging operation in the imaging system 7. The user operates the operation unit 247 to instruct the start of imaging (step S101). The operation unit 247 then transmits an imaging command to the imaging element 1 (step S102). Upon receiving the imaging command, the imaging element 1 (specifically, the system control circuit 36) performs imaging in a predetermined imaging method (step S103).

[0160] The image sensor 1 outputs light (image data) imaged on the light receiving surface via the optical system 241 and the shutter device 242 to the DSP circuit 243. Here, the image data refers to data for all pixels of pixel signals generated based on charges temporarily stored in the floating diffusion FD. The DSP circuit 243 performs predetermined signal processing (e.g., noise reduction processing) based on the image data input from the image sensor 1 (step S104). The DSP circuit 243 stores the image data that has undergone the predetermined signal processing in the frame memory 244, and the frame memory 244 stores the image data in the storage unit 246 (step S105). In this manner, imaging is performed in the image sensor system 7.

[0161] In this application example, the imaging element 1 is applied to an imaging system 7. This allows the imaging element 1 to be made smaller or have higher definition, so that a small or high-definition imaging system 7 can be provided.

[0162] FIG. 51 is a diagram showing an outline of a configuration example of a non-stacked solid-state imaging element (solid-state imaging element 23210) and a stacked solid-state imaging element (solid-state imaging element 23020) to which the technology according to the present disclosure can be applied.

[0163] A in Fig. 51 shows a schematic configuration example of a non-stacked solid-state imaging element. As shown in A in Fig. 51, a solid-state imaging element 23010 has one die (semiconductor substrate) 23011. This die 23011 is equipped with a pixel region 23012 in which pixels are arranged in an array, a control circuit 23013 that drives the pixels and performs various other controls, and a logic circuit 23014 that processes signals.

[0164] 51B and 51C show a schematic configuration example of a stacked solid-state imaging element. As shown in FIG. 51B and 51C, the solid-state imaging element 23020 is configured as a single semiconductor chip by stacking and electrically connecting two dies, a sensor die 23021 and a logic die 23024. The sensor die 23021 and the logic die 23024 correspond to a specific example of the "first substrate" and the "second substrate" of the present disclosure.

[0165] 51B, a pixel region 23012 and a control circuit 23013 are mounted on a sensor die 23021, and a logic circuit 23014 including a signal processing circuit for performing signal processing is mounted on a logic die 23024. Furthermore, the sensor die 23021 may be mounted with, for example, the readout circuit 22 described above.

[0166] In FIG. 51C, a pixel region 23012 is mounted on a sensor die 23021, and a control circuit 23013 and a logic circuit 23014 are mounted on a logic die 23024.

[0167] FIG. 52 is a cross-sectional view showing a first configuration example of a stacked solid-state imaging element 23020. As shown in FIG.

[0168] The sensor die 23021 is formed with a PD (photodiode), an FD (floating diffusion), a Tr (MOS FET), and a Tr that constitute a pixel that becomes a pixel region 23012, and a Tr that constitutes a control circuit 23013. Furthermore, the sensor die 23021 is formed with a wiring layer 23101 having multiple layers, three layers in this example, of wiring 23110. Note that the control circuit 23013 (or the Tr that constitutes the control circuit) can be configured in the logic die 23024, not in the sensor die 23021.

[0169] The logic die 23024 has transistors that constitute the logic circuit 23014 formed therein. Furthermore, the logic die 23024 has a wiring layer 23161 formed therein that has multiple layers, three layers in this example, of wiring 23170. Furthermore, the logic die 23024 has a connection hole 23171 formed on its inner wall surface, and a connection conductor 23173 that is connected to the wiring 23170, etc., buried in the connection hole 23171.

[0170] The sensor die 23021 and the logic die 23024 are bonded together so that their wiring layers 23101 and 23161 face each other, thereby forming a stacked solid-state imaging element 23020 in which the sensor die 23021 and the logic die 23024 are stacked. A film 23191 such as a protective film is formed on the surfaces where the sensor die 23021 and the logic die 23024 are bonded together.

[0171] The sensor die 23021 has a connection hole 23111 formed therein, which penetrates the sensor die 23021 from the back surface side (the side where light is incident on the PD) (upper side) of the sensor die 23021 to reach the wiring 23170 in the top layer of the logic die 23024. Furthermore, the sensor die 23021 has a connection hole 23121 formed therein, adjacent to the connection hole 23111, which penetrates the back surface side of the sensor die 23021 to reach the wiring 23110 in the first layer. An insulating film 23112 is formed on the inner wall surface of the connection hole 23111, and an insulating film 23122 is formed on the inner wall surface of the connection hole 23121. Connection conductors 23113 and 23123 are embedded in the connection holes 23111 and 23121, respectively. The connection conductor 23113 and the connection conductor 23123 are electrically connected on the back side of the sensor die 23021, thereby electrically connecting the sensor die 23021 and the logic die 23024 via the wiring layer 23101, the connection hole 23121, the connection hole 23111, and the wiring layer 23161.

[0172] FIG. 53 is a cross-sectional view showing a second configuration example of a stacked solid-state imaging element 23020. In FIG.

[0173] In a second configuration example of the solid-state imaging element 23020, one connection hole 23211 formed in the sensor die 23021 electrically connects the sensor die 23021 (the wiring layer 23101 (the wiring 23110)) and the logic die 23024 (the wiring layer 23161 (the wiring 23170)).

[0174] 53, the connection hole 23211 is formed so as to penetrate the sensor die 23021 from the back surface side thereof to reach the wiring 23170 in the uppermost layer of the logic die 23024 and also to reach the wiring 23110 in the uppermost layer of the sensor die 23021. An insulating film 23212 is formed on the inner wall surface of the connection hole 23211, and a connection conductor 23213 is embedded in the connection hole 23211. In the above-mentioned FIG. 52, the sensor die 23021 and the logic die 23024 are electrically connected by two connection holes 23111 and 23121, but in FIG. 53, the sensor die 23021 and the logic die 23024 are electrically connected by one connection hole 23211.

[0175] FIG. 54 is a cross-sectional view showing a third configuration example of a stacked solid-state imaging element 23020. In FIG.

[0176] The solid-state imaging element 23020 in Figure 54 differs from the case in Figure 52 in that a film 23191 such as a protective film is not formed on the surface where the sensor die 23021 and the logic die 23024 are bonded together, in that a film 23191 such as a protective film is not formed on the surface where the sensor die 23021 and the logic die 23024 are bonded together.

[0177] The solid-state imaging element 23020 in FIG. 54 is constructed by overlapping the sensor die 23021 and the logic die 23024 so that the wiring 23110 and 23170 are in direct contact with each other, and then heating them while applying a required load to directly bond the wiring 23110 and 23170.

[0178] FIG. 55 is a cross-sectional view showing another example of the configuration of a stacked solid-state imaging device to which the technology according to the present disclosure can be applied.

[0179] In FIG. 55, the solid-state imaging device 23401 has a three-layer laminated structure in which three dies, a sensor die 23411, a logic die 23412, and a memory die 23413, are laminated.

[0180] The memory die 23413 has, for example, a memory circuit that stores data that is temporarily required in the signal processing performed by the logic die 23412.

[0181] In FIG. 55, the logic die 23412 and the memory die 23413 are stacked in that order below the sensor die 23411, but the logic die 23412 and the memory die 23413 can be stacked below the sensor die 23411 in the reverse order, i.e., the memory die 23413 and the logic die 23412.

[0182] In FIG. 55, the sensor die 23411 has formed thereon the PDs that serve as the photoelectric conversion units of the pixels and the source / drain regions of the pixel Tr.

[0183] A gate electrode is formed around the PD via a gate insulating film, and the gate electrode and paired source / drain regions form pixels Tr23421 and Tr23422.

[0184] The pixel Tr23421 adjacent to the PD is a transfer Tr, and one of the pair of source / drain regions constituting the pixel Tr23421 is an FD.

[0185] An interlayer insulating film is formed on the sensor die 23411, and a connection hole is formed in the interlayer insulating film. A connection conductor 23431 connected to the pixel Tr23421 and the pixel Tr23422 is formed in the connection hole.

[0186] Furthermore, the sensor die 23411 is formed with a wiring layer 23433 having multiple layers of wiring 23432 connected to each of the connection conductors 23431 .

[0187] Furthermore, an aluminum pad 23434 serving as an electrode for external connection is formed on the bottom layer of the wiring layer 23433 of the sensor die 23411. That is, on the sensor die 23411, the aluminum pad 23434 is formed at a position closer to the bonding surface 23440 with the logic die 23412 than the wiring 23432. The aluminum pad 23434 is used as one end of a wiring related to inputting and outputting signals to and from the outside.

[0188] Furthermore, the sensor die 23411 is formed with a contact 23441 used for electrical connection with the logic die 23412. The contact 23441 is connected to a contact 23451 of the logic die 23412 and also to an aluminum pad 23442 of the sensor die 23411.

[0189] The sensor die 23411 has a pad hole 23443 formed therein so as to reach the aluminum pad 23442 from the rear surface (upper side) of the sensor die 23411 .

[0190] The technology according to the present disclosure can be applied to the above-described solid-state imaging device. For example, the wiring 23110 or the wiring layer 23161 may be provided with, for example, the above-described plurality of pixel driving lines 23 and plurality of vertical signal lines 24. In this case, by forming gaps G as shown in FIG. 1 between the plurality of vertical signal lines 24, the capacitance between the wirings can be reduced. Furthermore, by suppressing an increase in the capacitance between the wirings, the variation in the wiring capacitance can be reduced.

[0191] <4. Application Examples> (Application example 1) The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0192] FIG. 56 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0193] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 56, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0194] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0195] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0196] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0197] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0198] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0199] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0200] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0201] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0202] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 56, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0203] FIG. 57 is a diagram showing an example of the installation position of the imaging unit 12031.

[0204] In FIG. 57, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0205] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0206] 57 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0207] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0208] For example, the microcomputer 12051 can extract, as a preceding vehicle, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher) by calculating the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which travels autonomously without relying on driver operation.

[0209] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0210] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0211] An example of a mobile object control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the imaging element 1 according to the above-described embodiment and its modified example can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain a high-resolution captured image with little noise, thereby enabling high-precision control using the captured image in the mobile object control system.

[0212] (Application example 2) FIG. 58 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0213] Figure 58 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment instrument 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0214] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0215] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens towards an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0216] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0217] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0218] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0219] The light source device 11203 is configured from a light source such as an LED (Light Emitting Diode), and supplies irradiation light to the endoscope 11100 when photographing an operation site or the like.

[0220] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiating light, magnification, focal length, etc.) of the endoscope 11100.

[0221] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0222] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical site can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 11203. In this case, it is also possible to capture images corresponding to each RGB in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0223] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0224] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto body tissues and observing the fluorescence from the tissues (autofluorescence observation), or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0225] FIG. 59 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0226] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so that they can communicate with each other.

[0227] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0228] The imaging unit 11402 is configured with an imaging element. The imaging element constituting the imaging unit 11402 may be one (a so-called single-chip type) or multiple (a so-called multi-chip type). When the imaging unit 11402 is configured with a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured with a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. 3D display enables the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured with a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0229] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0230] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0231] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0232] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0233] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0234] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0235] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0236] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0237] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data sent from the camera head 11102 .

[0238] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0239] Furthermore, the control unit 11413 causes the display device 11202 to display a captured image showing the surgical site, etc., based on the image signal that has been image processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0240] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0241] In the illustrated example, communication is performed by wire using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0242] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. Of the configurations described above, the technology according to the present disclosure can be suitably applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100. By applying the technology according to the present disclosure to the imaging unit 11402, it is possible to reduce the size or increase the resolution of the imaging unit 11402, thereby providing a compact or high-resolution endoscope 11100.

[0243] The present disclosure has been described above with reference to the embodiment and its modifications 1 to 15, as well as application examples and modified examples. However, the present disclosure is not limited to the above-described embodiment and various modifications are possible. For example, in the above-described embodiment, the pixel drive lines 23 extend in the row direction and the vertical signal lines extend in the column direction. However, they may extend in the same direction. Furthermore, the pixel drive lines 23 may extend in any direction, such as vertically.

[0244] In addition, in the above-described embodiments, the present technology has been described using an image sensor having a three-dimensional structure as an example, but the present technology is not limited to this and can be applied to any semiconductor device that is a three-dimensional stacked large-scale integrated (LSI) device.

[0245] Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than the effects described in this specification.

[0246] The present disclosure can also be configured as follows. According to the present technology configured as follows, a first barrier film having a first end face is formed above one of a plurality of wirings on a wiring layer having the plurality of wirings extending in one direction, and a first insulating film is further formed to cover the wiring layer and the first barrier film. A first gap is formed between adjacent wirings, and a second gap is formed above the wiring on which the first end face of the first barrier film is provided and in the vicinity of the first end face. This reduces the capacitance between the wirings extending in one direction. This makes it possible to reduce the overall wiring capacitance. (1) a wiring layer having a plurality of wirings extending in one direction; a first barrier film stacked on the wiring layer and having a first end face above any one of the plurality of wirings; a first insulating film laminated on the wiring layer and the first barrier film; provided between the wiring layer and the first insulating film, a first gap provided between the plurality of adjacent wirings; a second gap provided above the wiring on which the first end surface is provided and in the vicinity of the first end surface; An imaging element comprising: (2) The imaging element according to (1), wherein the first end face has an inverse tapered shape in which the end on the wiring side is set back more. (3) The imaging element described in (1) or (2) further comprises a second insulating film provided between the first insulating film and the first barrier film and continuously covering the first end face and the upper and side surfaces of the plurality of wirings. (4) a second barrier film provided between the first barrier film and the second insulating film, having a second end face above the wiring together with the first end face, and having an etching rate different from that of the first barrier film; The imaging element according to (3), further comprising a third gap provided in the vicinity of the second end face of the second barrier film. (5) The imaging element according to (4), wherein the first end face and the second end face are formed at different positions from each other. (6) The imaging element according to any one of (1) to (5), further comprising a third insulating film stacked on the first insulating film and having a flat surface. (7) The imaging element according to (6), further comprising a first conductive film facing directly to at least some of the plurality of wirings, with the first insulating film and the third insulating film interposed therebetween. (8) The imaging element described in (7), wherein the first conductive film is electrically connected to a portion of the plurality of wirings via a connection portion that penetrates the first insulating film and the third insulating film. (9) The imaging element according to any one of (1) to (8), wherein the first insulating film has irregularities above the plurality of wirings. (10) The image sensor according to any one of (1) to (9), wherein the first insulating film is formed using a low-dielectric-constant material having a relative dielectric constant k of 3.0 or less. (11) The image sensor according to any one of (1) to (10), wherein the first barrier film is formed using an insulating material. (12) The image sensor according to any one of (1) to (11), wherein the first barrier film is formed for each of the plurality of wirings using a metal material. (13) The imaging element according to any one of (6) to (12), wherein the third insulating film is formed using a material having a higher polishing rate than the first insulating film. (14) The imaging element according to any one of (6) to (13), wherein the third insulating film is formed using silicon oxide, carbon-containing silicon oxide, fluorine-added silicon oxide, or silicon oxynitride. (15) a first substrate having a first semiconductor substrate having sensor pixels that perform photoelectric conversion and a multilayer wiring layer including the third insulating film in which the first conductive film is embedded; The pixel transistor further includes a second semiconductor substrate having a logic circuit for processing pixel signals based on the charges output from the sensor pixels, and a second substrate having a multi-layer wiring layer in which a second conductive film is embedded, The imaging element described in any one of (7) to (14), wherein the first substrate and the second substrate are electrically connected to each other by bonding the first conductive film and the second conductive film. (16) forming a wiring layer having a plurality of wirings extending in one direction; forming a first barrier film on the wiring layer; forming a first opening between the first barrier film and adjacent ones of the plurality of wirings in a predetermined region of the wiring layer; By forming a first insulating film, a first gap is formed between the adjacent wirings, and a second gap is formed in the vicinity of a first end surface formed by the first opening of the first barrier film. A method for manufacturing an imaging element. (17) The method for manufacturing an imaging element described in (16), wherein after forming the first opening, a third insulating film is formed to cover the upper surface of the first barrier film, the first end face, and the upper and side surfaces of the multiple wirings. (18) After forming the first barrier film, a second barrier film having an etching rate different from that of the first barrier film is formed; The method for manufacturing an imaging element according to (16) or (17), wherein, when forming the first insulating film, a third void is formed in the vicinity of a second end face formed by the first opening of the second barrier film, together with the first void and the second void.

[0247] This application claims priority based on Japanese Patent Application No. 2021-088786, filed on May 26, 2021, with the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0248] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. a wiring layer having a plurality of wirings extending in one direction; a first barrier film stacked on the wiring layer and having a first end face above any one of the plurality of wirings; a first insulating film laminated on the wiring layer and the first barrier film; provided between the wiring layer and the first insulating film, a first gap provided between the plurality of adjacent wirings; a second gap provided above the wiring on which the first end surface is provided and in the vicinity of the first end surface; An imaging element comprising:

2. The image sensor according to claim 1 , wherein the first end face has an inverse tapered shape in which an end on the wiring side is set back more.

3. 2. The image sensor according to claim 1, further comprising a second insulating film provided between the first insulating film and the first barrier film and continuously covering the first end surface and upper and side surfaces of the plurality of wirings.

4. a second barrier film provided between the first barrier film and the second insulating film, having a second end face above the wiring together with the first end face, and having an etching rate different from that of the first barrier film; The image sensor according to claim 3 , further comprising a third gap provided in the vicinity of the second end surface of the second barrier film.

5. The imaging element according to claim 4 , wherein the first end surface and the second end surface are formed at different positions from each other.

6. 2. The image sensor according to claim 1, further comprising a third insulating film laminated on the first insulating film and having a flat surface.

7. 7. The image sensor according to claim 6, further comprising a first conductive film that faces at least some of the plurality of wirings with the first insulating film and the third insulating film between them.

8. The image sensor according to claim 7 , wherein the first conductive film is electrically connected to some of the plurality of wirings via a connection portion that penetrates the first insulating film and the third insulating film.

9. The image sensor according to claim 1 , wherein the first insulating film has an uneven surface above the plurality of wirings.

10. 2. The image sensor according to claim 1, wherein the first insulating film is made of a low-dielectric-constant material having a relative dielectric constant k of 3.0 or less.

11. The image sensor according to claim 1 , wherein the first barrier film is made of an insulating material.

12. The image sensor according to claim 1 , wherein the first barrier film is formed for each of the plurality of wirings using a metal material.

13. The image sensor according to claim 6 , wherein the third insulating film is formed using a material having a higher polishing rate than the first insulating film.

14. 7. The image sensor according to claim 6, wherein the third insulating film is formed using silicon oxide, carbon-containing silicon oxide, fluorine-added silicon oxide, or silicon oxynitride.

15. a first substrate having a first semiconductor substrate having a sensor pixel that performs photoelectric conversion, and a multilayer wiring layer including the third insulating film in which the first conductive film is embedded; a second semiconductor substrate having a logic circuit for processing pixel signals based on the charges output from the sensor pixels; and a second substrate having a multi-layer wiring layer in which a second conductive film is embedded; The imaging device according to claim 7 , wherein the first substrate and the second substrate are electrically connected to each other by bonding the first conductive film and the second conductive film.

16. forming a wiring layer having a plurality of wirings extending in one direction; forming a first barrier film on the wiring layer; forming a first opening between the first barrier film and the plurality of adjacent wirings in a predetermined region of the wiring layer; By forming a first insulating film, a first gap is formed between the adjacent wirings, and a second gap is formed in the vicinity of a first end surface formed by the first opening of the first barrier film. A method for manufacturing an imaging element.

17. 17. The method for manufacturing an image sensor according to claim 16, further comprising forming a third insulating film that covers an upper surface of the first barrier film, the first end face, and upper and side surfaces of the plurality of wirings after forming the first opening.

18. After forming the first barrier film, a second barrier film having an etching rate different from that of the first barrier film is formed; 17. The method for manufacturing an image sensor according to claim 16, wherein, when the first insulating film is formed, a third void is formed in the vicinity of a second end face formed by the first opening of the second barrier film, together with the first void and the second void.

Images