Semiconductor device and manufacturing method thereof

Abstract

The present invention provides: a semiconductor device which achieves high bonding strength over the entire bonding regions between a sinterable metal bonding material and a semiconductor element and between the sinterable metal bonding material and a substrate, while being suppressed in breakage of the semiconductor element; and a method for producing this semiconductor device. A semiconductor device (10) according to the present invention is provided with: a substrate (1) that has a first surface (1A); and at least one semiconductor element (2) that is bonded onto the first surface (1A) by means of a sinterable metal bonding material (3). The first surface (1A) is provided with at least one height-difference part (11) on the outer side of the at least one semiconductor element (2) when viewed in plan. The at least one height-difference part (11) extends along at least a part of the outline of the at least one semiconductor element (2), while being arranged inside the outer edge of the substrate (1) when viewed in plan.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] A semiconductor device including a substrate and a semiconductor element bonded to the substrate by a sinterable metal material is known. A known method for manufacturing such a semiconductor device involves heating the substrate, the semiconductor element, and the sinterable metal material under pressure, followed by decompression and cooling, in order to sinter metal particles contained in the sinterable metal material and to diffuse the metal particles into the substrate and the semiconductor element.

[0003] When the heated sinterable metal material, semiconductor element, and substrate return to room temperature, the difference in linear expansion coefficient between the semiconductor element and the substrate causes thermal stress to be applied to the joints, the substrate, etc. In the semiconductor device described in JP 2021-158304 A (Patent Document 1), a gap is formed around the semiconductor element to relieve this thermal stress, and a buffer member made of resin is provided in the gap. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-158304 Summary of the Invention [Problem to be solved by the invention]

[0005] In the semiconductor device described in Patent Document 1, when the pressure is applied by pressing a cushioning material arranged on the semiconductor element with a pressing member, the pressed cushioning material deforms along the gap formed around the semiconductor element. Therefore, in the semiconductor device, it is difficult to uniformly press the semiconductor element and the sintered metal bonding material against the substrate, and as a result, it is difficult to increase the bonding strength over the entire bonding area between the sintered metal bonding material and the semiconductor element and the substrate.

[0006] On the other hand, in the semiconductor device described in Patent Document 1, the pressure is applied by directly pressing the semiconductor element with a pressing member, and therefore, if the semiconductor element is pressed with a stronger force in order to increase the bonding strength over the entire bonding area, there is a risk that the semiconductor element will be damaged.

[0007] The main object of the present disclosure is to provide a semiconductor device and a manufacturing method thereof that has high bonding strength throughout the entire bonding area between the sinterable metal bonding material and each of the semiconductor element and the substrate, while suppressing damage to the semiconductor element. [Means for solving the problem]

[0008] The semiconductor device according to the present disclosure includes a substrate having a first surface and at least one semiconductor element bonded to the first surface with a sinterable metal bonding material. The first surface has at least one stepped portion formed on the outer side of the at least one semiconductor element in a plan view. The at least one stepped portion extends along at least a portion of the outline of the at least one semiconductor element and is located inside the outer edge of the substrate in a plan view.

[0009] A method for manufacturing a semiconductor device according to the present disclosure includes the steps of: preparing a substrate including a first surface having at least one semiconductor element mounting area; forming at least one step portion on the first surface of the substrate, in a plan view, outside the at least one semiconductor element mounting area and inside the outer edge of the substrate; supplying a sinterable metal bonding material to the at least one semiconductor element mounting area; placing a semiconductor element on the sinterable metal bonding material; and placing a buffer material on the semiconductor element, and heating the substrate, sinterable metal bonding material, and semiconductor element while applying pressure with the buffer material. The at least one step portion has a wall surface extending along at least a portion of the outline of the semiconductor element. In the heating step, pressure is applied to bring the buffer material into contact with the wall surface of the at least one step portion. [Effects of the Invention]

[0010] According to the present disclosure, it is possible to provide a semiconductor device and a manufacturing method thereof in which the bonding strength is high throughout the entire bonding area between the sinterable metal bonding material and the semiconductor element and the substrate while suppressing damage to the semiconductor element. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view illustrating a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along the line II-II in FIG. [Figure 3] 3 is a cross-sectional view of a substrate for explaining one step of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 4] 4 is a cross-sectional view of the substrate after the step shown in FIG. 3 in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5A] 5 is a plan view illustrating the positional relationship between a semiconductor element mounting region on a first surface of a substrate and a step portion shown in FIG. 4 in the method for manufacturing a semiconductor device according to the first embodiment. FIG. [Figure 5B] FIG. 5B is a cross-sectional view taken along the arrow VB-VB in FIG. 5A. [Figure 6A] 5B in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 6B] FIG. 6B is a cross-sectional view taken along the arrow VIB-VIB in FIG. 6A. [Figure 7A] 6C is a plan view illustrating a step subsequent to the step shown in FIGS. 6A and 6B in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 7B] FIG. 7B is a cross-sectional view taken along the arrows VIIB-VIIB in FIG. 7A. [Figure 8A] 7C is a plan view for explaining a step subsequent to the step shown in FIGS. 7A and 7B in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 8B] FIG. 8B is a plan view for explaining a step subsequent to the step shown in FIG. 8A. [Figure 8C]FIG. 8C is a cross-sectional view taken along arrows VIIIC-VIIIC in FIG. 8B. [Figure 9] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 10A] FIG. 10 is a cross-sectional view illustrating one step of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 10B] 10B is a cross-sectional view illustrating a step subsequent to the step shown in FIG. 10A in the method for manufacturing the semiconductor device according to the second embodiment. [Figure 10C] 10C is a cross-sectional view illustrating a groove formed by the step shown in FIG. 10B in the method for manufacturing a semiconductor device according to the second embodiment. FIG. [Figure 11] FIG. 10 is a plan view of a semiconductor device according to a third embodiment. [Figure 12] FIG. 10 is a cross-sectional view illustrating a step of forming a step portion in a semiconductor device according to a third embodiment. [Figure 13] FIG. 10 is a plan view of a semiconductor device according to a fourth embodiment. [Figure 14] FIG. 14 is a cross-sectional view taken along the arrows XIV-XIV in FIG. [Figure 15] FIG. 11 is a plan view of a semiconductor device according to a fifth embodiment. [Figure 16] FIG. 16 is a cross-sectional view taken along the arrows XVI-XVI in FIG. [Figure 17A] FIG. 13 is a plan view illustrating one step of a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 17B] FIG. 17B is a cross-sectional view taken along the arrows XVIIB-XVIIB in FIG. 17A. [Figure 18A] 17B in the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. [Figure 18B] FIG. 18B is a cross-sectional view taken along the arrows XVIIIB-XVIIIB in FIG. 18A. [Figure 19] 18C is a plan view illustrating a step subsequent to the step shown in FIGS. 18A and 18B in the method for manufacturing a semiconductor device according to the fifth embodiment. FIG. [Figure 20]FIG. 13 is a plan view of a semiconductor device according to a sixth embodiment. [Figure 21] FIG. 21 is a cross-sectional view taken along the arrows XXI-XXI in FIG. 20. [Figure 22] FIG. 20 is a cross-sectional view illustrating a first modified example of the semiconductor device according to the sixth embodiment. [Figure 23] FIG. 20 is a plan view for explaining a second modified example of the semiconductor device according to the sixth embodiment. [Figure 24] FIG. 24 is a cross-sectional view taken along the arrows XXIV-XXIV in FIG. 23. [Figure 25] FIG. 20 is a cross-sectional view illustrating a third modified example of the semiconductor device according to the sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Embodiment 1 As shown in FIGS. 1 and 2, a semiconductor device 10 includes a substrate 1, a plurality of semiconductor elements 2, and a plurality of sinterable metal bonding materials 3.

[0013] The substrate 1 has a first surface 1A and a second surface 1B located on the opposite side of the first surface 1A. Hereinafter, a view of the first surface 1A viewed from a direction perpendicular to the first surface 1A will be referred to as a planar view. The material constituting the substrate 1 is, for example, a metal material, including, for example, aluminum (Al) or copper (Cu). The material constituting the substrate 1 may be any material, and may be a resin material, a semiconductor material, or the like.

[0014] The first surface 1A has a plurality of semiconductor element mounting areas. One semiconductor element 2 is mounted in each of the plurality of semiconductor element mounting areas. The plurality of semiconductor element mounting areas are arranged, for example, at intervals from one another in the first direction X. An electrode portion (hereinafter referred to as a board electrode) made of a conductive material is formed in each semiconductor element mounting area.

[0015] The first surface 1A is formed with a plurality of step portions 11. In this embodiment, each of the plurality of step portions 11 is a groove recessed into the first surface 1A. The step portions 11 will be described in detail later.

[0016] Each of the plurality of semiconductor elements 2 is bonded to the semiconductor element mounting region of the first surface 1A by a sinterable metal bonding material 3. Each of the plurality of semiconductor elements 2 is, for example, a vertical semiconductor element. Each of the plurality of semiconductor elements 2 has an electrode portion (hereinafter referred to as a back electrode) electrically connected to the substrate electrode via the sinterable metal bonding material 3, and an electrode portion (hereinafter referred to as a front electrode) disposed on the opposite side of the back electrode and intended to be electrically connected to the lead frame. Each semiconductor element 2 is, for example, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), or a free wheeling diode (FWD). The semiconductor element 2 may be a semiconductor element for power use. The semiconductor element for power use 2 is sometimes called a power semiconductor element. The thickness of each semiconductor element 2 is, for example, 50 μm or more and 300 μm or less. In plan view, each semiconductor element 2 has a polygonal shape with multiple corners and multiple sides. The planar shape of each semiconductor element 2 is, for example, a square. The length of each side of each semiconductor element 2 is, for example, 1 mm or more and 100 mm or less.

[0017] Each of the plurality of sinterable metal bonding materials 3 is disposed on the semiconductor element mounting area of ​​the first surface 1A of the substrate 1. On the first surface 1A of the substrate 1, each of the sinterable metal bonding materials 3 is not disposed outside the semiconductor element mounting area.

[0018] Each sinterable metal bonding material 3 is a bonding material used for sinter bonding. The material constituting the sinterable metal bonding material 3 includes at least one selected from the group consisting of gold (Au), silver (Ag), and copper (Cu). Before bonding, the sinterable metal bonding material 3 is a paste-like bonding material containing metal particles, a protective film, and an organic solvent. The sinterable metal bonding material 3 is, for example, a silver (Ag) sinter bonding material. In this case, it is desirable that the average particle size of the Ag particles is 100 μm or less. Each of the protective film and the organic solvent contains an organic component. The protective film protects the metal particles by covering them. The metal particles and the organic solvent are mixed. Preferably, the sinterable metal bonding material 3 does not contain an organic component after bonding.

[0019] Next, the configuration of the step portion 11 will be described with reference to FIGS. As shown in FIG. 1 , in a plan view, each of the plurality of step portions 11 is located inside the outer edge of the first surface 1A of the substrate 1. The step portion 11 is not connected to the outer edge of the first surface 1A. In a plan view, each of the plurality of step portions 11 is located outside the semiconductor element 2 and the sinterable metal bonding material 3, i.e., outside the semiconductor element mounting area. In a plan view, the wall surface of each of the plurality of step portions 11 extends along a part of the outline of the semiconductor element 2 that is closest to the wall surface. In a plan view, each step portion 11 extends, for example, along the side of the semiconductor element 2 that is closest to the step portion 11, and is preferably parallel to the side.

[0020] 1, the number of step portions 11 arranged around one semiconductor element 2 is equal to, for example, the number of sides of the semiconductor element 2. For example, one step portion 11 is formed between two semiconductor elements 2 adjacent to each other in the first direction X. The one step portion 11 is formed, for example, in the center of the two semiconductor elements 2 adjacent to each other with the one step portion 11 sandwiched therebetween.

[0021] The number of step portions 11 is not particularly limited. The number of step portions 11 arranged around one semiconductor element 2 may be greater than the number of sides of the semiconductor element 2, for example. A plurality of step portions 11 may be formed between two semiconductor elements 2 adjacent to each other in the first direction X.

[0022] As shown in FIG. 1, the shortest distance between each of the plurality of step portions 11 and the semiconductor element 2 is shorter than, for example, the shortest distance between each of the plurality of step portions 11 and the outer edge of the first surface 1A.

[0023] 1, in a plan view, each step portion 11 is not arranged on a line intersecting, for example, the center of the semiconductor element 2 closest to each step portion 11 and each of the multiple corners. In a plan view, each of the multiple step portions 11 arranged around one semiconductor element 2 is arranged at intervals from each other across a line intersecting, for example, the center of the semiconductor element 2 and each of the multiple corners. The length of the step portion 11 in the extension direction is, for example, equal to or less than the length of the side portion of the semiconductor element 2.

[0024] As shown in FIG. 2, the step portion 11 is, for example, a groove 11A recessed relative to the first surface 1A. The inner wall surfaces of the grooves 11A are provided so as to extend along the sides of the semiconductor element 2 that are closest to the respective inner wall surfaces in a plan view. The grooves 11A are formed by a single press process, which will be described later. The step portion 11 may also be a protrusion that protrudes from the first surface 1A. In this case, the outer wall surfaces of the protrusions are provided so as to extend along the sides of the semiconductor element 2 that are closest to the respective inner wall surfaces in a plan view.

[0025] There are no particular limitations on the dimensions of step portion 11. As an example, when substrate 1 is a metal plate and has a thickness of 2.5 mm, groove 11A may have a width of 0.25 mm and a depth of 0.07 mm.

[0026] Next, an example of a method for manufacturing the semiconductor device 10 according to the first embodiment will be described with reference to FIGS. 3 to 8A, 8B, and 8C.

[0027] First, a substrate 1 having a first surface 1A is prepared. The first surface 1A has a plurality of semiconductor element mounting areas 1A1. Each semiconductor element mounting area 1A1 is an area where one semiconductor element 2 is to be mounted. At least one substrate electrode is formed in each semiconductor element mounting area 1A1.

[0028] Next, as shown in FIGS. 3, 4, 5A, and 5B, a plurality of grooves 11A are formed on the first surface 1A as step portions 11. Each of the plurality of grooves 11A is formed, for example, by the press process shown in FIGS. 3 and 4. The plurality of grooves 11A are simultaneously formed, for example, by a single press process using a punch 21. Any method may be used to form the plurality of grooves 11A, and may be, for example, machining or etching. As shown in FIG. 5A, in a plan view, each of the plurality of grooves 11A is formed on the first surface 1A outside each of the regions 1A1 (semiconductor element mounting regions) where semiconductor elements are to be mounted.

[0029] Next, as shown in FIGS. 6A and 6B, a plurality of sinterable metal bonding materials 30 are respectively supplied onto a plurality of semiconductor element mounting regions 1A1. Each of the plurality of sinterable metal bonding materials 30 is applied onto a respective one of the plurality of semiconductor element mounting regions 1A1, for example, by printing using a metal mask. Each sinterable metal bonding material 30 is a paste-like bonding material containing metal particles, a protective film, and an organic solvent. Each sinterable metal bonding material 30 is a precursor of each sinterable metal bonding material 3, and becomes the sinterable metal bonding material 3 by drying and sintering in a process described below. Each sinterable metal bonding material 3 is in contact with the substrate electrode.

[0030] The thickness of the sinterable metal bonding material 30 can be set arbitrarily taking into consideration the bonding reliability, thermal resistance, and manufacturing variations required for the semiconductor device 10, but is, for example, 10 μm or more and 100 μm or less. As the thickness of the sinterable metal bonding material 30 increases, the content of organic components in the sinterable metal bonding material 30 also increases, making organic contamination a problem. The organic components in the sinterable metal bonding material 30 refer to the organic components contained in both the protective film and the organic solvent. From the perspective of suppressing the occurrence of organic contamination, the thickness of the sinterable metal bonding material 30 is preferably 50 μm or less.

[0031] The mass fraction of the organic solvent contained in the sinterable metal bonding material 30 supplied onto each semiconductor element mounting region 1A1 of the first surface 1A by the above printing is set from the viewpoint of suppressing variations in thickness among the sinterable metal bonding materials 30 supplied onto each semiconductor element mounting region 1A1. The mass fraction of the organic solvent contained in the sinterable metal bonding material 30 is, for example, 10 mass % or more and 20 mass % or less.

[0032] Next, each of the plurality of sinterable metal bonding materials 30 is heated. This heating step is performed to volatilize the organic components in the sinterable metal bonding material 30 and reduce the mass fraction of the organic components in the sinterable metal bonding material 30. If the mass fraction of the organic components contained in the sinterable metal bonding material 30 at the start of the sintering step described below is approximately the same as the mass fraction of the organic components contained in the sinterable metal bonding material 30 at the time of application, the organic components in the sinterable metal bonding material 30 will hinder the sintering bonding between the semiconductor element 2 and the substrate 1, and the organic components will remain in the sinterable metal bonding material 3 after sintering, making organic contamination more likely to occur.

[0033] The processing conditions of this heating step are set, for example, so that the organic components contained in the sinterable metal bonding material 30 after heating are 95% by mass or more less than the organic components contained in the sinterable metal bonding material 30 at the time of application. For example, the substrate 1 on which the sinterable metal bonding material 30 has been supplied is heated to 130°C for 20 minutes.

[0034] 7A and 7B, each of the plurality of semiconductor elements 2 is mounted on each of the dried sinterable metal bonding materials 30. Each of the plurality of semiconductor elements 2 has a back surface electrode, and is placed on the sinterable metal bonding material 30 so that the back surface electrode is in contact with each of the sinterable metal bonding materials 30. In this way, the semiconductor element 2 is positioned relative to the substrate 1.

[0035] 8A, 8B, and 8C, the substrate 1, the sinterable metal bonding material 30, and the semiconductor element 2 are heated while being pressed via the buffer material 8. As a result, the semiconductor element 2 is bonded to the semiconductor element mounting area 1A1 of the substrate 1 by the sinterable metal bonding material 3.

[0036] Specifically, first, as shown in FIG. 8A, buffer material 8 is placed on the opposite side of substrate 1 with respect to each of the multiple semiconductor elements 2. As shown in FIG. 8A, the depth of groove 11A from first surface 1A is equal to or less than the value obtained by subtracting the sum of the thicknesses of semiconductor elements 2 and sintered metal bonding material 30 from the thickness of buffer material 8 before pressure is applied. The thickness of buffer material 8 before pressure is applied is greater than the sum of the thickness of semiconductor elements 2, the thickness of sintered metal bonding material 30 after pressure is applied, and the depth of groove 11A. The thickness of buffer material 8 before pressure is applied is, for example, 1 mm.

[0037] Next, as shown in Figures 8B and 8C, a pressure head 9 arranged on the opposite side of the buffer material 8 from each of the multiple semiconductor elements 2 presses the buffer material 8 toward the substrate 1, and in this pressurized state, the substrate 1, the multiple sinterable metal bonding materials 30, and the multiple semiconductor elements 2 are heated.

[0038] The cushioning material 8 is provided so as to be deformed by the application of pressure by the pressure head 9. Specifically, the cushioning material 8 is deformed so as to become thinner by the application of pressure. For example, the thickness of the cushioning material 8 becomes thinner than 1 mm, which is the thickness before the application of pressure, by the application of pressure.

[0039] 8B , the buffer material 8 is provided so as to overlap each of the plurality of semiconductor elements 2 and each of the plurality of grooves 11A (step portions 11) formed around each of the plurality of semiconductor elements 2 in a plan view when the buffer material 8 is being pressed. The pressure head is configured to pressurize the plurality of semiconductor elements 2 and the plurality of sinterable metal bonding materials 30 together via the buffer material 8. The pressure head is provided so as to overlap each of the plurality of semiconductor elements 2 and each of the plurality of grooves 11A (step portions 11) formed around each of the plurality of semiconductor elements 2 in a plan view when the buffer material 8 is being pressed.

[0040] In addition, the buffer material 8 only needs to be arranged so that, when viewed in a plane while under pressure, it overlaps at least one semiconductor element 2 and each of the multiple grooves 11A (step portions 11) formed around the one semiconductor element 2.

[0041] As shown in FIG. 8C , the buffer material 8 is configured to deform under pressure and enter the multiple grooves 11A. When pressure is applied, the buffer material 8 deforms from the center of the semiconductor element mounting area 1A1 toward the outside in a plan view, but the grooves 11A and the portions of the buffer material 8 that enter the grooves 11A act as resistance to prevent this deformation. This is because, before the portions of the buffer material 8 that enter the grooves 11A can move outward beyond the grooves 11A, they must first move out of the grooves 11A against the direction of pressure. As a result, the buffer material 8 tends to remain on the semiconductor element 2 even under pressure. This makes the semiconductor element 2 less susceptible to damage due to pressure, and the semiconductor element 2 and the sinterable metal bonding material 30 can receive sufficient pressure via the buffer material 8, which has a sufficient thickness.

[0042] Preferably, the buffer material 8 is provided so as to fill the interior of each of the plurality of grooves 11A when in a pressurized state.

[0043] In this step, the substrate 1, the sinterable metal bonding material 30, and the semiconductor element 2 are heated to 300°C while being pressurized to 20 MPa by the pressure head 9 and the buffer material 8. From the viewpoints of heat resistance and buffering properties, the material constituting the buffer material 8 is preferably silicone rubber, polyimide, or fluorine-based resin.

[0044] The sinterable metal bonding material 3 formed from the sinterable metal bonding material 30 in this process utilizes a phenomenon (diffusion bonding) in which metal fine particles are sintered at a temperature lower than the melting point of the metal to bond between the sinterable metal bonding material 3 and the substrate 1, and also to bond between the sinterable metal bonding material 3 and the semiconductor element 2. Specifically, each of the multiple metal fine particles contained in the sinterable metal bonding material 3 is bonded to each other by diffusion bonding, and also to the back electrode or substrate electrode of the semiconductor element by diffusion bonding. The melting point of the metal fine particles bonded by diffusion bonding is the intrinsic melting point of the metal. The intrinsic melting point of the metal is higher than the heating temperature in this process. Therefore, the sinterable metal bonding material 3 has heat resistance higher than the heating temperature during diffusion bonding.

[0045] After this step, the buffer material 8 is removed from above the semiconductor element 2. In this manner, the semiconductor device 10 is manufactured.

[0046] Next, the effects of the semiconductor device 10 according to the first embodiment will be described in comparison with comparative examples 1 and 2.

[0047] The semiconductor device according to Comparative Example 1 differs from the semiconductor device 10 only in that the groove 11A is not formed around the semiconductor element mounting area 1A1. In Comparative Example 1, because the groove 11A is not formed, the buffer material is easily pushed out from above the semiconductor element to the periphery of the semiconductor element when pressure is applied. In particular, the buffer material near the outer edges (sides and corners) of the semiconductor element in a planar view is likely to become thinner than the buffer material near the center of the semiconductor element. The thinner portions of the buffer material are less likely to transmit force to the semiconductor element and the sintered metal bonding material when pressure is applied compared to the thicker portions. Therefore, in Comparative Example 1, the bonding strength of the sintered metal bonding may be partially reduced. On the other hand, in Comparative Example 1, if the pressure is increased to ensure sufficient bonding strength even in the thinner portions of the buffer material, a large force is applied to the center of the semiconductor element, which may damage the semiconductor element.

[0048] The semiconductor device according to Comparative Example 2 differs from semiconductor device 10 only in that the grooves are connected to the outer edge of the first surface. In Comparative Example 2, the pressurized buffer material may deform along the grooves toward the outer edge of the first surface, and the grooves connected to the outer edge of the first surface and the portions of the buffer material that penetrate into the grooves do not adequately act as resistance to prevent the deformation. Therefore, in Comparative Example 2, the buffer material is also likely to be extruded from above the semiconductor element toward the periphery of the semiconductor element under pressure, which may partially reduce the bonding strength of the sintered metal bond. Furthermore, in Comparative Example 2, if the pressure applied is increased to ensure sufficient bonding strength even in the thin portions of the buffer material, a large force is applied to the center of the semiconductor element, which may damage the semiconductor element.

[0049] In contrast, in the semiconductor device 10 according to the present embodiment, each of the plurality of grooves 11A is formed outward from the semiconductor element 2 in a plan view so as to follow the edge of the semiconductor element 2 and is disposed inside the outer edge of the first surface 1A in a plan view. This allows the buffer material 8 to easily remain near the outer edge of the semiconductor element 2 when pressurized. Therefore, the semiconductor element 2 is less likely to be damaged by pressure, and the semiconductor element 2 and the sintered metal bonding material 30 can receive a sufficient pressure through the buffer material 8, which has a sufficient thickness. As a result, in the semiconductor device 10, damage to the semiconductor element 2 is suppressed compared to Comparative Examples 1 and 2, while the bonding strength between the substrate 1 and the sintered metal bonding material 3 and the bonding strength between the semiconductor element 2 and the sintered metal bonding material 3 are increased throughout the entire bonding regions.

[0050] Furthermore, in the semiconductor device 10, adhesion of foreign matter to the semiconductor element 2 is suppressed compared to when the semiconductor element is directly pressed by the pressure head.

[0051] In the semiconductor device 10, in a plan view, each of the plurality of grooves 11A extends along a portion of the outline of each of the plurality of semiconductor elements 2. In other words, in a plan view, the buffer material 8 located near the remaining portion of the outline of each of the plurality of semiconductor elements 2 is more easily deformed under pressure than the buffer material 8 located near the portion of the outline of each of the plurality of semiconductor elements 2. Therefore, organic components volatilized from the sinterable metal bonding material 30 can be discharged to the outside of the buffer material 8 through the portion of the buffer material 8 that is relatively easy to deform. In other words, the portion of the buffer material 8 that is relatively easy to deform can serve as a discharge path for organic components volatilized from the sinterable metal bonding material 30. As a result, in the semiconductor device 10, organic contamination can be suppressed more effectively than when each of the plurality of grooves 11A is formed to surround the entire outline of one semiconductor element 2.

[0052] On the other hand, in the semiconductor device 10, each of the plurality of grooves 11A may extend along the entire outline of the plurality of semiconductor elements 2. In other words, each of the plurality of grooves 11A may be provided so as to surround the entire periphery of the outline of one semiconductor element 2. In this case, the grooves 11A are formed wider than in the semiconductor device 10, and therefore are more effective in preventing the above-mentioned deformation of the buffer material 8.

[0053] Furthermore, in semiconductor device 10, each of the plurality of grooves 11A is disposed at intervals across a straight line that intersects with the center and each of the plurality of corners of one semiconductor element 2. In other words, each of the plurality of grooves 11A is not connected to each other across the straight line, and grooves 11A extending along a first side of semiconductor element 2 are not connected to grooves 11A extending along a second side that intersects with the first side of semiconductor element 2. Such a plurality of grooves 11A can be easily formed, for example, by press working.

[0054] On the other hand, in the semiconductor device 10, the plurality of grooves 11A may be connected to one another across the straight line. The groove 11A extending along a first side of the semiconductor element 2 may be connected to a groove 11A extending along a second side intersecting the first side of the semiconductor element 2. Such a plurality of grooves 11A can be easily formed, for example, by a method other than press working.

[0055] According to the manufacturing method of the semiconductor device 10 of this embodiment, in the heating step, pressure is applied to bring the buffer material 8 into contact with the inner wall surface of each of the plurality of grooves 11A, which are formed along the edges of the semiconductor element 2 and outward from the semiconductor element 2 in a plan view and are disposed inward from the outer edge of the first surface 1A in a plan view. In other words, according to the manufacturing method of the semiconductor device 10, it is relatively easy to bring about a state in which the buffer material 8 remains sufficiently near the outer edge of the semiconductor element 2, and the diffusion bonding can proceed in this state. Therefore, according to the manufacturing method of the semiconductor device 10, it is relatively easy to manufacture a semiconductor device 10 in which the bonding strength between the substrate 1 and the sinterable metal bonding material 3 and the bonding strength between the semiconductor element 2 and the sinterable metal bonding material 3 are increased throughout the entire bonding regions while suppressing damage to the semiconductor element 2.

[0056] Embodiment 2 9, the semiconductor device 20 according to the second embodiment has basically the same configuration and produces the same effects as the semiconductor device 10 according to the first embodiment, but differs from the semiconductor device 10 in that each of the plurality of grooves 11A has a first portion 11A1 and a second portion 11A2. The following mainly describes the differences between the semiconductor device 20 and the semiconductor device 10.

[0057] 9, in a cross section perpendicular to the extension direction of groove 11A, first portion 11A1 has a first bottom surface 12 and a pair of first wall surfaces 13 that face each other across first bottom surface 12. First bottom surface 12 forms the bottom surface of groove 11A. Each of the pair of first wall surfaces 13 is connected to each end of first bottom surface 12 in a direction perpendicular to the extension direction of groove 11A.

[0058] The angle that each of the pair of first wall surfaces 13 forms with the first bottom surface 12 inside the groove 11A is an acute angle. The width of the first portion 11A1 in a direction perpendicular to the extension direction of the groove 11A, i.e., the distance between the pair of first wall surfaces 13, gradually narrows toward the first surface 1A. From a different perspective, the cross-sectional shape of the first portion 11A1 is a so-called inverted mesa shape. The minimum width of the first portion 11A1 in the direction perpendicular to the extension direction of the groove 11A is the distance between the ends (hereinafter referred to as upper ends) of the pair of first wall surfaces 13 located on the first surface 1A side. The maximum width of the first portion 11A1 in the direction perpendicular to the extension direction of the groove 11A is the width of the first bottom surface 12 in that direction.

[0059] 9, in a cross section perpendicular to the extension direction of the groove 11A, the second portion 11A2 is connected to an end portion of the first portion 11A1 located on the first surface 1A side. The second portion 11A2 has a pair of second bottom surfaces 14 connected to upper ends of the first wall surfaces 13, and a pair of second wall surfaces 15 facing each other with the pair of second bottom surfaces 14 interposed therebetween.

[0060] Each of the pair of second bottom surfaces 14 is parallel to the first bottom surface 12, for example. The angle that each of the pair of second bottom surfaces 14 forms with each of the pair of first wall surfaces 13 outside the groove 11A is an acute angle. Each of the pair of second wall surfaces 15 is connected to each end of the pair of second bottom surfaces 14 in a direction perpendicular to the extension direction of the groove 11A. Each of the pair of second wall surfaces 15 is perpendicular to each of the pair of second bottom surfaces 14, for example.

[0061] The width of the second portion 11A2 in a direction perpendicular to the extension direction of the groove 11A, i.e., the distance between the pair of second wall surfaces 15, is wider than the minimum width of the first portion 11A1. The width of the second portion 11A2 in a direction perpendicular to the extension direction of the groove 11A is wider than the maximum width of the first portion 11A1, for example. The depth of the second portion 11A2 is shallower than the depth of the first portion 11A1, for example.

[0062] The dimensions of the groove 11A are not particularly limited, but as an example, the maximum width of the first portion 11A1 is 0.15 mm, the depth of the first portion 11A1 is 0.07 mm, the maximum width of the second portion 11A2 is 0.25 mm, and the depth of the second portion 11A2 is 0.04 mm.

[0063] In the semiconductor device 20, it is sufficient that at least one groove 11A has a first portion 11A1 and a second portion 11A2.

[0064] The method for manufacturing semiconductor device 20 has basically the same configuration as the method for manufacturing semiconductor device 10, but differs from the method for manufacturing semiconductor device 10 in that the process for forming groove 11A includes a first process for forming first portion 11A1 and a second process for forming second portion 11A2. The following mainly describes the differences between the method for manufacturing semiconductor device 20 and the method for manufacturing semiconductor device 10.

[0065] In the step of forming groove 11A, first, a first groove 16 having a first width is formed as shown in Fig. 10A. First groove 16 can be formed by the same method as groove 11A of semiconductor device 10. First groove 16 is formed, for example, by a single press process using a punch having the first width.

[0066] In the step of forming groove 11A, next, as shown in Fig. 10B, first groove 16 is pressed with punch 22 having a second width wider than the first width. As a result, as shown in Fig. 10C, first groove 16 is deformed so that its wall surface tilts inward to form first portion 11A1, and further, second portion 11A2 continuous with first portion 11A1 is formed.

[0067] In the manufacturing method of the semiconductor device 20, in the step of heating the substrate 1, the sintered metal bonding material 30, and the semiconductor element 2 while being pressurized via the buffer material 8, the pressure is applied until the buffer material 8 contacts the first bottom surface 12 of the first portion 11A1, and then the heating is performed. Therefore, the buffer material 8 that has entered the inside of the first portion 11A1 is less likely to come out of the first portion 11A1, and the buffer material 8 is more likely to remain on the semiconductor element 2. As a result, in the semiconductor device 20, compared to the semiconductor device 10, the semiconductor element 2 is less likely to be damaged by pressure, and the semiconductor element 2 and the sintered metal bonding material 30 can more reliably receive a sufficient pressure force via the buffer material 8, which has a sufficient thickness.

[0068] Embodiment 3 11, the semiconductor device 130 according to the third embodiment has basically the same configuration as the semiconductor device 10 according to the first embodiment, but differs from the semiconductor device 10 in that each of the plurality of step portions 11 is arranged outward from the outermost semiconductor element 2 among the plurality of semiconductor elements 2 in a plan view. In other words, in the semiconductor device 130, no step portion 11 is formed between adjacent semiconductor elements 2.

[0069] 11, the plurality of semiconductor elements 2 are arranged side by side in a first direction along the first surface 1A, and are also arranged side by side in a second direction along the first surface 1A and perpendicular to the first direction. In plan view, the plurality of step portions 11 include a set of step portions 11 arranged outward from a first set of semiconductor elements 2 arranged outermost in the first direction, and a second set of step portions 11 arranged outermost from a set of semiconductor elements 2 arranged outermost in the second direction. In plan view, the step portions 11 are not formed between the semiconductor elements 2 adjacent to each other in the first direction and between the semiconductor elements 2 adjacent to each other in the second direction.

[0070] Such a semiconductor device 130 can be manufactured in the same manner as the semiconductor device 10. In the manufacturing method of the semiconductor device 130, the buffer material 8 is less likely to deform outward than the plurality of step portions 11, so it is relatively easy to achieve a state in which the buffer material 8 remains sufficiently near the outer edge of the semiconductor element 2, and the diffusion bonding can proceed in this state. Furthermore, in the semiconductor device 130, the step portions 11 are not formed between adjacent semiconductor elements 2, so the space between adjacent semiconductor elements 2 into which the buffer material 8 can enter is smaller than in the semiconductor device 10, and this space is filled with the buffer material 8 relatively quickly. As a result, in the semiconductor device 130, the adjacent semiconductor elements 2 and the sinterable metal bonding material 30 for bonding each semiconductor element 2 can receive a greater pressure than in the semiconductor device 10.

[0071] As shown in FIG. 11, a semiconductor device 130 includes a ceramic plate 4, a substrate 1 fixed to one surface of the ceramic plate 4, and a substrate 5 fixed to the other surface of the ceramic plate 4. A second surface 1B of the substrate 1 is fixed to one surface of the ceramic plate 4. A plurality of grooves 11A are formed, for example, by etching the first surface 1A of the substrate 1. As shown in FIG. 12, the etching is performed using a mask pattern 6 formed of, for example, a resist. The mask pattern 6 has through holes 6A formed in areas where the grooves 11A are to be formed.

[0072] The dimensions of the substrate 1, the ceramic plate 4, and the substrate 5 are not particularly limited, but as an example, the thickness of the ceramic plate 4 is 0.64 mm, and the thickness of each of the substrates 1 and 5 is 0.8 mm. The thickness of the resist is, for example, 10 μm or more and 20 μm or less. The depth of the groove 11A is, for example, 0.2 mm. The thickness of the semiconductor element 2 is, for example, 150 μm. The thickness of the sinterable metal bonding material 3 is, for example, 30 μm. The thickness of the buffer material 8 is, for example, 500 μm.

[0073] Embodiment 4 13 and 14, semiconductor device 40 according to the fourth embodiment has basically the same configuration as semiconductor device 10 according to the first embodiment and achieves the same effects, but differs from semiconductor device 10 in that step portion 11 is formed as protrusion 11B rather than groove 11A. The following mainly describes the differences between semiconductor device 40 and semiconductor device 10.

[0074] The protrusion 11B protrudes from the first surface 1A of the substrate 1. The dimensions of the protrusion 11B are not particularly limited, but as an example, the height of the protrusion 11B is 100 μm and the width of the protrusion 11B is 500 μm.

[0075] The thickness of the buffer material 8 is, for example, thicker than the sum of the thickness of the semiconductor element 2 and the thickness of the sintered metal bonding material 3. The thickness of the buffer material 8 is not particularly limited, but is, for example, 500 μm when the sum of the thickness of the semiconductor element 2 and the thickness of the sintered metal bonding material 3 is 180 μm.

[0076] In the semiconductor device 40, each of the multiple protrusions 11B is formed outside the semiconductor element 2 in a plan view so as to follow the edge of the semiconductor element 2 and is positioned inside the outer edge of the first surface 1A in a plan view. Therefore, the buffer material 8 is likely to remain near the outer edge of the semiconductor element 2 when pressurized. Specifically, the distance between the protrusions 11B and the pressure head 9 is narrower than the distance between the pressure head 9 and an area of ​​the first surface 1A where the protrusions 11B are not formed. Therefore, the buffer material 8 on the semiconductor element mounting area 1A1, which is inside the narrow space between the protrusions 11B and the pressure head 9, is unlikely to escape to the outside of the narrow space through the narrow space. Therefore, in the semiconductor device 40, as in the semiconductor device 10, the semiconductor element 2 is unlikely to be damaged by pressure, and the semiconductor element 2 and the sinterable metal bonding material 30 can receive sufficient pressure through the buffer material 8, which has a sufficient thickness. As a result, in the semiconductor device 40, compared to the above-mentioned Comparative Example 1 and Comparative Example 2, damage to the semiconductor element 2 is suppressed, while the bonding strength between the substrate 1 and the sintered metal bonding material 3 and the bonding strength between the semiconductor element 2 and the sintered metal bonding material 3 are increased throughout the entire bonding area.

[0077] Protrusion 11B may have a widened portion in which the width of protrusion 11B in a direction perpendicular to the extending direction of protrusion 11B gradually increases with increasing distance from first surface 1A. In this case, the widened portion of protrusion 11B can function in the same manner as first portion 11A1 of groove 11A in the second embodiment.

[0078] Embodiment 5. 15 and 16, a semiconductor device 50 according to the fifth embodiment includes a substrate 1, a semiconductor element 2, and a sinterable metal bonding material 3, which have the same configurations as those of the semiconductor device 10 according to the first embodiment, a first lead frame 51, a second lead frame 52, and a sealing body 53. The following mainly describes the differences between the semiconductor device 50 and the semiconductor device 10.

[0079] The first lead frame 51 is bonded to the surface electrodes of each of the semiconductor elements 2 by a conductive bonding material 54. The conductive bonding material 54 may be any bonding material having conductivity, such as solder. The first lead frame 51 may be ultrasonically bonded to the surface electrodes of each of the semiconductor elements 2.

[0080] The second lead frame 52 is bonded to, for example, the pad portion of the substrate 1 with a conductive bonding material (not shown). The second lead frame 52 is electrically connected via a plurality of wires 55 to the substrate electrodes, which are electrically connected to the back surface electrodes of the plurality of semiconductor elements 2.

[0081] The sealing body 53 covers the first surface 1A of the substrate 1, the sinterable metal bonding material 3, the plurality of semiconductor elements 2, and a portion of each of the first lead frame 51 and the second lead frame 52. A portion of the sealing body 53 is disposed inside the groove 11A. The inside of the groove 11A is filled with, for example, the sealing body 53. Note that a conductive bonding material may be present inside the groove 11A.

[0082] In the method for manufacturing the semiconductor device 50, first, the semiconductor device 10 shown in FIGS. 17A and 17B is prepared.

[0083] Second, as shown in FIGS. 18A and 18B , the first lead frame 51 is bonded to the surface electrode with a conductive bonding material 54, and the second lead frame 52 is bonded to the pad portion of the substrate 1 with a conductive bonding material. In this process, even if the molten conductive bonding material 54 flows out from the substrate electrode or the pad portion, the flowed conductive bonding material can flow into the grooves 11A. Therefore, each of the grooves 11A can prevent one of the conductive bonding material 54 bonded to the first lead frame 51 and the conductive bonding material bonded to the second lead frame 52 from flowing out and mixing with the other, which would cause an electrical short circuit between the first lead frame 51 and the second lead frame 52. From a different perspective, this process does not require forming a pattern for preventing the short circuit on the first surface 1A using a resist or the like.

[0084] 18A and 18B, in the semiconductor device 50, in a plan view, at least one step portion 11 is disposed between the first lead frame 51 and the second lead frame 52 and extends in a direction intersecting the direction in which the first lead frame 51 and the second lead frame 52 are arranged side by side. In a plan view, the at least one step portion 11 extends, for example, in a direction perpendicular to the direction in which the first lead frame 51 and the second lead frame 52 are arranged side by side.

[0085] 19, wires 55 are formed to electrically connect the second lead frame 52 and the back surface electrode. The wires 55 are ultrasonically bonded to the second lead frame 52 and the back surface electrode.

[0086] Fourth, the sealing body 53 is formed. The sealing body 53 is formed by, for example, a transfer molding method. In this case, the semiconductor device 10, and the first lead frame 51 and the second lead frame 52 joined to the semiconductor device 10 with a conductive bonding material are placed in a cavity and heated. The heating temperature is, for example, about 200°C. Then, molten resin is filled into the cavity. The pressure applied to the molten resin is, for example, 10 MPa. As a result, the molten resin also fills the interiors of the multiple grooves 11A. The molten resin filled into the cavity is cooled and hardened. In this manner, the semiconductor device 50 is manufactured.

[0087] In the process of forming the encapsulant 53, differences in the linear expansion coefficients between the material constituting the substrate 1 and the material constituting the encapsulant 53 result in differences in the amounts of expansion and contraction between the substrate 1 and the encapsulant 53. If the groove 11A were not formed on the first surface 1A of the substrate 1, the differences in the amounts of expansion and contraction would cause the encapsulant 53 to peel off from the first surface 1A of the substrate 1. In contrast, in the semiconductor device 50, the groove 11A is formed on the first surface 1A of the substrate 1, and a portion of the encapsulant 53 is disposed inside the groove 11A. This allows the encapsulant 53 to exert an anchor effect, thereby preventing the encapsulant 53 from peeling off. As a result, the semiconductor device 50 has a longer lifespan because the semiconductor element 2 is more stably protected than a semiconductor device in which the groove 11A is not formed on the first surface 1A of the substrate 1.

[0088] In addition, the step portion 11 in the semiconductor device 50 of embodiment 5 may be configured as the groove 11A in the semiconductor device 20 of embodiment 2 or the semiconductor device 130 of embodiment 3, or the protrusion 11B in the semiconductor device 40 of embodiment 4.

[0089] When the step portion 11 of the semiconductor device 50 is configured as a groove 11A of the semiconductor device 20, the molten conductive bonding material or the molten resin flows into each of the first portion 11A1 and the second portion 11A2 of the groove 11A. The contact angle of the molten conductive bonding material or the molten resin at the connection portion between the pair of first wall surfaces 13 and the pair of second bottom surfaces 14 of the groove 11A is larger than when the groove 11A has only a pair of wall surfaces. Therefore, the molten conductive bonding material or the molten resin that flows into the inside of the groove 11A is less likely to flow out of the groove 11A.

[0090] Embodiment 6 20 and 21 are a plan view and a cross-sectional view of a semiconductor device 60 according to a sixth embodiment. As shown in FIGS. 20 and 21, the semiconductor device 60 has basically the same configuration as the semiconductor device 10 according to the first embodiment and achieves the same effects, but differs from the semiconductor device 10 in that the step portion 11 is formed on the inner wall surface of a recess 61 having the first surface 1A as the bottom surface. The following mainly describes the differences between the semiconductor device 60 and the semiconductor device 10.

[0091] The substrate 1 is formed with a recess 61 having the first surface 1A as its bottom surface and an inner wall surface extending in a direction intersecting the first surface 1A as its outer edge. The step portion 11 includes an inner wall surface 1C of the recess 61. In a plan view, the semiconductor element mounting area 1A1 is formed inside the inner wall surface 1C of the recess 61. In a plan view, the inner wall surface 1C of the recess 61 is formed so as to surround, for example, a plurality of semiconductor elements 2 and a sinterable metal bonding material 30. In a plan view, the inner wall surface 1C of the recess 61 is not connected to, for example, the outer edge of the substrate 1. In a plan view, the inner wall surface 1C of the recess 61 extends along a part of the outline of the semiconductor element 2 closest to the inner wall surface 1C, and is preferably parallel to a part of the outline.

[0092] From a different perspective, the substrate 1 has a protrusion 62 protruding from the first surface 1A. The protrusion 62 is configured integrally with a main body portion 63 of the substrate 1 having the first surface 1A. The protrusion 62 has an inner edge that is an inner wall surface extending in a direction intersecting with the first surface 1A. The step portion 11 is formed on the inner edge of the protrusion 62. In a plan view, the protrusion 62 is formed so as to surround the entire periphery of, for example, the plurality of semiconductor elements 2 and the sinterable metal bonding material 30.

[0093] The depth of the recess 61 is preferably less than the sum of the thickness of the semiconductor element 2 and the thickness of the sinterable metal bonding material 3. More preferably, the depth of the recess 61 is approximately equal to the thickness of the sinterable metal bonding material 3. The depth of the recess 61 is, for example, 50 μm. The semiconductor element 2 has a front surface 2A on which a front surface electrode (not shown) is formed and which is bonded to the lead frame via a conductive bonding material, and a back surface 2B on which a back surface electrode (not shown) is formed and which is bonded by the sinterable metal bonding material 30. The potential of the substrate 1 is equal to the potential of the back surface 2B of the semiconductor element 2. A potential difference exists between the front surface electrode and the back surface electrode. Therefore, if the inner wall surface of the recess 61 approaches the front surface electrode of the semiconductor element 2, a short circuit may occur. In other words, if the depth of the recess 61 is approximately equal to the sum of the thickness of the semiconductor element 2 and the thickness of the sinterable metal bonding material 3, a short circuit may occur between the recess 61 and the front surface electrode of the semiconductor element 2 unless the distance between them is sufficiently long. On the other hand, if the depth of the recess 61 is less than the sum of the thickness of the semiconductor element 2 and the thickness of the sinterable metal bonding material 3, the short circuit is less likely to occur.

[0094] When the inner wall surface 1C of the recess 61 is formed at a position sufficiently far from the semiconductor element 2 in plan view, the depth of the recess 61 can be selected arbitrarily and is not limited as described above. This is because the probability of the above-mentioned short circuit defect occurring can be reduced even in this case.

[0095] The recess 61 in the semiconductor device 60 can achieve the same effect as the groove 11A in the semiconductor device 10 and the protrusion 11B in the semiconductor device 40. Specifically, in the manufacturing method of the semiconductor device 60, when the semiconductor element 2 is bonded to the semiconductor element mounting region 1A1 of the substrate 1 by the sinterable metal bonding material 3, the substrate 1, the sinterable metal bonding material 30, and the semiconductor element 2 are heated while being pressurized via the buffer material 8. In this state, the buffer material 8 tends to remain near the outer edge of the semiconductor element 2, so that the semiconductor element 2 is less likely to be damaged by the pressure, and the semiconductor element 2 and the sinterable metal bonding material 30 can receive a sufficient pressure force via the buffer material 8 having a sufficient thickness. As a result, in the semiconductor device 60, compared to the above-described Comparative Examples 1 and 2, damage to the semiconductor element 2 is suppressed, while the bonding strength between the substrate 1 and the sinterable metal bonding material 3 and the bonding strength between the semiconductor element 2 and the sinterable metal bonding material 3 are increased throughout the entire bonding region.

[0096] The semiconductor device 60 can be manufactured in the same manner as the semiconductor device 10. In the manufacturing method of the semiconductor device 60, the recess 61 may be formed by press working, or may be formed by at least one of cutting and laser working, similar to the groove 11A of the semiconductor device 10 according to the first embodiment.

[0097] It should be noted that in the semiconductor device 60, the recess 61 is not limited to the configuration shown in Figures 20 and 21. Figures 22 to 25 are diagrams for explaining modified examples of the semiconductor device 60.

[0098] 22, in a plan view, the inner wall surface 1C of the recess 61 is formed inside the outer edge of the substrate 1 in a first direction along the first surface 1A, and may reach the outer edge of the substrate 1 in a second direction along the first surface 1A and intersecting the first direction. In a plan view, the inner wall surface 1C of the recess 61 is formed so as to sandwich the semiconductor element 2 and the sinterable metal bonding material 3 only in the first direction.

[0099] The recess 61 shown in Fig. 22 can be formed more easily than the recess 61 shown in Fig. 20. For example, the recess 61 shown in Fig. 22 can be formed by cutting using an end mill.

[0100] 20 and 22, one recess 61 is formed for a plurality of (for example, two) semiconductor elements 2, but one recess 61 may be formed for each individual semiconductor element 2. From a different perspective, in the semiconductor device 60, a plurality of recesses 61 may be formed so as to be separated from one another.

[0101] 23, 24, and 25, a plurality of recesses with different depths may be formed on the first surface 1A side of the substrate 1. The substrate 1 may also have a second recess 64 formed therein, which is continuous with the recess 61.

[0102] 23 and 24, the bottom surface 1D of the second recess 64 is connected to the inner wall surface 1C of the recess 61 and may extend outward beyond the inner wall surface 1C. In plan view, the first inner wall surface 1E of the second recess 64 is formed, for example, to surround the inner wall surface 1C of the recess 61. From a different perspective, in plan view, the recess 61 is formed, for example, inside the second recess 64. In plan view, the protrusion 62 is formed, for example, to surround the entire periphery of the second recess 64.

[0103] The first inner wall surface 1E of the second recess 64 may be formed inside the outer edge of the substrate 1 in a first direction along the first surface 1A, and may reach the outer edge of the substrate 1 in a second direction that is along the first surface 1A and intersects with the first direction. In this case, the inner wall surface 1C of the recess 61 may also be formed inside the outer edge of the substrate 1 in the first direction along the first surface 1A, and may reach the outer edge of the substrate 1 in the second direction that is along the first surface 1A and intersects with the first direction.

[0104] 24, the depth of the bottom surface 1D of the second recess 64 relative to the top surface of the substrate 1 is different from the depth of the first surface 1A relative to the top surface of the substrate 1. The bottom surface 1D of the second recess 64 is disposed at a distance from the first surface 1A in a direction perpendicular to the first surface 1A.

[0105] 24, the depth of the bottom surface 1D of the second recess 64 relative to the top surface of the substrate 1 may be shallower than the depth of the first surface 1A relative to the top surface of the substrate 1. The bottom surface 1D of the second recess 64 may protrude relative to the first surface 1A. The bottom surface 1D of the second recess 64 may be located on the opposite side of the first surface 1A from the second surface 1B. In this case, the outer edge of the first surface 1A and the inner edge of the bottom surface 1D of the second recess 64 are connected via the inner wall surface 1C of the recess 61.

[0106] As shown in FIG. 25, the depth of the bottom surface 1D of the second recess 64 relative to the top surface of the substrate 1 may be deeper than the depth of the first surface 1A relative to the top surface of the substrate 1. The bottom surface 1D of the second recess 64 may be recessed relative to the first surface 1A. The bottom surface 1D of the second recess 64 may be located closer to the second surface 1B than the first surface 1A. In this case, the second recess 64 has a first inner wall surface 1E and a second inner wall surface 1F that face each other. The first inner wall surface 1E is located closer to the protrusion 62 (outside) than the bottom surface 1D of the second recess 64. The second inner wall surface 1F is located closer to the semiconductor element 2 (inside) than the bottom surface 1D of the second recess 64. The first inner wall surface 1E is connected to the inner wall surface 1C of the recess 61. For example, the first inner wall surface 1E is connected to the inner wall surface 1C of the recess 61 so as to form the same plane. The second inner wall surface 1F connects the outer edge of the first surface 1A and the inner edge of the bottom surface 1D of the second recess 64.

[0107] The first surface 1A of the recess 61 may have an outer portion located outside the second recess 64. The first inner wall surface 1E of the second recess 64 may be connected to the inner wall surface 1C of the recess 61 via the outer portion of the first surface 1A.

[0108] 23 to 25 can be manufactured in the same manner as the semiconductor device 60 shown in Figures 21 and 22. In the method for manufacturing the semiconductor device 60 shown in Figure 24, for example, the recess 61 is formed after the second recess 64 is formed. In the method for manufacturing the semiconductor device 60 shown in Figure 25, for example, the second recess 64 is formed after the recess 61 is formed.

[0109] The semiconductor device 60 shown in FIGS. 22 to 25 has basically the same configuration as the semiconductor device 60 shown in FIGS. 20 and 21, and can therefore achieve the same effects.

[0110] 22, the number of steps required to form the recess 61 can be reduced compared to the number of steps required to form the recess 61 shown in Fig. 20. Furthermore, the semiconductor device 60 shown in Fig. 24 can prevent the sinterable metal bonding material 30 from flowing out of the recess 61 and the second recess 64. Furthermore, in the semiconductor device 60 shown in Fig. 25, the second recess 64 acts in the same manner as the groove 11A of the semiconductor device 10, and therefore, compared to other semiconductor devices 60, the effect of suppressing deformation of the buffer material 8 can be more effectively exhibited.

[0111] Although the embodiments of the present disclosure have been described above, the above-described embodiments can be modified in various ways. Furthermore, the scope of the present disclosure is not limited to the above-described embodiments. The scope of the present disclosure is defined by the scope of the claims, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0112] 1 substrate, 1A first surface, 1A1 semiconductor element mounting area, 1B second surface, 2 semiconductor element, 3, 30 sinterable metal bonding material, 4 ceramic plate, 6 mask pattern, 6A through hole, 8 buffer material, 9 pressure head, 10, 20, 40, 50, 130 semiconductor device, 11 step portion, 11A groove, 11A1 first portion, 11A2 second portion, 11B protrusion, 12 first bottom surface, 13 first wall surface, 14 second bottom surface, 15 second wall surface, 16 first groove, 21, 22 punch, 51 first lead frame, 52 second lead frame, 53 sealing body, 54 conductive bonding material, 55 wire, 61 recess, 62 protrusion, 63 main body portion, 64 second recess.

Claims

1. a substrate including a first surface; at least one sinterable metal bonding material disposed on the first surface; at least one semiconductor element bonded to the first surface by the at least one sinterable metal bonding material; a plurality of step portions are formed on the first surface outside the at least one semiconductor element and inside an outer edge of the substrate in a plan view; the plurality of step portions extend along at least a part of an outline of the at least one semiconductor element; In the plan view, the at least one semiconductor element has one corner portion, and a first side portion and a second side portion that intersect with each other at the one corner portion, the plurality of step portions include a first step portion extending along the first side portion and a second step portion extending along the second side portion; The semiconductor device, wherein the first step portion and the second step portion are arranged with a gap between them.

2. A semiconductor device as described in Claim 1, wherein, in the planar view, the distance between the first step portion and the second step portion is positioned outside the one corner portion.

3. A semiconductor device as described in claim 1 or 2, wherein, in the planar view, each of the multiple step portions extends in a straight line.

4. each of the plurality of step portions is a groove recessed relative to the first surface, In a cross section perpendicular to the extension direction of the groove, the groove has a first portion in which the width of the groove in a direction along the first surface narrows as the width approaches the first surface, and a second portion connected to an end of the first portion located on the first surface side, 3. The semiconductor device according to claim 1, wherein a width of said second portion in a direction along said first surface is larger than a minimum width of said first portion in a direction along said first surface.

5. a lead frame bonded to the at least one semiconductor element; a sealing body covering the first surface, the at least one sinterable metal bonding material, the at least one semiconductor element, and the lead frame; The semiconductor device according to claim 4 , wherein a portion of said sealing body is disposed inside said groove.

6. the lead frame is bonded to the at least one semiconductor element with a conductive bonding material; The semiconductor device according to claim 5 , wherein a portion of said conductive bonding material is disposed inside said groove.

7. 3. The semiconductor device according to claim 1, wherein, in the planar view, an outer edge of the at least one sinterable metal bonding material is positioned outside an outer edge of the at least one semiconductor element, and each of the first step portion and the second step portion is positioned outside an outer edge of the at least one sinterable metal bonding material.

8. A substrate including a first surface; a plurality of sinterable metal bonding materials disposed on the first surface; a plurality of semiconductor elements bonded to the first surface by each of the plurality of sinterable metal bonding materials, At least one step portion is formed on the first surface inward from an outer edge of the substrate, the at least one step portion extends along at least a portion of an outline of each of the plurality of semiconductor elements; the plurality of semiconductor elements are arranged side by side at intervals in a first direction along the first surface, the at least one step portion includes a third step portion disposed between two semiconductor elements adjacent to each other in the first direction.

9. The at least one step portion is a plurality of step portions, In a plan view, each of the plurality of semiconductor elements has third side portions that are spaced apart from each other in the first direction and a fourth side portion that intersects with the third side portion, the plurality of step portions include a fourth step portion extending along the third side portion and a fifth step portion extending along the fourth side portion, The semiconductor device according to claim 8 , wherein the third step portion, the fourth step portion, and the fifth step portion are arranged at intervals from one another.

10. A semiconductor device as described in Claim 9, wherein, in the planar view, the outer edge of each of the plurality of sintered metal bonding materials is positioned outside the outer edge of each of the plurality of semiconductor elements, and each of the third step portion, the fourth step portion, and the fifth step portion is positioned outside the outer edge of each of the plurality of sintered metal bonding materials.

11. A semiconductor device as described in claim 9 or 10, wherein the plurality of step portions further have a step portion that is arranged outermost in the first direction among the plurality of semiconductor elements when viewed in the plane.

12. A substrate including a first surface; at least one sinterable metal bonding material disposed on the first surface; at least one semiconductor element bonded to the first surface by the at least one sinterable metal bonding material; the first surface has at least one stepped portion formed on the outer side of the at least one semiconductor element and on the inner side of an outer edge of the substrate in a plan view; the at least one step portion extends along at least a part of an outline of the at least one semiconductor element; a recess having a bottom surface defined by the first surface is formed in the substrate; an inner wall surface of the recessed portion extends along at least a part of an outline of the at least one semiconductor element; the at least one step portion includes the inner wall surface of the recessed portion, A semiconductor device, wherein the depth of the recess is less than the sum of the thickness of the at least one semiconductor element and the thickness of the at least one sinterable metallic bonding material.

13. 13. The semiconductor device according to claim 12, wherein, in the plan view, the inner wall surface of the recess is formed so as to surround an entire periphery of the at least one semiconductor element.

14. 13. The semiconductor device of claim 12, wherein, in the planar view, the inner wall surface of the recess is formed inside the outer edge of the substrate in a first direction along the first surface, and reaches the outer edge of the substrate in a second direction along the first surface and intersecting the first direction.

15. a second recess formed in the substrate and communicating with the recess; 15. The semiconductor device according to claim 12, wherein a bottom surface of said second recess is disposed at a distance from said first surface in a direction perpendicular to said first surface.

16. providing a substrate including a first surface having at least one semiconductor device mounting area; forming at least one step portion on the first surface of the substrate outside the at least one semiconductor element mounting region and inside an outer edge of the substrate in a plan view; providing a sinterable metal bonding material to the at least one semiconductor element mounting area; placing a semiconductor element on the sinterable metal bonding material; and a step of placing a buffer material on the semiconductor element and heating the substrate, the sinterable metal bonding material, and the semiconductor element while applying pressure with the buffer material. the at least one step portion has a wall surface extending along at least a part of an outline of the semiconductor element; In the heating step, the buffer material is brought into contact with the wall surface of the at least one step portion by the application of pressure.

17. the at least one step portion is a groove recessed relative to the first surface, 17. The method for manufacturing a semiconductor device according to claim 16, wherein in the heating step, the pressure is applied until the buffer material comes into contact with a bottom surface of the groove.

18. 18. The method for manufacturing a semiconductor device according to claim 17, wherein the depth of the groove from the first surface is equal to or less than a value obtained by subtracting the sum of the thickness of the semiconductor element and the sinterable metal bonding material from the thickness of the buffer material.

19. 19. The method for manufacturing a semiconductor device according to claim 17 or 18, wherein the step of forming the at least one step portion includes the steps of: forming a first groove having a first width in a direction along the first surface; and pressing the first groove with a punch having a second width wider than the first width.

20. a step of joining a lead frame to the semiconductor element with a conductive bonding material; 18. The method for manufacturing a semiconductor device according to claim 16, further comprising the step of forming a sealing body that covers the first surface, the at least one step portion, the sinterable metal bonding material, the semiconductor element, and the lead frame.

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