Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device and a method for manufacturing the same which is less prone to wire bonding defects.SOLUTION: An insulating layer OI includes an aperture OP1 that exposes the surface of a conductive layer CL1 and an aperture OP2 that exposes the surface of a conductive layer CL2 and has a smaller aperture area than the aperture OP1. The material of the surface of the conductive layer CL2 exposed through the aperture OP2 is a material different from that of the surface of the conductive layer CL1 exposed through the aperture OP1 and contains aluminum.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and can be suitably used, for example, in a semiconductor device having an electrode pad for detecting the potential of a source or emitter and a manufacturing method thereof. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2010-123686 (Patent Document 1) discloses a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a large-area source pad electrode and a small-area gate pad electrode. A metal film is formed on the surfaces of the gate pad electrode and the source pad electrode by plating or the like. This metal film is made of a laminated film of, for example, a nickel (Ni) layer and a gold (Au) layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-123686 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, when a metal film is simultaneously formed on a large-area source pad electrode and a small-area gate pad electrode by plating, nickel seeps onto the gold layer surface due to thermal history, the gold layer does not adhere to the palladium (Pd) layer (deposition failure), and zinc (Zn) deposits excessively, causing wire bonding failures on the small-area gate pad electrode.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] In a semiconductor device according to one embodiment, an insulating layer has a first opening exposing a surface of a first conductive layer and a second opening exposing a surface of a second conductive layer and having an opening area smaller than that of the first opening. The material of the surface of the second conductive layer exposed through the second opening is different from the material of the surface of the first conductive layer exposed through the first opening and contains aluminum.

[0007] A method for manufacturing a semiconductor device according to one embodiment includes the following steps.

[0008] A first layer made of a material containing aluminum is formed. A cover insulating layer exposing a first pad region of the first layer is formed. An insulating layer is formed having a first opening exposing the first pad region of the first layer and a second opening having an opening area smaller than the first opening and exposing the surface of the cover insulating layer. A plating layer is formed by electroless plating on the first pad region of the first layer exposed from the first opening. The cover insulating layer exposed from the second opening is removed to expose the second pad region of the first layer from the second opening. [Effects of the Invention]

[0009] According to the above embodiment, it is possible to realize a semiconductor device in which wire bonding defects are unlikely to occur and a method for manufacturing the same. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment. [Figure 2] 1 is a plan view showing the configuration of a semiconductor device according to an embodiment, with a sealing resin omitted; [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. [Figure 4] FIG. 4 is an enlarged cross-sectional view of a part of FIG. 3. [Figure 5] 1 is a cross-sectional view showing a first step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] 4 is a cross-sectional view showing a second step in the method for manufacturing a semiconductor device according to the embodiment. FIG. [Figure 7] 4 is a cross-sectional view showing a third step in the method for manufacturing a semiconductor device according to the embodiment. FIG. [Figure 8] FIG. 4 is a cross-sectional view showing a fourth step in the method for manufacturing a semiconductor device according to the embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing a fifth step of the method for manufacturing a semiconductor device according to the embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a sixth step in the method for manufacturing a semiconductor device according to the embodiment. [Figure 11] FIG. 10 is a diagram showing a configuration in which an etching tank is added to a plating apparatus. [Figure 12] FIG. 10 is a cross-sectional view showing a state in which nickel seeps out in a semiconductor device according to a comparative example. [Figure 13] FIG. 10 is a cross-sectional view showing a state in which a gold layer is not adhered in a semiconductor device according to a comparative example. [Figure 14] FIG. 10 is a cross-sectional view showing a state in which excessive deposition of zinc occurs in a semiconductor device according to a comparative example. [Figure 15] FIG. 1 is a cross-sectional view showing a configuration in which a power MOSFET is formed on a semiconductor substrate. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the specification and drawings, the same or corresponding components are designated by the same reference numerals, and redundant explanations will not be repeated. In addition, in the drawings, for the sake of convenience, configurations or manufacturing methods may be omitted or simplified.

[0012] In this specification, "planar view" refers to a viewpoint seen from a direction perpendicular to the first surface FS of the semiconductor substrate, "planar shape" refers to a shape in a planar view, and "opening area" refers to the area of ​​an opening in a planar view.

[0013] <Configuration of semiconductor device> First, the configuration of a semiconductor device according to an embodiment of the present disclosure will be described with reference to FIGS.

[0014] 1, the semiconductor device SD according to this embodiment is, for example, a semiconductor package in which a semiconductor chip SC is sealed with a sealing resin SRE. The semiconductor device SD according to this embodiment includes a chip mounting portion RB, a semiconductor chip SC, lead portions RD1 and RD2, clip conductors CC, bonding wires BW, and the sealing resin SRE.

[0015] The semiconductor chip SC is mounted on the chip mounting portion RB with solder SOL2 interposed therebetween. Each of the lead portions RD1 and RD2 is disposed at a distance from the chip mounting portion RB. The clip conductor CC electrically connects the emitter pad EP of the semiconductor chip SC to the lead portion RD1. The clip conductor CC is connected to the emitter pad EP of the semiconductor chip SC with solder SOL1 interposed therebetween. The clip conductor CC is connected to the lead portion RD1 with solder SOL3 interposed therebetween. The bonding wire BW electrically connects the Kelvin emitter pad KP of the semiconductor chip SC to the lead portion RD2.

[0016] The sealing resin SRE seals the chip mounting portion RB, the semiconductor chip SC, the lead portions RD1 and RD2, the clip conductor CC, and the bonding wires BW. Parts of the chip mounting portion RB and the lead portions RD1 and RD2 are exposed from the sealing resin SRE. The sealing resin SRE is made of, for example, a thermosetting resin material and may also contain a filler (for example, a filler made of silica particles).

[0017] 2, the semiconductor device SD according to this embodiment has an emitter pad EP, a Kelvin emitter pad KP, and a gate pad GP. Each of the emitter pad EP, the Kelvin emitter pad KP, and the gate pad GP has a rectangular planar shape. The planar occupation area of ​​the emitter pad EP is larger than the planar occupation area of ​​each of the Kelvin emitter pad KP and the gate pad GP.

[0018] The emitter pad EP is electrically connected to, for example, a clip conductor CC. The clip conductor CC is a plate-shaped conductor made of a metal with low electrical resistivity, such as copper (Cu) or silver (Ag).

[0019] By using the clip conductor CC, it is possible to pass a larger current than when a bonding wire is connected to the emitter pad EP. Meanwhile, a bonding wire BW is individually connected to each of the Kelvin emitter pad KP and the gate pad GP. Here, a case where the bonding wire BW is connected to both the Kelvin emitter pad KP and the gate pad GP will be described, but the clip conductor may be connected to either the Kelvin emitter pad KP or the gate pad GP.

[0020] As shown in FIG. 3, the semiconductor chip SC has a semiconductor substrate SB. The semiconductor substrate SB has a first surface FS and a second surface SS facing each other. An electric element having a vertical insulated gate field effect transistor portion is formed on the semiconductor substrate SB. This electric element is, for example, an IGBT. The vertical electric element means an electric element in which current flows between the first surface FS and the second surface SS of the semiconductor substrate SB. The electric element may be a power MOSFET, as will be described later.

[0021] An interlayer insulating layer IL is disposed on a first surface FS of the semiconductor substrate SB. A contact hole CH is provided in the interlayer insulating layer IL. The contact hole CH extends from the upper surface of the interlayer insulating layer IL to the first surface FS of the semiconductor substrate SB.

[0022] The semiconductor device SD further includes a conductive layer CL1, a conductive layer CL2, and a conductive layer CL3 (FIG. 2). Each of the conductive layers CL1, CL2, and CL3 is disposed on the first surface FS of the semiconductor substrate SB and on the interlayer insulating layer IL.

[0023] The conductive layer CL1 (first conductive layer) is directly connected to the emitter region (impurity region) of the IGBT through a contact hole CH in the interlayer insulating layer IL. The conductive layer CL1 has an emitter pad EP. A gate electrode GE of the IGBT is disposed directly below the conductive layer CL1.

[0024] The conductive layer CL2 (second conductive layer) is connected to the conductive layer CL1. The conductive layer CL2 has a Kelvin emitter pad KP. The gate electrode GE of the IGBT is not disposed in the region immediately below the conductive layer CL2. The gate electrode GE may be disposed in the region immediately below the conductive layer CL2, and the arrangement of the gate electrode is not limited.

[0025] 2 and 3, the conductive layer CL3 (second conductive layer) is disposed separately from the conductive layers CL1 and CL2. The conductive layer CL3 is electrically connected to the gate electrode GE of the IGBT through a contact hole (not shown) in the interlayer insulating layer IL. The conductive layer CL3 has a gate pad GP.

[0026] 3, the conductive layer CL1 has a barrier metal layer BM, a first layer FL, a second layer SL, and a third layer TL. The barrier metal layer BM is disposed in contact with the upper surface of the interlayer insulating layer IL and the wall surface of the contact hole CH. The barrier metal layer BM is made of, for example, titanium-tungsten (TiW). The barrier metal layer BM may be a single layer of titanium (Ti) or titanium nitride (TiN), or may be a laminated film of titanium and titanium nitride.

[0027] The first layer FL is disposed in contact with the upper surface of the barrier metal layer BM, and fills the contact hole CH. The first layer FL is made of a material containing, for example, aluminum (Al), such as pure aluminum, an alloy of aluminum and silicon (Si), an alloy of aluminum and copper, or an alloy of aluminum, silicon, and copper.

[0028] The second layer SL is disposed on the first layer FL. The second layer SL is made of a material containing a first metal. The first metal is a metal different from aluminum, such as nickel. The first metal may contain a small amount of phosphorus (P) in nickel.

[0029] Zinc may be present between the first layer FL and the second layer SL. The zinc is a remnant of the zinc coating formed when the first layer FL was subjected to a zincate treatment.

[0030] The third layer TL is disposed on the second layer SL. Specifically, the third layer TL is disposed in contact with the upper surface of the second layer SL. The third layer TL is made of a material containing a second metal. The second metal is a metal different from the first metal, such as gold.

[0031] The conductive layer CL2 has a barrier metal layer BM and a first layer FL. The barrier metal layer BM of the conductive layer CL2 is connected to the barrier metal layer BM of the conductive layer CL1 and is made of the same layer. The barrier metal layer BM of the conductive layer CL2 is disposed in contact with the upper surface of the interlayer insulating layer IL.

[0032] The first layer FL of the conductive layer CL2 is connected to the first layer FL of the conductive layer CL1 and is made of the same layer. The first layer FL of the conductive layer CL2 is disposed in contact with the upper surface of the barrier metal layer BM of the conductive layer CL2.

[0033] As shown in FIG. 2, the conductive layer CL3 has a barrier metal layer BM2 and a first layer FL2. The barrier metal layer BM2 is a layer formed by patterning the same layer as the barrier metal layers BM of the conductive layers CL1 and CL2 and separating them. The barrier metal layer BM2 is disposed in contact with the upper surface of the interlayer insulating layer IL and the inner wall surface of the contact hole. As a result, the barrier metal layer BM2 is directly connected to the gate electrode GE.

[0034] The first layer FL2 is a layer formed by separating it by patterning from the same layer as the first layer FL of the conductive layers CL1 and CL2. The first layer FL2 is disposed in contact with the upper surface of the barrier metal layer BM2.

[0035] The rest of the configuration of conductive layer CL3 is substantially the same as that of conductive layer CL2, and therefore description thereof will not be repeated.

[0036] 2 and 3, a cover insulating layer CL and an insulating layer OI (organic insulating layer) are disposed to cover each of the conductive layers CL1, CL2, and CL3. The insulating layer OI is made of a material containing an organic insulator. The organic insulator contained in the insulating layer OI is, for example, polyimide.

[0037] The cover insulating layer CL is disposed between the insulating layer OI and the semiconductor substrate SB and between the insulating layer OI and the first layer FL. The cover insulating layer CL is made of, for example, a silicon nitride film (Si3N4), a silicon oxynitride film (SiON), a silicon oxide film (SiO2), or the like.

[0038] Openings OP1, OP2, and OP3 are provided in the cover insulating layer CL and the insulating layer OI. Each of the openings OP1, OP2, and OP3 penetrates both the cover insulating layer CL and the insulating layer OI and reaches the surfaces of the first layers FL and FL2.

[0039] The second layer SL and the third layer TL are disposed within the opening OP1 (first opening). The opening OP1 exposes the surface of the conductive layer CL1. The surface of the conductive layer CL1 exposed from the opening OP1 is the upper surface of the third layer TL. Therefore, the material of the surface of the conductive layer CL1 exposed from the opening OP1 is, for example, gold. The upper surface of the third layer TL1, exposed from the insulating layer OI, forms an emitter pad EP.

[0040] The opening OP2 (second opening) exposes the surface of the conductive layer CL2. The opening OP2 has a smaller opening area than the opening OP1. The surface of the conductive layer CL2 exposed from the opening OP2 is the upper surface of the first layer FL. Therefore, the material of the surface of the conductive layer CL2 exposed from the opening OP2 is a material containing aluminum, which is different from the material of the surface of the conductive layer CL1 exposed from the opening OP1. The upper surface of the first layer FL of the conductive layer CL2 is exposed from the insulating layer OI, thereby forming a Kelvin emitter pad KP.

[0041] As shown in FIG. 2, the opening OP3 (second opening) exposes the surface of the conductive layer CL3. The opening OP3 has a smaller opening area than the opening OP1. The surface of the conductive layer CL3 exposed from the opening OP3 is the upper surface of the first layer FL2. Therefore, the material of the surface of the conductive layer CL3 exposed from the opening OP3 is a material containing aluminum, which is different from the material of the surface of the conductive layer CL1 exposed from the opening OP1. The upper surface of the first layer FL2 of the conductive layer CL3 is exposed from the insulating layer OI to form a gate pad GP.

[0042] 3, solder SOL1 is disposed on the surface of the conductive layer CL1 exposed from the opening OP1. The solder SOL1 is in contact with the upper surface of the conductive layer CL1. In other words, the solder SOL1 is in contact with the upper surface of the third layer TL1 that constitutes the emitter pad EP.

[0043] A clip conductor CC is disposed on the emitter pad EP. The clip conductor CC is electrically connected to the emitter pad EP via solder SOL1. That is, the clip conductor CC is connected to the upper surface of the third layer TL in the conductive layer CL1 via solder SOL1. In addition to solder SOL1, a bonding method using silver sintering or silver paste may also be used to connect the clip conductor CC to the emitter pad EP.

[0044] A bonding wire BW is directly connected to the surface of the conductive layer CL2 exposed from the opening OP2, that is, the bonding wire BW is directly connected to the upper surface of the first layer FL that constitutes the Kelvin emitter pad KP.

[0045] 2, a bonding wire BW is directly connected to the surface of the conductive layer CL3 exposed from the opening OP3. That is, the bonding wire BW is directly connected to the top surface of the first layer FL2 that constitutes the gate pad GP.

[0046] 3, a collector electrode CE is disposed on the second surface SS of the semiconductor substrate SB. The collector electrode CE is electrically connected to the collector region of the IGBT.

[0047] As shown in Fig. 4, the electric element formed on the semiconductor substrate SB is, for example, an IGBT. + Collector region CR and n + Region HR and n - A drift region DRI, a p-type base region BR, and a p + Contact area CON and n + It mainly has an emitter region ER and a gate electrode GE.

[0048] p + The collector region CR is disposed on the second surface SS of the semiconductor substrate SB. + On the collector region CR (p + On the first surface FS side relative to the collector region CR + Area HR is located. n + The area HR is p + It forms a pn junction with the collector region CR.

[0049] n + On area HR(n + n on the first surface FS side relative to the area HR - The drift region DRI is located. - The drift region DRI is n + It borders the region HR. -The drift region DRI is n + The n-type impurity concentration is lower than that of the region HR.

[0050] n - On the drift region DRI (n - A p-type base region BR is disposed on the first surface FS side with respect to the drift region DRI. - It forms a pn junction with the drift region DRI.

[0051] On the p-type base region BR (on the first surface FS side relative to the p-type base region BR), + Contact areas CON and n + The emitter region ER (first region) is arranged. + The contact region CON is in contact with the p-type base region BR. + The contact region CON has a p-type impurity concentration higher than the p-type impurity concentration of the p-type base region BR. + The emitter region ER is p + A pn junction is formed with each of the contact region CON and the p-type base region BR.

[0052] The semiconductor substrate SB is provided with a trench TR. The trench TR extends from the first surface FS to the n + The emitter region ER and the p-type base region BR are penetrated by n - The trench TR reaches the drift region DRI. A gate insulating layer GI is arranged along the inner wall of the trench TR. The inside of the trench TR is filled with a gate electrode GE. The gate electrode GE faces the p-type base region BR with the gate insulating layer GI interposed therebetween. This forms an IGBT having an insulated gate field effect transistor portion.

[0053] The conductive layer CL1 is connected to the n-type contact hole CH of the interlayer insulating layer IL. + The conductive layer CL1 is electrically connected to the emitter region ER to form an emitter electrode. +It is also electrically connected to the contact region CON.

[0054] A collector electrode CE is disposed on the second surface SS of the semiconductor substrate SB. + By contacting the collector region CR, + It is electrically connected to the collector region CR.

[0055] The semiconductor device SD according to the above embodiment may have a Kelvin collector pad (not shown) for detecting the potential of the collector. The Kelvin collector pad is a pad shown in FIG. + The Kelvin collector pad is electrically connected to the collector region CR. The Kelvin collector pad is arranged on the same side of the semiconductor substrate SB as the emitter pad EP, Kelvin emitter pad KP, etc. (i.e., on the first surface FS side). The Kelvin collector pad has an opening area smaller than that of the emitter pad EP. The conductive layer constituting the Kelvin collector pad has the same configuration as the conductive layer CL2 shown in FIG. 3. Specifically, the conductive layer constituting the Kelvin collector pad is formed separately from the same layer as the barrier metal layer BM and first layer FL of the conductive layer CL2 shown in FIG. 3. A bonding wire is connected to the Kelvin collector pad. The bonding wire is directly connected to the first layer of the Kelvin collector pad, which is made of a material containing aluminum. The configuration of the Kelvin collector pad is otherwise substantially the same as that of the Kelvin emitter pad, and therefore will not be described again.

[0056] <Method of manufacturing a semiconductor device> Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 5 to 10 and 3. FIG.

[0057] 5, a semiconductor substrate SB is first prepared, and an electric element (not shown) having a gate electrode GE such as an IGBT is formed on the semiconductor substrate SB. The gate electrode GE is made of, for example, polycrystalline silicon doped with impurities.

[0058] An interlayer insulating layer IL made of, for example, a silicon oxide film is formed so as to cover the first surface FS of the semiconductor substrate SB. A contact hole CH is formed in the interlayer insulating layer IL by photolithography and etching. The contact hole CH extends from the upper surface of the interlayer insulating layer IL to n + Emitter region ER and p + Each of the contact areas CON is reached.

[0059] On the interlayer insulating layer IL, a barrier metal layer made of, for example, titanium-tungsten and a first layer made of, for example, a material containing aluminum are laminated in this order. The barrier metal layer is connected to the n-type semiconductor layer through the contact hole CH. + Emitter region ER and p + The first layer is formed so as to be in direct contact with each of the contact regions CON. The first layer is formed so as to be in contact with the upper surface of the barrier metal layer. The first layer is made of, for example, pure aluminum, an alloy of aluminum and silicon (Si), an alloy of aluminum and copper, or an alloy of aluminum, silicon, and copper.

[0060] The first layer and the barrier metal layer are patterned using photolithography and etching techniques. This separates the barrier metal layer into barrier metal layers BM and BM2 (Fig. 2). The first layer is also separated into first layers FL and FL2 (Fig. 2). A stacked structure of the barrier metal layer BM and the first layer FL, and a stacked structure of the barrier metal layer BM2 and the first layer FL2 are also formed.

[0061] Thereafter, a cover insulating layer CL is formed over the entire first surface FS of the semiconductor substrate SB. The cover insulating layer CL is formed so as to cover the laminated structure of the barrier metal layer BM and the first layer FL and the laminated structure of the barrier metal layer BM2 and the first layer FL2. The cover insulating layer CL is formed of, for example, a silicon nitride film, a silicon oxynitride film, a silicon oxide film, or the like.

[0062] As shown in Figure 6, the cover insulating layer CL is patterned by photolithography and etching. As a result, an opening OPa is formed in the cover insulating layer CL. A part of the surface of the first layer FL (the emitter pad region (first pad region)) is exposed from the opening OPa. As a result, the cover insulating layer CL that exposes the emitter pad region of the first layer FL is formed.

[0063] 7, an insulating layer OI is then applied to the entire first surface FS of the semiconductor substrate SB. The insulating layer OI is formed so as to cover the laminated structure of the barrier metal layer BM and the first layer FL and the laminated structure of the barrier metal layer BM2 and the first layer FL2. The insulating layer OI is also formed so as to cover the surface of the first layer FL exposed from the opening OPa. The insulating layer OI is, for example, an organic photosensitive film, such as polyimide.

[0064] As shown in Figure 8, the insulating layer OI is patterned by photolithography (exposure and development). As a result, openings OPc and OPd are formed in the insulating layer OI. The opening OPc is formed so as to communicate with the opening OPa in the cover insulating layer CL. The openings OPa and OPc form an opening OP1 that defines the emitter pad EP. A portion of the surface of the first layer FL is exposed from the opening OP1.

[0065] The opening OPd is formed to expose the surface of the cover insulating layer CL, thereby forming an insulating layer OI having an opening OP1 that exposes the emitter pad region of the first layer FL and an opening OPd that has a smaller opening area than the opening OP1 and exposes the surface of the cover insulating layer CL.

[0066] 9, a plating layer is formed in the emitter pad region of the first layer FL exposed from the opening OP1 using electroless plating. The process of forming the plating layer includes a process of forming a second layer SL made of a material containing nickel on the first layer FL, and a process of forming a third layer TL made of a material containing gold on the second layer SL. The process of forming the second layer SL and the third layer TL by plating will be specifically described below.

[0067] First, the surface of the first layer FL is cleaned by degreasing. After this, the oxide layer on the surface is removed by etching, followed by acid cleaning and then a first zincate treatment. Next, the zinc formed in the first zincate treatment is removed by acid cleaning. Next, a second zincate treatment is performed on the first layer FL. In the second zincate treatment, a zincate solution is brought into contact with the surface, and a zinc coating is formed on the surface through a substitution reaction between aluminum and zinc. The zincate treatment is performed to facilitate plating on the aluminum surface. After the zinc coating is formed on the first layer FL, electroless plating, such as nickel plating and gold plating, is performed. Pure water rinsing is performed between each treatment. When hypophosphorous acid is used as a reducing agent in the electroless nickel plating solution, a small amount of phosphorus (P) is contained in the nickel film.

[0068] The nickel plating and gold plating are used to form a second layer SL made of nickel and a third layer TL made of gold (Ni / Au) on the first layer FL1. The upper surface of the third layer TL thus forms the emitter pad EP. The third layer TL is formed so as to be in contact with the second layer SL.

[0069] The nickel plating leaves almost no zinc coating on the surface of each of the first layers FL and FL2. However, a small amount of zinc may remain on the surface of each of the first layers FL and FL2. Palladium plating may also be performed on the nickel plating to make the third layer TL palladium (Ni / Pd). Palladium plating may also be performed between the nickel plating and the gold plating (Ni / Pd / Au). The plating performed between the nickel plating and the gold plating is not limited to palladium plating, and any plating of a metal that is nobler than the solder, bonding wire, etc. may be used.

[0070] 10, the cover insulating layer CL exposed from the opening OPd of the insulating layer OI is removed by wet etching using, for example, hydrofluoric acid. By this wet etching, the cover insulating layer CL exposed from the opening OPd is removed, and the surface of the Kelvin emitter pad region (second pad region) in the first layer FL is exposed.

[0071] Instead of wet etching, the cover insulating layer CL exposed from the opening OPd may be removed by dry etching using a resist mask, thereby exposing the surface of the Kelvin emitter pad region in the first layer FL.

[0072] By removing the cover insulating layer CL exposed from the opening OPd, an opening OPb communicating with the opening OPd is formed in the cover insulating layer CL. The openings OPb and OPd form an opening OP2 that defines the Kelvin emitter pad KP. The Kelvin emitter pad region of the first layer FL is exposed from the opening OP2.

[0073] The opening OP3 and conductive layer CL1 that define the gate pad GP shown in FIG. 2 are formed in the same manner as the opening OP2 and conductive layer CL2 that define the Kelvin emitter pad KP described above.

[0074] 3, after the second surface SS of the semiconductor substrate SB is polished to a predetermined thickness, a collector electrode CE is formed on the second surface SS. The collector electrode CE is formed by stacking, from the semiconductor substrate SB side, an aluminum-silicon (Si) alloy layer, a titanium layer, a nickel layer, and a gold layer. After this, the semiconductor wafer is diced and divided into a plurality of semiconductor chips SC.

[0075] In the state of the semiconductor chip SC, the clip conductor CC is connected to the plating layer (third layer TL) exposed in the emitter pad region via the solder SOL1. That is, the clip conductor CC is connected to the emitter pad EP via the solder SOL1.

[0076] In addition, in the state of the semiconductor chip, bonding wires BW are directly connected to the first layers FL and FL2 exposed in the Kelvin emitter pad region and the gate pad region, respectively. That is, the bonding wires BW are directly connected to the Kelvin emitter pad KP and the gate pad GP, respectively.

[0077] In this manner, the semiconductor device SD of this embodiment is manufactured.

[0078] The wet etching performed in Fig. 10 is performed by a conventional wet etching apparatus as a separate process from the plating performed in Fig. 9. The wet etching performed in Fig. 10 may also be performed consecutively after the plating performed in Fig. 9 is completed. In this case, the plating apparatus performing the plating performed in Fig. 9 additionally has an etching tank for the wet etching performed in Fig. 10. Hereinafter, a plating apparatus having this etching tank will be described with reference to Fig. 11.

[0079] 11, the plating apparatus PA includes, in order from the loading section L1 to the unloading section L2, a cleaner tank P1, an etching tank P3, an acid treatment tank P5, a zincate tank P7, an electroless nickel tank P9, an electroless palladium tank P11, electroless gold tanks P13 and P15, an insulating film etching tank P17, and a drying section P19. The plating apparatus PA also includes multiple water rinsing tanks P2, P4, P6, P8, P10, P12, P14, P16, and P18.

[0080] As described above, the plating equipment PA has an insulating film etching tank P17. The insulating film etching tank P17 is located closer to the unloading section L2 than the electroless gold tank P15 and the rinsing tank P16. This allows wet etching to be performed continuously after plating is completed in the plating equipment PA.

[0081] <Effects> Next, the effects of this embodiment will be described in comparison with a comparative example shown in FIGS.

[0082] As shown in FIGS. 12 to 14, in the comparative example, a metal film is formed by plating on both the large-area emitter pad EP and the small-area Kelvin emitter pad KP.

[0083] 12, the conductive layer CL1 has a barrier metal layer BM and a first layer FL, and further has a second layer SL1 and a third layer TL1 formed on the first layer FL by plating. Similarly to the conductive layer CL1, the conductive layer CL2 also has a barrier metal layer BM and a first layer FL, and further has a second layer SL2 and a third layer TL2 formed on the first layer FL by plating.

[0084] Each of the second layers SL1 and SL2 is made of a material containing, for example, nickel, and each of the third layers TL1 and TL2 is made of a material containing, for example, gold.

[0085] In this comparative example, nickel seeps out onto the surfaces of the third layers TL1 and TL2 due to thermal history in both the large-area emitter pad EP and the small-area Kelvin emitter pad KP, as shown in Fig. 12. The nickel seeps out because the nickel in the second layers SL1 and SL2 passes through the gold grain boundaries in the third layers TL1 and TL2 and reaches the upper surfaces of the third layers TL1 and TL2.

[0086] When connecting a large-area emitter pad EP with solder, the impact of Ni seepage is small due to the advantages of the combination of large area and solder connection. On the other hand, when connecting a small-area Kelvin emitter pad KP with bonding wire, the impact of nickel seepage is large.

[0087] Therefore, if nickel seeps out from the connection portion of the small-area Kelvin emitter pad KP to which the bonding wire BW is connected, the bonding wire BW is likely to peel off.

[0088] To suppress the nickel seepage, it is possible to place intermediate layers ML1 and ML2 between the second layers SL1 and SL2 and the third layers TL1 and TL2, as shown in Figures 13 and 14. The intermediate layers ML1 and ML2 are made of a material containing palladium, for example. A layer containing a noble metal such as palladium functions as a barrier film for nickel. Therefore, the placement of the intermediate layers ML1 and ML2 makes it possible to suppress the nickel seepage.

[0089] However, even if the intermediate layers ML1 and ML2 are provided, the problem of unbonded portions of the third layer TL2 occurs in the small-area Kelvin emitter pad KP, as shown in Fig. 13. This problem will be explained below.

[0090] As shown in Figure 13, electrons (Ni → Ni) generated in the small-area Kelvin emitter pad KP + +e - ) may escape into the emitter region ER (Figure 4). In this case, gold is not sufficiently deposited on the small-area Kelvin emitter pad KP, resulting in areas where the third layer TL2 is not formed. In this small-area Kelvin emitter pad KP, the difference in area between the emitter pad EP and the Kelvin emitter pad KP results in areas where the third layer TL2 is not sufficiently formed. This causes poor connection of the bonding wire BW to the Kelvin emitter pad KP, making the bonding wire BW more likely to peel off.

[0091] In particular, in a configuration in which the intermediate layer ML2 is disposed between the second layer SL2 and the third layer TL2, electrons emitted from the second layer SL2 are received by Au ions through the intermediate layer ML2, which results in a significant lack of adhesion of the third layer TL2 compared to a laminated structure of nickel and gold layers in which Au ions receive electrons on the surface of the second layer SL2.

[0092] Furthermore, even if the intermediate layers ML1 and ML2 are provided, the small-area Kelvin emitter pad KP still suffers from the problem of excessive deposition of zinc on the first layer FL, as shown in Fig. 14. This problem will be explained below.

[0093] 14, the emitter pad EP and the Kelvin emitter pad KP share the first layer FL made of aluminum. A large area of ​​the first layer FL is exposed from the insulating layer OI in the region that will become the emitter pad EP, and a small area of ​​the first layer FL is exposed from the insulating layer OI in the region that will become the Kelvin emitter pad.

[0094] During zincate treatment of the first layer FL made of aluminum, Al in the first layer FL is converted into Al → Al 3+ +3e - In addition, the Zn in the chemical solution 2+ is the electron density in the first layer FL (e - ) and Zn 2+ +2e - →Zn reacts. This forms a zinc coating on the first layer FL. The reaction stops when the entire aluminum surface is replaced with zinc.

[0095] In addition, in zincate treatment, Zn in the chemical solution 2+ are not sufficiently supplied to the first layer FL of the emitter pad EP region, which is exposed over a large area, but are sufficiently supplied to the first layer FL of the Kelvin emitter pad KP region, which is exposed over a small area. Therefore, the excess electrons (e - ) moves in the first layer FL from the emitter pad EP region side, which is exposed over a large area, to the Kelvin emitter pad KP region side, which is exposed over a small area.

[0096] As a result, zinc is excessively deposited on the first layer FL in the small exposed area of ​​the Kelvin emitter pad KP, and a thick zinc film ZN grows. In the Kelvin emitter pad KP area, this thick zinc film ZN reduces the adhesion between the first layer FL and the second layer SL2, making it more likely that peeling will occur at the location where the bonding wire BW is connected.

[0097] In contrast, in this embodiment, as shown in Figures 2 and 3, in small-area pads such as the Kelvin emitter pad KP and the gate pad GP, the bonding wire BW is directly connected to the first layer FL, which is made of a material containing aluminum. Because there is no nickel or gold plating layer at the location where the bonding wire BW is connected, problems such as nickel seepage (Figure 12), non-adhesion of the third layer TL2 (Figure 13), and excessive zinc deposition (Figure 14) do not occur. Furthermore, the bonding wire BW has good adhesion to the material containing aluminum. This makes it difficult for the bonding wire BW to peel off from the small-area pad.

[0098] 3, in this embodiment, the large-area emitter pad EP is connected to a plate-shaped clip conductor CC via solder SOL1, which allows a larger current to flow than with a linear bonding wire.

[0099] 3, the conductive layer CL1 has a first layer FL made of a material containing aluminum, a second layer SL made of a material containing nickel, and a third layer TL made of a material containing gold, which makes it easy to connect the clip conductor CC to the conductive layer CL1 via the solder SOL1.

[0100] Furthermore, according to this embodiment, the third layer TL is in contact with the second layer SL, as shown in Fig. 3. In this way, an extra layer is not required between the second layer SL and the third layer TL, and therefore the conductive layer CL1 can be configured with a simple structure.

[0101] Furthermore, the solder SOL1 wets nickel, so the clip conductor CC can be connected to the conductive layer CL1 with good adhesion through the solder SOL1 without the need for a layer such as palladium between the second layer SL and the third layer TL.

[0102] Furthermore, according to this embodiment, the conductive layer CL1 is connected to the emitter region ER as shown in Fig. 3. This allows a large current to flow through the clip conductor CC.

[0103] 3, the conductive layer CL2 is connected to either the emitter region or the gate electrode GE, which allows the potential of the emitter to be detected through the Kelvin emitter pad KP, and also allows the potential of the gate electrode GE to be controlled.

[0104] According to this embodiment, as shown in Fig. 9, after plating layers (second layer SL, third layer TL) are formed by electroless plating on the first layer FL exposed from the opening OP1, the cover insulating layer CL exposed from the opening OPd is removed as shown in Fig. 10. This makes it possible to selectively remove the cover insulating layer CL exposed from the opening OPd without separately forming a dedicated mask. Therefore, the semiconductor device of this embodiment can be manufactured with a small number of steps.

[0105] (others) In the above embodiment, a vertical IGBT has been described as an electric element formed on the semiconductor substrate SB. However, the electric element to which the present disclosure is applied is not limited to a vertical IGBT, and may be a vertical power MOSFET as shown in FIG.

[0106] As shown in Figure 15, a vertical power MOSFET has + Drain region DR and n - A drift region DRI, a p-type base region BR, and a p + Contact area CON and n + It has a source region SR and a gate electrode GE.

[0107] n + The drain region DR is disposed on the second surface SS of the semiconductor substrate SB. + The n - The drift region DRI is located.- The drift region DRI is n + The n-type impurity concentration is lower than that of the drain region DR. - The drift region DRI and the pn junction are formed by - On the drift region DRI (n - A p-type base region BR is arranged on the first surface FS side with respect to the drift region DRI.

[0108] On the p-type base region BR (on the first surface FS side with respect to the p-type base region BR) so as to be in contact with the p-type base region BR + Contact areas CON and n + The source region SR is located. + The contact region CON has a p-type impurity concentration higher than the p-type impurity concentration of the p-type base region BR. + The source region SR is p + A pn junction is formed with each of the contact region CON and the p-type base region BR.

[0109] The semiconductor substrate SB has a first surface FS to a second surface FS. + The n-type semiconductor layer is formed through each of the source region SR and the p-type base region BR. - A trench TR is provided that reaches the drift region DRI. A gate insulating layer GI is disposed along the wall surface of the trench TR. The inside of the trench TR is filled with a gate electrode GE. The gate electrode GE faces the p-type base region BR with the gate insulating layer GI interposed therebetween. This provides the power MOSFET with an insulated gate field effect transistor portion.

[0110] The conductive layer CL1 is connected to the n-type contact hole CH of the interlayer insulating layer IL. + The conductive layer CL1 forms a source electrode by contacting with the source region SR. The conductive layer CL1 has a source pad SP exposed from the insulating layer OI. In this embodiment, the Kelvin emitter pad KP in the first and second embodiments becomes a Kelvin source pad, and n + The conductive layer s disposed on the second surface SS of the semiconductor substrate SB is used to measure the potential of the source region SR.+ A drain electrode DE is formed by contacting the drain region DR.

[0111] With such a MOSFET, the same effects as those of the above embodiment can be obtained.

[0112] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0113] BM barrier metal layer, BR p-type base region, BW bonding wire, CE collector electrode, CH, CH1 contact hole, CL cover insulating layer, CL1, CL2, CL3, s conductive layer, CON p + Contact area, CR p + Collector region, DE Drain electrode, DR n + Drain region, DRI n - Drift region, EP Emitter pad, ER n + Emitter region, FL, FL1, FL2 first layer, FS first surface, GE gate electrode, GI gate insulating layer, GP gate pad, HR n + area, IL interlayer insulating layer, KP Kelvin emitter pad, L1 load part, L2 unload part, ML1,ML2 Pd layer, OI insulating layer, OP1,OP2,OP3,OPa,OPb,OPc,OPd opening, P1 cleaner bath, P2,P4,P6,P8,P10,P12,P14,P16,P18 water rinsing bath, P3 etching bath, P5 acid treatment bath, P7 zincate bath, P9 electroless Ni bath, P11 electroless Pd bath, P13,P15 electroless Au bath, P17 insulating film etching bath, P19 drying part, RB chip mounting part, RD1,RD2 lead part, SB semiconductor substrate, SC semiconductor chip, SD semiconductor device, SL,SL1,SL2 second layer, SOL1,SOL2,SOL3 solder, SP source pad, SR n +Source region, SRE encapsulation resin, SS second surface, TL, TL1, TL2 third layer, TR trench, ZN zinc coating.

Claims

1. A first layer made of a material containing aluminum; an insulating layer having a first opening and a second opening having an opening area smaller than that of the first opening; a second layer disposed in the first opening and on the first layer, the second layer being made of a material containing nickel; a third layer disposed in the first opening and on the second layer, the third layer being made of a material including gold; a solder connected to a surface of the third layer exposed from the first opening; a plate-shaped clip conductor electrically connected to the third layer via the solder; a bonding wire directly connected to the surface of the first layer exposed through the second opening; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein said third layer is in contact with said second layer.

3. a semiconductor substrate; a first region of either an emitter region or a source region disposed in the semiconductor substrate; Equipped with 2. The semiconductor device according to claim 1, wherein a first conductive layer having said first layer, said second layer, and said third layer is electrically connected to said first region.

4. a gate electrode; a second region of either a collector region or a drain region disposed in the semiconductor substrate; 4. The semiconductor device according to claim 3, wherein the second conductive layer having said first layer is electrically connected to any one of said first region, said gate electrode and said second region.

5. 2. The semiconductor device according to claim 1, wherein said insulating layer is an organic insulating layer.

6. forming a first layer made of a material including aluminum; forming a cover insulating layer exposing a first pad region of the first layer; forming an insulating layer having a first opening exposing the first pad region of the first layer and a second opening having an opening area smaller than that of the first opening exposing a surface of the cover insulating layer; forming a plating layer by electroless plating on the first pad region of the first layer exposed from the first opening; removing the cover insulating layer exposed from the second opening to expose a second pad region of the first layer from the second opening; connecting a clip conductor to the plating layer exposed in the first pad region via solder; directly connecting a bonding wire to the first layer exposed in the second pad region; Equipped with a step of forming a plating layer comprising: a step of forming a second layer made of a material containing nickel on the first layer; and a step of forming a third layer made of a material containing gold on the second layer.

7. 7. The method for manufacturing a semiconductor device according to claim 6, wherein said third layer is formed so as to be in contact with said second layer.

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