Wafer for uniform graphene CVD growth and its manufacturing method

Abstract

Wafer for CVD growth of uniform graphene and method for its manufacture. A wafer for CVD growth of uniform graphene at temperatures above 700° C. is provided, the wafer comprising, in order, a planar silicon substrate, an insulating layer disposed over the silicon substrate, and a barrier layer disposed over the insulating layer, the insulating layer being a silicon nitride and / or aluminum nitride layer, the barrier layer having a consistent thickness of 50 nm or less, and providing a growth surface for the CVD growth of uniform graphene.

Description

[Technical Field]

[0001] The present invention provides a wafer for CVD growth of graphene. More specifically, the present invention provides a wafer suitable for growing uniform graphene at temperatures above 700°C. The present invention also relates to a stack comprising at least a portion of the wafer and a graphene layer formed thereon, in particular formed by CVD at temperatures above 700°C. The present invention further provides methods for producing the wafer and the stack. [Background technology]

[0002] Two-dimensional materials, of which graphene is one of the most prominent, are currently the subject of intense research. Graphene, in particular, has been shown to exhibit extraordinary properties, both theoretically and, more recently, practically. Graphene's electronic properties are particularly remarkable and have enabled the fabrication of electronic devices that are orders of magnitude better than non-graphene-based devices. However, there remains a need in the art for wafers, also known as substrates, that facilitate the production of high-quality, uniform graphene. In particular, there remains a need in the microelectronics industry for wafers that are suitable for use in established semiconductor fabrication plants and that may be used directly to grow graphene and subsequently to fabricate graphene-based electronic devices on an industrial scale.

[0003] A semiconductor manufacturing plant (also known as a "fab") is a factory where devices such as integrated circuits are manufactured. The cost of building and equipping a fab typically runs into the billions of dollars. In 2020, it was reported that one fab cost over $17 billion. Each fab is equipped for a specific manufacturing method, leaving little room for the introduction of new technologies or methods. Typically, during the historical development of silicon-based devices, new fabs have been built with each technological development to enable the use of such new technologies. Thus, globally, fabs are primarily built to manufacture electronic devices from silicon wafers.

[0004] It is known in the art that graphene can be synthesized, manufactured, or formed directly on non-metallic surfaces of substrates. These include silicon and sapphire, along with other more exotic surfaces such as III-V semiconductors. The inventors have discovered that the most effective method for producing high-quality graphene, particularly directly on such non-metallic surfaces, is the method disclosed in WO 2017 / 029470. The method of WO 2017 / 029470 is ideally carried out using an MOCVD reactor. MOCVD stands for metal-organic chemical vapor deposition, due to its origins in the production of semiconductor materials such as AlN and GaN from metal-organic precursors such as AlMe3 (TMAl) and GaMe3 (TMGa), although such equipment and reactors are well known and understood by those skilled in the art to be suitable for use with non-metal-organic precursors. MOCVD may also be used synonymously with metal-organic vapor phase epitaxy (MOVPE).

[0005] While there is a need to use silicon wafers to meet the stringent requirements of existing semiconductor foundries, there is also a need to grow graphene, which is an excellent conductor, directly on an insulating surface for many electronic devices. It is known in the art that silicon wafers may be provided with an insulating surface, for example, silicon with a silicon oxide or silicon nitride surface (i.e., Si / SiO2 or Si / SiN x wafers are well known).

[0006] US Patent Application Publication No. 2005 / 142715 discloses a semiconductor device including a silicon substrate, a silicon oxide layer formed on a surface of the silicon substrate, and a first oxide layer formed on the silicon oxide layer, the first oxide layer having a higher dielectric constant than silicon oxide. The disclosure does not mention graphene growth.

[0007] US Patent Application Publication No. 2011 / 175060 discloses a substrate having a graphene film grown thereon, the substrate comprising a base substrate, a patterned aluminum oxide film, and a graphene film preferentially grown on the patterned aluminum oxide film, wherein the base substrate may be a single crystal silicon substrate having a silicon oxide film formed thereon.

[0008] US Patent Application Publication No. 2001 / 029092 is silent about graphene growth and relates to a method for forming a gate structure, which includes thermally growing a thin silicon dioxide layer on top of a semiconductor device by using wet H2 / O2 or dry O2, and then forming an aluminum oxide layer on top of the semiconductor device while doping it in situ with a dopant. Summary of the Invention [Means for solving the problem]

[0009] The present inventors have sought to bridge the gap between the need for silicon-based wafers and insulating surfaces for graphene growth in order to facilitate the adoption of graphene in industrial electronic device manufacturing, and particularly in industrial fabs, and have consequently developed both improved wafers and methods for manufacturing such wafers. The present invention therefore overcomes, or at least substantially alleviates, various problems associated with the prior art, or at least provides an industrially useful alternative.

[0010] Thus, in a first aspect, there is provided a wafer for CVD growth of uniform graphene at temperatures above 700°C, comprising: a planar silicon substrate; an insulating layer disposed over a silicon substrate; a barrier layer disposed over the insulating layer; the insulating layer is a silicon nitride and / or aluminum nitride layer; A wafer is provided in which the barrier layer has a uniform thickness of 50 nm or less and provides a growth surface for uniform graphene CVD growth.

[0011] The present disclosure will now be further described. In the following sections, different aspects / embodiments of the present disclosure are defined in more detail. Each aspect / embodiment thus defined may be combined with any other aspect / embodiment or aspects / embodiments, unless expressly indicated to the contrary. In particular, any feature indicated as being preferred or advantageous may be combined with any other feature or features indicated as being preferred or advantageous.

[0012] The present invention relates to wafers. Wafer is a standard term in the art and is equivalent to substrate. In this context, a wafer comprises multiple distinct layers (i.e., a silicon layer, an insulating layer, and a barrier layer). Wafers are used for the fabrication and manufacturing of electronic devices. Specifically, the wafers of the present invention are silicon-based, making them suitable for use in existing fabs. In other words, the wafers of the present invention comprise a silicon substrate. The silicon substrate is of substantially constant thickness and is planar, consisting of a single layer of elemental silicon. However, silicon may be doped with small amounts of other elements, such as boron, nitrogen, and phosphorus, as is well known in the art. If doped, the semiconductor substrate may be either p-type doped or n-type doped. Preferably, the doped semiconductor substrate is 10 15 cm -3 Greater than, preferably 10 16 cm -3 Greater than and / or 1020 cm -3 Less than 10 19 cm -3 The most preferred range is 10 16 cm -3 ~10 18 cm -3 The silicon substrate may also include a CMOS substrate, which is a silicon-based substrate that includes various additional layers or circuits embedded therein.

[0013] The wafers are suitable for uniform graphene growth by CVD at temperatures above 700° C. Typically, graphene is grown at temperatures above 700° C. when using CVD to achieve high quality and uniformity, and therefore wafers suitable for such subsequent processing are required.

[0014] The inventors have found that when using known fab-suitable hybrid wafers, such as Si / SiO2, the conditions used to grow graphene on insulating surfaces, particularly high temperatures above 700°C, result in damage to the insulating layer, thereby reducing its function as an insulator. This effect is, of course, more pronounced at the preferred higher growth temperatures, and therefore the wafers of the present invention are suitable for use at higher temperatures, preferably above 800°C, above 900°C, and even more preferably above 1000°C, e.g., above 1100°C.

[0015] The wafers of the present invention, as described herein, address this issue through the presence of both an insulating layer and a barrier layer. Specifically, the wafer comprises a planar silicon substrate, with an insulating layer disposed over the silicon substrate. Furthermore, a barrier layer is disposed over the insulating layer, such that the wafer comprises these three layers in a specific order, sandwiched between the planar silicon substrate and the barrier layer, upon which graphene may be grown directly by CVD. As a result, there are no intervening layers between the layers of the wafers or stacks described herein. Thus, a layer may be described as being directly on top of its associated adjacent layer.

[0016] In some embodiments, the insulating layer may not be particularly limited. As a result, the conductivity of the insulating layer is lower than that of silicon, which is a semiconductor. For example, the conductivity of an insulator is 10 -5 S / cm or less, preferably 10 -6 Alternatively, it may be measured in terms of the bandgap of the material: silicon has a bandgap of about 1.1 eV to about 1.6 eV, while insulators have much larger bandgaps, typically greater than 3 eV, and preferably greater than 4 eV.

[0017] According to a first embodiment, the insulating layer is silicon nitride and / or aluminum nitride. Such silicon wafers are well known and commercially available. Similarly, the insulating layer may be formed over the silicon substrate surface using conventional techniques. The thickness of the insulating layer is not particularly limited, and may be, for example, Si / SiO2 and Si / SiN xA wide range of thicknesses is available for wafers. The thickness may be preferably 10 nm to 100 μm, e.g., 20 nm to 10 μm. More preferably, the thickness may be 50 to 500 nm, and in some embodiments, 100 to 250 nm or 100 to 200 nm. The advantages of the present invention are most pronounced for thinner insulating layers, insofar as the relatively thin barrier layer is sufficient to provide adequate insulation between the graphene and the silicon substrate without relying on the bulk of the insulating layer (e.g., 20 nm to 500 nm, 20 nm to 250 nm, or preferably 20 nm to 200 nm). That is, there is an unexpected synergy between the insulating layer and the barrier layer described herein, preferably formed by ALD.

[0018] In another aspect, the insulating layer is silicon oxide, and statements referring to silicon nitride and aluminum nitride may be interpreted as equally applicable to silicon oxide. The inventors have discovered additional unexpected advantages when using silicon nitride and / or aluminum nitride, but silicon oxide insulating layers have also been advantageous in certain embodiments, particularly those described herein with thin barrier layers (e.g., 5 nm or less), especially when the insulating layer is at least 10 nm thick. For certain embodiments, for example, in silicon photonics for the manufacture of electro-optical modulators, where the silicon nitride forms a waveguide in the silicon oxide (thereby providing an insulating layer with regions of silicon nitride and silicon oxide, i.e., different surface regions on which a barrier layer is provided opposite the layer), or the insulating layer may consist of a layer of nitride on a layer of silicon oxide, a combination of silicon oxide with silicon nitride and / or aluminum nitride may be preferred.

[0019] The wafer further comprises a barrier layer disposed over the insulating layer, the barrier layer being the barrier layer of the wafer that provides a suitable growth surface for uniform graphene CVD growth. The barrier layer may also be referred to as an additional insulating layer, but is nevertheless distinct from the insulating layer on the silicon substrate. As will be appreciated, the opposite surface of the barrier layer is the surface that is in direct contact with and extends over the entire surface of the underlying insulating layer.

[0020] Furthermore, the barrier layer is relatively thin, at least relative to the thickness of a standard silicon substrate, and has a constant thickness of 50 nm or less. As described herein, the barrier layer thickness may be at least 1 nm, or at least 2 nm. Thus, in some embodiments, the barrier layer thickness may be 1-10 nm, preferably 1-5 nm, 2-10 nm, or even 2-5 nm, particularly for aluminum nitride insulating layers. In an exemplary embodiment, a silicon nitride insulating layer having a thickness of, for example, 10-50 nm is combined with a barrier layer having a thickness of 10-50 nm, preferably 30-50 nm. In another exemplary embodiment, an aluminum nitride insulating layer having a thickness of, for example, 100-250 nm is combined with a barrier layer having a thickness of 2-5 nm.

[0021] Barrier layers are made of metal oxides such as Al2O3, HfO2, MgAl2O4, MgO, ZnO, Ga2O3, aluminum gallium oxide (AGO), TiO2, SrTiO3, LaAlO3, Ta2O5, LiNbO3, Y2O3, Y-stabilized ZrO2 (YSZ), ZrO2, and Y3Al5O 12 (YAG), CeO2 and / or h-BN, GaN, and / or SiC, and / or CaF2. Preferably, the barrier layer is Al2O3, HfO2, MgAl2O4, MgO, Ga2O3, AGO, Ta2O5, Y2O3, Y-stabilized ZrO2 (YSZ), ZrO2, Y3Al5O 12(YAG), CeO2 and / or h-BN and / or CaF2, more preferably alumina, yttria, zirconia and / or YSZ, and most preferably alumina (and in some embodiments, alumina and / or hafnium oxide). All portions of the description herein of barrier layers that refer to alumina and / or hafnium oxide should be construed as applying equally to barrier layers formed from any of these additional materials, which may in some embodiments be combined with alumina and / or hafnium oxide. Alumina and hafnium oxide may be expressed as Al2O3 or HfO2, respectively, although the exact stoichiometry of these and other materials disclosed herein may vary within normal ranges (thus, for example, AlO x It should be understood that the

[0022] Preferably, the barrier layer is made of one material, most preferably alumina. However, in some embodiments, the barrier layer may comprise multiple insulating layers, for example, the barrier layer is made of one or more layers of alumina and one or more layers of hafnium oxide (provided that the total thickness of the barrier layer is a constant thickness of less than 50 nm as described herein). Thus, the barrier layer may be a nanolaminate, such as an Al2O3-HfO2 nanolaminate.

[0023] While not wishing to be bound by theory, the inventors believe that growing graphene at temperatures above 700°C, e.g., above 1000°C, and particularly above 1100°C, can damage the insulating layer. Typically, graphene is grown using hydrocarbon precursors, or organic compounds containing at least carbon and hydrogen, and / or a carrier gas containing hydrogen. It has been shown that the presence of hydrogen and radical hydrocarbon species in the reaction chamber during graphene growth can corrode the insulating layer, which reduces its function as an effective insulator. Corrosion creates grooves that can subsequently be filled with conductive carbon during graphene growth, providing a path for current to leak to the underlying silicon. The inventors have found that a barrier layer on the surface of the insulating layer can protect its insulating properties. The inventors were particularly surprised that this is true even for the thin thicknesses described herein.

[0024] The inventors have also found that silicon nitride and aluminum nitride offer additional advantages over other insulating layers, such as silicon oxide, for wafers to be used for CVD growth of graphene at temperatures above 700°C, particularly above 1000°C or 1100°C. At these relatively high growth temperatures, the inventors have found that the silicon oxide surface can react with the silicon substrate to generate volatile species. For example, without wishing to be bound by theory, an insulating silicon dioxide layer can liberate silicon oxide gas (e.g., SiO), particularly in the presence of hydrogen, which may be liberated during graphene synthesis or included as an inert carrier gas. The formation of such gas has been found to lead to damage to the insulating layer, which could otherwise be filled with conductive carbon, providing a path for current leakage from the graphene to the underlying silicon substrate. Advantageously, the present invention avoids such risks by using silicon nitride and / or aluminum nitride insulating layers.

[0025] The inventors also investigated whether it would be possible to provide a barrier layer directly on a silicon substrate, but found that the lattice mismatch between the silicon and the preferred barrier layer could be the source of defects / dislocations at the interface, which could then diffuse through the layer, in turn providing a path into which conductive carbon could fill during graphene growth, thereby failing to provide an effective graphene-on-insulator.

[0026] Alumina and hafnium oxide are common materials for forming dielectric layers in electronic device fabrication. Such layers are ubiquitous in electronic devices and are known to be suitable materials for deposition on graphene, such as in the formation of graphene transistors or as protective layers in graphene Hall sensors. Barrier layers can be grown using ALD (atomic layer deposition). Other suitable techniques include physical vapor deposition methods such as sputtering, e-beam, and thermal evaporation, as well as chemical methods such as MOCVD. ALD is a technique known in the art and involves the sequential, self-limiting reaction of at least two suitable precursors. Repeated cycles of separate precursors allow for the growth of thin barrier layers via a layer-by-layer growth mechanism, making ALD particularly advantageous.

[0027] Despite the advantages offered by ALD, the inventors have found that thicker barrier layers, such as those greater than 50 nm, result in poor-quality graphene. This was surprising in itself, since at least sapphire substrates (Al2O3) have been used in a significant portion of the inventors' previous work to provide a nonmetallic surface suitable for the growth of very high-quality graphene. Thicker barrier layers were found to have a surface roughness greater than that of thinner barrier layers, which then propagated as defects in any graphene formed thereon. The inventors have surprisingly found that a thin barrier layer, less than 50 nm, is sufficient to protect the insulating properties of the insulating layer and, more specifically, is essential for promoting graphene growth on the barrier layer at temperatures above 700°C, and more specifically, above 1100°C.

[0028] Without wishing to be bound by theory, the inventors believe that by reducing the thickness of the barrier layer grown by ALD, the roughness resulting from adjacent crystallites of polycrystalline alumina or hafnium oxide is reduced due to reduced variation between different crystallite sizes during barrier layer growth. However, a balance remains in providing a barrier layer containing larger crystallite sizes. In general, growing a thicker barrier layer can provide larger crystallite sizes, which is also believed to affect graphene quality.

[0029] Accordingly, in a second aspect of the present invention there is provided a method for producing a wafer for CVD growth of uniform graphene at temperatures above 700°C, comprising the steps of: providing a planar silicon substrate having an insulating layer disposed over a surface thereof; forming a barrier layer over the insulating layer by ALD using water or ozone as an oxidant precursor; Including, the insulating layer is a silicon nitride and / or aluminum nitride layer; A method is provided in which the barrier layer has a consistent thickness of 50 nm or less and provides a growth surface for uniform graphene CVD growth at temperatures above 700°C.

[0030] Preferably, the method is for manufacturing a wafer according to the first aspect of the invention.

[0031] As described herein, the insulating layer may be composed of silicon nitride and / or aluminum nitride. Therefore, the insulating layer does not include silicon oxide and, therefore, does not include any native surface oxide. In one embodiment of the method, the first step of providing a planar silicon substrate with an insulating layer to remove any native oxide present on the silicon substrate includes heating the silicon substrate with the native oxide to a temperature above 900°C in a reaction chamber and contacting the surface with hydrogen gas, thereby removing the native oxide. This method is particularly preferred because it can be performed in situ in the reaction chamber before forming the insulating layer. This is fast, reliable, and effective for removing native oxide.

[0032] In this embodiment, the hydrogen gas preferably consists of hydrogen; that is, the hydrogen is provided with only unavoidable impurities. Hydrogen with a purity of 99.99% is readily obtainable. The hydrogen can be further purified by passing it through a suitable purifier that removes traces of organics, water, and oxygen from the gas stream. A high purity hydrogen source is required to ensure the absence of undesirable side reactions.

[0033] In an alternative embodiment, the first step involves treating the silicon substrate with hydrofluoric acid, thereby removing native oxide from the growth surface, and introducing the silicon substrate into a reaction chamber for nitridation. This method is less preferred because silicon is reactive and precautions must be taken before the substrate is added to the reaction chamber. However, the use of hydrofluoric acid or equivalent helps to quickly remove oxide without the need for a high-temperature treatment step.

[0034] In either case, the silicon nitride and / or aluminum nitride layers may be formed using standard growth or deposition techniques.

[0035] This method involves forming a barrier layer over an insulating layer by ALD using water or ozone as a precursor, specifically as an oxygen atom source. The inventors have found that thinner layers, such as 1-50 nm, 1-10 nm, or 2-5 nm, are particularly preferred when using water to form the barrier layer. Without wishing to be bound by theory, the inventors have found that such thin layers significantly reduce the ability to increase H pressure. Upon heating to the temperature required for graphene growth, the liberation of hydrogen gas caused blistering on the barrier layer surface. The roughness of the barrier layer compromised the quality of the graphene subsequently formed thereon. When ozone is used as a precursor, the thickness of the barrier layer is preferably 2-40 nm, preferably 5-20 nm, due to the slightly inferior insulating properties observed when ozone is used as a precursor.

[0036] Therefore, the step of forming the barrier layer is preferably carried out using water as a precursor. Likewise, the wafer of the invention preferably comprises a barrier layer that is obtainable, preferably obtained, by ALD using water as a precursor.

[0037] Suitable precursors providing the aluminum or hafnium atoms required for alumina or hafnium oxide are well known and commercially available, and are not particularly limited. Metal halides, such as metal chlorides (e.g., AlCl3 and HfCl4), may be used. Alternatively, metal amides, metal alkoxides, or organometallic precursors may be used. Hafnium precursors include, for example, tetrakis(dimethylamido)hafnium(IV), tetrakis(diethylamido)hafnium(IV), hafnium(IV)-tert-butoxide, and dimethylbis(cyclopentadienyl)hafnium(IV). Preferably, the barrier layer is alumina, and the additional precursor for ALD is preferably a trialkylaluminum or trialkoxide aluminum, such as trimethylaluminum, tris(dimethylamido)aluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), or aluminum tris(acetylacetonate). Suitable equivalent precursors for other barrier layers are also known.

[0038] The deposition temperature for forming the barrier layer may be any conventional temperature known in the art. Typically, the deposition temperature is between 40°C and 300°C, although the inventors have found that temperatures above 100°C are preferred and provide better quality barrier layers.

[0039] In another aspect of the invention, there is provided a method for producing a laminate, the method comprising providing a wafer (or a portion of a wafer after dicing) as described herein and forming a graphene layer on a growth surface of a barrier layer by CVD at a temperature above 700°C.

[0040] Accordingly, there is also provided a stack comprising at least a portion of a wafer as described herein and a graphene layer formed on the growth surface of the barrier layer by CVD at a temperature above 700°C.

[0041] As will be appreciated, the wafer may be diced using conventional techniques such as sawing or laser cutting to provide a plurality of diced wafers, and then, as described herein, a graphene layer may be formed on the diced wafers by CVD to provide a stack comprising a portion of the wafer.

[0042] Preferably, the graphene layer is formed by a CVD method described below prior to wafer dicing. For example, the graphene layer is formed by CVD on a wafer having a diameter of at least 5 cm (2 inches). Multiple electronic devices may then be formed using standard microfabrication techniques, so that the multiple devices share at least a common silicon substrate. The multiple devices may then be separated by wafer dicing, thereby providing electronic devices comprising a stack, each comprising a portion of the original wafer.

[0043] The present invention also provides an electronic device comprising the laminate described herein. The electronic device may then be installed in an electrical or electronic circuit, typically by wire bonding to additional circuitry or by other methods known in the art, such as soldering using "flip-chip" style solder bumps. Thus, an electronic device is a device that functions when installed in an electronic circuit and an electrical current is applied to the device. Preferred electronic devices are sensors, such as Hall sensors, current sensors, and biosensors, modulators, such as electro-optical modulators, and transistors. The present invention also provides the use of the laminate to form an electronic device. In some embodiments, the silicon substrate of the wafer of the laminate may be removed to obtain an electronic device free of the silicon substrate. This may be achieved by grinding or etching the silicon in the manner described in UK Patent Application No. 2102218.1, the contents of which are incorporated herein by reference.

[0044] Both the stack and the method for making the stack require a graphene layer formed by CVD on the growth surface of a barrier layer of a wafer, the graphene being grown by CVD at a temperature above 700°C, preferably above 1000°C, and the wafer being suitable for such graphene growth by CVD at such temperatures.

[0045] Preferably, graphene is grown by CVD according to the disclosure of WO 2017 / 029470, the contents of which are incorporated herein by reference. This publication discloses methods for producing graphene that generally rely on heating a substrate (such as the wafers described herein) held in a reaction chamber to a temperature within the decomposition range of a carbon-based precursor for graphene growth, and introducing the precursor into the reaction chamber through a relatively cold inlet to establish a sufficiently steep temperature gradient extending away from the substrate surface toward the point where the precursor enters the reaction chamber, such that the proportion of precursor reacting in the gas phase is sufficiently low to allow graphene formation from carbon released from the decomposed precursor. Preferably, the apparatus includes a showerhead with multiple precursor entry points or inlets, the spacing of which from the substrate surface may vary and is preferably less than 100 mm.

[0046] Forming graphene is synonymous with synthesizing, manufacturing, producing, or growing graphene. Graphene is a well-known two-dimensional material that refers to an allotrope of carbon containing a single layer of carbon atoms in a hexagonal lattice. As used herein, graphene refers to one or more layers of graphene. Accordingly, some embodiments of the present invention include the formation of a single layer of graphene as well as multilayer graphene (sometimes referred to as a graphene layer structure). Preferably, graphene refers to a graphene layer structure having 1 to 10 single layers of graphene. For many applications for subsequent stacking, a single layer of graphene on a wafer is particularly preferred. Therefore, the graphene formed is preferably single-layer graphene. Nevertheless, for other applications, multilayer graphene is preferred, and two- or three-layer graphene may be preferred.

[0047] The method for producing the laminate involves forming graphene by CVD, which occurs in a CVD reaction chamber. This process for forming graphene typically involves introducing gas-phase precursors and / or precursors suspended in a gas into the CVD reaction chamber. CVD generally refers to various chemical vapor deposition techniques, each of which involves vacuum deposition to produce thin-film materials, including two-dimensional crystalline materials like graphene. Volatile precursors (in the gas phase or suspended in a gas) decompose to liberate the necessary species to form the desired material (carbon, in the case of graphene). As will be appreciated, wafers are similarly and preferably suitable for uniform graphene growth by the preferred CVD methods described herein.

[0048] Preferably, the method includes forming graphene by thermal CVD, where decomposition is the result of heating a precursor. Preferably, the CVD reaction chamber used is a cold-wall reaction chamber, where a heater coupled to the substrate is the only heat source to the chamber.

[0049] In a particularly preferred embodiment, the CVD reaction chamber includes a close-coupled showerhead having multiple precursor entry points or an array of precursor entry points. Such CVD apparatuses with close-coupled showerheads are sometimes known as those used in MOCVD processes. Therefore, the method can alternatively be said to be performed using an MOCVD reactor with a close-coupled showerhead. In either case, the showerhead is preferably configured to provide a minimum spacing between the surface of the wafer and the multiple precursor entry points of less than 100 mm, more preferably less than 25 mm, and even more preferably less than 10 mm. As should be understood, a constant spacing means that the minimum spacing between the surface of the wafer and each precursor entry point is substantially the same. The minimum spacing refers to the minimum spacing between the precursor entry points and the wafer surface. Therefore, such an embodiment includes a "vertical" configuration in which the plane containing the precursor entry points is substantially parallel to the plane of the wafer surface, i.e., the growth surface of the barrier layer.

[0050] The precursor entry points into the reaction chamber are preferably cooled. To maintain a relatively low temperature at the precursor entry points, such that the temperature of the precursors as they pass through the multiple precursor entry points and enter the reaction chamber is less than 100° C., preferably less than 50° C., the inlets, or showerheads if used, are preferably actively cooled by an external coolant, such as water.

[0051] Preferably, the combination of sufficiently small spacing between the wafer surface and the multiple precursor entry points and cooling of the precursor entry points, coupled with heating the wafer into the precursor decomposition range and above 700°C, creates a sufficiently steep temperature gradient extending from the substrate surface to the precursor entry points to enable graphene formation on the substrate surface. As disclosed in WO 2017 / 029470, extremely steep temperature gradients may be used to facilitate the formation of high-quality, uniform graphene directly on non-metallic substrates, preferably across the entire surface of the substrate. Wafers of the invention may have a diameter of at least 5 cm (2 inches), at least 15 cm (6 inches), or at least 30 cm (12 inches). Apparatus particularly suitable for the methods described herein include the Aixtron® Close-Coupled Showerhead® reactor and the Veeco® TurboDisk reactor.

[0052] As a result, in particularly preferred embodiments in which the formation of graphene comprises using the methods disclosed in WO 2017 / 029470, the formation of graphene comprises: providing a wafer comprising a barrier layer having a growth surface on a heated susceptor in a close-coupled reaction chamber, the close-coupled reaction chamber having a plurality of cooled inlets positioned such that, in use, the inlets are distributed across the wafer and spaced apart from the wafer; cooling the inlet to less than 100°C; introducing a precursor in a vapor phase and / or suspended in a gas into a CVD reaction chamber through an inlet, thereby decomposing the precursor and forming graphene on a growth surface of a barrier layer of the wafer; heating the susceptor to a temperature at least 50° C. above the decomposition temperature of the precursor to provide a thermal gradient between the growth surface and the inlet that is steep enough to enable the formation of graphene from carbon released from the decomposed precursor; Including, The regular spacing is less than 100 mm, preferably less than 25 mm, and even more preferably less than 10 mm.

[0053] In a preferred embodiment of the present invention, the precursor is introduced into the CVD reaction chamber as a mixture with a carrier gas. Carrier gases are well known in the art and may be referred to as dilution gases or diluents. Carrier gases typically include inert gases such as noble gases, and in the case of graphene growth, hydrogen gas. Thus, the carrier gas is preferably one or more of hydrogen (H), nitrogen (N), helium (He), and argon (Ar). More preferably, the carrier gas is one of nitrogen, helium, and argon, or the carrier gas is a mixture of hydrogen and one of nitrogen, helium, and argon.

[0054] In another aspect of the invention, there is provided a wafer for CVD growth of uniform graphene at temperatures above 700°C, comprising: a planar silicon substrate; an insulating layer disposed over a silicon substrate; a barrier layer disposed over the insulating layer; The barrier layer is an alumina and / or hafnium oxide layer having a uniform thickness of 20 nm or less, providing a growth surface for uniform graphene CVD growth on a wafer.

[0055] Similarly, another aspect of the invention is a method for producing a wafer for CVD growth of uniform graphene at temperatures above 700°C, comprising the steps of: providing a planar silicon substrate having an insulating layer disposed over a surface thereof; forming a barrier layer over the insulating layer by ALD using water or ozone as a precursor; Including, The barrier layer is an alumina and / or hafnium oxide layer having a consistent thickness of 20 nm or less, and provides a growth surface for uniform graphene CVD growth at temperatures above 700°C. Methods and methods for producing stacks are provided, along with such stacks, that include providing at least a portion of a wafer and forming a graphene layer on the growth surface of the barrier layer by CVD at temperatures above 700°C. [Brief explanation of the drawings]

[0056] The invention will now be further described with reference to the following non-limiting drawings. [Figure 1] 1 is a plot of resistance (Ω) against bias (V) for a comparative stack. [Figure 2] 1 is a plot of resistance (Ω) against bias (V) for a stack according to the present invention. [Figure 3A] AFM image of graphene grown by a comparative method directly on a silicon nitride surface. [Figure 3B] AFM images of graphene grown by a comparative method directly on a silicon oxide surface. [Figure 4] 1 is an AFM image of graphene grown according to an example. [Figure 5] 1 is an AFM image of graphene grown according to an example. DETAILED DESCRIPTION OF THE INVENTION

[0057] Figure 1 shows a plot of data obtained from measuring the resistance between graphene and the silicon substrate of a comparison wafer. The graphene was grown on a 200-nm-thick insulating Si3N4 layer on the silicon substrate using CVD at growth temperatures exceeding 1300 °C.

[0058] Figure 2 is a plot of data obtained from measuring the resistance between graphene and the silicon substrate of a wafer described herein. The wafer is similar to that of the comparative example, with an insulating Si3N4 layer on a silicon substrate and 5 nm of AlO formed by ALD using water as a precursor. x The graphene is grown using CVD at the same growth temperature of over 1300°C. x The AlO layer was grown on the growth surface of the barrier layer. x The presence of the barrier layer reduces the resistance by an average of 10 Ω over biases from -3 V to +3 V as a result of protecting the insulating Si3N4 layer during graphene growth by CVD. 5 Demonstrate that it brings about improvements in

[0059] Figure 3A is an AFM image showing the morphology of graphene grown directly on a silicon nitride surface. Figure 3B is an AFM image showing the morphology of graphene grown directly on a silicon oxide surface. Figure 4 is an AFM image showing the improved morphology of graphene grown according to the method of the present invention, particularly on a thin (<5 nm) alumina layer on silicon nitride. Figure 5 is an AFM image showing the improved morphology of graphene grown according to the method of the present invention, particularly on a thin (<5 nm) alumina layer on aluminum nitride. [Example]

[0060] Example A silicon wafer with a pre-grown silicon nitride or aluminum nitride coating is placed in an ALD chamber and maintained at a deposition temperature of 150 °C under a vacuum of approximately 220 mTorr (approximately 27 Pa) using a 27 sccm nitrogen gas flow to equilibrate the chamber temperature and pressure and to desorb moisture from the sample surface. Al2O3 is then deposited using trimethylaluminum (TMAl) and either deionized water (DIH2O) or ozone (O3) as the organometallic and oxidant precursors, respectively. Trimethylaluminum (TMAl) and either deionized water or ozone are introduced into the deposition chamber with nitrogen as the carrier and purge gas. The precursors are pulsed into the chamber at a 3:2 ratio with a pulse time of 0.6 seconds and purge times of 20 seconds, 18 seconds, or 25 seconds for TMAl and DIH2O or O3, respectively. Films are deposited at 150 °C for various cycles (10 to 1000 cycles) depending on the desired film thickness.

[0061] The ALD-capped wafer is placed on a silicon carbide-coated graphite susceptor in an MOCVD reactor chamber. The reactor chamber itself is protected in an inert atmosphere within a glovebox. The reactor is then sealed and purged under a flow of nitrogen, argon, or hydrogen gas at a rate of 10,000–60,000 sccm. The susceptor is rotated at a rate of 40–60 rpm. The pressure in the reactor chamber is reduced to 30–100 mbar. An optical probe is used to monitor the wafer's reflectivity and temperature during growth; the wafer is not yet heated, and is rotated beneath the probe to establish a baseline signal. A resistive heating coil positioned directly below the susceptor is then used to heat the wafer to a set point of 1000–1500 °C at a rate of 0.1–3.0 K / s. The wafer is optionally baked under a flow of hydrogen gas for 10-60 minutes, after which the ambient gas is switched to nitrogen or argon and the pressure reduced to 30-50 mbar. The wafer is annealed at the growth temperature and pressure for 5-10 minutes, after which a hydrocarbon precursor is introduced into the chamber. It is transported from its liquid state in a bubbler by passing a carrier gas (nitrogen, argon, or hydrogen) through a liquid held at constant temperature and pressure. The vapor enters a gas mixing manifold and proceeds through a showerhead into the reactor chamber via numerous small inlets, commonly referred to in the art as a plenum / plena, ensuring uniform vapor distribution and growth across the wafer's surface. The wafer is exposed to the hydrocarbon vapor under constant flow rate, pressure, and temperature for 1,800-10,800 seconds, at which point the precursor supply valve is shut off. The wafer is then cooled while continuing to flow nitrogen, argon, or hydrogen gas at a rate of 0.1-4 K / min. Once the wafer temperature reaches less than 200°C, the chamber is evacuated to vacuum and purged with inert gas. Rotation is stopped and the heater is turned off. Once the heater temperature reaches less than 150°C, the reactor chamber is opened and the graphene-coated wafer is removed from the susceptor.

[0062] The graphene formed was then characterized using standard techniques, including Raman spectroscopy and atomic force microscopy. Figures 3A and 3B show the morphology of graphene grown directly on silicon nitride and silicon oxide surfaces, respectively. In contrast, Figures 4 and 5 show the morphology of graphene grown according to the examples on a thin (<5 nm) alumina layer grown on silicon nitride or aluminum nitride, respectively. Rather than growing as discrete strands or flakes of graphene, the graphene grows as a continuous single layer, making it useful for applications in electronic devices. Importantly, the alumina barrier also preserves the insulating behavior of the underlying dielectric, allowing graphene to be gated via the field effect. In the absence of an alumina barrier, graphene growth degrades the insulating dielectric, creating electrical contact between the graphene layer and the underlying silicon wafer.

[0063] As used herein, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Use of the term "comprising" is intended to be interpreted as including such features but not excluding other features, and is also intended to include options of features necessarily limited to those recited. In other words, unless the context clearly dictates otherwise, this term also includes the limitations "consisting essentially of" (intended to mean that certain additional ingredients may be present provided that they do not materially affect the essential properties of the recited feature) and "consisting of" (intended to mean that no other features may be included such that, when the components are expressed as percentages by their proportions, they add up to 100%, taking into account any unavoidable impurities).

[0064] While terms such as “first,” “second,” and the like may be used herein to describe various elements, layers, and / or portions, it should be understood that the elements, layers, and / or portions are not limited by these terms. These terms are used only to distinguish one element, layer, or portion from another or further element, layer, or portion. It will be understood that the term “on” is intended to mean “directly on,” such that there is no intervening layer between one material that is said to be “on” another material. Spatially relative terms such as “below,” “beneath,” “lower,” “above,” and “upper” may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s). It will be understood that spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the drawings. For example, if a wafer or device described herein is flipped over, elements described as "below" or "beneath" another element or feature would then be oriented "above" that other element or feature. Thus, the exemplary term "below" can encompass both an orientation of above and below. The wafer or device may be otherwise oriented, and the spatially relative descriptors used herein would be interpreted accordingly.

[0065] The foregoing detailed description has been provided by way of illustration and example, and is not intended to limit the scope of the appended claims. Many variations of the presently preferred embodiments illustrated herein will be apparent to those skilled in the art and fall within the scope of the appended claims and their equivalents.

Claims

1. 1. A wafer for CVD growth of uniform graphene at temperatures above 700°C, comprising: a planar silicon substrate; an insulating layer disposed over the planar silicon substrate; a barrier layer disposed over the insulating layer, the insulating layer is a silicon nitride and / or aluminum nitride layer; the barrier layer has a uniform thickness of 50 nm or less and provides a growth surface for uniform graphene CVD growth; A wafer wherein the barrier layer is an alumina, yttria, zirconia and / or YSZ layer.

2. The wafer of claim 1 , wherein the insulating layer has a constant thickness of 10 nm to 100 μm.

3. 3. The wafer of claim 1, wherein the barrier layer has a constant thickness of 1 to 10 nm.

4. The wafer of claim 3, wherein the barrier layer has a constant thickness of 1 to 5 nm.

5. A laminate comprising at least a portion of the wafer according to any one of claims 1 to 4 and a graphene layer formed on the growth surface of the barrier layer.

6. An electronic device comprising the laminate according to claim 5 .

7. 1. A method for producing a wafer for CVD growth of uniform graphene at temperatures above 700°C, comprising: providing a planar silicon substrate having an insulating layer disposed over a surface thereof; forming a barrier layer over the insulating layer by ALD using water or ozone as a precursor; Including, the insulating layer is a silicon nitride and / or aluminum nitride layer; the barrier layer has a uniform thickness of 50 nm or less and provides a growth surface for uniform graphene CVD growth at temperatures above 700°C; The method wherein the barrier layer is an alumina, yttria, zirconia and / or YSZ layer.

8. 8. The method of claim 7, wherein the barrier layer is alumina and the further precursor for ALD is a trialkylaluminum or a trialkoxide aluminum.

9. The method according to claim 7 or 8, wherein the wafer is one according to any one of claims 1 to 4.

10. A method for manufacturing a laminate Providing a wafer according to any one of claims 1 to 4 or a wafer obtained by the method according to any one of claims 7 to 9; forming a graphene layer on the growth surface of the barrier layer by CVD at a temperature greater than 700°C.

Images