Nitride semiconductor devices and compound semiconductor devices

Abstract

To provide a nitride semiconductor device and a compound semiconductor device capable of reducing a capacity between a gate and a drain.SOLUTION: A nitride semiconductor device comprises: a nitride semiconductor substrate of a first conductivity type; a drift region of the first conductivity type provided on the nitride semiconductor substrate; a well region of a second conductivity type provided on the drift region; a source region of the first conductivity type provided in the well region; a mesa region provided on the drift region and adjacent to the source region via the well region; a gate insulating film provided on the well region; and a gate electrode provided from the top of the gate insulating film to the top of the mesa region. A low dielectric constant film having a dielectric constant lower than that of the gate insulating film is arranged in the mesa region.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to nitride semiconductor devices and compound semiconductor devices. [Background technology]

[0002] In a typical DMOS, a gate oxide film (SiO2) is placed between the gate electrode and the semiconductor substrate, resulting in a gate-drain capacitance (hereinafter simply referred to as "gate capacitance") C GD This limits the switching speed. GD Increasing the thickness of the gate oxide film is an effective way to reduce this, but there is a trade-off between the thickness of the gate oxide film and the on-resistance of the DMOS. Therefore, a structure in which a thick field oxide film is formed in a region that does not contribute to the channel is known (see, for example, Patent Document 1). With this structure, the increase in the on-resistance is suppressed while the gate capacitance C GD It is possible to reduce [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 6-204484 Summary of the Invention [Problem to be solved by the invention]

[0004] The structure disclosed in Patent Document 1 is premised on forming a field oxide film by partially thermally oxidizing a silicon substrate. In nitride semiconductor devices that use, for example, gallium nitride (GaN) as the substrate instead of silicon, the process of forming a field oxide film by thermal oxidation cannot be applied. Even in nitride semiconductor devices, the gate capacitance C GD Therefore, a structure that can reduce this is desired. The present invention has been made in view of the above circumstances, and has an object to provide a nitride semiconductor device and a compound semiconductor device that are capable of reducing the gate-drain capacitance. [Means for solving the problem]

[0005] In order to solve the above problems, a nitride semiconductor device according to one aspect of the present invention includes a first conductivity type nitride semiconductor substrate, a first conductivity type drift region provided on the nitride semiconductor substrate, a second conductivity type well region provided on the drift region, a first conductivity type source region provided in the well region, a mesa region provided on the drift region and adjacent to the source region with the well region interposed therebetween, a gate insulating film provided on the well region, and a gate electrode provided from above the gate insulating film to above the mesa region. A low-k film having a dielectric constant lower than that of the gate insulating film is disposed in the mesa region.

[0006] A compound semiconductor device according to one aspect of the present invention includes a first conductivity type compound semiconductor substrate mainly made of a compound semiconductor having a gap wider than that of silicon, a first conductivity type drift region provided on the compound semiconductor substrate, a second conductivity type well region provided on the drift region, a first conductivity type source region provided in the well region, a mesa region provided on the drift region and adjacent to the source region with the well region interposed therebetween, a gate insulating film provided on the well region, and a gate electrode provided on the gate insulating film and extending over the mesa region. A low-k film having a dielectric constant lower than that of the gate insulating film is disposed in the mesa region. [Effects of the Invention]

[0007] According to one aspect of the present invention, it is possible to provide a nitride semiconductor device and a compound semiconductor device capable of reducing the gate-drain capacitance. [Brief explanation of the drawings]

[0008] [Figure 1]FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view showing an example of the configuration of the GaN semiconductor device according to the first embodiment of the present invention. [Figure 3] FIG. 3 is a cross-sectional view showing an example of the configuration of a vertical MOSFET according to the first embodiment of the present invention. [Figure 4] 4A to 4C are cross-sectional views showing the manufacturing method of the vertical MOSFET according to the first embodiment of the present invention in the order of steps. [Figure 5] 5A to 5D are cross-sectional views showing the manufacturing method of the vertical MOSFET according to the first embodiment of the present invention in the order of steps. [Figure 6] FIG. 6 is a cross-sectional view showing a configuration example of a vertical MOSFET according to the second embodiment of the present invention. [Figure 7] 7A to 7D are cross-sectional views showing a method for manufacturing a vertical MOSFET according to the second embodiment of the present invention in the order of steps. [Figure 8] FIG. 8 is a cross-sectional view showing a vertical MOS transistor according to an embodiment of the present invention and MOS transistors according to first and second comparative examples. [Figure 9] FIG. 9 is a graph showing the results of calculating the relationship between the gate capacitance CGD and the drain voltage VD for each of the example and the first and second comparative examples. [Figure 10] FIG. 10 is a graph showing data from an example, and is a graph showing the relationship between the effective dielectric constant of the insulating film and the gate capacitance CGD (A), and the relationship between the effective dielectric constant of the insulating film and the reduction rate of the gate capacitance CGD relative to Comparative Example 2 (B). [Figure 11] FIG. 11 is a cross-sectional view showing the model (Example, Comparative Example 2) used in calculating the graph shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] An embodiment of the present invention will be described below. In the following description of the drawings, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each component, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0010] The definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0011] In the following description, directions may be described using the terms X-axis direction, Y-axis direction, and Z-axis direction. For example, the X-axis direction and Y-axis direction are directions parallel to the surface of the GaN layer 20. The X-axis direction and Y-axis direction are also referred to as horizontal directions. The Z-axis direction is the normal direction to the surface of the GaN layer 20. The X-axis direction, Y-axis direction, and Z-axis direction are perpendicular to each other.

[0012] In the following description, + or - attached to P or N indicating the conductivity type of a semiconductor region means that the semiconductor region has a relatively higher or lower impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if semiconductor regions are attached with the same P and P (or N and N), this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same. <Embodiment 1> (Configuration example)

[0013] Fig. 1 is a plan view showing an example of the configuration of a GaN semiconductor device 100 according to embodiment 1 of the present invention. Fig. 2 is a cross-sectional view showing an example of the configuration of a GaN semiconductor device 100 according to embodiment 1 of the present invention. Fig. 2 shows a cross section taken along line AA' in the plan view of Fig. 1. 1 and 2 is, for example, a power semiconductor device, and includes a gallium nitride substrate (hereinafter, GaN substrate) 10 and a plurality of vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 1 provided on the GaN substrate 10. In the GaN semiconductor device 100, the vertical MOSFETs 1 are repeatedly provided in one direction (for example, the X-axis direction). One vertical MOSFET 1 is a repeated unit structure, and this unit structure is arranged side by side in one direction (for example, the X-axis direction).

[0014] The region where multiple unit structures are provided is called the active region. Although not shown, an edge termination structure that functions to prevent electric field concentration in the active region is provided around the active region. The edge termination structure may include one or more of a guard ring structure, a field plate structure, and a JTE (JunctiOn Termination ExtentSiOn) structure.

[0015] 3 is a cross-sectional view showing an example of the configuration of a vertical MOSFET 1 according to Embodiment 1 of the present invention. As shown in Fig. 3, the vertical MOSFET 1 includes a GaN substrate 10, a GaN layer 20 provided on the GaN substrate 10, a trench H provided in the GaN layer 20, a gate insulating film 42, a low-k film 35 provided in the trench H, a gate electrode 51, a source electrode 53, and a drain electrode 55.

[0016] The GaN substrate 10 is a GaN single crystal substrate. The GaN substrate 10 is a substrate of a first conductivity type (N-type). The N-type impurities contained in the GaN substrate 10 are one or more elements selected from the group consisting of Si (silicon), O (oxygen), and Ge (germanium). For example, the N-type impurities contained in the GaN substrate 10 are Si or O, and the impurity concentration of Si or O in the GaN substrate 10 is 2×10 18 cm -3 That's all.

[0017] The GaN substrate 10 has a dislocation density of 1×10 7 cm -2The GaN substrate 10 may be a low-dislocation freestanding substrate having a dislocation density of less than 1000 nm. When the GaN substrate 10 is a low-dislocation freestanding substrate, the dislocation density of the GaN layer 20 formed on the GaN substrate 10 is also low. Furthermore, by using a low-dislocation substrate for the GaN substrate 10, leakage current in the power device can be reduced even when a large-area power device is formed on the GaN substrate 10. This allows the manufacturing equipment to manufacture power devices with a high yield rate. Furthermore, it is possible to prevent ion-implanted impurities from diffusing deeply along dislocations during heat treatment.

[0018] The GaN layer 20 is provided on the surface (top surface in FIG. 3 ) of the GaN substrate 10. The GaN layer 20 is a GaN single crystal layer, and is a layer epitaxially formed on the surface of the GaN substrate 10. The GaN layer 20 is provided with an N-type drift region 21, a P-type well region 22, an N+-type source region 23, and an N-type JFET region 24.

[0019] The drift region 21 functions as a current path between the GaN substrate 10 and the JFET region 24. The drift region 21 is formed by doping with N-type impurities during the epitaxial growth process that forms the GaN layer 20. The drift region 21 has a lower concentration of N-type impurities than the source region 23 and the JFET region 24.

[0020] Well region 22 is formed by doping with P-type impurities during the epitaxial growth process that forms GaN layer 20. Alternatively, well region 22 may be formed by ion-implanting P-type impurities to a predetermined depth from the surface of GaN layer 20, followed by heat treatment. In well region 22, the portion in contact with gate insulating film 42 and its vicinity become the channel region of vertical MOSFET 1.

[0021] The source region 23 is provided on the surface side of the GaN layer 20 and is located inside the well region 22. The source region 23 and the well region 22 are in contact with each other in the X-axis direction, the Y-axis direction, and the Z-axis direction. The source region 23 is formed by ion-implanting N-type impurities to a predetermined depth from the surface of the GaN layer 20 and then performing a heat treatment. The source region 23 has a higher N-type impurity concentration than the first JFET region 24A described below.

[0022] The JFET region 24 is located around the trench H and functions as a current path between the drift region 21 and the well region 22. The JFET region 24 is formed by ion-implanting N-type impurities to a predetermined depth from the surface of the GaN layer 20 and then performing heat treatment. The JFET region 24 has a first JFET region 24A and a second JFET region 24B adjacent to the first JFET region 24A in the Z-axis direction. The second JFET region 24B is located closer to the back surface (the bottom surface in FIG. 3 ) of the GaN layer 20 than the first JFET region 24A.

[0023] For example, the first JFET region 24A is located between the trench H and the well region 22 in the X-axis direction. The first JFET region 24A faces the side surface of the trench H and is adjacent to the well region 22. The second JFET region 24B is located between the trench H and the back surface of the GaN layer 20 in the Z-axis direction. The second JFET region 24B faces the bottom surface of the trench H and is adjacent to the drift region 21. The first JFET region 24A has a higher N-type impurity concentration than the second JFET region 24B.

[0024] The gate insulating film 42 is provided on the well region 22. The gate insulating film 42 also has an extension portion 421 that extends from above the well region 22 into the trench H. The extension portion 421 is a part of the gate insulating film 42 and has the same composition and thickness as the gate insulating film 42. The extension portion 421 is disposed in the trench H and covers the first JFET region 24A facing the side surface of the trench H and the second JFET region 24B facing the bottom surface of the trench H. The gate insulating film 42 is, for example, a silicon oxide film (SiO2 film) or aluminum oxide (Al2O3). The thickness of the gate insulating film 42 is, for example, not less than 50 nm and not more than 100 nm.

[0025] The low dielectric constant film 35 is disposed in the trench H via the extension portion 421 of the gate insulating film 42. The dielectric constant of the low dielectric constant film 35 is lower than that of the gate insulating film 42. The low dielectric constant film 35 is, for example, a carbon-containing silicon oxide film (SiOC) in which carbon (C) is added to a silicon oxide film (SiO), or a fluorine-containing silicon oxide film (SiOF) in which fluorine (F) is added to a silicon oxide film (SiO). The film thickness of the low dielectric constant film 35 is, for example, 0.5 μm or more and 2.0 μm or less.

[0026] The sum of the thickness of the extension portion 421 and the thickness of the low dielectric constant film 35 may be the same as the depth from the surface of the well region 22 to the bottom surface of the trench H. This allows the surface of the low dielectric constant film 35 and the surface of the well region 22 to be aligned at the same height. In this specification, the insulating region disposed in the trench H is also referred to as a mesa region. As shown in Figures 2 and 3, in the vertical MOSFET 1 according to the first embodiment, the low-k film 35 and the extension portion 421 are disposed in the trench H, and therefore the low-k film 35 and the extension portion 421 correspond to the mesa region.

[0027] The gate electrode 51 is provided continuously from above the gate insulating film 42 to above the low dielectric constant film 35 (that is, above the mesa region). The gate electrode 51 is made of, for example, polysilicon doped with impurities. The source electrode 53 is provided on the source region 23 and is electrically connected to the source region 23. The source electrode 53 may be provided so as to cover the gate electrode 51 via an interlayer insulating film (not shown).

[0028] Source electrode 53 is made of, for example, Al or an Al-Si alloy. Source electrode 53 may have a barrier metal layer between itself and the surface of GaN layer 20. Titanium (Ti) may be used as the material for the barrier metal layer. That is, source electrode 53 may be a film in which a Ti layer and an Al layer are stacked, or a film in which a Ti layer and an Al-Si alloy layer are stacked. The drain electrode 55 is provided on the back surface side of the GaN substrate 10 and is electrically connected to the GaN substrate 10. The drain electrode 55 is also made of the same material as the source electrode 53.

[0029] In the vertical MOSFET 1, the impurity concentrations and dimensions of the well region 22 and the JFET region 24 preferably satisfy the following conditions. That is, let Na be the acceptor concentration in the well region 22 obtained by offsetting the N-type impurity concentration from the P-type impurity concentration. Let da be the length in the X-axis direction of the portion of the well region 22 covered with the gate insulating film 42 (see FIG. 4 described later). Let Nd1 be the donor concentration in the first JFET region 24A obtained by offsetting the P-type impurity concentration from the N-type impurity concentration. Let dd1 be the length in the X-axis direction of the first JFET region 24A (see FIG. 4 described later). Let Nd2 be the donor concentration in the second JFET region 24B. Let dd2 be the length in the X-axis direction of the second JFET region 24B (see FIG. 4 described later). In this case, it is preferable that the vertical MOSFET 1 satisfy the following formula (1). By satisfying the following formula (1), the vertical MOSFET 1 can increase the off-state breakdown voltage between the drain and source. Na×da>Nd1×dd1>Nd2×dd2…(1)

[0030] Alternatively, the P-type impurity concentration in the well region 22 may be NA, the N-type impurity concentration in the first JFET region 24A may be ND1, and the N-type impurity concentration in the second JFET region 24B may be ND2. When NA≈Na, ND1≈Nd1, and ND2≈Nd2, the vertical MOSFET 1 preferably satisfies the following formula (1)'. By satisfying the following formula (1)', the vertical MOSFET 1 achieves the same effect as when the above formula (1) is satisfied. NA×da>ND1×dd1>ND2×dd2…(1)'

[0031] (Manufacturing method) Next, a method for manufacturing the vertical MOSFET 1 according to the first embodiment of the present invention will be described. FIGS. 4 and 5 are cross-sectional views showing the manufacturing method of the vertical MOSFET 1 according to the first embodiment of the present invention in the order of steps. The vertical MOSFET 1 is manufactured using various types of equipment, such as a film formation equipment, an exposure equipment, and an etching equipment. Hereinafter, these equipments will be collectively referred to as the manufacturing equipment.

[0032] 4, the manufacturing equipment forms a GaN layer 20 on a GaN substrate 10 (step ST1). For example, the manufacturing equipment epitaxially forms the GaN layer 20 on the N-type GaN substrate 10 by metal organic chemical vapor deposition (MOCVD), halide vapor phase epitaxy (HVPE), or the like. In the process of forming the GaN layer 20, a drift region 21 containing Si as an N-type impurity and a well region 22 containing Mg as a P-type impurity are formed successively.

[0033] In the process of epitaxially forming the GaN layer 20, the impurity contained in the GaN layer 20 is changed to an N-type impurity, thereby forming the drift region 21. Furthermore, by switching the impurity contained in the GaN layer 20 from an N-type impurity such as Si to a P-type impurity such as Mg, a well region 22 is formed in the GaN layer 20. The concentration of Si in the drift region 21 is, for example, 5×10 15 cm -3 5x10 or more 16 cm -3The following is the case. The thickness of the drift region 21 is, for example, 5 μm or more and 50 μm or less. The concentration of Mg in the well region 22 is, for example, 5×10 16 cm -3 or more and 5×10 17 cm -3 or less. The thickness of the well region 22 is, for example, 0.5 μm or more and 2 μm or less.

[0034] Next, the manufacturing apparatus forms a first mask (not shown) on the GaN layer 20. The first mask is composed of a SiO2 film, an Al2O3 film, or a photoresist that can be selectively removed with respect to the GaN layer 20. The first mask has a shape that opens above the region where the trench H is formed (hereinafter referred to as the trench formation region) and covers above other regions. The manufacturing apparatus forms the trench H in the GaN layer 20 by etching the portion of the GaN layer 20 exposed from the first mask (step ST2). The manufacturing apparatus forms the trench H shallower than the well region 22.

[0035] That is, when the depth from the surface of the GaN layer 20 to the bottom surface of the trench H is T1 and the depth from the surface of the GaN layer 20 to the bottom surface of the well region 22 is T2, the manufacturing apparatus forms the trench H so that T1 < T2. For example, the depth T1 is 0.2 μm or more and 1 μm or less. The depth T2 is 0.5 μm or more and 1.5 μm or less.

[0036] Next, the manufacturing apparatus uses the first mask as it is and ion-implants O or Si as an N-type impurity into the side surface and the bottom surface of the trench H (step ST3). The dose amount of the N-type impurity is 5×10 11 cm -2 or more and 1×10 13 cm -2 or less. In this ion implantation process, the manufacturing apparatus introduces more N-type impurities into the side surface than the bottom surface of the trench H.

[0037] For example, the manufacturing equipment performs a first ion implantation into the bottom and side surfaces of trench H, and then removes the first mask. Next, the manufacturing equipment forms a second mask (not shown) that exposes the side surfaces of trench H and covers the other areas (including the bottom surface of trench H). Then, the manufacturing equipment performs a second ion implantation into the side surfaces exposed from the second mask. This allows the manufacturing equipment to introduce more N-type impurities into the side surfaces of trench H than into the bottom surface. After performing the second ion implantation, the manufacturing equipment removes the second mask.

[0038] Next, the manufacturing equipment ion-implants Si as an N-type impurity into a region of GaN layer 20 where source region 23 is to be formed (hereinafter referred to as source formation region). For example, the manufacturing equipment forms a third mask (not shown) on GaN layer 20. The third mask is made of an SiO2 film, an Al2O3 film, or a photoresist. The third mask has a shape that opens above the source formation region and covers above the other regions. The manufacturing equipment ion-implants Si into GaN layer 20 on which the third mask has been formed. After the ion implantation, the manufacturing equipment removes the third mask from above GaN layer 20.

[0039] Next, the manufacturing equipment subjects the stack including the GaN substrate 10 and the GaN layer 20 to a heat treatment at a maximum temperature of 1000°C to 1200°C. This heat treatment is, for example, a rapid thermal treatment. This heat treatment activates the N-type impurities such as Si and O introduced into the GaN layer 20, and forms a JFET region 24 and a source region 23 in the GaN layer 20. This heat treatment also allows defects in the GaN layer 20 caused by the ion implantation to be repaired to some extent.

[0040] In this heat treatment step, a protective film (not shown) may be formed on the surface 20a of the GaN layer 20 beforehand. The protective film preferably has high heat resistance, does not allow impurities to diffuse from the protective film toward the GaN layer 20, and is selectively removable from the GaN layer 20. High heat resistance means that the protective film does not substantially decompose, to the extent that no pits (through openings) are formed in the protective film, even when heat treated at a temperature of 1000°C or higher and 1200°C or lower. Examples of the protective film include an aluminum nitride (AlN) film, a SiO2 film, and a silicon nitride (SiN) film. The protective film may be a laminated film in which another film is laminated on an AlN film. Examples of the other film include one or more of a SiO2 film, a SiN film, and a GaN film.

[0041] 5, the manufacturing equipment forms a gate insulating film 42 on the well region 22 and also forms an extension portion 421 of the gate insulating film 42 on the side and bottom surfaces of the trench H (step ST4). For example, the manufacturing equipment forms an insulating film by a CVD method, and then forms the insulating film into a predetermined shape using photolithography and etching techniques. In this way, the manufacturing equipment forms the gate insulating film 42 and the extension portion 421 from the insulating film.

[0042] Next, the manufacturing equipment forms the low-k film 35 on the bottom surface of the trench H via the extension portion 421 (step ST5). For example, the manufacturing equipment forms a material film (e.g., SiOC or SiOF) having a lower dielectric constant than an SiO film on the surface of the GaN layer 20 by plasma CVD. Next, the manufacturing equipment shapes the material film into a predetermined shape using photolithography and etching techniques. As a result, the manufacturing equipment forms the low-k film 35 on the bottom surface of the trench H via the extension portion 421. Thereafter, the manufacturing equipment sequentially forms gate electrode 51, source electrode 53, and drain electrode 55 (see FIG. 3) (step ST6). Through the above steps, vertical MOSFET 1 is completed.

[0043] (Effects of the First Embodiment) As described above, the vertical MOSFET 1 according to the first embodiment of the present disclosure includes an N-type GaN substrate 10, an N-type drift region 21 provided on the GaN substrate 10, a P-type well region 22 provided on the drift region 21, an N-type source region 23 provided in the well region 22, a mesa region provided on the drift region 21 and adjacent to the source region 23 with the well region 22 interposed therebetween, a gate insulating film 42 provided on the well region 22, and a gate electrode 51 provided from above the gate insulating film 42 to above the mesa region. A low-k film 35 having a dielectric constant lower than that of the gate insulating film 42 is disposed in the mesa region.

[0044] According to this, since the low dielectric constant film 35 is disposed between the gate electrode 51 and the drain electrode 55, the vertical MOSFET 1 has a gate-drain capacitance (i.e., gate capacitance) C GD The vertical MOSFET 1 can reduce the gate capacitance C GD It is possible to reduce

[0045] The JFET region 24 also includes an N-type first JFET region 24A located between the well region 22 and the mesa region, and an N-type second JFET region 24B located between the mesa region and the drift region 21 and connected to the first JFET region 24A. The first JFET region 24A has a higher N-type impurity concentration than the second JFET region 24B. This allows the first JFET region 24A to function as a current path along the side surface of the trench H. This current path may limit the on-resistance, but the electrical resistance of this current path is reduced by increasing the concentration of N-type impurities. This further suppresses the increase in on-resistance of the vertical MOSFET 1.

[0046] <Embodiment 2> (Configuration example) 6 is a cross-sectional view showing a configuration example of a vertical MOSFET 1A according to Embodiment 2 of the present invention. The vertical MOSFET 1A shown in FIG. 6 differs from the vertical MOSFET 1 shown in FIG. 3 in that the extension portion 421 of the gate insulating film 42 is provided on the low-k film 35 rather than on the side and bottom surfaces of the trench H. This allows the extension portion 43 of the gate insulating film 42 in the vertical MOSFET 1A to be formed flat. Furthermore, since the low-k film 35 contacts the side and bottom surfaces of the trench H, carriers induced on the side and bottom surfaces of the trench H can be reduced compared to the vertical MOSFET 1 of Embodiment 1, thereby enabling further reduction in parasitic capacitance. 6 also preferably satisfies the above formula (1) or (1)', similarly to the vertical MOSFET 1 shown in FIG. 3. This enables the vertical MOSFET 1A to have a high off-state breakdown voltage between the drain and source.

[0047] (Manufacturing method) Next, a method for manufacturing the vertical MOSFET 1A according to Embodiment 2 of the present invention will be described. Fig. 7 is a cross-sectional view showing the manufacturing method of the vertical MOSFET 1A according to Embodiment 2 of the present invention in the order of steps. In Fig. 7, the steps up to the step of forming the JFET region 24 and the source region 23 in the GaN layer 20 are the same as the manufacturing method of the vertical MOSFET 1 according to Embodiment 1 (steps T1 to ST3 in Fig. 4).

[0048] After the JFET region 24 is formed on the side and bottom surfaces of the trench in the GaN layer 20, the manufacturing equipment forms a low-dielectric-constant film 35 in the trench H (step ST11). For example, the manufacturing equipment forms a low-dielectric-constant material film (e.g., SiOC or SiOF) on the surface of the GaN layer 20 by plasma CVD to fill the trench H. Next, the manufacturing equipment performs a planarization process such as CMP (Chemical Mechanical Polishing) on ​​the material film to leave the material film inside the trench and remove the material film from outside the trench H. In this way, the manufacturing equipment forms a low-dielectric-constant film 35 that directly contacts the side and bottom surfaces of the trench H. Because the low-dielectric-constant film 35 is formed by the CMP process, the surface of the well region 22 and the surface of the low-dielectric-constant film 35 are aligned at the same height (i.e., are flush).

[0049] Next, the manufacturing equipment forms the gate insulating film 42 on the well region 22, and also forms the extension portion 421 of the gate insulating film 42 on the low dielectric constant film 35 (step ST12). The method of forming the gate insulating film 42 and its extension portion 421 is the same as in embodiment 1. Since the surfaces of the well region 22 and the low dielectric constant film 35 are flush with each other, the gate insulating film 42 and the extension portion 421 are formed flat. Thereafter, the manufacturing equipment sequentially forms gate electrode 51, source electrode 53, and drain electrode 55 (see FIG. 3) (step ST13). Through the above steps, vertical MOSFET 1A is completed.

[0050] (Effects of the second embodiment) In the vertical MOSFET 1A according to the second embodiment of the present invention, the low-k film 35 is in contact with the side and bottom surfaces of the trench H, and therefore, compared to the vertical MOSFET 1 according to the first embodiment, carriers induced on the side and bottom surfaces of the trench H can be reduced, and the parasitic capacitance can be further reduced. As a result, the gate capacitance C GD Further reduction of is possible. Furthermore, the gate insulating film 42 is formed after the low dielectric constant film 35 is planarized by CMP or the like. Since the low dielectric constant film 35 can be formed into a predetermined shape without using photolithography and etching techniques, the process can be simplified.

[0051] That is, in the second embodiment, when the low-k film 35 is formed, the gate insulating film 42 is not formed and is not present on the surface of the GaN layer 20. A low-k material film is present on the surface of the GaN layer 20, and this material film forms the outermost surface of the substrate. Therefore, by using CMP, the low-k film 35 can be planarized and formed simultaneously. Since the low-k film 35 can be formed using CMP instead of photolithography and etching techniques, the process becomes easier. [Example]

[0052] From the three models, the inventors have found that the gate-drain capacitance (i.e., gate capacitance) of the low-k material implant is C GD The extent to which the reduction could be achieved was calculated. First, three models are shown: an example of the present invention and comparative examples 1 and 2.

[0053] FIG. 8 is a cross-sectional view showing a vertical MOS transistor according to an example of the present invention and MOS transistors according to comparative examples 1 and 2. In each of the columns for the example, comparative examples 1, and 2 in FIG. 8, the upper diagram shows one MOS transistor (a repeating unit structure as shown in FIGS. 2, 3, and 6), and the lower diagram shows an enlarged view of the portion surrounded by the dashed line in the upper diagram. In comparative example 1, the portion surrounded by the dashed line is a portion that overlaps with the JFET region in a plan view and is the main current path of the drain current. In comparative example 1, the length in the X-axis direction (i.e., the channel length direction) of the portion surrounded by the dashed line is 1 μm. In comparative example 2 and the example, the portion surrounded by the dashed line is a portion corresponding to the JFET region in comparative example 1 and is the main current path of the drain current. In comparative example 2 and the example, the length in the X-axis direction of the portion surrounded by the dashed line (i.e., the width of the trench) is also 1 μm, corresponding to comparative example 1.

[0054] In addition, in Figure 8, "N Sub" indicates an N-type GaN substrate, "N-" indicates an N-type drift region, "P" indicates a P-type well region, "N+" indicates a source region, "JFET" indicates an N-type JFET region, "low-k" indicates a low-k film, "G" indicates a gate electrode, "D" indicates a drain electrode, and "S" indicates a source electrode.

[0055] (Example) In the MOS transistor according to the embodiment, a low-k dielectric film is disposed in the mesa region. The low-k dielectric film has a thickness of 500 nm. N-type JFET regions are disposed on both sides of the low-k dielectric film. The thickness of the JFET regions in the embodiment (i.e., the length in the X-axis direction) is 10 nm or more and 500 nm or less. An SiO2 film is disposed between the gate electrode and the low-k dielectric film. The SiO2 film has a thickness of 100 nm.

[0056] (Comparative Example 1) In the MOS transistor of Comparative Example 1, a JFET region is disposed below the gate electrode. The thickness of the JFET region is 500 nm. An SiO2 film is disposed between the gate electrode and the JFET region. The thickness of the SiO2 film is 100 nm. (Comparative Example 2) In the MOS transistor according to Comparative Example 2, a thick SiO2 film is disposed under the gate electrode. The thickness of the SiO2 film is 600 nm. N-type JFET regions are disposed on both sides of the SiO2 film. The thickness of the JFET regions in the comparative example (i.e., the length in the X-axis direction) is 10 nm or more and 500 nm or less.

[0057] (gate capacitance) FIG. 9 shows the gate capacitance C GD and drain voltage V D This is a graph showing the results of calculations of the relationship between the following formulas (2) to (4). In formulas (2) to (4), C GD is the gate capacitance. X jfetis the length of the JFET region in the X-axis direction (i.e., the channel length direction). cell is the spacing between MOS transistors (i.e., repeating unit structures) in the X-axis direction.

[0058] C ox is the capacitance between the gate electrode and the semiconductor layer via the insulating film. Specifically, in Comparative Example 1, it is the capacitance between the gate electrode and the JFET region via the SiO2 film, in Comparative Example 2, it is the capacitance between the gate electrode and the N-type drift region via the SiO2 film, and in the Example, it is the capacitance between the gate electrode and the N-type drift region via the low-k material.

[0059] C S is the capacitance of the depletion layer formed in the semiconductor layer. V D is the drain voltage. N D is the N-type concentration of the semiconductor layer in contact with the bottom of the mesa region; specifically, in Comparative Example 1, it is the N-type concentration of the JFET region, and in Comparative Example 2 and the Example, it is the N-type concentration of the N-type drift region. S is the dielectric constant of the semiconductor layer in contact with the bottom of the mesa region. ε ox is the effective dielectric constant of the insulating film (SiO2 or low-k material). ox is the thickness of the insulating film (SiO2 or low-k material) between the drain electrode and the gate electrode.

[0060]

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[0061]

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[0062]

number

[0063] This calculation gives the drain voltage V DGate capacitance C when GD The gate capacitance of the example was 502 pF / cm2, while that of the comparative example 1 was 3330 pF / cm2 and that of the comparative example 2 was 645 pF / cm2. From this result, it was confirmed that the example can greatly reduce the gate capacitance compared to the comparative examples 1 and 2. For example, it was confirmed that the example can reduce the gate capacitance by 22% compared to the comparative example 2.

[0064] (Relationship between gate capacitance and effective dielectric constant of insulating film) Next, the inventors calculated the gate capacitance C GD The relationship between the dielectric constant and the effective dielectric constant of an insulating film made by stacking a low-k material and SiO2 was calculated. FIG. 10 is a graph showing data from an example, showing the effective relative dielectric constant of the insulating film and the gate capacitance C GD The relationship (A) between the effective dielectric constant of the insulating film and the gate capacitance C GD 10 is a graph showing the relationship between the gate capacitance C GD The left axis indicates the gate capacitance C GD 11 is a cross-sectional view showing the model (Example, Comparative Example 2) used in the calculation of the graph shown in FIG.

[0065] The graph shown in FIG. 10 was calculated based on the model shown in FIG. 11 and the following formula (5). In formula (5), ε r,SiO2 is the relative dielectric constant of the silicon oxide film. SiO2 indicates the thickness of the silicon oxide film (see FIG. 11). r,lowk represents the relative dielectric constant of the low dielectric constant film. lowk is the film thickness of the low dielectric constant film (see Figure 11). total is the total thickness of the silicon oxide film and the low dielectric constant film (see FIG. 11). r,effect is the effective relative dielectric constant of the insulating film.

[0066]

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[0067] In addition, ε r,SiO2 The value of ε is 3.9. When the low-k material is SiOF, r,lowk The value of ε is 3.4. When the low-k material is SiOC, r,lowk The value of is 2.7. As shown in FIG. 10, the gate capacitance C GD is the effective dielectric constant ε of the insulating film r,effect and the effective relative permittivity ε r,effect It was confirmed that the gate capacitance C GD The reduction rate of ε r,effect It was confirmed that the smaller the value, the larger the tendency. As shown in FIG. 10, the gate capacitance C GD It has been confirmed that the formula (5)' can be reduced by approximately 10%. Therefore, in the embodiment of the present invention, it is preferable to satisfy the formula (5)'.

[0068]

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[0069] 10, the gate capacitance C GD It has been confirmed that the formula (5)'' can be reduced by approximately 20%. Therefore, in the embodiment of the present invention, it is more preferable to satisfy the formula (5)''.

[0070]

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[0071] Unlike the first embodiment, the second embodiment does not have the extension portion 421 of the gate insulating film 42 disposed inside the trench H (i.e., inside the mesa region). As a result, the second embodiment can reduce the parasitic capacitance generated between the JFET region and the insulating film in the lateral direction of the mesa region (for example, the X-axis direction in FIGS. 3 and 6) compared to the first embodiment. <Other embodiments>

[0072] As described above, the present invention has been described with reference to embodiments and modifications. However, the descriptions and drawings that form part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure. For example, while the above embodiments describe the use of a GaN substrate as a compound semiconductor substrate, the compound semiconductor substrate of the present invention is not limited to GaN. The compound semiconductor substrate of the present invention may also be a substrate primarily made of a compound semiconductor with a wider bandgap than silicon (e.g., silicon carbide (SiC)). The present invention naturally encompasses various embodiments not described herein. Various omissions, substitutions, and / or modifications of components may be made without departing from the spirit of the above-described embodiments and modifications. Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also be present. The technical scope of the present invention is defined solely by the claims that are appropriate from the above description. [Explanation of symbols]

[0073] 1.1A vertical MOSFET 10 GaN substrate 20 GaN layers 20a surface 21 Drift Region 22 well area 23 Source Region 24 JFET area 24A 1st JFET area 24B 2nd JFET area 35 Low dielectric constant film (low-k film) 42 Gate insulating film 43 Extension section 51 gate electrode 53 Source electrode 55 Drain electrode 100 GaN semiconductor devices 421 Extension section C GDGate-drain capacitance (gate capacitance) H Trench V D Drain Voltage

Claims

1. a first conductivity type nitride semiconductor substrate; a first conductivity type drift region provided on the nitride semiconductor substrate; a well region of a second conductivity type provided on the drift region; a first conductivity type source region provided in the well region; a mesa region provided on the drift region and adjacent to the source region with the well region interposed therebetween; a gate insulating film provided on the well region; a gate electrode provided on the gate insulating film and on the mesa region, The mesa region includes: a low dielectric constant film having a dielectric constant lower than that of the gate insulating film is disposed; an extension portion of the gate insulating film is disposed in the mesa region; The extension portion is disposed between the well region and the low-k film, and between the drift region and the low-k film.

2. A first conductivity type nitride semiconductor substrate; a first conductivity type drift region provided on the nitride semiconductor substrate; a well region of a second conductivity type provided on the drift region; a first conductivity type source region provided in the well region; a mesa region provided on the drift region and adjacent to the source region with the well region interposed therebetween; a gate insulating film provided on the well region; a gate electrode provided on the gate insulating film and on the mesa region, The mesa region includes: a low dielectric constant film having a dielectric constant lower than that of the gate insulating film is disposed; The extended portion of the gate insulating film is disposed on the low dielectric constant film and is formed flat.

3. A first conductivity type nitride semiconductor substrate; a first conductivity type drift region provided on the nitride semiconductor substrate; a well region of a second conductivity type provided on the drift region; a first conductivity type source region provided in the well region; a mesa region provided on the drift region and adjacent to the source region with the well region interposed therebetween; a gate insulating film provided on the well region; a gate electrode provided on the gate insulating film and on the mesa region, The mesa region includes: a low dielectric constant film having a dielectric constant lower than that of the gate insulating film is disposed; an extension portion of the gate insulating film is disposed in the mesa region; the extension portion is a silicon oxide film, The relative dielectric constant of the extension portion is ε ｒ，ＳｉＯ２ year, The film thickness of the extension portion is t ＳｉＯ２ year, The relative dielectric constant of the low dielectric constant film is ε ｒ，ｌｏｗｋ year, The thickness of the low dielectric constant film is t ｌｏｗｋ year, The total thickness of the low dielectric constant film and the silicon oxide film is t ｔｏｔａｌ Then, A nitride semiconductor device in which the following formula (1) is satisfied: ε ｒ，ＳｉＯ２ ×(t ＳｉＯ２ / t ｔｏｔａｌ ) + ε ｒ，ｌｏｗｋ ×(t ｌｏｗｋ / t ｔｏｔａｌ ) < 3.4 …(1)

4. the extension portion is a silicon oxide film, The relative dielectric constant of the extension portion is ε ｒ，ＳｉＯ２ year, The film thickness of the extension portion is t ＳｉＯ２ year, The relative dielectric constant of the low dielectric constant film is ε ｒ，ｌｏｗｋ year, The thickness of the low dielectric constant film is t ｌｏｗｋ year, The total thickness of the low dielectric constant film and the silicon oxide film is t ｔｏｔａｌ Then, 2. The nitride semiconductor device according to claim 1, wherein the following formula (2) holds: ε ｒ，ＳｉＯ２ ×(t ＳｉＯ２ / t ｔｏｔａｌ ) + ε ｒ，ｌｏｗｋ ×(t ｌｏｗｋ / t ｔｏｔａｌ ) < 3.4 …(2)

5. a first impurity region of a first conductivity type provided on the drift region and located between the well region and the mesa region; The nitride semiconductor device according to claim 1 , wherein said source region has a higher concentration of impurities of the first conductivity type than said first impurity region.

6. a second impurity region of the first conductivity type provided between the mesa region and the drift region and connected to the first impurity region; The nitride semiconductor device according to claim 5 , wherein said first impurity region has a higher concentration of the first conductivity type impurity than said second impurity region.

7. an acceptor concentration obtained by subtracting the impurity concentration of the first conductivity type from the impurity concentration of the second conductivity type in the well region is defined as Na; a first direction is a direction parallel to a surface of the well region and extending from the well region toward the mesa region; a length in the first direction of a portion of the well region covered with the gate insulating film is defined as da; a donor concentration obtained by subtracting the impurity concentration of the second conductivity type from the impurity concentration of the first conductivity type in the first impurity region is defined as Ndl; a length of the first impurity region in the first direction is denoted by ddl; the concentration of the first conductivity type impurity in the second impurity region is Nd2; When the length of the second impurity region in the first direction is dd2, 7. The nitride semiconductor device according to claim 6, wherein Na×da>Ndl×ddl>Nd2×dd2 is satisfied.

8. A nitride semiconductor device according to claim 1, wherein the extension portion has the same composition as the gate insulating film.

9. a first conductivity type compound semiconductor substrate mainly made of a compound semiconductor having a gap wider than that of silicon; a first conductivity type drift region provided on the compound semiconductor substrate; a well region of a second conductivity type provided on the drift region; a first conductivity type source region provided in the well region; a mesa region provided on the drift region and adjacent to the source region with the well region interposed therebetween; a gate insulating film provided on the well region; a gate electrode provided on the gate insulating film and on the mesa region, The mesa region includes: a low dielectric constant film having a dielectric constant lower than that of the gate insulating film is disposed; an extension portion of the gate insulating film is disposed in the mesa region; The compound semiconductor device, wherein the extension portion is disposed between the well region and the low-k film, and between the drift region and the low-k film.

10. A first conductivity type compound semiconductor substrate mainly made of a compound semiconductor having a gap wider than that of silicon; a first conductivity type drift region provided on the compound semiconductor substrate; a well region of a second conductivity type provided on the drift region; a first conductivity type source region provided in the well region; a mesa region provided on the drift region and adjacent to the source region with the well region interposed therebetween; a gate insulating film provided on the well region; a gate electrode provided on the gate insulating film and on the mesa region, The mesa region includes: a low dielectric constant film having a dielectric constant lower than that of the gate insulating film is disposed; The compound semiconductor device has an extended portion of the gate insulating film disposed on the low dielectric constant film and formed flat.

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