Semiconductor Devices

Abstract

To suppress an ineffective region of transistor operation, the ineffective region being generated by providing a lifetime control region.SOLUTION: A semiconductor device 100 comprises: a semiconductor substrate 10 which has a transistor portion 70 and a diode portion 80; and an emitter electrode 52 and a gate electrode (gate electroconductive portion), which are provided above the front side 21 of the semiconductor substrate. The transistor portion has: a plurality of trench portions 40 electrically connected to the gate electrode; a first electroconductivity type drift region 18 provided on the semiconductor substrate; a second electroconductivity type base region 14 provided above the drift region; and a second electroconductivity type trench bottom barrier region 75 which is provided between the drift region and the base region and which is higher in doping concentration than the base region. The trench bottom barrier region is electrically connected to the emitter electrode.SELECTED DRAWING: Figure 2B

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, in a semiconductor device in which a transistor section such as an insulated gate bipolar transistor (IGBT) and a diode section are formed on the same substrate, a technique is known in which a particle beam such as helium ions is irradiated to a predetermined depth position in the semiconductor substrate to provide a lifetime control region including a lifetime killer (for example, Patent Documents 1 and 2). Patent Document 1: JP 2017-135339 A Patent Document 2: JP 2014-175517 A Summary of the Invention [Problem to be solved by the invention]

[0003] In such a semiconductor device, the lifetime control region is provided not only in the diode section but also in the region of the transistor section adjacent to the diode section, thereby suppressing hole injection during reverse recovery. However, there is a problem in that the region of the transistor section where the lifetime control region is provided becomes an ineffective region that does not function as a transistor. [Means for solving the problem]

[0004] A first aspect of the present invention provides a semiconductor device comprising: a semiconductor substrate having a transistor portion and a diode portion; and an emitter electrode and a gate electrode provided above a front surface of the semiconductor substrate, the transistor portion having a plurality of trench portions electrically connected to the gate electrode, a drift region of a first conductivity type provided in the semiconductor substrate, a base region of a second conductivity type provided above the drift region, and a trench bottom barrier region of the second conductivity type provided between the drift region and the base region and having a doping concentration higher than that of the base region, the trench bottom barrier region being electrically connected to the emitter electrode.

[0005] The trench bottom barrier region may be provided in a region adjacent to the diode portion in a top view of the semiconductor substrate.

[0006] The width of the trench bottom barrier region in the arrangement direction of the plurality of trench portions may be 2 μm or more and 100 μm or less.

[0007] The width of the trench bottom barrier region may be 10 μm or more and 50 μm or less.

[0008] The doping concentration of the trench bottom barrier region is 1E11 cm -3 Above, 1E13cm -3 It may be the following:

[0009] In the depth direction of the semiconductor substrate, the lower end of the trench bottom barrier region may be located below the bottoms of the plurality of trench portions.

[0010] The transistor portion may have an accumulation region of the first conductivity type above the trench bottom barrier region, the accumulation region having a doping concentration higher than that of the drift region.

[0011] The drift region and the accumulation region may be further provided in the diode portion.

[0012] The transistor portion may further have a well region of a second conductivity type provided on the front surface of the semiconductor substrate and extending around the periphery of the active region, and an interlayer insulating film provided above the semiconductor substrate, and the trench bottom barrier region may be connected to the well region, and the well region may be electrically connected to the emitter electrode.

[0013] A part of the plurality of mesa portions located above the trench bottom barrier region may be electrically connected to the emitter electrode via a contact hole provided in the interlayer insulating film.

[0014] The transistor portion may further include an electrically floating second conductivity type floating barrier region provided between the drift region and the base region.

[0015] In the arrangement direction of the plurality of trench portions, the distance between the trench bottom barrier region and the floating barrier region may be equal to or greater than the pitch of the plurality of trench portions and equal to or less than 10 μm.

[0016] In the extension direction of the plurality of trench portions, the distance between the well region and the floating barrier region may be equal to or greater than the pitch and equal to or less than 10 μm.

[0017] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a diagram illustrating an example of the top surface of a semiconductor device 100 according to an embodiment of the present invention. [Figure 2A] FIG. 2 is an enlarged view showing an example of an area A in FIG. [Figure 2B] FIG. 2B is a diagram showing a cross section taken along line aa' in FIG. 2A. [Figure 2C] FIG. 2B is a diagram showing a cross section taken along the line bb' in FIG. 2A. [Figure 2D] FIG. 2B is a diagram showing a cross section taken along the line cc' in FIG. 2A. [Figure 3A] 2 is an enlarged view showing an example of a region B in FIG. 1. FIG. [Figure 3B] FIG. 3B is a diagram showing a cross section taken along the line dd' in FIG. 3A. [Figure 4] 10 is a graph showing the change over time in collector current Ic during reverse recovery. [Figure 5A] 1. FIG. 4 is an enlarged view showing another example of the region A in FIG. [Figure 5B] FIG. 5B is a diagram showing a cross section taken along line aa' in FIG. 5A. [Figure 6A]1. FIG. 4 is an enlarged view showing another example of the region A in FIG. [Figure 6B] FIG. 6B is a diagram showing a cross section taken along the line ee' in FIG. 6A. [Figure 6C] FIG. 6B is a diagram showing the ff' cross section in FIG. 6A. DETAILED DESCRIPTION OF THE INVENTION

[0019] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0020] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as the "top" or "front" and the other side as the "bottom" or "back." Of the two main surfaces of a substrate, layer, or other member, one is referred to as the front surface and the other as the back surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0021] In this specification, technical matters may be explained using the orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is mentioned without specifying positive or negative, it means the +Z-axis and -Z It means the direction parallel to the axis.

[0022] In this specification, orthogonal axes parallel to the front and back surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the front and back surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the front and back surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0023] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0024] In this specification, the conductivity type of a doped region doped with impurities is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.

[0025] In this specification, the doping concentration refers to the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration refers to the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any point is N D -N A This becomes:

[0026] Donors have the function of supplying electrons to semiconductors. Acceptors have the function of receiving electrons from semiconductors. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, which are formed by the combination of vacancies (V), oxygen (O), and hydrogen (H) in semiconductors, function as donors that supply electrons.

[0027] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Also, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type.

[0028] In this specification, chemical concentration refers to the concentration of an impurity measured regardless of its state of electrical activation. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may also be used as the net doping concentration. The carrier concentration measured by CV or SR may be used as a value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is sufficiently larger than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration.

[0029] In addition, when the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the donor, acceptor, or net doping concentration in the region. In cases where the donor, acceptor, or net doping concentration is approximately uniform, the average value of the donor, acceptor, or net doping concentration in the region may be taken as the donor, acceptor, or net doping concentration.

[0030] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The decrease in carrier mobility occurs when carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0031] The donor or acceptor concentration calculated from the carrier concentration measured by the CV or SR method may be lower than the chemical concentration of the element that represents the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which act as donors in silicon semiconductors, or the acceptor concentration of boron, which acts as an acceptor, is approximately 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the chemical concentration of hydrogen.

[0032] Fig. 1 is a diagram showing an example of the top surface of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the front surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0033] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 has an edge 102 in a top view. In this specification, the term "top view" simply refers to a view from the front surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of edge 102 that face each other in a top view. In FIG. 1, the X-axis and Y-axis are parallel to one of the edge 102. The Z-axis is perpendicular to the front surface of the semiconductor substrate 10.

[0034] An active region 160 is provided in the semiconductor substrate 10. The active region 160 is a region through which a main current flows in the depth direction between the front and back surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active region 160, but is not shown in FIG.

[0035] The active region 160 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 1, the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the front surface of the semiconductor substrate 10. In another example, the active region 160 may be provided with only one of the transistor section 70 and the diode section 80.

[0036] In FIG. 1, the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0037] The diode section 80 has an N+ type cathode region in a region that contacts the back surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region other than the cathode region on the back surface of the semiconductor substrate 10. In this specification, an extension region in which the diode section 80 is extended in the Y-axis direction to a gate runner, which will be described later, may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region.

[0038] The transistor section 70 has a P+ type collector region in a region in contact with the back surface of the semiconductor substrate 10. In addition, the transistor section 70 has a gate structure periodically arranged on the front surface side of the semiconductor substrate 10, the gate structure having an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0039] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. As an example, the semiconductor device 100 shown in FIG. 1 has a gate pad G, but this is merely an example. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge 102. The vicinity of the edge 102 refers to the region between the edge 102 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0040] A gate potential is applied to the gate pad G. The gate pad G is electrically connected to a conductive portion of the gate trench portion of the active region 160. The semiconductor device 100 includes a gate runner 48 that electrically connects the gate pad G and the gate trench portion.

[0041] The gate runner 48 is disposed between the active region 160 and the edge 102 of the semiconductor substrate 10 in a top view. The gate runner 48 of this example surrounds the active region 160 in a top view. The region surrounded by the gate runner 48 in a top view may be the active region 160.

[0042] The gate runner 48 is disposed above the semiconductor substrate 10. In this example, the gate runner 48 may be formed of impurity-doped polysilicon or the like. The gate runner 48 is electrically connected to a gate conductive portion provided inside the gate trench portion via a gate insulating film.

[0043] The semiconductor device 100 of this example includes an edge termination structure 190 between the active region 160 and the edge 102. The edge termination structure 190 of this example is disposed between the gate runner 48 and the edge 102. The edge termination structure 190 reduces electric field concentration on the front surface side of the semiconductor substrate 10.

[0044] Edge termination structure 190 may include a guard ring 92. Guard ring 92 is a P-type region that contacts the front surface of semiconductor substrate 10. Note that although edge termination structure 190 in this example includes multiple guard rings 92, only one guard ring 92 is shown in FIG. 1 . By providing multiple guard rings 92, the depletion layer on the upper surface side of active region 160 can be extended outward, improving the breakdown voltage of semiconductor device 100. Edge termination structure 190 may further include at least one of a field plate and a resurf annularly arranged around active region 160.

[0045] The semiconductor device 100 may also include a temperature sensing section (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting section (not shown) which operates in the same manner as a transistor section provided in the active region 160.

[0046] Fig. 2A is an enlarged view showing an example of region A in Fig. 1. The semiconductor device 100 includes a semiconductor substrate having a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a free wheel diode (FWD).

[0047] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15, which are provided inside the front surface side of a semiconductor substrate. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion.

[0048] The semiconductor device 100 of this example also includes a gate metal layer 50 and an emitter electrode 52 provided above the front surface of the semiconductor substrate. The gate metal layer 50 and the emitter electrode 52 are provided separately from each other. The gate metal layer 50 and the emitter electrode 52 are electrically insulated from each other.

[0049] An interlayer insulating film is provided between the emitter electrode 52 and the gate metal layer 50 and the front surface of the semiconductor substrate, but is not shown in Fig. 1. In this example, contact holes 49, 54, and 56 are provided through the interlayer insulating film. In Fig. 1, each contact hole is hatched with diagonal lines.

[0050] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 is electrically connected to the emitter region 12, the base region 14, and the contact region 15 on the front surface of the semiconductor substrate via contact holes 54.

[0051] The emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 by a contact hole 56. A connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is provided on the front surface of the semiconductor substrate via an insulating film such as an interlayer insulating film and a dummy insulating film in the dummy trench portion 30.

[0052] The gate metal layer 50 is electrically connected to the gate runner 48 through a contact hole 49. The gate runner 48 may be formed of impurity-doped polysilicon or the like. The gate runner 48 is connected to the gate conductive portion in the gate trench portion 40 on the front surface of the semiconductor substrate. The gate runner 48 is not electrically connected to the dummy conductive portion in the dummy trench portion 30 or the emitter electrode 52.

[0053] The gate runner 48 and the emitter electrode 52 are electrically isolated by an insulating material such as an interlayer insulating film and an oxide film. The gate runner 48 in this example is provided from below the contact hole 49 to the end of the gate trench portion 40. At the end of the gate trench portion 40, the gate conductive portion is exposed on the front surface of the semiconductor substrate and is connected to the gate runner 48.

[0054] The emitter electrode 52 and the gate metal layer 50 are formed of a conductive material containing metal, such as aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal layer made of titanium, a titanium compound, or the like beneath the region made of aluminum or the like.

[0055] Each electrode may have a plug formed of tungsten or the like in the contact hole. The plug has a barrier metal on the side that contacts the semiconductor substrate, and the tungsten is in contact with the barrier metal. Each electrode may be embedded with Aluminum on tungsten By forming a film of may be formed.

[0056] The plug is provided in a contact hole that contacts the contact region 15 or the base region 14. A P++ type plug region 17 is formed under the contact hole of the plug, and has a higher doping concentration than the contact region 15. This can improve the contact resistance between the barrier metal and the contact region 15. The depth of the plug region 17 is approximately 0.1 μm or less, which is 10% or less of the depth of the contact region 15.

[0057] The plug region 17 has the following characteristics: In the operation of the transistor section 70, improved contact resistance improves latch-up resistance. On the other hand, in the operation of the diode section 80, without the plug region 17, the contact resistance between the barrier metal and the base region 14 is high, resulting in increased conduction loss and switching loss. However, by providing the plug region 17 in the diode section 80, the increase in conduction loss and switching loss can be suppressed.

[0058] The well region 11 overlaps with the gate runner 48, extends around the periphery of the active region 160, and is provided in a ring shape in top view. The well region 11 also extends with a predetermined width into an area where it does not overlap with the gate runner 48, and is provided in a ring shape in top view. In this example, the well region 11 is provided away from the end of the contact hole 54 in the Y-axis direction toward the gate runner 48. The well region 11 is a region of the second conductivity type that has a higher doping concentration than the base region 14. The gate runner 48 is electrically insulated from the well region 11.

[0059] In this example, the base region 14 is P- type, and the well region 11 is P+ type. The well region 11 is formed from the front surface of the semiconductor substrate to a position deeper than the bottom end of the base region 14. The base region 14 is provided in contact with the well region 11 in the transistor section 70 and the diode section 80. Therefore, the well region 11 is electrically connected to the emitter electrode 52.

[0060] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction. The transistor section 70 of this example has one or more gate trench sections 40 arranged along the arrangement direction. The diode section 80 of this example has a plurality of dummy trench sections 30 arranged along the arrangement direction. The diode section 80 of this example does not have a gate trench section 40.

[0061] The gate trench portion 40 in this example may have two straight portions 39 (portions of the trench that are straight along the extension direction) extending along an extension direction perpendicular to the arrangement direction, and a tip portion 41 connecting the two straight portions 39.

[0062] At least a portion of the tip 41 may be curved in top view. The tip 41 connects the ends of the two straight portions 39 in the Y-axis direction to the gate runner 48, thereby functioning as a gate electrode to the gate trench portion 40. On the other hand, by making the tip 41 curved, electric field concentration at the end can be alleviated more effectively than if the tip 41 were completed at the straight portion 39.

[0063] In another example, the transistor section 70 may have one or more gate trench sections 40 and one or more dummy trench sections 30 alternately arranged along the arrangement direction. In the transistor section 70, the dummy trench sections 30 are provided between the respective straight line sections 39 of the gate trench sections 40. One dummy trench section 30 may be provided between each straight line section 39, or multiple dummy trench sections 30 may be provided between each straight line section 39.

[0064] Furthermore, the dummy trench portion 30 does not have to be provided between the respective straight portions 39, and the gate trench portion 40 may be provided instead. With such a structure, the electron current from the emitter region 12 can be increased, thereby reducing the on-state voltage.

[0065] The dummy trench portion 30 may have a linear shape extending in the extension direction, and may have a linear portion 29 and an end portion 31, similar to the gate trench portion 40. The semiconductor device 100 shown in FIG. 2A has only dummy trench portions 30 having end portions 31 arranged therein, but in other examples, the semiconductor device 100 may include linear dummy trench portions 30 that do not have end portions 31.

[0066] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0067] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region inside the semiconductor substrate that is sandwiched between the trench portions. For example, the depth position of the mesa portion is from the front surface of the semiconductor substrate to the bottom end of the trench portion.

[0068] The mesa portion in this example is sandwiched between adjacent trench portions in the X-axis direction and is provided on the front surface of the semiconductor substrate, extending in the extension direction (Y-axis direction) along the trenches. As will be described later with reference to FIG. 2B, in this example, the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. In this specification, the mesa portion simply referred to as a mesa portion refers to both the mesa portion 60 and the mesa portion 61.

[0069] Each mesa portion is provided with a base region 14. In each mesa portion, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in a region sandwiched between the base regions 14 in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate in the depth direction.

[0070] The mesa portion of the transistor section 70 has an emitter region 12 exposed on the front surface of the semiconductor substrate. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion in contact with the gate trench portion 40 has a contact region 15 exposed on the front surface of the semiconductor substrate.

[0071] The contact regions 15 and emitter regions 12 in the mesa portion are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and emitter regions 12 in the mesa portion are alternately arranged along the extension direction of the trench portions (the Y-axis direction).

[0072] In another example, the contact region 15 and the emitter region 12 of the mesa portion may be provided in a stripe shape along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0073] The mesa portion of the diode portion 80 does not have an emitter region 12. A base region 14 may be provided on the upper surface of the mesa portion of the diode portion 80. The base region 14 may be disposed over the entire mesa portion of the diode portion 80.

[0074] A contact hole 54 is provided above each mesa portion. The contact holes 54 are arranged in a region sandwiched between the base regions 14 in the extension direction (Y-axis direction). In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 may be arranged in the center in the arrangement direction (X-axis direction) of the mesa portions.

[0075] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the rear surface of the semiconductor substrate. A P+ type collector region 22 may be provided in a region of the rear surface of the semiconductor substrate where the cathode region 82 is not provided. In Figure 2A, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0076] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed deep, thereby suppressing hole injection from the well region 11 and reducing reverse recovery loss. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0077] The transistor section 70 has a trench bottom barrier region 75 of a second conductivity type, which has a higher doping concentration than the base region 14, between a drift region (to be described later) and the base region 14. In this example, the trench bottom barrier region 75 is of P type. In FIG. 2A, the range of the trench bottom barrier region 75 is indicated by a dotted line.

[0078] In this example, the trench bottom barrier region 75 is provided in a region adjacent to the diode section 80 when viewed from above the semiconductor substrate. The region adjacent to the diode section 80 is an end region in the arrangement direction (X-axis direction) of the transistor section 70, and refers to a region that is in direct contact with the diode section 80 at the boundary with the diode section 80 extending in the extension direction (Y-axis direction). The trench bottom barrier region 75 also contacts the well region 11 at an end in the Y-axis direction.

[0079] 2B is a diagram showing the a-a' cross section in Fig. 2A. The a-a' cross section is an XZ plane passing through the contact region 15, the base region 14, the gate trench portion 40, and the dummy trench portion 30. In the a-a' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0080] The interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is an insulating film such as silicate glass doped with impurities such as boron or phosphorus. The interlayer insulating film 38 may be in contact with the front surface 21, or another film such as an oxide film may be provided between the interlayer insulating film 38 and the front surface 21. The interlayer insulating film 38 has a contact hole 54, as described with reference to FIG. 2A.

[0081] The emitter electrode 52 is provided on the front surface 21 of the semiconductor substrate 10 and on the upper surface of the interlayer insulating film 38. The emitter electrode 52 is electrically connected to the front surface 21 through a contact hole 54 in the interlayer insulating film 38. A plug of tungsten (W) or the like may be provided inside the contact hole 54. The collector electrode 24 is provided on the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a material containing metal or a laminate film thereof.

[0082] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0083] The semiconductor substrate 10 has a drift region 18 of a first conductivity type. In this example, the drift region 18 is N-type. The drift region 18 may be a remaining region of the semiconductor substrate 10 without other doped regions being provided therein.

[0084] One or more accumulation regions 16 may be provided in the Z-axis direction above the drift region 18. The accumulation region 16 is a region in which the same dopant as the drift region 18 accumulates at a higher concentration than the drift region 18. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18.

[0085] The accumulation region 16 in this example is N-type. The accumulation region 16 may be provided only in the transistor section 70, or may be provided in both the transistor section 70 and the diode section 80. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage can be reduced.

[0086] In the transistor section 70, an emitter region 12 is provided above the base region 14 in contact with the front surface 21. The emitter region 12 is provided in contact with the gate trench section 40. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. Examples of dopants for the emitter region 12 include arsenic (As), phosphorus (P), and antimony (Sb).

[0087] The diode section 80 is provided with a base region 14 exposed on the front surface 21. The base region 14 of the diode section 80 operates as an anode.

[0088] A buffer region 20 of the first conductivity type may be provided below the drift region 18. In this example, the buffer region 20 is N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0089] In the transistor section 70, a collector region 22 is provided below the buffer region 20. The collector region 22 may be provided in contact with the cathode region 82 on the back surface 23.

[0090] In the diode section 80, a cathode region 82 is provided below the buffer region 20. The cathode region 82 may be provided at the same depth as the collector region 22 of the transistor section 70. The diode section 80 may function as a freewheeling diode (FWD) that conducts a freewheeling current in the reverse direction when the transistor section 70 is turned off.

[0091] The semiconductor substrate 10 is provided with a gate trench portion 40 and a dummy trench portion 30. The gate trench portion 40 and the dummy trench portion 30 are provided so as to pass from the front surface 21 through the base region 14 and the accumulation region 16 to reach the drift region 18. The trench portion passing through the doped region is not limited to a case where the trench portion is formed after the doped region is formed. A case where the doped region is formed between the trench portions after the trench portions are formed is also included in the case where the trench portion passes through the doped region.

[0092] The gate trench portion 40 has a gate trench provided on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed of an oxide film or a nitride film. The gate conductive portion 44 is provided so as to fill the inside of the gate trench more inward than the gate insulating film 42. The upper surface of the gate conductive portion 44 may be located in the same XY plane as the front surface 21. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of impurity-doped polysilicon or the like.

[0093] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the base region 14 at the interface that contacts the gate trench.

[0094] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the XZ cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the front surface 21. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy insulating film 32 may be formed of an oxide film or a nitride film. The dummy conductive portion 34 is provided so as to fill the inside of the dummy trench further than the dummy insulating film 32. The upper surface of the dummy conductive portion 34 may be located in the same XY plane as the front surface 21. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.

[0095] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered on the front surface 21 with an interlayer insulating film 38. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a downwardly convex curved shape (a curved shape in cross section).

[0096] In the transistor section 70, a P-type trench bottom barrier region 75 is provided in a region adjacent to the diode section 80. In this example, the trench bottom barrier region 75 is provided below the accumulation region 16. The doping concentration of the trench bottom barrier region 75 is 1E11 cm -3 Above, 1E13cm -3 The following is the result.

[0097] The width W of the trench bottom barrier region 75 in the X-axis direction is 2 μm or more and 100 μm or less. The width W of the trench bottom barrier region 75 may be 10 μm or more and 50 μm or less. In FIG. 2B , the end of the trench bottom barrier region 75 on the positive side in the X-axis direction (the diode section 80 side) coincides with the boundary between the cathode region 82 and the collector region 22, but it may extend further toward the diode section 80 or may recede into the transistor section 70.

[0098] In the depth direction of the semiconductor substrate 10, the lower end of the trench bottom barrier region 75 is located below the bottom of the gate trench portion 40. In other words, the trench bottom barrier region 75 covers the bottom of the gate trench portion 40.

[0099] In the diode section 80, a lifetime control region including a lifetime killer may be locally provided in the drift region 18. The lifetime control region promotes recombination between holes generated in the base region 14 and electrons injected from the cathode region 82 when the diode section 80 is turned off, and suppresses peak current during reverse recovery. The lifetime control region may be formed by irradiating protons or helium from the front surface 21 or the back surface 23.

[0100] 2C is a diagram showing the bb' cross section in FIG. 2A. The bb' cross section passes through the mesa portion 60 in the region where the trench bottom barrier region 75 of the transistor portion 70 is provided. YZ plane The b-b' cross section is a cross section of a region spanning active region 160 and edge termination structure 190. In this example, edge termination structure 190 has a guard ring structure and a channel stopper structure.

[0101] The guard ring structure may include a plurality of guard rings 92. In this example, the guard ring structure includes five guard rings 92. Each guard ring 92 may be provided on the front surface 21 to surround the active region 160.

[0102] The guard ring structure may have the function of expanding the depletion layer generated in the active region 160 to the outside of the semiconductor substrate 10. This makes it possible to prevent electric field concentration inside the semiconductor substrate 10. Therefore, the breakdown voltage of the semiconductor device 100 can be improved compared to when no guard ring structure is provided.

[0103] The guard ring 92 is a P+ type semiconductor region formed by ion implantation near the front surface 21. The guard ring 92 is electrically connected to a field plate 94. The field plate 94 may be made of the same material as the gate metal layer 50 or the emitter electrode 52.

[0104] The multiple guard rings 92 are electrically insulated from one another by the interlayer insulating film 38. The depth of the bottom of the guard rings 92 may be the same as the depth of the bottom of the well region 11. The depth of the bottom of the guard rings 92 may be deeper than the depth of the bottom of the gate trench portion 40.

[0105] The channel stopper structure has a channel stopper 96 and a field plate 94. The channel stopper 96 is electrically connected to the field plate 94 through an opening in the interlayer insulating film 38. The conductivity type of the channel stopper 96 may be either the first conductivity type or the second conductivity type. In this example, the conductivity type of the channel stopper 96 is N+ type. The channel stopper 96 has the function of terminating a depletion layer generated in the active region 160 at the outer edge of the semiconductor substrate 10.

[0106] The trench bottom barrier region 75 is connected to the well region 11 at its end in the Y-axis direction. The depth of the bottom of the well region 11 may be deeper than the lower end of the trench bottom barrier region 75.

[0107] The trench bottom barrier region 75 is in contact with the base region 14 at its end in the Y-axis direction. The base region 14 is connected to the well region 11 at its end in the Y-axis direction.

[0108] Furthermore, an insulating film such as an interlayer insulating film and a gate insulating film is provided between the lower surface of the gate runner 48 and the well region 11, and the gate runner 48 and the well region 11 are not electrically connected.

[0109] 2D is a diagram showing a cross section taken along the line cc' in FIG. 2A. The cross section cc' is a cross section passing through the longitudinal direction (extension direction) of the gate trench portion 40 in the region where the trench bottom barrier region 75 of the transistor portion 70 is provided. YZ plane In FIG. 2D, elements other than the gate trench portion 40 are common to those in FIG. 2C.

[0110] The negative end of the gate trench portion 40 in the Y-axis direction is covered by the well region 11. Further, on the positive side of the well region 11 in the Y-axis direction, the bottom of the gate trench portion 40 is entirely covered by the trench bottom barrier region 75.

[0111] Figure 3A is an enlarged view showing an example of region B in Figure 1. Region B, like the region shown in Figure 2C, is a region that spans active region 160 and edge termination structure 190. Figure 3A will focus on the X-axis direction end region of active region 160.

[0112] The well region 11 extends around the periphery of the active region 160 and is provided in a ring shape in top view. In the semiconductor device 100 of this example, the transistor sections 70 and the diode sections 80 are arranged alternately in the X-axis direction, with the transistor section 70 being arranged on the outermost side in the X-axis direction (the end region on the positive or negative side). FIG. 3A shows the outermost transistor section 70-1 on the positive side in the X-axis direction. In top view, the transistor section 70-1 contacts the well region 11 at its end on the positive side in the X-axis direction and at both ends on the Y-axis direction.

[0113] In the transistor section 70-1, the emitter region 12 is not provided in the region on the well region 11 side. In the region of the transistor section 70-1 where the emitter region 12 is not provided, for example, from the end in the X-axis direction to the fifth gate trench portion 40, the contact region 15 is provided between the base regions 14 exposed on the front surface 21.

[0114] 3B is a diagram showing the dd' cross section in FIG. 3A. The dd' cross section is an XZ plane that passes through the emitter region 12, the contact region 15, and the well region 11 and crosses the gate trench portion 40 in the arrangement direction. In FIG. 3B, the description will focus on the outermost transistor portion 70-1 on the positive side in the X-axis direction.

[0115] In the transistor portion 70-1, in a region not adjacent to the well region 11, an emitter region 12 is provided above the base region 14 in contact with the front surface 21. However, from the end in the X-axis direction to the fifth gate trench portion 40, a contact region 15 is provided instead of the emitter region 12.

[0116] In this way, on the well region 11 side of the transistor section 70-1, the gate trench section 40 that is not in contact with the emitter region 12 is disabled (does not function as a transistor), so a gap is created between the active region of the transistor section 70 (the region that functions as a transistor) and the well region 11. Also, by disrupting the periodicity of the arrangement, electric field concentration at the end of the active region 160 can be alleviated, thereby improving safety. Furthermore, by providing the contact region 15 in the region where the emitter region 12 is not provided, excess holes can be swept out.

[0117] A trench bottom barrier region 75 may be provided above the drift region 18 on the well region 11 side of the transistor portion 70-1. When the trench bottom barrier region 75 is provided on the well region 11 side of the transistor portion 70-1, it may be formed by the same process as the process for providing the trench bottom barrier region 75 on the diode portion 80 side of the transistor portion 70-1 and in other transistor portions 70.

[0118] 4 is a graph showing the change in collector current Ic over time during reverse recovery. In the graph of Fig. 4, the solid line shows the behavior of collector current Ic in a semiconductor device without a trench bottom barrier region, and the dashed line shows the behavior of collector current Ic in semiconductor device 100 of this example with trench bottom barrier region 75.

[0119] At time t1, the transistor section is turned off and the diode section becomes conductive. An electron current flows from the cathode region to the base region, which acts as an anode layer, generating a reverse recovery current. When the electron current reaches the base region, conductivity modulation occurs, causing a hole current to flow from the anode layer. Furthermore, the electron current diffuses from the cathode region 82 to the base region 14 of the transistor section.

[0120] The electron current diffusing toward the transistor promotes hole injection from the contact region, which has a higher doping concentration than the base region, and increases the hole density in the semiconductor substrate, so it takes time for the holes to disappear when the diode is turned off. As a result, the reverse recovery peak current Irp increases and the reverse recovery loss also increases.

[0121] Here, in a semiconductor device without a trench bottom barrier region, the collector current Ic reaches the reverse recovery peak current Irp at time t2, then gradually decreases and becomes almost zero around time t3. If the reverse recovery peak current Irp is large, it takes a long time for the current to reach zero, which increases heat generation and reverse recovery loss.

[0122] On the other hand, the semiconductor device 100 of this example has a trench bottom barrier region 75 in a region of the transistor portion 70 adjacent to the diode portion 80. The trench bottom barrier region 75 is electrically connected to the emitter electrode 52, and therefore suppresses hole injection and blocks current.

[0123] The trench bottom barrier region 75 covers the bottom of the gate trench portion 40, thereby suppressing hole injection from the transistor portion 70 to the diode portion 80. As described above, in the semiconductor device 100 of this example, the reverse recovery peak current Irp is smaller and the time until the current reaches zero is shorter than in a semiconductor device that does not have a trench bottom barrier region, thereby reducing reverse recovery loss.

[0124] One known technique for suppressing hole injection is to provide a lifetime control region containing a lifetime killer from the diode section to part of the transistor section. The lifetime control region promotes hole annihilation at turn-off and reduces reverse recovery loss.

[0125] Generally, the lifetime control region provided in the transistor section needs to have a width of about 100 to 150 μm from the boundary on the diode section side in order to eliminate holes injected at turn-off. However, in the transistor section, the region where the lifetime control region is provided becomes an ineffective region that does not function as a transistor.

[0126] In contrast, the trench bottom barrier region 75 of this embodiment cuts off current and suppresses hole injection, so it can be narrower than the lifetime control region. In this way, the trench bottom barrier region 75 reduces the ineffective region compared to when a lifetime control region is provided in the transistor section 70, thereby improving device characteristics and suppressing heat generation.

[0127] Fig. 5A is an enlarged view showing another example of region A in Fig. 1. Fig. 5B is a view showing the a-a' cross section in Fig. 5A. Note that the b-b' and c-c' cross sections in Fig. 5A may be similar to those shown in Fig. 2C and Fig. 2D, respectively, and therefore description thereof will be omitted here.

[0128] In this example, in the region of the transistor section 70 where the trench bottom barrier region 75 is provided, contact holes 54 are provided only above some of the mesa portions 60, and no contact holes 54 are provided above the other mesa portions 60. In this respect, Figures 5A and 5B differ from Figures 2A and 2B, in which contact holes 54 are provided above each mesa portion. As shown in Figures 5A and 5B, only one contact hole 54 may be provided above the trench bottom barrier region 75.

[0129] In other words, in this example, of the multiple mesa portions 60 located above the trench bottom barrier region 75, only some of the mesa portions 60 are electrically connected to the emitter electrode 52 via the contact holes 54, and the other mesa portions 60 are covered with the interlayer insulating film 38.

[0130] In this way, only a portion of the multiple mesa portions 60 located above the trench bottom barrier region 75 is electrically connected to the emitter electrode 52, thereby providing a hole extraction effect, which promotes hole annihilation at turn-off and reduces reverse recovery loss.

[0131] Fig. 6A is an enlarged view showing another example of region A in Fig. 1. The semiconductor device 100 of this example has a floating barrier region 77 in the transistor section 70. Here, a description of elements common to Fig. 2A will be omitted.

[0132] The floating barrier region 77 is an electrically floating region of the second conductivity type provided between the drift region 18 and the base region 14. In Fig. 6A, the range of the floating barrier region 77 is indicated by a dotted line.

[0133] Being electrically floating means that it is not electrically connected to a predetermined potential like the emitter electrode 52. The floating barrier region 77 is separated from the trench bottom barrier region 75 and the well region 11 in a top view of the semiconductor substrate 10. The trench bottom barrier region 75 and the well region 11 are electrically connected to the emitter electrode 52.

[0134] The floating barrier region 77 in this example is P-type. The doping concentration of the floating barrier region 77 is higher than the doping concentration of the base region 14. The doping concentration of the floating barrier region 77 may be the same as the doping concentration of the trench bottom barrier region 75. The floating barrier region 77 may be formed by the same process as the process for providing the trench bottom barrier region 75.

[0135] When the transistor section 70 is turned on, the change in voltage over time dV / dt in the diode section 80 depends on the gate resistance Rg of the transistor section 70. In this example, by providing a floating barrier region 77 in the transistor section, the dependency of dV / dt on the gate resistance Rg is reduced, that is, driving with a small gate resistance Rg is possible. A smaller gate resistance Rg reduces power consumption during turn-on.

[0136] Fig. 6B is a diagram showing the e-e' cross section in Fig. 6A. In the transistor section 70, a trench bottom barrier region 75 is provided in a region adjacent to the diode section 80, and a floating barrier region 77 is further provided spaced apart from the trench bottom barrier region 75.

[0137] In the X-axis direction, the distance D1 between the trench bottom barrier region 75 and the floating barrier region 77 may be equal to or greater than the pitch of the gate trench portions 40 and may be equal to or less than 10 μm. Here, the pitch of the gate trench portions 40 refers to the distance between the gate trench portions 40. The pitch of the gate trench portions 40 is, for example, 2.3 μm.

[0138] In the depth direction of the semiconductor substrate 10, the floating barrier region 77 is provided below the accumulation region 16. The lower end of the floating barrier region 77 is located below the bottom of the gate trench portion 40. In other words, the floating barrier region 77 covers the bottom of the gate trench portion 40, similar to the trench bottom barrier region 75. The depth position of the floating barrier region 77 may be the same as the depth position of the trench bottom barrier region 75.

[0139] 6C is a diagram showing the f-f' cross section in FIG. 6A. The floating barrier region 77 is spaced apart from the well region 11. The depth of the bottom of the well region 11 may be deeper than the lower end of the floating barrier region 77. In the Y-axis direction, the distance D2 between the well region 11 and the floating barrier region 77 may be equal to or greater than the pitch of the gate trench portion 40 and equal to or less than 10 μm.

[0140] In this way, the floating barrier region 77 in this example is spaced apart while ensuring a sufficient area so that the emitter potential is not affected by the trench bottom barrier region 75 and the well region 11. As a result, the floating barrier region 77 reduces the dependency of dV / dt on the gate resistance Rg in the diode section 80, enabling driving with a small gate resistance Rg, thereby improving the turn-on characteristics.

[0141] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0142] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0143] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 17 plug region, 18 drift region, 20 buffer region, 21 front surface, 22 collector region, 23 back surface, 24 collector electrode, 25 connection portion, 29 straight portion, 30 dummy trench portion, 31 tip portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 39 straight portion, 40 gate trench portion, 41 tip portion, 42 gate insulating film, 4 4. Gate conductive portion, 48. Gate runner, 49. Contact hole, 50. Gate metal layer, 52. Emitter electrode, 54. Contact hole, 56. Contact hole, 60. Mesa portion, 61. Mesa portion, 70. Transistor portion, 75. Trench bottom barrier region, 77. Floating barrier region, 80. Diode portion, 82. Cathode region, 92. Guard ring, 94. Field plate, 96. Channel stopper, 100. Semiconductor device, 102. Edge, 160. Active region, 190. Edge termination structure portion

Claims

1. A semiconductor device including a semiconductor substrate provided with one or more transistor portions having a P-type base region on the front surface side, and a P-type well region located outside the transistor portion, One of the transistor units includes: a plurality of trench portions extending in a first direction and arranged in a stripe pattern in a second direction; a P-type first bottom region and a P-type second bottom region covering from a bottom of one of the trench portions to a bottom of the other of the trench portions in the second direction; an N-type third bottom region disposed between the first bottom region and the second bottom region in the second direction; an N-type high concentration region having a doping concentration higher than that of the third bottom region, the N-type high concentration region being provided above the base region and overlapping with the first bottom region or the second bottom region in a top view of the semiconductor substrate; and The first bottom region and the second bottom region are electrically isolated from each other. Semiconductor device.

2. The third bottom region is a drift region. The width of the third bottom region between the first bottom region and the second bottom region is equal to or greater than the pitch of the trench portions and is equal to or less than 10 μm. The semiconductor device according to claim 1 .

3. One of the transistor portions has an N-type accumulation region between the base region and the first bottom region or the second bottom region, the N-type accumulation region having a doping concentration higher than that of the drift region. The semiconductor device according to claim 2 .

4. The first bottom region is connected to the well region. The semiconductor device according to claim 1 .

5. The second bottom region is an electrically floating region. The semiconductor device according to claim 1 .

6. The high concentration region is provided so as to overlap the first bottom region, the second bottom region, and the third bottom region when viewed from above the semiconductor substrate. The semiconductor device according to claim 1 .

7. The well region is in contact with the third bottom region of the transistor portion in the second direction. The semiconductor device according to claim 1 .

8. The third bottom region has a longitudinal direction in the first direction. The semiconductor device according to claim 1 .

9. A semiconductor device including a semiconductor substrate provided with one or more transistor portions having a P-type base region on the front surface side, and a P-type well region located outside the transistor portion, One of the transistor units includes: a plurality of trench portions extending in a first direction and arranged in a stripe pattern in a second direction; a P-type first bottom region and a P-type second bottom region covering from a bottom of one of the trench portions to a bottom of the other of the trench portions in the second direction; and The first bottom region is a region connected to the well region, and the second bottom region is an electrically floating region.

10. The depth of the bottom of the well region is deeper than the lower ends of the first bottom region and the second bottom region. The semiconductor device according to claim 1 .

11. The first bottom region and the second bottom region have a doping concentration higher than that of the base region. The semiconductor device according to claim 1 .

12. The semiconductor substrate is provided with one or more diode portions having a P-type anode region on the front surface side. The semiconductor device according to claim 1 .

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