Driver Circuit

Abstract

This driver circuit comprises: a differential output circuit (1); a capacitor (C1) that is inserted between the output terminal of the positive phase side of the differential output circuit (1) and the output terminal of the positive phase side of the driver circuit; a capacitor (C2) that is inserted between the output terminal of the negative phase side of the differential output circuit (1) and the output terminal of the negative phase side of the driver circuit; and an offset circuit (2) that applies offset voltages to output signals (Voutp, Voutn) of the driver circuit in such a manner that the difference between the midpoint of the output signal (Voutp) of the positive phase side of the driver circuit and the midpoint of the output signal (Voutn) of the negative phase side thereof is equivalent to or greater than the amplitudes of the output signals (Vp, Vn) of the differential output circuit (1).

Description

[Technical Field]

[0001] The present invention relates to a driver circuit for driving a load circuit such as an optical modulator. [Background technology]

[0002] As wired communication speeds increase, driver circuits, which are the output stage of transmitters, are required to output wideband, high-speed signals. To reduce the size of transmitters, driver circuits made up of semiconductor transistors are used. However, circuits using semiconductor transistors cannot output amplitudes greater than the operating voltage of the circuit. Furthermore, to achieve broadband, it is desirable to use semiconductor transistors with a high current gain cutoff frequency ft, but there is a trade-off between the current gain cutoff frequency ft and the operating voltage (see Non-Patent Document 1). For this reason, widening the bandwidth of a driver circuit leads to the problem of lower output voltage amplitude. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Akira Matsuzawa, "CMOS Devices and RF Fundamental Circuits", ISSCC Dig. Tech. Papers, p.104, 2001,<https: / / www.apmc-mwe.org / mwe2005 / src / TL / TL02-01.pdf> Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made to solve the above-mentioned problems, and has an object to provide a wideband driver circuit that can obtain an output voltage amplitude higher than the power supply voltage of a differential output circuit. [Means for solving the problem]

[0005] The driver circuit of the present invention comprises a differential output circuit of a differential input / differential output type constituted by transistors, a first capacitor inserted between a positive phase output terminal of the differential output circuit and a positive phase output terminal of a driver circuit, a second capacitor inserted between a negative phase output terminal of the differential output circuit and a negative phase output terminal of the driver circuit, and an offset circuit configured to apply offset voltages to the positive phase output signal and the negative phase output signal of the driver circuit, respectively, so that the difference between the midpoint of the positive phase output signal of the driver circuit and the midpoint of the negative phase output signal is equal to or greater than the amplitude of the output signal of the differential output circuit. The offset circuit includes a first voltage generating unit configured to generate a first voltage, a second voltage generating unit configured to generate a second voltage lower than the first voltage, a first unity gain buffer configured to fix a midpoint of an output signal on a positive phase side of the driver circuit to the first voltage, and a second unity gain buffer configured to fix a midpoint of an output signal on a negative phase side of the driver circuit to the second voltage, and a difference between the first voltage and the second voltage is equal to or greater than the amplitude of the output signal of the differential output circuit. It is characterized by the following.

[0006] Also In one configuration example of the driver circuit of the present invention, the first unity gain buffer comprises a first operational amplifier to which the first voltage is input at its inverting input terminal, a PMOS transistor having a gate terminal connected to the output terminal of the first operational amplifier, a source terminal to which a power supply voltage is applied, and a drain terminal connected to the positive phase output terminal of the offset circuit, a first low-pass filter having an input terminal connected to the drain terminal of the PMOS transistor and an output terminal connected to the non-inverting input terminal of the first operational amplifier, and a first resistor having one end connected to the drain terminal of the PMOS transistor and the other end connected to ground. The second unity gain buffer is characterized by comprising: a second operational amplifier having an inverting input terminal to which the second voltage is input; an NMOS transistor having a gate terminal connected to the output terminal of the second operational amplifier, a source terminal connected to ground, and a drain terminal connected to the opposite phase output terminal of the offset circuit; a second low-pass filter having an input terminal connected to the drain terminal of the NMOS transistor and an output terminal connected to the non-inverting input terminal of the second operational amplifier; and a second resistor having one end connected to the drain terminal of the NMOS transistor and the other end to which the power supply voltage is applied.

[0007] The driver circuit of the present invention a differential input / output type differential output circuit formed by transistors; a first capacitor inserted between a positive phase output terminal of the differential output circuit and a positive phase output terminal of a driver circuit; a second capacitor inserted between a negative phase output terminal of the differential output circuit and a negative phase output terminal of the driver circuit; and an offset circuit configured to apply offset voltages to the positive phase output signal and the negative phase output signal of the driver circuit, respectively, so that the difference between the midpoint of the positive phase output signal of the driver circuit and the midpoint of the negative phase output signal is equal to or greater than the amplitude of the output signal of the differential output circuit;The offset circuit is characterized by comprising: a first low-pass filter that receives as its input the output signal of the positive phase side of the differential output circuit; a second low-pass filter that receives as its input the output signal of the negative phase side of the differential output circuit; a replica circuit configured to output a signal that is the same as the output signal of the differential output circuit when no signal is input; a first differential circuit configured to output the difference between the output signal of the first low-pass filter and the output signal of the positive phase side of the replica circuit; a second differential circuit configured to output the difference between the output signal of the second low-pass filter and the output signal of the negative phase side of the replica circuit; a first bias adding circuit configured to superimpose the output signal of the first differential circuit on the output signal of the positive phase side of a driver circuit; and a second bias adding circuit configured to superimpose the output signal of the second differential circuit on the output signal of the negative phase side of the driver circuit. In one configuration example of the driver circuit of the present invention, the time constant of the high-pass filter formed by the first capacitance and the output resistance of the first bias adding circuit is the same as the time constant of the first low-pass filter, and the time constant of the high-pass filter formed by the second capacitance and the output resistance of the second bias adding circuit is the same as the time constant of the second low-pass filter. [Effects of the Invention]

[0008] According to the present invention, by providing offset circuits that apply offset voltages to the positive phase output signal and the negative phase output signal of the driver circuit so that the difference between the midpoint of the positive phase output signal and the midpoint of the negative phase output signal of the driver circuit is equal to or greater than the amplitude of the output signal of the differential output circuit, it is possible to realize a wideband driver circuit that can obtain an output voltage amplitude higher than the power supply voltage of the differential output circuit. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing the configuration of a driver circuit according to a first embodiment of the present invention. [Figure 2]FIG. 2 is a diagram showing an example of connection between a driver circuit and a load circuit according to the first embodiment of the present invention. [Figure 3] FIG. 3 is a block diagram showing the configuration of a bias circuit according to a first embodiment of the present invention. [Figure 4] FIG. 4 is a diagram showing waveforms of a differential signal input to a differential output circuit according to the first embodiment of the present invention, a waveform of a differential signal output from the differential output circuit, and a waveform of a differential signal output from a driver circuit. [Figure 5] FIG. 5 is a block diagram showing the configuration of a driver circuit according to a second embodiment of the present invention. [Figure 6] FIG. 6 is a block diagram showing the configuration of an offset circuit according to a second embodiment of the present invention. [Figure 7] FIG. 7 is a waveform diagram illustrating the operation of the offset circuit according to the second embodiment of the present invention. [Figure 8] FIG. 8 is a waveform diagram illustrating the operation of the offset circuit according to the second embodiment of the present invention. [Figure 9] FIG. 9 is a diagram showing waveforms of a differential signal input to a differential output circuit according to a second embodiment of the present invention, a waveform of a differential signal output from the differential output circuit, and a waveform of a differential signal output from a driver circuit. DETAILED DESCRIPTION OF THE INVENTION

[0010] [First Example] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 is a block diagram showing the configuration of a driver circuit according to a first embodiment of the present invention. The driver circuit is composed of a differential input / differential output type differential output circuit 1 that amplifies differential signals Vinp and Vinn, a capacitor C1 inserted between the positive phase output terminal of the differential output circuit 1 and the positive phase output terminal of the driver circuit, a capacitor C2 inserted between the negative phase output terminal of the differential output circuit 1 and the negative phase output terminal of the driver circuit, and an offset circuit 2 that applies an offset voltage to the output signals Voutp and Voutn of the driver circuit so that the difference between the midpoint of the positive phase output signal Voutp and the midpoint of the negative phase output signal Voutn of the driver circuit is equal to or greater than the amplitude of the output signals Vp and Vn of the differential output circuit 1.

[0011] As shown in Figure 2, a load circuit 3 is connected to the differential output terminals of the driver circuit. The differential output circuit 1 amplifies the input differential signals Vinp and Vinn to a level that can drive the load circuit 3. In the case of optical communications, a Mach-Zehnder optical modulator or an electro-absorption optical modulator is used as the load circuit 3.

[0012] The differential output circuit 1 may be configured in any manner as long as it is a differential input / differential output type that operates upon receiving a supply of power supply voltage Vhf. An example of the differential output circuit 1 is a differential amplifier circuit. It may also be configured with a plurality of amplifier circuits connected in cascade. It may also be configured with a variable gain amplifier circuit included in the configuration of a plurality of amplifier circuits connected in cascade.

[0013] The offset circuit 2 is composed of a bias circuit 20 that outputs an offset voltage, a resistor R1 inserted between the positive-phase output terminal of the bias circuit 20 and the positive-phase output terminal of the driver circuit, and a resistor R2 inserted between the negative-phase output terminal of the bias circuit 20 and the negative-phase output terminal of the driver circuit. The resistors R1 and R2 have the same value. However, as will be described later, the values ​​of the resistors R1 and R2 may be zero.

[0014] The positive output terminal of the offset circuit 2 is connected to the positive output terminal of the differential output circuit 1 via the capacitor C1. The negative output terminal of the offset circuit 2 is connected to the negative output terminal of the differential output circuit 1 via the capacitor C2. The values of the capacitors C1 and C2 are the same.

[0015] Fig. 3 shows a configuration example of the bias circuit 20. The bias circuit 20 includes a voltage generation unit 21 that generates a voltage V1 from a power supply voltage Vlf (Vlf > Vhf), a unity-gain buffer 22 that fixes the midpoint of the positive output signal Vbp of the bias circuit 20 to the voltage V1, a voltage generation unit 23 that generates a voltage V2 (V2 < V1) from the power supply voltage Vlf, and a unity-gain buffer 24 that fixes the midpoint of the negative output signal Vbn of the bias circuit 20 to the voltage V2.

[0016] The unity-gain buffer 22 includes an operational amplifier 25 to which the voltage V1 is input to the inverting input terminal, a pmos transistor Q1 whose gate terminal is connected to the output terminal of the operational amplifier 25, whose source terminal is applied with the power supply voltage Vlf, and whose drain terminal is connected to the positive output terminal of the bias circuit 20, a low-pass filter (LPF) 26 whose input terminal is connected to the drain terminal of the transistor Q1 and whose output terminal is connected to the non-inverting input terminal of the operational amplifier 25, and a resistor R3 whose one end is connected to the drain terminal of the transistor Q1 and whose other end is connected to the ground.

[0017] The LPF 26 outputs the average voltage of the positive output signal Vbp of the bias circuit 20. The operational amplifier 25 compares the output of the LPF 26 with the voltage V1. By controlling the transistor Q1 by the output of the operational amplifier 25, the positive output of the bias circuit 20 is controlled so that the average of the output signal Vbp becomes V1.

[0018] The unity gain buffer 24 is composed of an operational amplifier 27 having an inverting input terminal to which a voltage V2 is input, an nmos transistor Q2 having a gate terminal connected to the output terminal of the operational amplifier 27, a source terminal connected to ground, and a drain terminal connected to the negative-phase output terminal of the bias circuit 20, an LPF 28 having an input terminal connected to the drain terminal of the transistor Q2 and an output terminal connected to the non-inverting input terminal of the operational amplifier 27, and a resistor R4 having one end connected to the drain terminal of the transistor Q2 and the other end to which a power supply voltage Vlf is applied.

[0019] LPF 28 outputs the average voltage of the negative-phase output signal Vbn of bias circuit 20. Operational amplifier 27 compares the output of LPF 28 with voltage V2. By controlling transistor Q2 using the output of operational amplifier 27, the negative-phase output of bias circuit 20 is controlled so that the average of output signal Vbn becomes V2. Resistors R3 and R4 have the same value. Furthermore, the time constant of LPF 26 and the time constant of LPF 28 are the same.

[0020] In this embodiment, the average of the positive-phase output signal of the bias circuit 20 is fixed to V1, and the average of the negative-phase output signal Vbn is fixed to V2. Therefore, if the load circuit 3 is an electro-absorption optical modulator, fluctuations in the offset V1-V2 between the positive and negative phase sides due to the photocurrent generated by the optical modulator can be suppressed.

[0021] When using the configuration of this embodiment, the values ​​of resistors R1 and R2 may be zero. In this case, the positive phase output terminal of bias circuit 20 is connected to the positive phase output terminal of the driver circuit, and the negative phase output terminal of bias circuit 20 is connected to the negative phase output terminal of the driver circuit.

[0022] Figure 4 shows the waveforms of the differential signals Vinp and Vinn input to the differential output circuit 1, the waveforms of the differential signals Vp and Vn output from the differential output circuit 1, and the waveforms of the differential signals Voutp and Voutn output from the driver circuit. As shown in (a) of Figure 4, the differential signals Vinp and Vinn are input to the differential output circuit 1, and as shown in (b) and (c) of Figure 4, the differential output circuit 1 outputs differential signals Vp and Vn with an amplitude Vpp / 2 lower than the power supply voltage Vhf.

[0023] When no high-frequency signal is input to the differential output circuit 1, the voltage of the positive-phase output Voutp of the driver circuit is biased to V1, and the voltage of the negative-phase output Voutn is biased to V2, as shown in Figure 4(d). When a high-frequency signal is input to the differential output circuit 1, after a transient state, the positive-phase output signal Voutp of the driver circuit varies around V1, and the negative-phase output signal Voutn varies around V2. In other words, the midpoint of the positive-phase output signal Voutp of the driver circuit is V1, and the midpoint of the negative-phase output signal Voutn is V2.

[0024] A voltage equal to the difference between the driver circuit's positive-phase output signal Voutp and negative-phase output signal Voutn is applied to the load circuit 3. If the difference between voltages V1 and V2 is Vpp / 2, a voltage of up to Vpp is applied. In other words, a high-frequency signal with an amplitude of Vpp is applied to the load circuit 3. Because the power supply voltage of the differential output circuit 1 can be set to Vhf, which is lower than Vpp, it is possible to configure the differential output circuit 1 using transistors with a high current gain cutoff frequency ft.

[0025] As described above, in this embodiment, a wideband driver circuit that can obtain an output voltage amplitude higher than the power supply voltage Vhf of the differential output circuit 1 can be realized. In the above explanation, the difference between the voltages V1 and V2 is Vpp / 2, but if it is desired to apply a bias voltage of zero or more to the load circuit 3, the difference between the voltages V1 and V2 may be greater than Vpp / 2.

[0026] [Second Example] Next, a second embodiment of the present invention will be described. Fig. 5 is a block diagram showing the configuration of a driver circuit according to the second embodiment of the present invention. The driver circuit of this embodiment is composed of a differential output circuit 1, capacitors C1 and C2, and an offset circuit 4 that applies an offset voltage to the output signal of the driver circuit and suppresses changes in the output signal of the driver circuit due to transient changes in the DC component of the AC signal output from the differential output circuit 1. As in the first embodiment, a load circuit is connected to the differential output terminals of the driver circuit.

[0027] 6 shows an example configuration of the offset circuit 4. The offset circuit 4 is composed of an LPF 40 that receives as its input an output signal Vp on the positive phase side of the differential output circuit 1, an LPF 41 that receives as its input an output signal Vn on the negative phase side of the differential output circuit 1, a replica circuit 42 that outputs signals identical to the output signals Vp, Vn of the differential output circuit 1 when no high-frequency signal is input, a differential circuit 43 that outputs the difference between an output signal VLPFp of the LPF 40 and an output signal Vp' on the positive phase side of the replica circuit 42, a differential circuit 44 that outputs the difference between an output signal VLPFn of the LPF 41 and an output signal Vn' on the negative phase side of the replica circuit 42, a bias addition circuit 45 that superimposes the output signal of the differential circuit 43 on an output signal Voutp on the positive phase side of the driver circuit, and a bias addition circuit 46 that superimposes the output signal of the differential circuit 44 on an output signal Voutn on the negative phase side of the driver circuit.

[0028] The operation of the offset circuit 4 will be described with reference to Figures 7 and 8. The replica circuit 42 outputs voltages Vp' and Vn' that are the same as the output signals Vp and Vn of the differential output circuit 1 when no signal is present (Figures 7 and 8(b)). When a high-frequency signal is input to the differential output circuit 1, the output VLPFp of the LPF 40 changes toward the midpoint of the output signal Vp on the positive phase side of the differential output circuit 1, with transient response characteristics determined by the time constant of the LPF 40, as shown in Figure 7(b). Similarly, the output VLPFn of the LPF 41 changes toward the midpoint of the output signal Vn on the negative phase side of the differential output circuit 1, with transient response characteristics determined by the time constant of the LPF 41, as shown in Figure 8(b).

[0029] A high-pass filter is formed by the capacitance C1 and the output resistance of the bias adding circuit 45, and similarly, a high-pass filter is formed by the capacitance C2 and the output resistance of the bias adding circuit 46. For this reason, when there is no processing by the offset circuit 4, the midpoints of the output signals Voutp and Voutn of the driver circuit asymptotically approach the bias voltages (Vp', Vn') when there is no signal, due to the transient response characteristics determined by the time constant of the high-pass filter.

[0030] The differential circuit 43 outputs a difference Dp between the output signal VLPFp of the LPF 40 and the output signal Vp' on the positive phase side of the replica circuit 42. The signal Dp represents the fluctuation component at the midpoint of the output signal Vp on the positive phase side of the differential output circuit 1, as shown in (c) of FIG. 7. Similarly, the differential circuit 44 outputs a difference Dn between the output signal VLPFn of the LPF 41 and the output signal Vn' on the negative phase side of the replica circuit 42. The signal Dn represents the fluctuation component at the midpoint of the output signal Vn on the negative phase side of the differential output circuit 1, as shown in (c) of FIG.

[0031] The bias adding circuit 45 superimposes the output voltage Dp of the differential circuit 43 on the positive-phase output signal Voutp of the driver circuit. The bias adding circuit 46 superimposes the output voltage Dn of the differential circuit 44 on the negative-phase output signal Voutn of the driver circuit. This makes it possible to suppress fluctuations in the midpoints of the output signals Voutp and Voutn of the driver circuit when high-frequency signals Vinp and Vinn are input, as shown in (d) of FIG. 7 and (d) of FIG. 8. Voutp' in (d) of FIG. 7 and Voutn' in (d) of FIG. 8 show the output signals Voutp and Voutn when voltage fluctuations are not suppressed by the offset circuit 4.

[0032] The time constant of the high-pass filter formed by the capacitor C1 and the output resistance of the bias adding circuit 45 is set to be the same as the time constant of the LPF 40, and the time constant of the high-pass filter formed by the capacitor C2 and the output resistance of the bias adding circuit 46 is set to be the same as the time constant of the LPF 41. This makes it possible to suppress fluctuations in the midpoint of the output signals Voutp, Voutn of the driver circuit even during the time it takes for the outputs VLPFp, VLPFn of the LPFs 40, 41 to stabilize at the midpoint of the output signals Vp, Vn of the differential output circuit 1.

[0033] 9 shows the waveforms of the differential signals Vinp and Vinn input to the differential output circuit 1, the waveforms of the differential signals Vp and Vn output from the differential output circuit 1, and the waveforms of the differential signals Voutp and Voutn output from the driver circuit. As shown in (a) of Fig. 9, the differential signals Vinp and Vinn are input to the differential output circuit 1, and as shown in (b) and (c) of Fig. 9, the differential output circuit 1 outputs differential signals Vp and Vn with an amplitude Vpp / 2 lower than the power supply voltage Vhf.

[0034] A high-frequency signal is applied to the load circuit via capacitors C1 and C2, but due to the operation of the offset circuit 4 described above, the high-frequency signal does not undergo transient fluctuations and is applied with a constant amplitude. A voltage equal to the difference between the positive-phase output signal Voutp and the negative-phase output signal Voutn of the driver circuit is applied to the load circuit. Therefore, a high-frequency signal with an amplitude Vpp is applied to the load circuit. The difference between the midpoint of the positive-phase output signal Voutp and the midpoint of the negative-phase output signal Voutn is Vpp / 2.

[0035] As in the first embodiment, the power supply voltage of the differential output circuit 1 can be set to Vhf, which is lower than Vpp, so that the differential output circuit 1 can be configured using transistors with a high current gain cutoff frequency ft. In this way, in this embodiment, a wideband driver circuit can be realized that can obtain an output voltage amplitude higher than the power supply voltage Vhf of the differential output circuit 1. [Industrial Applicability]

[0036] The present invention can be applied to a driver circuit. [Explanation of symbols]

[0037] 1...differential output circuit, 2,4...offset circuit, 3...load circuit, 20...bias circuit, 21,23...voltage generation section, 22,24...unity gain buffer, 25,27...operational amplifier, 26,28,40,41...low-pass filter, 42...replica circuit, 43,44...differential circuit, 45,46...bias addition circuit, Q1...pmos transistor, Q2...nmos transistor, C1,C2...capacitance, R1 to R4...resistor.

Claims

1. a differential input / differential output type differential output circuit configured by transistors; a first capacitor inserted between a positive phase output terminal of the differential output circuit and a positive phase output terminal of a driver circuit; a second capacitor inserted between the output terminal on the reverse phase side of the differential output circuit and the output terminal on the reverse phase side of the driver circuit; an offset circuit configured to apply offset voltages to the positive-phase output signal and the negative-phase output signal of the driver circuit so that the difference between the midpoint of the positive-phase output signal and the midpoint of the negative-phase output signal of the driver circuit is equal to or greater than the amplitude of the output signal of the differential output circuit; The offset circuit a first voltage generator configured to generate a first voltage; a second voltage generator configured to generate a second voltage lower than the first voltage; a first unity gain buffer configured to fix a midpoint of an output signal on a positive phase side of the driver circuit to the first voltage; a second unity gain buffer configured to fix a midpoint of an output signal on the negative phase side of the driver circuit to the second voltage; A driver circuit, wherein the difference between the first voltage and the second voltage is equal to or greater than the amplitude of the output signal of the differential output circuit.

2. 2. The driver circuit of claim 1, The first unity gain buffer comprises: a first operational amplifier having an inverting input terminal to which the first voltage is input; a PMOS transistor having a gate terminal connected to the output terminal of the first operational amplifier, a source terminal to which a power supply voltage is applied, and a drain terminal connected to the positive phase output terminal of the offset circuit; a first low-pass filter having an input terminal connected to the drain terminal of the PMOS transistor and an output terminal connected to the non-inverting input terminal of the first operational amplifier; a first resistor having one end connected to the drain terminal of the PMOS transistor and the other end connected to ground; The second unity gain buffer comprises: a second operational amplifier having an inverting input terminal to which the second voltage is input; an nmos transistor having a gate terminal connected to the output terminal of the second operational amplifier, a source terminal connected to ground, and a drain terminal connected to the negative-phase output terminal of the offset circuit; a second low-pass filter having an input terminal connected to the drain terminal of the nmos transistor and an output terminal connected to the non-inverting input terminal of the second operational amplifier; a second resistor having one end connected to the drain terminal of the nmos transistor and the other end to which the power supply voltage is applied.

3. A differential input / differential output type differential output circuit configured with transistors; a first capacitor inserted between a positive phase output terminal of the differential output circuit and a positive phase output terminal of a driver circuit; a second capacitor inserted between the output terminal on the reverse phase side of the differential output circuit and the output terminal on the reverse phase side of the driver circuit; an offset circuit configured to apply offset voltages to the positive-phase output signal and the negative-phase output signal of the driver circuit so that the difference between the midpoint of the positive-phase output signal and the midpoint of the negative-phase output signal of the driver circuit is equal to or greater than the amplitude of the output signal of the differential output circuit; The offset circuit a first low-pass filter to which the output signal on the positive phase side of the differential output circuit is input; a second low-pass filter to which the output signal from the opposite phase side of the differential output circuit is input; a replica circuit configured to output a signal identical to the output signal of the differential output circuit when no signal is input; a first differential circuit configured to output a difference between an output signal of the first low-pass filter and an output signal of a positive phase side of the replica circuit; a second differential circuit configured to output a difference between an output signal of the second low-pass filter and an output signal of the opposite phase side of the replica circuit; a first bias adding circuit configured to superimpose an output signal of the first differential circuit on an output signal of a positive phase side of a driver circuit; a second bias adding circuit configured to superimpose the output signal of the second differential circuit on the output signal of the reverse phase side of the driver circuit.

4. 4. The driver circuit of claim 3, a time constant of a high-pass filter formed by the first capacitor and the output resistance of the first bias adding circuit is equal to a time constant of the first low-pass filter; a high-pass filter formed by the second capacitor and the output resistance of the second bias adding circuit and a time constant of the second low-pass filter that is the same as the time constant of the second low-pass filter;

Images