High electron mobility transistor and method for manufacturing the same

Abstract

To provide a high electron mobility transistor and a manufacturing method for the same.SOLUTION: A high electron mobility transistor includes a gate electrode provided on a depletion forming layer. The gate electrode includes a first gate electrode provided so as to form ohmic contact with the depletion forming layer, and a second gate electrode provided so as to form Schottky contact with the depletion forming layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to high electron mobility transistors and methods for fabricating same. [Background technology]

[0002] Various power conversion systems require power devices, which control the flow of current through on / off switching. The efficiency of the power devices in a power conversion system determines the efficiency of the entire system.

[0003] It is difficult to improve the efficiency of silicon-based power devices due to limitations in the physical properties of silicon and limitations in the manufacturing process. To overcome these limitations, research and development is underway to improve the conversion efficiency by applying III-V compound semiconductors such as GaN to power devices. In recent years, research has been conducted on high electron mobility transistors (HEMTs) that utilize heterojunction structures of compound semiconductors. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE INVENTION Exemplary embodiments provide high electron mobility transistors and methods for fabricating same. [Means for solving the problem]

[0005] In one aspect, a channel layer comprising a first semiconductor material; a channel supply layer including a second semiconductor material and inducing a two-dimensional electron gas (2DEG) in the channel layer; a source electrode and a drain electrode provided on both sides of the channel supply layer; at least one depletion forming layer provided on the channel supply layer and forming a depletion region in the two-dimensional electron gas; a gate electrode provided on the at least one depletion forming layer, The gate electrode includes at least one first gate electrode provided to form an ohmic contact with the at least one depletion forming layer; A high electron mobility transistor is provided, including at least one second gate electrode configured to form a Schottky contact with the at least one depletion-forming layer.

[0006] The at least one depletion forming layer may include a depletion forming layer extending in a direction parallel to the source electrode and the drain electrode.

[0007] At least one protrusion may be formed in a middle portion of the depletion forming layer along a direction parallel to the source electrode and the drain electrode.

[0008] The at least one first gate electrode may include a first gate electrode extending in a direction parallel to the source electrode and the drain electrode at an intermediate portion of an upper surface of the depletion forming layer.

[0009] The at least one second gate electrode may include a second gate electrode provided on an upper surface of the depletion forming layer so as to cover the first gate electrode.

[0010] The at least one second gate electrode may include a plurality of second gate electrodes spaced apart from each other and provided on an upper surface of the depletion forming layer so as to cover a portion of the first gate electrode.

[0011] The at least one first gate electrode may include a plurality of first gate electrodes spaced apart from each other in a direction parallel to the source electrode and the drain electrode at an intermediate portion of an upper surface of the depletion forming layer.

[0012] The at least one depletion forming layer may include a plurality of depletion forming layers spaced apart in a direction parallel to the source electrode and the drain electrode.

[0013] A protrusion may be provided in an intermediate portion of each of the depletion forming layers along a direction parallel to the source electrode and the drain electrode.

[0014] In another aspect, forming a channel layer and a channel supply layer; forming at least one depletion forming layer on the channel supply layer; forming at least one first gate electrode forming an ohmic contact on the at least one depletion forming layer; forming at least one second gate electrode forming a Schottky contact on the at least one depletion-forming layer and the at least one first gate electrode. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a plan view illustrating a high electron mobility transistor according to an example embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA' in FIG. [Figure 3A] 2 is a diagram showing the flow of gate leakage current according to a turn-on voltage applied to a gate electrode in the high electron mobility transistor shown in FIG. 1; [Figure 3B] 2 is a diagram showing the flow of gate leakage current according to a turn-on voltage applied to a gate electrode in the high electron mobility transistor shown in FIG. 1; [Figure 4] 2 shows simulation results showing gate leakage current depending on the area of ​​the Schottky contact in the high electron mobility transistor shown in FIG. 1. [Figure 5] 2 is a diagram for explaining a method for manufacturing the high electron mobility transistor shown in FIG. [Figure 6] 2 is a diagram for explaining a method for manufacturing the high electron mobility transistor shown in FIG. [Figure 7]2 is a diagram for explaining a method for manufacturing the high electron mobility transistor shown in FIG. [Figure 8] 2 is a diagram for explaining a method for manufacturing the high electron mobility transistor shown in FIG. [Figure 9] 1 is a diagram illustrating a high electron mobility transistor according to another exemplary embodiment; [Figure 10] FIG. 10 is a plan view illustrating a high electron mobility transistor according to yet another illustrative embodiment. [Figure 11] FIG. 11 is a cross-sectional view taken along the line BB' in FIG. [Figure 12] FIG. 11 is a cross-sectional view taken along the line CC' in FIG. [Figure 13] FIG. 11 is a cross-sectional view taken along the line DD' in FIG. [Figure 14] FIG. 10 is a plan view illustrating a high electron mobility transistor according to yet another illustrative embodiment. [Figure 15] 15 is a cross-sectional view taken along the line EE' in FIG. 14. [Figure 16] FIG. 15 is a cross-sectional view taken along the line FF' in FIG. [Figure 17] 15 is a cross-sectional view taken along line GG' in FIG. 14. [Figure 18] FIG. 10 is a plan view illustrating a high electron mobility transistor according to yet another illustrative embodiment. [Figure 19] 19 is a cross-sectional view taken along line HH' in FIG. 18. [Figure 20] FIG. 19 is a cross-sectional view taken along line II' in FIG. [Figure 21] 19 is a cross-sectional view taken along the line JJ' in FIG. 18. [Figure 22] FIG. 10 is a plan view illustrating a high electron mobility transistor according to yet another illustrative embodiment. [Figure 23] 23 is a cross-sectional view taken along the line K-K' in FIG. 22. [Figure 24] 23 is a cross-sectional view taken along line LL' in FIG. 22. [Figure 25] 23 is a cross-sectional view taken along line MM' in FIG. 22. [Figure 26] FIG. 10 is a cross-sectional view illustrating a high electron mobility transistor according to yet another illustrative embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component may be exaggerated in the drawings for clarity and convenience. Meanwhile, the embodiments described below are merely examples, and various modifications are possible from these embodiments.

[0017] In the following, the terms "top" and "above" include not only those that are in contact with each other but also those that are not in contact with each other. A singular expression includes a plural expression unless the context clearly dictates otherwise. Furthermore, when a part "includes" a certain element, this does not mean that it excludes other elements, but that it further includes other elements, unless otherwise specified.

[0018] Use of the term "said" and similar directives refers to both the singular and the plural. Unless a method step is expressly stated or stated to the contrary, the steps may be performed in any suitable order and are not necessarily limited to the order stated.

[0019] Furthermore, terms such as "unit" and "module" used in the specification refer to a unit that processes at least one function or operation, and may be implemented by hardware or software, or by a combination of hardware and software.

[0020] The line connections or connecting members between components shown in the drawings are illustrative of functional connections and / or physical or circuit connections, and in an actual device, they may be represented as various alternative or additional functional connections, physical connections, or circuit connections.

[0021] The use of any examples or exemplary terms is merely for the purpose of illustrating the technical concept in detail, and the scope is not limited by the examples or exemplary terms unless otherwise limited by the claims.

[0022] A high electron mobility transistor (HEMT) contains semiconductor layers with different electrical polarization properties. In a high electron mobility transistor, a semiconductor layer with a relatively large polarization induces a two-dimensional electron gas (2DEG) in another semiconductor layer that is in contact with it, and the 2DEG has a very high electron mobility.

[0023] Meanwhile, in a high electron mobility transistor, if a gate voltage is 0V, a normally-on state in which current flows due to low resistance between the drain electrode and the source electrode results in current and power consumption, and a negative voltage must be applied to the gate electrode to turn off the current between the drain electrode and the source electrode.To solve this problem, a depletion layer is provided, which can realize a normally-off characteristic in which the current between the drain electrode and the source electrode is turned off when the gate voltage is 0V.

[0024] 1 is a plan view illustrating a high electron mobility transistor 100 according to an exemplary embodiment, and FIG. 2 is a cross-sectional view taken along line AA' in FIG.

[0025] 1 and 2, a channel layer 120 is provided on a substrate 110. The substrate 110 may include, for example, sapphire, Si, SiC, or GaN. However, this is merely an example, and the substrate 110 may also include various other materials.

[0026] The channel layer 120 includes a first semiconductor material. Here, the first semiconductor material is a III-V compound semiconductor material, but is not necessarily limited thereto. For example, the channel layer 120 may be a GaN-based material layer, specifically, a GaN layer. In this case, the channel layer 120 may be an undoped GaN layer, or in some cases, a GaN layer doped with a predetermined impurity.

[0027] Although not shown, a buffer layer may be further provided between the substrate 110 and the channel layer 120. The buffer layer serves to reduce the difference in lattice constant and thermal expansion coefficient between the substrate 110 and the channel layer 120. The buffer layer includes a nitride containing at least one of Al, Ga, In, and B, and has a single-layer or multi-layer structure. For example, the buffer layer may include at least one of AlN, GaN, AlGaN, InGaN, AlInN, and AlGaInN. A seed layer (not shown) for growing the buffer layer may be further provided between the substrate 110 and the buffer layer.

[0028] The channel layer 120 is provided with a channel supply layer 130. The channel supply layer 130 induces a two-dimensional electron gas (2DEG) in the channel layer 120. Here, the two-dimensional electron gas (2DEG) is formed in the channel layer 120 below the interface between the channel layer 120 and the channel supply layer 130. The channel supply layer 130 includes a second semiconductor material that is different from the first semiconductor material that constitutes the channel layer 120. The second semiconductor material differs from the first semiconductor material in at least one of polarization characteristics, energy band gap, and lattice constant.

[0029] The second semiconductor material has at least one of a polarizability and an energy band gap larger than those of the first semiconductor material. The channel supply layer 130 includes, for example, a nitride containing at least one of Al, Ga, In, and B, and has a single-layer or multi-layer structure. Specific examples of the channel supply layer 130 include, but are not limited to, at least one of AlGaN, AlInN, InGaN, AlN, and AlInGaN. The channel supply layer 130 may be an undoped layer or a layer doped with a predetermined impurity.

[0030] A source electrode 171 and a drain electrode 172 are provided in parallel on the channel layer 120 on both sides of the channel supply layer 130. Here, the source electrode 171 and the drain electrode 172 are electrically connected to a two-dimensional electron gas (2DEG). Alternatively, the source electrode 171 and the drain electrode 172 may be provided on the channel supply layer 130.

[0031] A depletion forming layer 140 is provided in the channel supply layer 130 between the source electrode 171 and the drain electrode 172. Here, the depletion forming layer 140 extends in a direction parallel to the source electrode 171 and the drain electrode 172 and is provided integrally with them.

[0032] A protrusion 140a is formed to a predetermined height in the middle portion of the upper surface of the depletion formation layer 140. The protrusion 140a extends in a direction parallel to the source electrode 171 and the drain electrode 172 and is formed integrally with them.

[0033] The depletion forming layer 140 includes a p-type semiconductor material. That is, the depletion forming layer 140 is a semiconductor layer doped with p-type impurities. The depletion forming layer 140 includes a III-V nitride semiconductor. The depletion forming layer 140 includes, for example, at least one of GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN doped with p-type impurities. As a specific example, the depletion forming layer 140 is a p-GaN layer.

[0034] The depletion-forming layer 140 increases the energy bandgap of the portion of the channel supply layer 130 located thereunder, thereby forming a depletion region of the two-dimensional electron gas (2DEG) in the portion of the channel layer 120 corresponding to the depletion-forming layer 140. As a result, the portion of the two-dimensional electron gas (2DEG) corresponding to the depletion-forming layer 140 is disconnected or has characteristics (e.g., electron concentration) different from those of the remaining portion. The region where the two-dimensional electron gas (2DEG) is disconnected is called a 'disconnection region,' and this disconnection region allows the high electron mobility transistor 100 to have normally-off characteristics in which current between the drain electrode and the source electrode is in an off state when the gate voltage is 0 V.

[0035] A gate electrode is provided in the depletion forming layer 140. The gate electrodes include first and second gate electrodes 150 and 160. The first gate electrode 150 is provided so as to be in contact with the upper surface of the protruding portion 140a of the depletion forming layer 140. The first gate electrode 150 extends along the protruding portion 140a of the depletion forming layer 140 and is provided integrally.

[0036] The first gate electrode 150 is provided to form an ohmic contact with the depletion-forming layer 140. When the depletion-forming layer 140 includes a p-type semiconductor material, the first gate electrode 150 includes a material having a higher work function than the depletion-forming layer 140. For example, when the depletion-forming layer 140 is a p-GaN layer, the first gate electrode 150 includes, for example, Pd or TiN. The work function of TiN can be adjusted by the ratio of Ti to N. However, the above-mentioned materials are merely examples, and the first gate electrode 150 may include various other materials.

[0037] The second gate electrode 160 is provided on the depletion forming layer 140 so as to cover the first gate electrode 150. Here, the second gate electrode 160 is provided so as to be in contact with both side surfaces of the protruding portion 140a of the depletion forming layer 140 and with the upper surface of the depletion forming layer 140 adjacent to the protruding portion 140a. The second gate electrode 160 extends along the first gate electrode 150 and is provided integrally with it.

[0038] The second gate electrode 160 is provided to form a Schottky contact with the depletion formation layer 140. Here, the second gate electrode 160 serves to prevent an increase in leakage current through the gate electrode when a high voltage is applied to the gate electrodes (specifically, the first and second gate electrodes 150 and 160), as will be described later.

[0039] When the depletion-forming layer 140 includes a p-type semiconductor material, the second gate electrode 160 includes a material having a lower work function than the depletion-forming layer 140. For example, when the depletion-forming layer 140 is a p-GaN layer, the second gate electrode 160 includes, for example, TiN. However, this is merely an example, and the second gate electrode 160 may also include various other materials.

[0040] The second gate electrode 160 serves to prevent an increase in leakage current through the gate electrode when a high voltage (for example, about 3 V or more, but not limited to this) is applied to the gate electrode during the turn-on operation of the high electron mobility transistor 100.

[0041] Specifically, the second gate electrode 160 forms a Schottky junction with the depletion-forming layer 140. In this case, when a predetermined high voltage is applied to the gate electrode, the depletion region due to the Schottky junction expands, thereby restricting the flow of leakage current from the gate electrode to the depletion-forming layer 140. Here, the amount of leakage current can be adjusted by changing the area ratio and height of the Schottky contact (i.e., the area ratio and height of the second gate electrode 160 in contact with the depletion-forming layer 140).

[0042] 3A and 3B show the flow of gate leakage current in the high electron mobility transistor 100 shown in FIG. 1 as a function of the turn-on voltage applied to the gate electrode.

[0043] Figure 3A shows the flow of gate leakage current when a low voltage is applied to the gate electrode, and Figure 3B shows the flow of gate leakage current when a high voltage is applied to the gate electrode.

[0044] 3A, when the voltage applied to the gate electrode is low, the depletion region formed by the Schottky junction between the depletion-forming layer 140 and the second gate electrode 160 is limited, and thus the flow of leakage current through the gate electrode is not limited. On the other hand, when the voltage applied to the gate electrode is high, the depletion region 145 formed by the Schottky junction between the depletion-forming layer 140 and the second gate electrode 160 is expanded, and thus the flow of leakage current through the gate electrode is limited, as shown in FIG.

[0045] 4 shows simulation results showing the gate leakage current as a function of the area of ​​the Schottky contact in the high electron mobility transistor 100 shown in FIG. 4. The results shown in FIG. 4 were measured when the Schottky contact height was 50 nm and the Schottky contact area ratios were 67%, 80%, and 93%, respectively. Here, the Schottky contact height refers to the height of the second gate electrode 160 that contacts both side surfaces of the protruding portion 140a of the depletion-forming layer 140. The Schottky contact area ratio refers to the ratio of the surface of the depletion-forming layer 140 that is in contact with the second gate electrode 160 to the surface of the depletion-forming layer 140 that is in contact with the first and second gate electrodes 150 and 160.

[0046] Referring to FIG. 4, when the gate voltage Vg is high, about 3 V or more, the gate leakage current I decreases as the area ratio of the Schottky contact increases.

[0047] In the high electron mobility transistor 100 according to this embodiment, a first gate electrode 150 that forms an ohmic contact with the depletion-forming layer 140 and a second gate electrode 160 that forms a Schottky contact are provided. When a high voltage is applied to the gate electrode, a depletion region 145 due to a Schottky junction formed between the depletion-forming layer 140 and the second gate electrode 160 expands, thereby preventing an increase in leakage current through the gate electrode.

[0048] In this embodiment, the amount of leakage current can be adjusted by controlling the area ratio and height of the Schottky contact formed by the second gate electrode 160. For example, if a certain amount of leakage current is required to reduce the on-resistance of the high electron mobility transistor 100, the area ratio and height of the Schottky contact can be adjusted to increase the gate current as desired. In addition, the gate bias voltage can be increased, for example, to approximately 10 V or more.

[0049] 5 to 8 are diagrams illustrating a method for manufacturing the high electron mobility transistor 100 shown in FIG. 5 to 8, each layer is formed by, for example, metal-organic chemical vapor deposition (MOCVD), but is not limited thereto.

[0050] 5, a channel layer 120 and a channel supply layer 130 are sequentially deposited on a substrate 110. The channel layer 120 includes a first semiconductor material, which may be, but is not limited to, a III-V compound semiconductor material.

[0051] The channel supply layer 130 includes a second semiconductor material different from the first semiconductor material forming the channel layer 120. The second semiconductor material differs from the first semiconductor material in at least one of polarization characteristics, energy band gap, and lattice constant. The channel supply layer 130 includes at least one selected from nitrides containing at least one of Al, Ga, In, and B, for example.

[0052] A source electrode 171 and a drain electrode 172 are formed on the channel layer 120 on both sides of the channel supply layer 130. The source electrode 171 and the drain electrode 172 may be formed in various shapes, and the order of forming them may also be varied.

[0053] Next, the depletion forming layer 140 is deposited on the channel supply layer 130 and then etched into a predetermined shape. The depletion forming layer 140 includes a p-type semiconductor material. The depletion forming layer 140 extends in a direction parallel to the source electrode 171 and the drain electrode 172 and is integrally formed.

[0054] 6, both sides of the depletion forming layer 140 are etched to form a protrusion 140a in the middle of the depletion forming layer 140. Here, the protrusion 140a extends along the depletion forming layer 140 and is integrally formed.

[0055] 7, a first gate electrode 150 is deposited on the upper surface of the protrusion 140a of the depletion forming layer 140. The first gate electrode 150 includes a material capable of forming an ohmic contact with the depletion forming layer 140. For example, when the depletion forming layer 140 is a p-GaN layer, the first gate electrode 150 includes, but is not limited to, Pd or TiN.

[0056] 8, the second gate electrode 160 is deposited on the depletion forming layer 140 to cover the first gate electrode 150. The second gate electrode 160 includes a material capable of forming a Schottky junction with the depletion forming layer 140. For example, when the depletion forming layer 140 is a p-GaN layer, the second gate electrode 160 may include, but is not limited to, TiN.

[0057] Although the above description has been given of a case in which the protrusion 140a is formed in the depletion forming layer 140, it is also possible for the protrusion 140a not to be formed in the depletion forming layer 140, as will be described later. Furthermore, although the above description has been given of a case in which the depletion forming layer 140 and the protrusion 140a are integrally formed, it is also possible for a plurality of depletion forming layers (not shown) and a plurality of protrusions (not shown) to be formed at predetermined intervals in a direction parallel to the source electrode 171 and the drain electrode 172, as will be described later. Furthermore, although the above description has been given of a case in which the first and second gate electrodes 150 and 160 are integrally formed, it is also possible for a plurality of first gate electrodes (not shown) and a plurality of second gate electrodes (not shown) to be formed at predetermined intervals in a direction parallel to the source electrode 171 and the drain electrode 172, as will be described later.

[0058] Figure 9 illustrates a high electron mobility transistor 100 according to another exemplary embodiment. The high electron mobility transistor 100 illustrated in Figure 9 is similar to the high electron mobility transistor 100 illustrated in Figure 2, except that the high electron mobility transistor 100 uses a substrate 210 as a channel layer.

[0059] 9, a channel supply layer 130 is provided on a substrate 210. The substrate 210 includes a first semiconductor material as a channel material. Here, the first semiconductor material is a III-V compound semiconductor material, but is not limited thereto. For example, the substrate 210 includes a GaN-based material.

[0060] The channel supply layer 130 induces a two-dimensional electron gas (2DEG) in the substrate 210. The channel supply layer 130 includes a second semiconductor material different from the first semiconductor material forming the substrate 210. A source electrode 171 and a drain electrode 172 are provided on the substrate 210 on both sides of the channel supply layer 130.

[0061] A depletion forming layer 140 is provided in the channel supply layer 130. A protruding portion 140a is formed in the middle portion of the depletion forming layer 140, and a first gate electrode 150 is provided on the upper surface of the protruding portion 140a. A second gate electrode 160 is provided in the depletion forming layer 140 so as to cover the first gate electrode 150. The depletion forming layer 140, the first gate electrode 150, and the second gate electrode 160 have been described above, so a description thereof will be omitted.

[0062] Figure 10 is a plan view showing a high electron mobility transistor 300 according to yet another exemplary embodiment. Figure 11 is a cross-sectional view taken along line B-B' in Figure 10, Figure 12 is a cross-sectional view taken along line CC' in Figure 10, and Figure 13 is a cross-sectional view taken along line D-D' in Figure 10. The following description will focus on differences from the above-described embodiments.

[0063] 10 to 13, a depletion forming layer 340 is provided in the channel supply layer 130 between the source electrode 171 and the drain electrode 172. Here, the depletion forming layer 340 extends in a direction parallel to the source electrode 171 and the drain electrode 172 and is provided integrally.

[0064] A plurality of protrusions 340a are formed at a predetermined height in the middle of the upper surface of the depletion-forming layer 340. The protrusions 340a are spaced apart at predetermined intervals along a direction parallel to the source electrode 171 and the drain electrode 172. The depletion-forming layer 340 includes a p-type semiconductor material. For example, the depletion-forming layer 340 is a p-GaN layer.

[0065] A gate electrode is provided in the depletion forming layer 340. The gate electrode includes a plurality of first gate electrodes 350 and a second gate electrode 360. The plurality of first gate electrodes 350 are provided on the respective protruding portions 340a of the depletion forming layer 340. Here, each of the first gate electrodes 350 is provided so as to be in contact with the upper surface of each of the protruding portions 340a of the depletion forming layer 340. Each of the first gate electrodes 350 is provided so as to form an ohmic contact with the depletion forming layer 340, specifically, with each of the protruding portions 340a of the depletion forming layer 340.

[0066] The second gate electrode 360 ​​is provided in the depletion forming layer 340 so as to cover the multiple first gate electrodes 350. The second gate electrode 360 ​​is provided integrally with the source electrode 171 and the drain electrode 172 and extends in a direction parallel to them. The second gate electrode 360 ​​is provided so as to be in contact with the side surface of the protruding portion 340a of the depletion forming layer 340 and with the upper surface of the depletion forming layer 340 adjacent to the protruding portion 340a. The second gate electrode 360 ​​is provided so as to form a Schottky contact with the depletion forming layer 340.

[0067] When a high voltage is applied to the gate electrode during the turn-on operation of the high electron mobility transistor 200, the second gate electrode 360 ​​prevents an increase in leakage current through the gate electrode due to the expansion of a depletion region caused by a Schottky junction formed between the depletion-forming layer 340 and the second gate electrode 360.

[0068] Fig. 14 is a plan view showing a high electron mobility transistor 400 according to yet another illustrative embodiment. Fig. 15 is a cross-sectional view taken along line E-E' in Fig. 14, Fig. 16 is a cross-sectional view taken along line F-F' in Fig. 14, and Fig. 17 is a cross-sectional view taken along line G-G' in Fig. 14.

[0069] 14 to 17, a depletion forming layer 440 is provided in the channel supply layer 130 between the source electrode 171 and the drain electrode 172. Here, the depletion forming layer 440 extends in a direction parallel to the source electrode 171 and the drain electrode 172 and is provided integrally.

[0070] A protrusion 440a is formed at a predetermined height in the middle of the upper surface of the depletion forming layer 440. The protrusion 440a extends in a direction parallel to the source electrode 171 and the drain electrode 172 and is integrally formed with them. The depletion forming layer 440 includes a p-type semiconductor material. For example, the depletion forming layer 440 is a p-GaN layer.

[0071] A gate electrode is provided in the depletion forming layer 440. The gate electrode includes a first gate electrode 450 and a plurality of second gate electrodes 460. The first gate electrode 450 extends along the protruding portion 440a of the depletion forming layer 440 and is provided integrally. Here, the first gate electrode 450 is provided so as to be in contact with the upper surface of the protruding portion 440a of the depletion forming layer 440. The first gate electrode 450 is provided so as to form an ohmic contact with the depletion forming layer 440.

[0072] The plurality of second gate electrodes 460 are provided on the upper surface of the depletion forming layer 440 so as to cover a portion of the first gate electrode 450. The plurality of second gate electrodes 460 are provided at predetermined intervals along the first gate electrode 450. Here, each of the second gate electrodes 460 is provided so as to be in contact with the upper surface of the protruding portion 440a of the depletion forming layer 440. Each of the second gate electrodes 460 is provided so as to form a Schottky contact with the depletion forming layer 440.

[0073] Figure 18 is a plan view showing a high electron mobility transistor 500 according to yet another illustrative embodiment. Figure 19 is a cross-sectional view taken along line H-H' in Figure 18, Figure 20 is a cross-sectional view taken along line I-I' in Figure 18, and Figure 21 is a cross-sectional view taken along line J-J' in Figure 18.

[0074] 18 to 21, a plurality of depletion forming layers 540 are provided in the channel supply layer 130 between the source electrode 171 and the drain electrode 172. The depletion forming layers 540 are provided in a direction parallel to the source electrode 171 and the drain electrode 172, spaced apart at predetermined intervals.

[0075] Adjacent depletion-forming layers 540 are spaced apart by a distance sufficient to allow a depletion region of a two-dimensional electron gas (2DEG) to form. For example, the distance between the depletion-forming layers 540 is approximately 1 μm or less. However, the distance is not limited thereto. As a specific example, the distance between the depletion-forming layers 540 is approximately 200 nm or less.

[0076] A protrusion 540a is formed at a predetermined height in the middle of the top surface of each depletion forming layer 540. The depletion forming layer 540 includes a p-type semiconductor material. For example, the depletion forming layer 540 is a p-GaN layer.

[0077] Gate electrodes are provided on the multiple depletion forming layers 540. The gate electrodes include multiple first gate electrodes 550 and second gate electrodes 560. The multiple first gate electrodes 550 are provided on the upper surfaces of the protruding portions 540a of the multiple depletion forming layers 540, respectively. Each first gate electrode 550 is provided so as to form an ohmic contact with each depletion forming layer 540.

[0078] The second gate electrode 560 is provided in the depletion forming layer 540 and the channel supply layer 130 so as to cover the multiple first gate electrodes 550. The second gate electrode 560 extends in a direction parallel to the source electrode 171 and the drain electrode 172 and is provided integrally with them. In each depletion forming layer 540, the second gate electrode 560 is provided on both sides of the protrusion 540a and the first gate electrode 550. The second gate electrode 560 is provided so as to form Schottky contacts with the multiple depletion forming layers 540.

[0079] Figure 22 is a plan view showing a high electron mobility transistor 600 according to yet another illustrative embodiment. Figure 23 is a cross-sectional view taken along line K-K' in Figure 22, Figure 24 is a cross-sectional view taken along line L-L' in Figure 22, and Figure 25 is a cross-sectional view taken along line M-M' in Figure 22.

[0080] 22 to 25, a plurality of depletion forming layers 640 are provided in the channel supply layer 130 between the source electrode 171 and the drain electrode 172. The depletion forming layers 640 are provided in a direction parallel to the source electrode 171 and the drain electrode 172, spaced apart at predetermined intervals.

[0081] A protrusion 640a is formed at a predetermined height in the middle of the top surface of each depletion forming layer 640. The depletion forming layer 640 includes a p-type semiconductor material. For example, the depletion forming layer 640 is a p-GaN layer.

[0082] Gate electrodes are provided on the multiple depletion forming layers 640. The gate electrodes include multiple first gate electrodes 650 and second gate electrodes 660. The multiple first gate electrodes 650 are provided on the upper surfaces of the protruding portions 640a of the multiple depletion forming layers 640, respectively. Each first gate electrode 650 is provided so as to form an ohmic contact with each depletion forming layer 640.

[0083] The second gate electrode 660 is provided in the depletion forming layer 640 and the channel supply layer 130 so as to cover the multiple first gate electrodes 650. The second gate electrode 660 extends in a direction parallel to the source electrode 171 and the drain electrode 172 and is provided integrally with them. In each depletion forming layer 640, the second gate electrode 660 is provided so as to surround the protrusion 640a and the first gate electrode 650. The second gate electrode 660 is provided so as to form a Schottky contact with the depletion forming layer 640.

[0084] Figure 26 is a cross-sectional view showing a high electron mobility transistor 700 according to yet another illustrative embodiment. The high electron mobility transistor 700 shown in Figure 26 has a plan view similar to the plan view shown in Figure 1. In this case, the high electron mobility transistor 700 shown in Figure 26 is similar to the high electron mobility transistor 100 shown in Figures 1 and 2, except that the depletion-forming layer 740 does not have a protrusion formed therein.

[0085] 26 , a depletion forming layer 740 is provided in the channel supply layer 130 in a direction parallel to the source electrode 171 and the drain electrode 172. A first gate electrode 750 is provided in an intermediate portion of the upper surface of the depletion forming layer 740, and a second gate electrode 760 is provided on the upper surface of the depletion forming layer 740 so as to cover the first gate electrode 750.

[0086] The first gate electrode 750 is provided to be in contact with a middle portion of the upper surface of the depletion-forming layer 740, and the second gate electrode 760 is provided to be in contact with the upper surface of the depletion-forming layer 740 adjacent to both sides of the first gate electrode 750. The first gate electrode 750 is provided to form an ohmic contact with the depletion-forming layer 740, and the second gate electrode 760 is provided to form a Schottky contact with the depletion-forming layer 740.

[0087] In this embodiment, when a predetermined high voltage is applied to the gate electrode, the depletion region formed by the Schottky junction between the second gate electrode 760 and the depletion-forming layer 740 expands, thereby restricting the flow of leakage current from the gate electrode to the depletion-forming layer 740. In addition, the amount of leakage current can be adjusted by changing the area ratio of the Schottky contact.

[0088] 26 may have a plan view similar to that shown in FIG. 10. In this case, the depletion forming layer 740 is provided integrally with and extends in a direction parallel to the source electrode 171 and the drain electrode 172. A plurality of first gate electrodes 750 are provided at intervals in the middle of the upper surface of the depletion forming layer 740, and a second gate electrode 760 is provided in the depletion forming layer 740 so as to cover the plurality of first gate electrodes 750.

[0089] 26 may have a plan view similar to that shown in FIG. 14. In this case, the depletion-forming layer 740 is integrally formed and extends in a direction parallel to the source electrode 171 and the drain electrode 172, and a first gate electrode 750 is provided in the middle of the upper surface of the depletion-forming layer 740. A plurality of second gate electrodes 760 are provided spaced apart on the upper surface of the depletion-forming layer 740 so as to partially cover the first gate electrode 750.

[0090] 26 may have a plan view similar to that shown in FIG. 18. In this case, a plurality of depletion forming layers 740 are provided in the channel supply layer 130, spaced apart at predetermined intervals in a direction parallel to the source electrode 171 and the drain electrode 172. A plurality of first gate electrodes 750 are provided in the middle portions of the upper surfaces of the plurality of depletion forming layers 740, respectively.

[0091] The second gate electrode 760 is provided in the depletion forming layer 740 and the channel supply layer 130 so as to cover the multiple first gate electrodes 750. The second gate electrode 760 extends in a direction parallel to the source electrode 171 and the drain electrode 172 and is provided integrally with them. In each depletion forming layer 740, the second gate electrode 760 is provided on both sides of the first gate electrode 750. The high electron mobility transistor 700 shown in FIG. 26 may also have a plane similar to the plane shown in FIG. 22. In that case, in each depletion forming layer 740, the second gate electrode 760 is provided so as to surround the first gate electrode 750.

[0092] According to the above exemplary embodiment, the depletion-forming layer is provided with a first gate electrode for ohmic contact and a second gate electrode for Schottky contact. When a high voltage is applied to the gate electrode, the depletion region formed by the Schottky junction between the depletion-forming layer and the second gate electrode expands, thereby preventing an increase in leakage current through the gate electrode.

[0093] The amount of gate leakage current can be adjusted by controlling the area ratio and height of the Schottky contact. For example, if a certain amount of leakage current is required to reduce the on-resistance of a high electron mobility transistor, the gate current can be increased as desired by adjusting the area ratio and height of the Schottky contact.

[0094] Although the embodiments have been described above, they are merely examples, and various modifications can be made therefrom by those skilled in the art. [Industrial Applicability]

[0095] The present invention is applicable to, for example, technical fields related to power elements. [Explanation of symbols]

[0096] 2DEG Two-dimensional electron gas 100 High electron mobility transistor 110 Substrate 120 Channel Layer 130 Channel Supply Layer 140 Depletion formation layer 140a Protrusion 145 Depletion region 150 first gate electrode 160 Second gate electrode 171 Source electrode 172 Drain electrode

Claims

1. a channel layer comprising a first semiconductor material; a channel supply layer including a second semiconductor material and inducing two-dimensional electron gas (2DEG) in the channel layer; a source electrode and a drain electrode provided on both sides of the channel supply layer; at least one depletion forming layer provided on the channel supply layer and forming a depletion region in the two-dimensional electron gas; a gate electrode provided on the at least one depletion forming layer, the gate electrodes include at least one first gate electrode provided to form an ohmic contact with the at least one depletion forming layer, and at least one second gate electrode provided to form a Schottky contact with the at least one depletion forming layer; a second gate electrode having a lower surface located lower than a lower surface of the at least one first gate electrode;

2. 2. The high electron mobility transistor according to claim 1, wherein the at least one depletion forming layer includes a depletion forming layer extending in a direction parallel to the source electrode and the drain electrode.

3. A channel layer comprising a first semiconductor material; a channel supply layer including a second semiconductor material and inducing two-dimensional electron gas (2DEG) in the channel layer; a source electrode and a drain electrode provided on both sides of the channel supply layer; at least one depletion forming layer provided on the channel supply layer and forming a depletion region in the two-dimensional electron gas; a gate electrode provided on the at least one depletion forming layer, the gate electrodes include at least one first gate electrode provided to form an ohmic contact with the at least one depletion forming layer, and at least one second gate electrode provided to form a Schottky contact with the at least one depletion forming layer; the at least one depletion forming layer includes a depletion forming layer extending in a direction parallel to the source electrode and the drain electrode, A high electron mobility transistor, characterized in that at least one protrusion is formed in an intermediate portion of the depletion forming layer along a direction parallel to the source electrode and the drain electrode.

4. 3. The high electron mobility transistor according to claim 2, wherein the at least one first gate electrode comprises a first gate electrode extending in a direction parallel to the source electrode and the drain electrode at an intermediate portion of an upper surface of the depletion forming layer.

5. 5. The high electron mobility transistor according to claim 4, wherein the at least one second gate electrode includes a second gate electrode provided on an upper surface of the depletion forming layer so as to cover the first gate electrode.

6. A channel layer comprising a first semiconductor material; a channel supply layer including a second semiconductor material and inducing two-dimensional electron gas (2DEG) in the channel layer; a source electrode and a drain electrode provided on both sides of the channel supply layer; at least one depletion forming layer provided on the channel supply layer and forming a depletion region in the two-dimensional electron gas; a gate electrode provided on the at least one depletion forming layer, the gate electrode includes at least one first gate electrode provided to form an ohmic contact with the at least one depletion forming layer, and at least one second gate electrode provided to form a Schottky contact with the at least one depletion forming layer, the at least one depletion forming layer includes a depletion forming layer extending in a direction parallel to the source electrode and the drain electrode, the at least one first gate electrode includes a first gate electrode extending in a direction parallel to the source electrode and the drain electrode at an intermediate portion of an upper surface of the depletion forming layer, the at least one second gate electrode includes a plurality of second gate electrodes spaced apart on an upper surface of the depletion forming layer so as to cover a portion of the first gate electrode.

7. 3. The high electron mobility transistor according to claim 2, wherein the at least one first gate electrode comprises a plurality of first gate electrodes spaced apart in a direction parallel to the source electrode and the drain electrode at an intermediate portion of an upper surface of the depletion forming layer.

8. A channel layer comprising a first semiconductor material; a channel supply layer including a second semiconductor material and inducing two-dimensional electron gas (2DEG) in the channel layer; a source electrode and a drain electrode provided on both sides of the channel supply layer; at least one depletion forming layer provided on the channel supply layer and forming a depletion region in the two-dimensional electron gas; a gate electrode provided on the at least one depletion forming layer, the gate electrode includes at least one first gate electrode provided to form an ohmic contact with the at least one depletion forming layer, and at least one second gate electrode provided to form a Schottky contact with the at least one depletion forming layer, 2. A high electron mobility transistor, wherein the at least one depletion-forming layer includes a plurality of depletion-forming layers spaced apart in a direction parallel to the source electrode and the drain electrode.

9. 9. The high electron mobility transistor according to claim 8, wherein a protrusion is provided in an intermediate portion of each of the depletion forming layers along a direction parallel to the source electrode and the drain electrode.

10. forming a channel layer and a channel supply layer; forming at least one depletion forming layer on the channel supply layer; forming at least one first gate electrode forming an ohmic contact on the at least one depletion forming layer; an etching step of etching the at least one depletion forming layer around the first gate electrode; and forming at least one second gate electrode forming a Schottky contact on the at least one depletion-forming layer and the at least one first gate electrode.

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