Semiconductor device manufacturing method

Abstract

To improve a performance of a semiconductor device.SOLUTION: A manufacturing method of a semiconductor device, includes: a step (S1) of forming an interlayer film onto a substrate; a step (S2) of forming an uneven pattern to the interlayer film in which the uneven pattern includes an electrode convex part in which an electrode penetration hole is formed in a wiring region, a column convex part formed in at least the wiring region, and a concave part formed in the portion other than the electrode convex part and the column convex part; a step (S3) of forming a sacrificial film covering the uneven pattern; a step (S4) of removing the sacrificial film to an upper direction from the electrode convex part and the column convex part in the wiring region; a step (S6) of forming a plating film to the upper direction of the electrode convex part and the column convex part and into an inner part of the electrode penetration hole in the wiring region; and a step (S15) of removing the sacrificial film after the plurality of plating films laminated to a vertical direction are formed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] In the manufacture of semiconductor devices, various processes such as film formation and etching are repeatedly performed on semiconductor substrates to produce desired devices. In response to the recent trend toward higher integration and finer design, multilayer wiring structures in which metal wiring is embedded in interlayer insulating films are being adopted for these semiconductor devices.

[0003] To improve the performance of semiconductor devices, it is essential to reduce the delay time of interconnects. The main factors that determine the delay time of interconnects are the wiring resistance and the wiring capacitance. In other words, to reduce the delay time of interconnects, it is necessary to reduce the wiring resistance as well as the wiring capacitance.

[0004] To reduce wiring resistance, copper (Cu) is used for wiring. When forming this copper wiring in a multilayer wiring structure, the damascene process is used, for example. In the damascene process, a barrier film and a seed film are formed in the wiring trench, and then electroplating is performed using the seed as a power supply, filling the wiring trench with copper.

[0005] Furthermore, in order to reduce the wiring capacitance in a multilayer wiring structure, a low-k film made of a material with a low dielectric constant, such as silicon nitride (SiN) or silicon dioxide (SiO2), has conventionally been used as an interlayer insulating film. Furthermore, in order to further reduce the dielectric constant of the interlayer insulating film, it has been proposed to form voids (hereinafter sometimes referred to as "air gaps") in the interlayer insulating film (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-193104 Summary of the Invention [Problem to be solved by the invention]

[0007] As mentioned above, when using the damascene process, a barrier film and a seed film are required to form copper wiring. These barrier and seed films have high wiring resistance, so it is preferable to make them as thin as possible. However, particularly with the recent trend toward finer wiring, the volume ratio of the barrier and seed films in the wiring has increased, so the influence of the wiring resistance of these barrier and seed films cannot be ignored.

[0008] In recent years, the use of cobalt (Co) and ruthenium (Ru) as wiring materials has been considered to eliminate the need for barrier and seed films. However, the wiring resistance of these materials is high, and they are not yet sufficient to reduce the wiring resistance. Furthermore, cobalt and ruthenium are expensive, so it is desirable to use inexpensive copper.

[0009] Furthermore, as mentioned above, forming an air gap in the interlayer insulating film has been proposed to reduce the wiring capacitance, but this weakens the structural mechanical strength of the semiconductor device. Therefore, from the viewpoint of wiring capacitance as well, there is room for improvement in conventional semiconductor devices.

[0010] The present invention has been made in view of the above circumstances, and has as its object to improve the performance of semiconductor devices. [Means for solving the problem]

[0011] The present invention, which solves the above-mentioned problems, is a method for manufacturing a semiconductor device, comprising: (a) a step of forming an interlayer film on a substrate; (b) a step of forming a concave-convex pattern on the interlayer film, the concave-convex pattern having electrode convex portions in a wiring region where electrode through holes are formed, support convex portions formed at least in the wiring region, and concave portions formed in areas other than the electrode convex portions and the support convex portions; (c) a step of forming a sacrificial film so as to cover the concave-convex pattern; (d) a step of removing the sacrificial film above the electrode convex portions and support convex portions in the wiring region; (e) a step of forming a plating film above the electrode convex portions and support convex portions and inside the electrode through holes in the wiring region; and (f) a step of repeatedly performing the steps (a) to (e) to form a plurality of the plating films stacked in the vertical direction, and then removing the sacrificial film. (g) forming a barrier film on the surface of the plating film after removing the sacrificial film, and in the (g) step, a current leakage test is performed on the plating film in the wiring region when the barrier film is formed. It is characterized by the following. Another aspect of the present invention is a method for manufacturing a semiconductor device, the method comprising: (a) forming an interlayer film on a substrate; (b) forming a concave-convex pattern on the interlayer film, the concave-convex pattern having electrode convex portions in a wiring region where electrode through holes are formed, support post convex portions formed at least in the wiring region, and concave portions formed in areas other than the electrode convex portions and the support post convex portions; (c) forming a sacrificial film so as to cover the concave-convex pattern; (d) removing the sacrificial film above the electrode convex portions and support post convex portions in the wiring region; (e) forming a plating film above the electrode convex portions and support post convex portions and inside the electrode through holes in the wiring region; and (f) removing a plating film from the step (a). and (e) repeating the process from step (a) to step (e) to form a plurality of the plating films stacked in the vertical direction, and then removing the sacrificial film. The process (b) comprises the steps of dry etching the upper parts of the electrode convex parts to form the upper parts of the electrode through holes, and wet etching the lower parts of the electrode convex parts to form the lower parts of the electrode through holes, and the wet etching comprises the steps of supplying a first etching solution from above the interlayer film, forming an electric field in the first etching solution to move first etching ions contained in the first etching solution toward the interlayer film, and oxidizing the first etching ions that have moved toward the interlayer film. Another aspect of the present invention is a method for manufacturing a semiconductor device, the method comprising: (a) forming an interlayer film on a substrate; (b) forming a concave-convex pattern on the interlayer film, the concave-convex pattern having electrode convex portions in a wiring region where electrode through holes are formed, support post convex portions formed at least in the wiring region, and concave portions formed in areas other than the electrode convex portions and the support post convex portions; (c) forming a sacrificial film so as to cover the concave-convex pattern; (d) removing the sacrificial film above the electrode convex portions and support post convex portions in the wiring region; (e) forming a plating film above the electrode convex portions and support post convex portions in the wiring region and inside the electrode through holes; and (f) repeating steps (a) to (e) to form a plurality of the plating films stacked vertically. and removing the sacrificial film after forming the plating film. The step (e) comprises the steps of arranging crystal nuclei of the plating film on the surface of the support convex portion, growing crystal grains from the crystal nuclei to form the plating film, and growing crystal grains from the bottom of the electrode through-hole to form the plating film, and planarizing the surface of the plating film after forming the plating film. The step of planarizing the surface of the plating film comprises the steps of supplying a second etching solution to the surface of the plating film, forming an electric field in the second etching solution to move second etching ions contained in the second etching solution toward the plating film, and further polishing and planarizing the surface of the plating film while oxidizing the second etching ions that have moved toward the plating film. According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method comprising: (a) forming an interlayer film on a substrate; (b) forming a concave-convex pattern on the interlayer film, the concave-convex pattern having electrode convex portions in a wiring region where electrode through holes are formed, support post convex portions formed at least in the wiring region, and concave portions formed in areas other than the electrode convex portions and the support post convex portions; (c) forming a sacrificial film to cover the concave-convex pattern; (d) removing the sacrificial film above the electrode convex portions and support post convex portions in the wiring region; (e) forming a plating film above the electrode convex portions and support post convex portions and inside the electrode through holes in the wiring region; and (f) repeatedly performing steps (a) to (e) to form a plurality of the plating films stacked in the vertical direction, and then removing the sacrificial film, the step (e) including the steps of arranging crystal nuclei of the plating film on surfaces of the support post convex portions, and forming the plating film by growing crystal grains from the bottom of the electrode through-holes; supplying a plating solution to the area from which the sacrificial film was removed in step (d); forming an electric field in the plating solution to migrate plating ions contained in the plating solution toward the substrate, further reducing the plating ions that have migrated toward the substrate, and growing the crystal grains to form the plating film; and planarizing the surface of the plating film after the plating film is formed, wherein the planarizing the surface of the plating film includes supplying a second etching solution to the surface of the plating film; and forming an electric field in the second etching solution to migrate second etching ions contained in the second etching solution toward the plating film, and polishing and planarizing the surface of the plating film while oxidizing the second etching ions that have migrated toward the plating film. According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method comprising the steps of: (a) forming an interlayer film on a substrate; (b) forming a concave-convex pattern on the interlayer film, the concave-convex pattern having electrode convex portions in a wiring region where electrode through holes are formed, support convex portions formed at least in the wiring region, and concave portions formed in areas other than the electrode convex portions and the support convex portions; (c) forming a sacrificial film so as to cover the concave-convex pattern; (d) removing the sacrificial film above the electrode convex portions and support convex portions in the wiring region; and (e) removing the electrode convex portions and the support convex portions in the wiring region. (f) forming a plating film above the support convex portion and inside the electrode through-hole; and (f) repeatedly performing steps (a) to (e) to form a plurality of the plating films stacked in the vertical direction, and then removing the sacrificial film, wherein step (f) comprises the steps of supplying a third etching solution from above the sacrificial film, forming an electric field in the third etching solution to move third etching ions contained in the third etching solution toward the sacrificial film, and further oxidizing the third etching ions that have moved toward the sacrificial film, thereby removing the sacrificial film. Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising: (a) forming an interlayer film on a substrate; (b) forming a concave-convex pattern on the interlayer film, the concave-convex pattern having electrode convex portions in a wiring region where electrode through holes are formed, support convex portions formed at least in the wiring region, and concave portions formed other than the electrode convex portions and the support convex portions; (c) forming a sacrificial film to cover the concave-convex pattern; (d) removing the sacrificial film above the electrode convex portions and support convex portions in the wiring region; (e) forming a plating film above the electrode convex portions and support convex portions and inside the electrode through holes in the wiring region; and (f) repeatedly performing steps (a) to (e) to form a plurality of the plating films stacked in the vertical direction, and then removing the sacrificial film, wherein a space formed by removing the sacrificial film in step (f) is a space for circulating a cooling medium.

[0012] According to the present invention, the steps (a) to (e) are repeatedly performed to form multiple layers of plating films, and in each layer, plating films are formed over the entire wiring region to form wiring. Therefore, by using plating films with low wiring resistance, the wiring resistance of the entire semiconductor device can be reduced.

[0013] Furthermore, after forming multiple layers of plating films, the sacrificial film is removed. This allows air gaps to be formed throughout the entire interlayer film. Furthermore, because support pillar protrusions and plating films (pillars) are formed above them in the wiring region, even if air gaps are formed throughout the entire interlayer film, the wiring is properly supported by the pillars. Therefore, the wiring capacitance can be reduced by the air gaps while maintaining high structural mechanical strength of the semiconductor device.

[0014] As described above, since it is possible to reduce both the wiring resistance and the wiring capacitance, it is possible to reduce the wiring delay speed and improve the performance of the semiconductor device.

[0018] In the step (b), the support post convex portions are formed in the wiring region and the non-wiring region; in the step (d), the sacrificial film above the electrode convex portions and support post convex portions in the wiring region is removed, and the sacrificial film above the support post convex portions in the non-wiring region is also removed; and in the step (e), a plating film may be formed above the electrode convex portions and support post convex portions in the wiring region, and a plating film may be formed above the support post convex portions in the non-wiring region.

[0019] In the step (b), the electrode projections and the support projections may be disposed at equal intervals.

[0020] In the step (b), a heat dissipation through-hole may be formed in the support post protrusion in the non-wiring region, and in the step (e), a plating film may be formed inside the heat dissipation through-hole. In this case, the plating film inside the heat dissipation through-hole (heat dissipation wiring formed in the non-wiring region) may be connected to a heat sink outside the semiconductor device.

[0025] The substrate may be rotated when polishing the surface of the plating film.

[0028] The plating film may be a copper plating film. [Effects of the Invention]

[0029] According to the present invention, the performance of a semiconductor device can be improved. [Brief explanation of the drawings]

[0030] [Figure 1] 1 is a flowchart showing main steps of substrate processing performed in a semiconductor device manufacturing method. [Figure 2A] FIG. 2 is an explanatory diagram of step S1 of substrate processing. [Figure 2B] FIG. 10 is an explanatory diagram of step S2 of the substrate processing. [Figure 2C] FIG. 10 is an explanatory diagram of step S2 of the substrate processing. [Figure 2D] FIG. 10 is an explanatory diagram of step S3 of the substrate processing. [Figure 2E] FIG. 10 is an explanatory diagram of step S4 of substrate processing. [Figure 2F] FIG. 10 is an explanatory diagram of step S4 of substrate processing. [Figure 2G] FIG. 10 is an explanatory diagram of step S5 of substrate processing. [Figure 2H] FIG. 10 is an explanatory diagram of step S6 of substrate processing. [Figure 2I] FIG. 10 is an explanatory diagram of step S7 of substrate processing. [Figure 2J] FIG. 10 is an explanatory diagram of step S8 of substrate processing. [Figure 2K] FIG. 10 is an explanatory diagram of step S9 of substrate processing. [Figure 2L] FIG. 10 is an explanatory diagram of step S10 of substrate processing. [Figure 2M] FIG. 10 is an explanatory diagram of step S11 of substrate processing. [Figure 2N] FIG. 10 is an explanatory diagram of step S12 of the substrate processing. [Figure 2O] FIG. 10 is an explanatory diagram of step S13 of substrate processing. [Figure 2P] FIG. 10 is an explanatory diagram of step S14 of substrate processing. [Figure 2Q] FIG. 10 is an explanatory diagram of step S15 of substrate processing. [Figure 2R] FIG. 10 is an explanatory diagram of step S16 of substrate processing. [Figure 3] FIG. 1 is an explanatory diagram illustrating an outline of the configuration of a plating processing apparatus. [Figure 4] FIG. 1 is a flow chart showing the main steps of a plating process. [Figure 5] FIG. 10 is an explanatory diagram of step T2 of the plating treatment. [Figure 6] FIG. 10 is an explanatory diagram of step T2 of the plating treatment. [Figure 7]FIG. 10 is an explanatory diagram of step T3 of the plating treatment. [Figure 8] FIG. 10 is an explanatory diagram of steps S2 and S9 of substrate processing according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0031] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted.

[0032] <Method of manufacturing a semiconductor device> A method for manufacturing a semiconductor device according to this embodiment will be described. In this embodiment, a semiconductor device to be manufactured has a multi-layer wiring structure, and the wiring is copper wiring. For ease of explanation, an example in which the semiconductor device has a two-layer wiring structure will be described below, but the semiconductor device may have a three-layer or more wiring structure.

[0033] FIG. 1 is a flow diagram showing the main steps of substrate processing performed in a semiconductor device manufacturing method. In the substrate processing, various processes are performed on a substrate W, which is a semiconductor substrate (e.g., a semiconductor wafer). FIGS. 2A to 2R are explanatory diagrams of the main steps of the substrate processing, and the substrate processing shown in FIGS. 2A to 2R is a continuous process. Note that FIGS. 2A to 2R illustrate a portion of the substrate W. Also, FIGS. 2A to 2I show the first layer wiring structure, with (a) showing an AA cross-sectional view and (b) showing a plan view. FIGS. 2J to 2R show the second layer wiring structure, with (a) showing a BB cross-sectional view and (b) showing a plan view. Note that in the drawings used in the following explanation, the dimensions of each component do not necessarily correspond to the actual dimensions, in order to prioritize ease of understanding the technology.

[0034] (Step S1) As shown in FIG. 2A, a first interlayer insulating film 100 is formed on a substrate W. A low-dielectric-constant material (Low-K material), such as silicon nitride (SiN), is used for the interlayer insulating film 100. The interlayer insulating film 100 has a wiring region 101 where wiring is formed and a non-wiring region 102 where no wiring is formed. The interlayer insulating film 100 may be formed by any method.

[0035] (Step S2) 2B and 2C, a concave-convex pattern 110 is formed on the interlayer insulating film 100. The concave-convex pattern 110 has electrode convex portions 111, first support convex portions 112, second support convex portions 113, and concave portions 114. The convex portions 111, 112, and 113 are arranged at equal intervals.

[0036] The electrode protrusion 111 is a protrusion in the wiring region 101 where a through electrode is formed, and an electrode through hole 115 for the through electrode is formed so as to penetrate in the vertical direction. The electrode through hole 115 is formed at the position of the through electrode that connects the upper layer wiring with the lower layer wiring. The first support post protrusion 112 is a protrusion formed in the wiring region 101 and is part of a post for supporting the wiring. The second support post protrusion 113 is a protrusion formed in the non-wiring region 102 and is part of a dummy post. The dummy post is provided to increase the structural mechanical strength of the semiconductor device, as will be described later. The recess 114 is formed in an area other than the protrusions 111, 112, and 113.

[0037] The concave-convex pattern 110 and the electrode through holes 115 are formed by, for example, photolithography and wet etching. That is, as shown in Fig. 2B, a predetermined resist pattern 103 is formed on the interlayer insulating film 100 by photolithography, and then the interlayer insulating film 100 is wet-etched using the resist pattern 103 as a mask, as shown in Fig. 2C, to form the concave-convex pattern 110 and the electrode through holes 115.

[0038] (Step S3) Next, as shown in FIG. 2D, a sacrificial film 120 is formed so as to cover the concave-convex pattern 110. The sacrificial film 120 is made of, for example, amorphous silicon. The sacrificial film 120 is a film that is removed in a wet etching process described later, and the material of the sacrificial film 120 is determined in relation to the etching solution. The sacrificial film 120 is not formed inside the electrode through-hole 115. The method for forming the sacrificial film 120 is arbitrary.

[0039] (Step S4) 2E and 2F, the sacrificial film 120 in a predetermined region is removed. The predetermined region includes the wiring region 101 and a region in the non-wiring region 102 where the second support post protrusion 113 is formed. In other words, the sacrificial film 120 in a region in the non-wiring region 102 where the second support post protrusion 113 is not formed is not removed.

[0040] The removal of the sacrificial film 120 in the predetermined region is performed by, for example, photolithography and wet etching. That is, as shown in Fig. 2E, a predetermined resist pattern 121 is formed on the sacrificial film 120 by photolithography, and then the sacrificial film 120 is wet-etched using the resist pattern 121 as a mask, as shown in Fig. 2F, to remove the sacrificial film 120 in the predetermined region.

[0041] During this wet etching, the sacrificial film 120 formed in the recess 114 in the wiring region 101 is not removed. In the wiring region 101, the wet etching is stopped when the sacrificial film 120 above the electrode protrusion 111 and the first support post protrusion 112 has been removed.

[0042] (Step S5) Next, as shown in Fig. 2G, crystal nuclei 130 (plating nuclei) of a plating film are placed on the upper surfaces of the first support post convex portion 112 and the second support post convex portion 113. The crystal nuclei 130 are copper atoms. The crystal nuclei 130 are placed at one point on the upper surfaces of the support post convex portions 112 and 113.

[0043] The method for disposing the crystal nuclei 130 is arbitrary. For example, the crystal nuclei 130 may be disposed by electroless plating, atomic layer deposition (ALD), ion dosing, or the like.

[0044] (Step S6) Next, as shown in Fig. 2H, plating film 140 is formed. Plating film 140 includes plating films 140a to 140d, which will be described later.

[0045] In the wiring region 101, crystal grains of the plating film are grown from the bottom of the electrode through hole 115 to form a plating film 140a inside the electrode through hole 115. This plating film 140a constitutes the through electrode 141. In addition, the crystal grains from the electrode through hole 115 are further grown to form a plating film 140b above the electrode protrusion 111 and above a part of the sacrificial film 120.

[0046] In the wiring region 101, crystal grains 131 are grown from crystal nuclei 130 on the first support post protrusions 112, forming plating films 140c above the first support post protrusions 112 and above a portion of the sacrificial film 120. The crystal grains 131 grow into spherical shapes. Then, the plating films 140b and 140c are connected to form wiring 142. In this embodiment, the first support post protrusions 112 themselves form pillars that support the wiring 142.

[0047] In the non-wiring region 102, crystal grains 131 are grown from crystal nuclei 130 on the second support post convex portions 113, and a plating film 140d is formed above the second support post convex portions 113. Then, the second support post convex portions 113 and the plating film 140d form a support post.

[0048] Here, a description will be given of an example of a method for forming the plating film 140. In the following description, a case where the plating film 140c is formed from the crystal nuclei 130 on the first support post convex portion 112 will be described.

[0049] <Configuration of plating processing equipment> 3 is an explanatory diagram showing an outline of the configuration of a plating processing apparatus 500. An electrode 510 is provided above the substrate W, facing the first support column protrusion 112 and the crystal nuclei 130. In the following description, the first support column protrusion 112 and the crystal nuclei 130 may be referred to as a structure 150. A plating solution M is filled between the structure 150 and the electrode 510, and the structure 150 and the electrode 510 are electrically connected to the plating solution M. For example, a solution in which copper sulfate is dissolved is used as the plating solution M. That is, the plating solution M contains copper ions as plating ions. The substrate W and the crystal nuclei 130 are capacitively coupled.

[0050] A first wiring 520 is connected to the electrode 510, and a second wiring 521 is connected to the substrate W. A switch 522 is provided on the first wiring 520, and a charging wiring 523 and a discharging wiring 524 are connected to the second wiring 521. The switch 522 switches between the connection between the first wiring 520 and the charging wiring 523 and the connection between the first wiring 520 and the discharging wiring 524. In other words, the first wiring 520 and the second wiring 521 are connected via the charging wiring 523 or the discharging wiring 524 by switching the switch 522. The switching of the switch 522 is controlled by a control unit 540, which will be described later.

[0051] The charging wiring 523 is provided with a DC power supply 530 and a charging resistor 531. For example, the DC power supply 530 is provided on the second wiring 521 side, and the charging resistor 531 is provided on the first wiring 520 side. The electrode 510 is connected to the positive electrode side of the DC power supply 530. The substrate W is connected to the negative electrode side of the DC power supply 530.

[0052] The discharge wiring 524 is provided with a discharge resistor 532. The resistance value of the discharge resistor 532 is greater than the resistance value of the charge resistor 531.

[0053] The plating processing apparatus 500 described above is provided with a control unit 540. The control unit 540 is, for example, a computer equipped with a CPU, a memory, etc., and has a program storage unit (not shown). The program storage unit stores a program for controlling the processing of the substrate W in the plating processing apparatus 500. Note that the program may be recorded on a computer-readable storage medium and installed into the control unit 540 from the storage medium.

[0054] <Plating method> Next, a description will be given of a plating process (formation of the plating film 140c) using the plating processing device 500 configured as described above. Figure 4 is a flow chart showing the main steps of the plating process.

[0055] (Step T1) In the plating processing apparatus 500, an electrode 510 is disposed above the substrate W as shown in FIG. 3 , and the plating solution M is filled between the structure 150 and the electrode 510. The electrode 510 can be disposed and the plating solution M can be filled (supplied) by any method. For example, the electrode 510 may be disposed, and then the plating solution M may be supplied from a nozzle (not shown) to fill the space. Alternatively, the electrode 510 may be disposed, and then the plating solution M may be supplied onto the structure 150 from a nozzle. The electrode 510 and the structure 150 are then electrically connected to the plating solution M.

[0056] (Step T2) Next, as shown in FIG. 5, the first wiring 520, the charging wiring 523, and the second wiring 521 are connected by the switch 522, and the substrate W (structure 150) and the electrode 510 are connected via a DC power supply 530. Then, a DC voltage is applied with the electrode 510 as the anode and the structure 150 as the cathode to form an electric field (electrostatic field) in the plating solution M. As a result, a positive charge is accumulated in the electrode 510, and anions A, which are negatively charged particles in the plating solution M, gather at the electrode 510. Meanwhile, a negative charge is accumulated in the structure 150, and copper ions C, which are positively charged particles in the plating solution M, move to the structure 150. In FIG. 5, dotted arrows indicate the flow of current.

[0057] At this time, the charging voltage applied to the plating solution M is greater than the ionization voltage for generating copper ions C. Then, as shown in FIG. 6, anions A accumulate on the electrode 510, and an oxidation reaction occurs at the electrode 510. Meanwhile, in the structure 150, the copper ions C accumulated on the crystal nuclei 130 acquire an electric charge, and the copper ions C are reduced. At this time, the copper ions C on the surface of the crystal nuclei 130 are reduced, but the copper ions C on the first support column protrusions 112 are not reduced. Then, crystal grains 131 grow from the crystal nuclei 130.

[0058] In the following description, the state in which charge is accumulated in electrode 510 in step T2 and crystal grains 131 grow from crystal nuclei 130 may be referred to as "charging."

[0059] (Step T3) Next, as shown in Fig. 7, the first wiring 520, the discharge wiring 524, and the second wiring 521 are connected by the switch 522, and the substrate W (structure 150) and the electrode 510 are connected without the DC power supply 530. This causes the charge stored in the capacitance of the structure 150 to be discharged. In Fig. 7, the dotted arrow indicates the flow of current.

[0060] As described above, the resistance value of the discharge resistor 532 is greater than the resistance value of the charge resistor 531. As a result, a large amount of voltage is absorbed by the discharge resistor 532 during discharge, and the discharge voltage applied to the plating solution M is smaller than the ionization voltage for generating copper ions C. For this reason, in step T3, hydrogen, which has a lower ionization tendency than copper, is oxidized, and the reduced copper atoms are not oxidized.

[0061] In the following description, the state in which the charge stored in the capacitance of the structure 150 is discharged in step T3 may be referred to as "discharging."

[0062] (Step T4) Next, the charging step in step T2 and the discharging step in step T3 are repeated in this order. By repeating the charging and discharging steps in this manner, the plating film 140c shown in FIG. 2H is formed to a desired thickness.

[0063] In this case, since the substrate W and the crystal nuclei 130 are capacitively coupled, performing steps T1 to T4 allows the crystal grains 131 to grow from the crystal nuclei 130, thereby efficiently forming the plating film 140c. Also, since the single-crystal crystal grains 131 are grown from the crystal nuclei 130, it is possible to grow large crystal grains 131. Furthermore, although not shown, since the first support column protrusions 112 are arranged at equal intervals, adjacent crystal grains 131, 131 can be connected to each other, allowing even larger crystal grains 131 to grow.

[0064] The other plating films 140a, 140b, and 140d are also formed by performing steps T1 to T4 using the plating processing device 500. The plating film 140d is formed above the second support post convex portion 113, and is formed in the same manner as the above-mentioned plating film 140c.

[0065] When forming the plating films 140a and 140b, in step T1, a plating solution M is supplied to the inside of the electrode through-hole 115 and onto the electrode protrusion 111. Here, a through electrode 141 connecting the upper and lower layers is formed inside the electrode through-hole 115. In other words, a structure in which an insulating layer (interlayer insulating film) and a conductive layer (copper wiring) are stacked in this order from the substrate W side is formed in the lower layer of the electrode through-hole 115. Then, in the charging step of step T2, an electric field (electrostatic field) is formed in the plating solution M, and copper ions C in the plating solution M migrate to the bottom of the electrode through-hole 115 and are further reduced. Next, a discharging step of step T3 is performed. Steps T2 and T3 are repeated in this order, and crystal grains 131 grow from bottom to top (bottom-up), forming the plating film 140a. Subsequently, steps T2 and T3 are repeatedly performed to further grow the crystal grains 131 from the plating film 140a, thereby forming a plating film 140b above the electrode projections 111 and above a part of the sacrificial film 120.

[0066] Although the methods for forming the plating films 140a to 140d have been described individually above, these plating films 140a to 140d are formed simultaneously.

[0067] Furthermore, the method for forming the plating film 140 in steps T1 to T4 is an example, and is not limited to this. For example, copper ions C may be moved toward the structure 150 in the charging step, and then the copper ions C may be reduced in the discharging step. That is, the plating film 140 may be formed in a non-contact manner by discharging only when a positive electric field is formed in the plating solution M to reduce the copper ions C, and by charging and discharging in the electrostatic field when a negative electric field is formed in the plating solution M, without causing an oxidation or reduction reaction.

[0068] (Step S7) After the plating film 140 is formed in step S6 (steps T1 to T4) as shown in FIG. 2H, the upper surface of the plating film 140 is then flattened as shown in FIG. 2I.

[0069] Any method may be used to planarize the upper surface of the plating film 140. For example, chemical mechanical polishing (CMP) may be used.

[0070] The upper surface of the plating film 140 may also be wet-etched using a plating solution M. For wet etching, for example, a plating apparatus in which the anode and cathode of the DC power supply 530 of the plating apparatus 500 shown in FIG. 3 are reversed is used. That is, the electrode 510 is connected to the negative electrode side of the DC power supply 530, and the substrate W is connected to the positive electrode side of the DC power supply 530.

[0071] In this case, in step T2, a DC voltage is applied to the electrode 510 as a cathode and the plating film 140 as an anode to form an electric field (electrostatic field) in the plating solution M. As a result, anions A move toward the plating film 140. At this time, the charging voltage applied to the plating solution M is greater than the ionization voltage for generating anions A. As a result, anions A are oxidized in the plating film 140.

[0072] In step T3, the electric charge stored in the capacitance of the plating film 140 is discharged. The charging step in step T2 and the discharging step in step T3 are repeated in this order, and the plating film 140 is etched.

[0073] Alternatively, the upper surface of the plating film 140 may be polished while being wet-etched. For the wet etching, similar to the wet etching described above, for example, a plating apparatus in which the anode and cathode of the DC power supply 530 of the plating apparatus 500 shown in FIG. 3 are reversed is used.

[0074] In such a case, in step T1 of the wet etching process, an etching solution is filled between the upper surface of the plating film 140 and the electrode 510. The etching solution is selected depending on the material of the plating film 140, and may include, for example, hydrofluoric acid.

[0075] In step T2, a DC voltage is applied to the electrode 510 as a cathode and the plating film 140 as an anode, forming an electric field (electrostatic field) in the etching solution. This causes etching ions to move toward the plating film 140. At this time, the charging voltage applied to the etching solution is greater than the ionization voltage for generating etching ions. This causes the etching ions to be oxidized in the plating film 140.

[0076] In step T3, the electric charge stored in the capacitance of the plating film 140 is discharged. The charging step in step T2 and the discharging step in step T3 are repeated in this order, and the plating film 140 is etched.

[0077] Then, while wet etching the upper surface of the plating film 140 in this manner, the upper surface of the plating film 140 is polished. At this time, by polishing while rotating the substrate W, the upper surface of the plating film 140 can be polished appropriately.

[0078] As described above, steps S1 to S7 are performed to form the first-layer wiring structure. Subsequently, the second-layer wiring structure is formed. As described above, (a) of Figures 2J to 2R shows the cross-sectional view taken along line BB, and (b) shows a plan view.

[0079] (Step S8) 2J, a second-layer interlayer insulating film 200 is formed on the first-layer wiring structure. Step S8 is the same as step S1 above, and the material of the interlayer insulating film 200 is the same as the material of the interlayer insulating film 100. The interlayer insulating film 200 has a wiring region 201 where wiring is formed and a non-wiring region 202 where no wiring is formed.

[0080] (Step S9) Next, as shown in FIG. 2K, a concave-convex pattern 210 is formed on the interlayer insulating film 200. Step S9 is the same as step S2 above, and detailed description thereof will be omitted. The concave-convex pattern 210 is the same as the concave-convex pattern 110, and has electrode convex portions 211, first support convex portions 212, second support convex portions 213, and concave portions 214. Furthermore, electrode through holes 215 are formed in the electrode convex portions 211.

[0081] (Step S10) 2L, a sacrificial film 220 is formed so as to cover the concave-convex pattern 210. Step S10 is the same as step S3 above, and the material of the sacrificial film 220 is the same as the material of the sacrificial film 120.

[0082] (Step S11) Next, as shown in FIG. 2M, the sacrificial film 220 in a predetermined region is removed. Step S11 is the same as step S4 above, and a detailed description thereof will be omitted. The predetermined region includes the wiring region 201 and a region in the non-wiring region 202 where the second support post protrusion 113 is formed. In other words, the sacrificial film 220 in a region in the non-wiring region 202 where the second support post protrusion 213 is not formed is not removed.

[0083] (Step S12) 2N, crystal nuclei 230 of a plating film are placed on the upper surfaces of the first support column protrusion 212 and the second support column protrusion 213. Step S12 is similar to step S5 above, and a detailed description thereof will be omitted.

[0084] (Step S13) Next, a plating film 240 is formed as shown in Fig. 2O. Step S13 is the same as step S6 above, and detailed description thereof will be omitted. The plating film 240 includes plating films 240a to 240d. The plating film 240a forms a through electrode 241, and the plating films 240b and 240c form wiring 242.

[0085] (Step S14) Next, the upper surface of the plating film 240 is planarized as shown in Fig. 2P. Step S14 is similar to step S7 above, and a detailed description thereof will be omitted.

[0086] As described above, steps S1 to S7 are carried out to form the first layer wiring structure, and steps S8 to S14 are carried out to form the second layer wiring structure.

[0087] (Step S15) Next, as shown in FIG. 2Q, the first sacrificial film 120 and the second sacrificial film 220 are simultaneously removed. The sacrificial films 120 and 220 are removed by, for example, wet etching. The wet etching is performed in the same manner as in steps S7 and S14 above, using a plating apparatus in which the anode and cathode of the DC power supply 530 of the plating apparatus 500 shown in FIG. 3 are reversed.

[0088] In such a case, in step T1 of the wet etching process, an etching solution is filled between the sacrificial film 220 and the electrode 510. The etching solution is selected depending on the material of the sacrificial film 220, but may contain, for example, hydrofluoric acid.

[0089] In step T2, a DC voltage is applied to the electrode 510 as a cathode and the sacrificial film 220 as an anode, forming an electric field (electrostatic field) in the etching solution. This causes etching ions to move toward the sacrificial film 220. At this time, the charging voltage applied to the etching solution is greater than the ionization voltage for generating the etching ions. This causes the etching ions to be oxidized in the sacrificial film 220.

[0090] In step T3, the charge stored in the capacitance of the sacrificial film 220 is discharged. The charging process in step T2 and the discharging process in step T3 are repeated in this order, and the sacrificial film 220 is etched and removed, and then the sacrificial film 120 is etched and removed.

[0091] As described above, the sacrificial films 120 and 220 are removed, and an air gap 300 is formed in the removed space. The air gap 300 can reduce the wiring capacitance in the semiconductor device. Furthermore, by circulating a cooling medium (e.g., cooling air, cooling water, etc.) through the air gap 300, it is possible to cool the semiconductor device.

[0092] (Step S16) 2R, a barrier film 310 is formed on the exposed surfaces of the first plating film 140 and the second plating film 240. The method for forming the barrier film 310 is arbitrary.

[0093] When forming this barrier film 310, a current leakage test may be performed between the wiring 142 (plating film 140 in the wiring region 101) and the wiring 242 (plating film 240 in the wiring region 201). Note that any method for the leakage test may be used. The current leakage test is performed during the formation of the barrier film 310, and leakage will disappear once the barrier film 310 is properly formed.

[0094] As described above, steps S1 to S16 are performed to manufacture a semiconductor device with a two-layer wiring structure. When manufacturing a semiconductor device with an N-layer wiring structure of three or more layers, steps S1 to S7 are repeated N times to form wiring in each layer, and then the sacrificial films are simultaneously removed in step S15 to form air gaps 300, and barrier film 310 is formed in step S16.

[0095] According to the above embodiment, steps S1 to S7 and steps S8 to S14 are performed to form plating films 140, 240 over the entire wiring regions 101, 201 of each layer, thereby forming wirings 142, 242. The formation of these wirings 142, 242 is performed before forming the barrier film 310 in step S16. This makes it possible to increase the proportion of the volume of the wirings 142, 242 in the wiring structure of each layer. Therefore, by using copper, which has low wiring resistance, for the wirings 142, 242, it is possible to reduce the wiring resistance of the entire semiconductor device.

[0096] In steps S6 and S13, plating films 140 and 240 are formed by performing steps T1 to T4 using a plating processing device 500. This eliminates the need for a conventional seed film. Therefore, the proportion of the volume of the wiring 142 and 242 in the wiring structure of each layer can be increased, further reducing the wiring resistance of the entire semiconductor device.

[0097] Furthermore, after steps S1 to S14 are performed to form the two-layer plating films 140 and 240, the sacrificial films 120 and 220 are removed in step S15. This allows the air gap 300 to be formed over the entire area of ​​the interlayer insulating films 100 and 200. Therefore, the air gap 300 can reduce the wiring capacitance.

[0098] As described above, since it is possible to reduce both the wiring resistance and the wiring capacitance, it is possible to reduce the wiring delay speed and improve the performance of the semiconductor device. Moreover, since copper wiring is inexpensive, it is possible to reduce the manufacturing cost of the semiconductor device.

[0099] Furthermore, first support post protrusions 112, 212 are formed in the wiring regions 101, 201 of each layer, and the first support post protrusions 112, 212 support the wirings 142, 242. Furthermore, second support post protrusions 113 and plating films 140d, 240d are formed above them in the non-wiring region 102. Therefore, even if air gaps 300 are formed throughout the interlayer insulating films 100, 200, the structural mechanical strength of the semiconductor device can be maintained at a high level.

[0100] Furthermore, since the electrode protrusions 111, 211, the first support post protrusions 112, 212, and the second support post protrusions 113, 213 are arranged at equal intervals in each layer, the structural mechanical strength of the semiconductor device can be further maintained at a high level.

[0101] Furthermore, in steps S6 and S13, steps T1 to T4 are performed using a plating processing device 500 to grow crystal grains and form plating films 140 and 240. Here, the diffusion phenomenon of copper at the gas-solid interface is one of the causes of so-called fisker formation. In this regard, in this embodiment, additives are not required when forming plating films 140 and 240, and the purity of copper can be improved. Therefore, the fisker formation can be suppressed, and the copper diffusion phenomenon can be inhibited.

[0102] Conventionally, a seed film is formed over the entire surface of the wiring trench before the plating film is formed.The plating film is then annealed to increase the crystal grain size, but the use of a low-k film as the interlayer insulating film places a temperature limit on how large the crystals can be.

[0103] In this embodiment, in steps S6 and S13, crystal grains 131 and 231 are grown from single crystal nuclei 130 and 230 to form plating films 140 and 240. In this case, the crystal grains 131 and 231 can be enlarged. This eliminates the need for annealing, which is a conventional method for enlarging crystal grains.

[0104] The spacing between the crystal nuclei 130, 230 (spacing between the first support post protrusions 112, 212) is preferably based on the depth of the wiring trench. To embed the plating film in the wiring trench, the crystal grains 131, 231 need to grow from the bottom to the top. Because the crystal grains 131, 231 grow spherically, the spacing between the crystal nuclei 130, 230 is the spacing at which adjacent crystal nuclei 130, 230 connect, i.e., the depth of the wiring trench.

[0105] Conventionally, air gaps have been formed in an interlayer insulating film by photolithography and wet etching. In such cases, if the resist pattern is misaligned during the photolithography process, the air gaps cannot be formed in the proper positions. This can result in the electrode through-holes communicating with the air gaps, preventing the electrode through-holes from being properly filled with a plating film, and thus preventing the proper formation of through-electrodes.

[0106] In this regard, in this embodiment, after the through electrodes 141, 241 and the wirings 142, 242 are formed in steps S1 to S14, the sacrificial films 120, 220 are simultaneously removed in step S15 to form the air gap 300, so the above-mentioned conventional problem of misalignment does not occur. Therefore, the through electrodes 141, 241 can be properly formed, and the air gap 300 can also be properly formed.

[0107] Here, conventionally, after forming a barrier film, a wet etching process is performed to form the through-hole for the electrode. In this case, if the barrier film causes a deviation in the formation position of the through-hole for the electrode, the through-electrode cannot be formed properly.

[0108] In this regard, in this embodiment, the through electrodes 141, 241 and the wirings 142, 242 are formed in steps S1 to S14, and then the barrier film 310 is formed in step S16, so the above-mentioned problem of misalignment in the formation of the electrode through holes does not occur. Therefore, the barrier film 310 can be formed appropriately while the through electrodes 141, 241 are formed appropriately.

[0109] Furthermore, since the barrier film 310 is formed in the final step S16, the conventional formation of a so-called cap metal and the formation of a through hole for the cap metal are not required.

[0110] <Other embodiments> In the above embodiments, when forming the electrode through holes 115, 215 in the interlayer insulating films 100, 200 in steps S2 and S9, they are formed by photolithography and wet etching processes, but the method of forming the electrode through holes 115, 215 is not limited to this.

[0111] The upper portions of the electrode through holes 115, 215 may be formed by dry etching, and then the lower portions of the electrode through holes 115, 215 may be formed by wet etching. That is, first, the upper portions of the electrode protrusions 111, 211 are subjected to dry etching to form the upper portions of the electrode through holes 115, 215.

[0112] Next, wet etching is performed on the lower parts of the electrode convex parts 111, 211 to form the lower parts of the electrode through holes 115, 215. The wet etching at this time is performed in the same manner as in steps S7 and S14 above, using a plating device in which the anode and cathode of the DC power supply 530 of the plating device 500 shown in FIG.

[0113] In step T1 of the wet etching process, an etching solution is filled between the electrode protrusions 111, 211 and the electrode 510. The etching solution is selected depending on the material of the electrode protrusions 111, 211, and includes, for example, hydrofluoric acid.

[0114] In step T2, a DC voltage is applied to the electrode 510 as a cathode and the electrode protrusions 111 and 211 as anodes to form an electric field (electrostatic field) in the etching solution. This causes etching ions to move toward the electrode protrusions 111 and 211. At this time, the charging voltage applied to the etching solution is greater than the ionization voltage for generating etching ions. This causes the etching ions to be oxidized at the electrode protrusions 111 and 211.

[0115] In step T3, the electric charge stored in the capacitance of the electrode protrusions 111, 211 is discharged. The charging process in step T2 and the discharging process in step T3 are repeated in this order to etch the electrode protrusions 111, 211 and form the electrode through-holes 115, 215.

[0116] Conventionally, when forming through holes for electrodes, the interlayer insulating film is dry-etched. In this case, if the dry etching position is misaligned with respect to the lower layer, the through electrodes cannot be formed properly.

[0117] In this regard, in this embodiment, the lower portions of the electrode through holes 115, 215 are formed by the above-described wet etching process, so that etching progresses toward a predetermined position in the lower layer. In the above-described wet etching process, etching progresses due to capacitive coupling between the substrate W and the electrode protrusions 111, 211, that is, oxidation and reduction reactions progress in proportion to the electrostatic capacitance. For this reason, etching progresses from the lower portions of the electrode through holes 115, 215, which have strong capacitive coupling, toward the lower-layer wiring. Therefore, the electrode through holes 115, 215 can be formed in appropriate positions relative to the lower layer, and the through electrodes 141, 241 can be formed appropriately.

[0118] <Other embodiments> When forming the concave-convex patterns 110, 210 in the interlayer insulating films 100, 200 in steps S2, S9 of the above-described embodiments, heat dissipation through holes 400, 401 for heat dissipation paths may be formed in the second support post convex portions 113, 213 as shown in Fig. 8. Thereafter, when forming the plating films 140, 240 in steps S6, S13, plating films 410, 411 are formed inside the heat dissipation through holes 400, 401.

[0119] In this case, plating films 410, 140d, 411, and 240d are formed in this order from bottom to top in the non-wiring regions 102 and 202. That is, the conductive plating films 410, 140d, 411, and 240d penetrate vertically and are electrically connected, which can function as a heat dissipation path. This improves the performance of the semiconductor device.

[0120] The heat dissipation wiring formed by the plating films 410, 140d, 411, and 240d may be connected to a heat sink outside the semiconductor device.

[0121] Although the present invention has been described above by way of example, it is understood that the present invention is not limited to such examples. It is clear that a person skilled in the art can conceive of various modifications and alterations within the scope of the technical ideas set forth in the claims, and that such modifications and alterations are also within the technical scope of the present invention. [Explanation of symbols]

[0122] 100, 200 Interlayer insulating film 101, 201 wiring area 102, 202 No wiring area 103 Resist Pattern 110, 210 uneven pattern 111, 211 Electrode protrusions 112, 212 First support convex portion 113, 213 Second support convex part 114, 214 recess 115, 215 Through hole for electrode 120, 220 Sacrificial film 121 Resist Pattern 130, 230 Crystal nuclei 131, 231 grains 140 (140a-140d), 240 (240a-240d) plating film 141, 241 Through electrode 142, 242 wiring 150 Structure 300 Air Gap 310 Barrier Film 400, 401 Through hole for heat radiation 410, 411 Plating film 500 plating processing equipment 510 electrode 520 First Wiring 521 Second Wiring 522 Switch 523 Charging wiring 524 Discharge wiring 530 DC power supply 531 Charging resistance 532 Discharge resistor 540 Control Unit A anion C Copper ions M plating solution W substrate

Claims

1. A method for manufacturing a semiconductor device, comprising: (a) forming an interlayer film on a substrate; (b) forming a concave-convex pattern on the interlayer film, the concave-convex pattern having electrode convex portions in which electrode through holes are formed in a wiring region, support convex portions formed at least in the wiring region, and concave portions formed other than the electrode convex portions and the support convex portions; (c) forming a sacrificial film so as to cover the concave-convex pattern; (d) removing the sacrificial film above the electrode convex portions and the support convex portions in the wiring region; (e) forming a plating film above the electrode convex portion and the support convex portion and inside the electrode through hole in the wiring region; (f) repeating the steps (a) to (e) to form a plurality of the plating films stacked in the vertical direction, and then removing the sacrificial film; (g) forming a barrier film on the surface of the plating film after removing the sacrificial film, 10. A method for manufacturing a semiconductor device, wherein in the step (g), when the barrier film is formed, a current leakage test is performed on the plating film in the wiring region.

2. A method for manufacturing a semiconductor device, comprising: (a) forming an interlayer film on a substrate; (b) forming a concave-convex pattern on the interlayer film, the concave-convex pattern having electrode convex portions in which electrode through holes are formed in a wiring region, support convex portions formed at least in the wiring region, and concave portions formed other than the electrode convex portions and the support convex portions; (c) forming a sacrificial film so as to cover the concave-convex pattern; (d) removing the sacrificial film above the electrode convex portions and the support convex portions in the wiring region; (e) forming a plating film above the electrode convex portion and the support convex portion and inside the electrode through hole in the wiring region; (f) repeatedly performing the steps (a) to (e) to form a plurality of the plating films stacked in the vertical direction, and then removing the sacrificial film; The step (b) comprises: performing dry etching on the upper portion of the electrode convex portion to form the upper portion of the electrode through hole; and performing wet etching on the lower portion of the electrode convex portion to form the lower portion of the electrode through hole, The wet etching is supplying a first etching solution from above the interlayer film; forming an electric field in the first etching solution to move first etching ions contained in the first etching solution toward the interlayer film, and oxidizing the first etching ions that have moved toward the interlayer film.

3. A method for manufacturing a semiconductor device, comprising: (a) forming an interlayer film on a substrate; (b) forming a concave-convex pattern on the interlayer film, the concave-convex pattern having electrode convex portions in which electrode through holes are formed in a wiring region, support convex portions formed at least in the wiring region, and concave portions formed other than the electrode convex portions and the support convex portions; (c) forming a sacrificial film so as to cover the concave-convex pattern; (d) removing the sacrificial film above the electrode convex portions and the support convex portions in the wiring region; (e) forming a plating film above the electrode convex portion and the support convex portion and inside the electrode through hole in the wiring region; (f) repeatedly performing the steps (a) to (e) to form a plurality of the plating films stacked in the vertical direction, and then removing the sacrificial film; The step (e) is a step of arranging crystal nuclei of the plating film on the surface of the support post projection; forming the plating film by growing crystal grains from the crystal nuclei and by growing crystal grains from the bottom of the electrode through-holes; and after forming the plating film, planarizing the surface of the plating film, The step of planarizing the surface of the plating film includes: supplying a second etching solution to the surface of the plating film; forming an electric field in the second etching solution to move second etching ions contained in the second etching solution toward the plating film, and further polishing and planarizing the surface of the plating film while oxidizing the second etching ions that have moved toward the plating film.

4. A method for manufacturing a semiconductor device, comprising: (a) forming an interlayer film on a substrate; (b) forming a concave-convex pattern on the interlayer film, the concave-convex pattern having electrode convex portions in which electrode through holes are formed in a wiring region, support convex portions formed at least in the wiring region, and concave portions formed other than the electrode convex portions and the support convex portions; (c) forming a sacrificial film so as to cover the concave-convex pattern; (d) removing the sacrificial film above the electrode convex portions and the support convex portions in the wiring region; (e) forming a plating film above the electrode convex portion and the support convex portion and inside the electrode through hole in the wiring region; (f) repeatedly performing the steps (a) to (e) to form a plurality of the plating films stacked in the vertical direction, and then removing the sacrificial film; The step (e) is a step of arranging crystal nuclei of the plating film on the surface of the support post projection; forming the plating film by growing crystal grains from the crystal nuclei and by growing crystal grains from the bottom of the electrode through-holes; supplying a plating solution to the region from which the sacrificial film has been removed in the step (d); forming an electric field in the plating solution to move plating ions contained in the plating solution toward the substrate, and further reducing the plating ions that have moved toward the substrate, thereby growing the crystal grains and forming the plating film; and after forming the plating film, planarizing the surface of the plating film, The step of planarizing the surface of the plating film includes: supplying a second etching solution to the surface of the plating film; forming an electric field in the second etching solution to move second etching ions contained in the second etching solution toward the plating film, and further polishing and planarizing the surface of the plating film while oxidizing the second etching ions that have moved toward the plating film.

5. 5. The method for manufacturing a semiconductor device according to claim 3, wherein the substrate is rotated when polishing the surface of the plating film.

6. A method for manufacturing a semiconductor device, comprising: (a) forming an interlayer film on a substrate; (b) forming a concave-convex pattern on the interlayer film, the concave-convex pattern having electrode convex portions in which electrode through holes are formed in a wiring region, support convex portions formed at least in the wiring region, and concave portions formed other than the electrode convex portions and the support convex portions; (c) forming a sacrificial film so as to cover the concave-convex pattern; (d) removing the sacrificial film above the electrode convex portions and the support convex portions in the wiring region; (e) forming a plating film above the electrode convex portion and the support convex portion and inside the electrode through hole in the wiring region; (f) repeatedly performing the steps (a) to (e) to form a plurality of the plating films stacked in the vertical direction, and then removing the sacrificial film; The step (f) is supplying a third etching solution from above the sacrificial film; forming an electric field in the third etching solution to move third etching ions contained in the third etching solution toward the sacrificial film, and further oxidizing the third etching ions that have moved toward the sacrificial film, thereby removing the sacrificial film.

7. A method for manufacturing a semiconductor device, comprising: (a) forming an interlayer film on a substrate; (b) forming a concave-convex pattern on the interlayer film, the concave-convex pattern having electrode convex portions in which electrode through holes are formed in a wiring region, support convex portions formed at least in the wiring region, and concave portions formed other than the electrode convex portions and the support convex portions; (c) forming a sacrificial film so as to cover the concave-convex pattern; (d) removing the sacrificial film above the electrode convex portions and the support convex portions in the wiring region; (e) forming a plating film above the electrode convex portion and the support convex portion and inside the electrode through hole in the wiring region; (f) repeatedly performing the steps (a) to (e) to form a plurality of the plating films stacked in the vertical direction, and then removing the sacrificial film; 4. A method for manufacturing a semiconductor device, wherein the space formed by removing the sacrificial film in the step (f) is a space through which a cooling medium flows.

8. In the step (b), the support post protrusions are formed in the wiring region and the non-wiring region; In the step (d), the sacrificial film is removed above the electrode convex portion and the support convex portion in the wiring region, and the sacrificial film is removed above the support convex portion in the non-wiring region; 8. The method for manufacturing a semiconductor device according to claim 1, wherein in the step (e), a plating film is formed above the electrode convex portions and the support convex portions in the wiring region, and a plating film is formed above the support convex portions in the non-wiring region.

9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein in the step (b), the electrode convex portions and the support convex portions are arranged at equal intervals.

10. In the step (b), a heat dissipation through hole is formed in the support post protrusion in the non-wiring region, 10. The method for manufacturing a semiconductor device according to claim 8, wherein in the step (e), a plating film is formed inside the heat dissipation through hole.

11. 11. The method for manufacturing a semiconductor device according to claim 1, wherein the plating film is a copper plating film.

Images