Semiconductor device and failure detection method

Abstract

To detect a failure of a bypass capacitor not only after an internal circuit is started, but also before the internal circuit is started.SOLUTION: A semiconductor device includes an internal circuit that operates by receiving power from a power supply line, a first signal output circuit that outputs a first signal indicating the rising timing of a power supply voltage applied to the power supply line, a second signal output circuit that outputs a second signal indicating the timing specified by the internal circuit, a load current control circuit that varies the load current flowing through the power supply line on the basis of the first signal and the second signal, and a determination circuit that determines the level of power supply voltage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a failure detection method. [Background technology]

[0002] The following techniques are known as techniques for detecting faults in bypass capacitors connected to power lines. For example, Patent Document 1 describes a semiconductor device that operates by receiving power from a DC power supply to an internal circuit with a bypass capacitor connected to a power supply terminal, and that includes a load current control unit that changes the current supplied from the power supply terminal for a predetermined operating period, and a detection unit that detects the voltage of the power supply terminal and outputs a detection signal if the voltage exceeds an upper threshold value when an upper threshold value is set, or if the voltage falls below a lower threshold value when a lower threshold value is set. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-075626 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described in Patent Document 1, a pulse signal output at regular intervals from a pulse generating unit included in the internal circuit drives a switch in a load current control unit to increase the load current, and a failure in the bypass capacitor is detected based on a change in voltage at the power supply terminal that accompanies the increase in load current. According to the semiconductor device described in Patent Document 1, failure detection in the bypass capacitor is triggered by the pulse signal output from the internal circuit, so failure detection in the bypass capacitor cannot be performed during the period from when the power is turned on until the internal circuit starts up. A delay in detecting a failure in the bypass capacitor could have a fatal impact on the system.

[0005] The present invention has been made in view of the above points, and has an object to enable fault detection of a bypass capacitor not only after startup of an internal circuit but also before startup of the internal circuit. [Means for solving the problem]

[0006] The semiconductor device includes an internal circuit that operates by receiving power from a power supply line, a first signal output circuit that outputs a first signal that indicates the timing of a rise in a power supply voltage applied to the power supply line, a second signal output circuit that outputs a second signal that indicates a timing specified by the internal circuit, a load current control circuit that varies a load current flowing through the power supply line based on the first signal and the second signal, and a determination circuit that determines the level of the power supply voltage.

[0007] The fault detection method of the present invention is a fault detection method for a bypass capacitor connected to a power supply line, and includes varying a load current flowing through the power supply line at the timing when a power supply voltage applied to the power supply line rises and at a timing specified by an internal circuit that operates by receiving power from the power supply line, and determining whether or not there is a fault in the bypass capacitor based on the level of the power supply voltage when the load current is varied. [Effects of the Invention]

[0008] According to the present invention, it is possible to detect a failure in a bypass capacitor not only after the internal circuit has been started up but also before the internal circuit has been started up. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a circuit block diagram showing an example of a configuration of a semiconductor device according to an embodiment of the present invention; [Figure 2] 10 is a time chart showing an example of the operation of a semiconductor device when power is turned on when no failure occurs in a bypass capacitor. [Figure 3]10 is a time chart showing an example of an operation of a semiconductor device when power is turned on in a case where a failure occurs in a bypass capacitor; [Figure 4] 10 is a time chart showing an example of an operation of the semiconductor device after the internal circuit is started up; [Figure 5] 10 is a flowchart showing an example of the flow of processing carried out in the internal circuit as the internal circuit executes a fault detection program. [Figure 6] FIG. 2 is a diagram illustrating an example of the configuration of a reference voltage generating circuit and a determination circuit. [Figure 7] FIG. 10 is a diagram illustrating another example of the configuration of the reference voltage generating circuit and the determination circuit. [Figure 8] FIG. 10 is a diagram illustrating another example of the configuration of the reference voltage generating circuit and the determination circuit. [Figure 9] FIG. 10 is a diagram illustrating another example of the configuration of the reference voltage generating circuit and the determination circuit. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings, in which the same reference numerals are used to designate substantially the same or equivalent components or parts.

[0011] 1 is a circuit block diagram showing an example of the configuration of a semiconductor device 10 according to an embodiment of the present invention. The semiconductor device 10 includes a power-on reset circuit 11, a test signal output circuit 12, an AND circuit 13, a pulse signal generation circuit 14, a load current control circuit 15, a reference voltage generation circuit 16, a determination circuit 17, an alarm signal output circuit 18, and an internal circuit 19. The semiconductor device 10 also includes a power supply terminal 22, a ground terminal 23, an output terminal 24, a power supply line L1, and a ground line L2. The power supply line L1 is connected to the power supply terminal 22, and the ground line L2 is connected to the ground terminal 23. The above-described components constituting the semiconductor device 10 are provided on a semiconductor substrate.

[0012] The anode of a DC power supply 40 is connected to the power supply terminal 22, and the cathode of the DC power supply 40 is connected to the ground terminal 23. The DC power supply 40 applies a power supply voltage VDD between the power supply line L1 and the ground line L2. A bypass capacitor 41 is provided between the power supply terminal 22 and the ground terminal 23. The bypass capacitor 41 serves to stabilize the power supply voltage VDD applied to the power supply line L1. The semiconductor device 10 has a function of detecting a failure of the bypass capacitor 41.

[0013] The power-on reset circuit 11 outputs a reset signal S1 indicating the timing of the rise of the power supply voltage VDD applied to the power supply line L1. The reset signal S1 is a control signal used for power-on reset of the internal circuit 19. That is, when the power is turned on, the internal circuit 19 performs a reset operation to initialize its internal register in response to the reset signal S1 output from the power-on reset circuit 11. The reset signal S1 is also used as a trigger signal for detecting a failure in the bypass capacitor 41 before starting up the internal circuit 19. After power is turned on, the reset signal S1 transitions to a low level when the level of the power supply voltage VDD reaches a predetermined detection level Vd, and after maintaining the low level for a certain period of time, transitions to a high level. The reset signal S1 is supplied to the AND circuit 13 and the internal circuit 19. The power-on reset circuit 11 is an example of a "first signal output circuit" in the present invention, and the reset signal S1 is an example of a "first signal" in the present invention.

[0014] The test signal output circuit 12 outputs a test signal S2 that indicates the timing for detecting a failure in the bypass capacitor 41, which is specified by the internal circuit 19 after the internal circuit 19 has been started. The timing for detecting a failure in the bypass capacitor 41 by the internal circuit 19 is specified by an instruction signal S i In this embodiment, the test signal S2 is generated by the instruction signal S output from the internal circuit 19. iThe test signal S2 transitions to a low level in response to a signal from the AND circuit 12, and after maintaining the low level for a certain period of time, transitions to a high level. The test signal S2 is supplied to the AND circuit 13. The test signal output circuit 12 is an example of a "second signal output circuit" in the present invention, and the test signal S2 is an example of a "second signal" in the present invention.

[0015] The AND circuit 13 outputs a control signal S corresponding to the logical product of the reset signal S1 and the test signal S2. 12 and supplies this to the pulse signal generating circuit 14.

[0016] The pulse signal generating circuit 14 generates a control signal S 12 A single pulse signal S with a constant pulse width depending on p The pulse signal generating circuit 14 outputs a pulse signal S at the timing when the level of the reset signal S1 or the test signal S2 transitions from a low level to a high level. p That is, the pulse signal S p The pulse signal S is generated at the timing of the rise of the power supply voltage VDD and at the timing of detecting a failure in the bypass capacitor 41 designated by the internal circuit 19. p is supplied to the load current control circuit 15.

[0017] The load current control circuit 15 is configured to include a series circuit having a resistor element 31 and a switch 32, which are provided between the power supply line L1 and the ground line L2. One end of the resistor element 31 is connected to the power supply line L1, and the other end is connected to one end of the switch 32. The other end of the switch 32 is connected to the ground line L2. The switch 32 is connected to the pulse signal S output from the pulse signal generating circuit 14. p When the switch 32 is turned on, the load current flowing through the power supply line L1 increases. That is, the load current control circuit 15 varies the load current at the timing of the rise of the power supply voltage VDD and at the timing of failure detection of the bypass capacitor 41 specified by the internal circuit 19.

[0018] As the load current increases, the level of the power supply voltage VDD applied to the power supply line L1 decreases. If the bypass capacitor 41 is normal, the fluctuation range of the power supply voltage VDD associated with fluctuations in the load current is relatively small. The level of the power supply voltage VDD then returns to an appropriate level. If a fault such as leakage occurs in the bypass capacitor 41, the fluctuation range of the power supply voltage VDD associated with fluctuations in the load current becomes larger than under normal conditions, and it takes longer for the level of the power supply voltage VDD to return to an appropriate level than under normal conditions.

[0019] The determination circuit 17 determines the level of the power supply voltage VDD applied to the power supply line L1. Specifically, the determination circuit 17 compares the level of the power supply voltage VDD with the level of the reference voltage Vref generated by the reference voltage generation circuit 16, and outputs a determination signal S j If there is no failure in the bypass capacitor 41, the level of the power supply voltage VDD is maintained higher than the level of the reference voltage Vref even when the load current fluctuates. On the other hand, if there is a failure in the bypass capacitor 41, the level of the power supply voltage VDD becomes lower than the level of the reference voltage Vref when the load current fluctuates. Therefore, a determination signal S indicating the result of comparing the level of the power supply voltage VDD with the level of the reference voltage Vref is output. j is a signal indicating whether or not there is a fault in the bypass capacitor 41. j is supplied to an alarm signal output circuit 18 and an internal circuit 19.

[0020] The reference voltage generation circuit 16 generates a reference voltage Vref used by the determination circuit 17 to determine the level of the power supply voltage VDD. The level of the reference voltage Vref is set to an appropriate level that enables detection of a failure in the bypass capacitor 41. That is, the level of the reference voltage Vref is set based on the level of the power supply voltage VDD that has dropped due to fluctuations in the load current when the bypass capacitor 41 has failed. The level of the reference voltage Vref is also set to a level higher than the detection level Vd used by the power-on reset circuit 11 to detect the rising edge of the power supply voltage VDD.

[0021] The alarm signal output circuit 18 outputs a determination signal S j The alarm signal S3 is generated and output based on the determination signal S j Similarly to the alarm signal S3, the alarm signal S3 is a signal indicating the presence or absence of a fault in the bypass capacitor 41. The alarm signal S3 can be monitored from outside the semiconductor device 10 via the output terminal 24. By monitoring the alarm signal S3, it is possible to know the presence or absence of a fault in the bypass capacitor 41. The alarm signal output circuit 18 is an example of the "third signal output circuit" in the present invention. The alarm signal S3 is an example of the "third signal" in the present invention.

[0022] The internal circuit 19 operates by receiving power from the power supply line L1. After power is turned on, the internal circuit 19 performs a reset operation to initialize its internal registers based on a reset signal S1 output from the power-on reset circuit 11. When the reset signal S1 is output, the internal circuit 19 is in a state before startup.

[0023] The internal circuit 19 has a memory circuit 20 in which a fault detection program 21 is stored. When the reset operation is completed, the internal circuit 19 enters a state after startup and executes the fault detection program 21 stored in the memory circuit 20. The internal circuit 19 receives an instruction signal S i That is, the timing for detecting a failure in the bypass capacitor 41 is determined by the instruction signal S i The internal circuit 19 is designated by the instruction signal S i The instruction signal S is output repeatedly at a predetermined interval. i is supplied to the test signal output circuit 12.

[0024] The internal circuit 19 outputs a determination signal S indicating that a failure has occurred in the bypass capacitor 41. j When the internal circuit 19 receives the determination signal S jWhen receiving this signal, the device may, for example, perform a process to stop the operation of itself or other circuits, or a process to notify other circuits of a failure in the bypass capacitor.

[0025] The operation of the semiconductor device 10 will be described below. Figures 2 and 3 are time charts showing an example of the operation of the semiconductor device 10 when power is turned on. Figure 2 shows the case where no failure occurs in the bypass capacitor 41, and Figure 3 shows the case where a failure occurs in the bypass capacitor 41. During the periods shown in Figures 2 and 3, the internal circuit 19 is in a state before startup.

[0026] When power is turned on at time t0, the power supply voltage VDD applied to the power supply line L1 gradually increases. The reset signal S1 output from the power-on reset circuit 11 transitions to a low level at time t1 when the level of the power supply voltage VDD reaches a predetermined detection level Vd, and transitions to a high level at time t2, a predetermined period of time after time t1. The test signal S2 output from the test signal output circuit 12 is maintained at a high level. Here, the high level and low level are logical levels, for example, the high level is a logical value 1, and the low level is a logical value 0. Furthermore, the high level voltage is a voltage that follows the power supply voltage VDD, and the low level voltage is a voltage that does not follow the power supply voltage VDD, for example, a voltage that follows a ground voltage different from the power supply voltage VDD.

[0027] The pulse signal generating circuit 14 generates a single pulse signal S having a constant pulse width in response to the transition of the reset signal S1 to a high level. pAs a result, at time t2, the switch 32 of the load current control circuit 15 is turned on, and the load current increases. As the load current increases, the power supply voltage VDD applied to the power supply line L1 decreases. If the bypass capacitor 41 is normal, the fluctuation range of the power supply voltage VDD caused by the fluctuation of the load current is relatively small, and the power supply voltage VDD immediately returns to an appropriate level. In other words, if the bypass capacitor 41 is normal, as shown in FIG. 2, the level of the power supply voltage VDD, which decreases as the load current increases, does not fall below the level of the reference voltage Vref. In this case, the determination signal S output from the determination circuit 17 j The alarm signal S3 output from the alarm signal output circuit 18 is maintained at a low level, which indicates that the bypass capacitor 41 is normal.

[0028] On the other hand, if a fault such as leakage occurs in the bypass capacitor 41, the fluctuation range of the power supply voltage VDD accompanying fluctuations in the load current becomes larger than in normal cases, and the time until the level of the power supply voltage VDD returns to an appropriate level becomes longer than in normal cases. In other words, if a fault occurs in the bypass capacitor 41, the level of the power supply voltage VDD, which decreases with an increase in the load current, falls below the level of the reference voltage Vref, as shown in FIG. 3. The determination signal S output from the determination circuit 17 j and the alarm signal S3 output from the alarm signal output circuit 18 each transition to a high level, indicating that a failure has occurred in the bypass capacitor 41, at time t3 when the level of the power supply voltage VDD falls below the level of the reference voltage Vref. The alarm signal S3 is output from the output terminal 24 to the outside of the semiconductor device 10. In this way, the semiconductor device 10 can detect a failure in the bypass capacitor 41 when the power is turned on while the internal circuit 19 is in a pre-startup state.

[0029] 4 is a time chart showing an example of the operation of the semiconductor device 10 after the start-up of the internal circuit 19. After the start-up of the internal circuit 19, failure detection of the bypass capacitor 41 is performed in accordance with the failure detection program 21 executed by the internal circuit 19.

[0030] At time t11, the internal circuit 19 outputs an instruction signal S i The test signal S2 output from the test signal output circuit 12 is i In response to this, the reset signal S1 goes to a low level at time t11, and goes to a high level at time t12, a predetermined period of time after time t11. The reset signal S1 output from the power-on reset circuit 11 is maintained at a high level.

[0031] The pulse signal generating circuit 14 generates a single pulse signal S having a constant pulse width in response to the transition of the test signal S2 to a high level. p As a result, at time t12, the switch 32 of the load current control circuit 15 is turned on, and the load current increases. As the load current increases, the power supply voltage VDD applied to the power supply line L1 decreases. FIG. 4 shows a case where the bypass capacitor 41 is normal at time t12. If the bypass capacitor 41 is normal, the level of the power supply voltage VDD, which decreases as the load current increases, does not fall below the level of the reference voltage Vref. In this case, the determination signal S output from the determination circuit 17 j The alarm signal S3 output from the alarm signal output circuit 18 is maintained at a low level, which indicates that the bypass capacitor 41 is normal.

[0032] At time t13, when a predetermined period has elapsed since time t11, the internal circuit 19 outputs the instruction signal Si again. The test signal S2 output from the test signal output circuit 12 is i In response to this, the signal transitions to a low level at time t13, and transitions to a high level at time t14, when a predetermined period has elapsed since time t13.

[0033] The pulse signal generating circuit 14 generates a single pulse signal S having a constant pulse width in response to the transition of the test signal S2 to a high level. pAs a result, at time t14, the switch 32 of the load current control circuit 15 is turned on, and the load current increases. As the load current increases, the power supply voltage VDD applied to the power supply line L1 decreases. FIG. 4 shows a case where a failure occurs in the bypass capacitor 41 at time t14. When a failure occurs in the bypass capacitor 41, the level of the power supply voltage VDD, which decreases as the load current increases, falls below the level of the reference voltage Vref. The determination signal S output from the determination circuit 17 j and the alarm signal S3 output from the alarm signal output circuit 18 transition to a high level, indicating that a failure has occurred in the bypass capacitor 41, at time t15 when the level of the power supply voltage VDD falls below the level of the reference voltage Vref. j In response to this, failure information indicating that a failure has occurred in the bypass capacitor 41 is stored in the memory circuit 20. The alarm signal S3 is output from the output terminal 24 to the outside of the semiconductor device 10.

[0034] 5 is a flowchart showing an example of the flow of processing carried out in the internal circuit 19 as a result of the internal circuit 19 executing the fault detection program 21. The fault detection program 21 is executed after the internal circuit 19 is started up.

[0035] In step ST1, the internal circuit 19 determines whether it is time to detect a failure in the bypass capacitor 41. The internal circuit 19 determines the failure detection timing using its own timer function. If it is determined that it is time to detect a failure, the process proceeds to step ST2.

[0036] In step ST2, the internal circuit 19 outputs an instruction signal S i In response to this, the test signal output circuit 12, the pulse signal generating circuit 14, the load current control circuit 15, the reference voltage generating circuit 16, and the determination circuit 17 perform the operations illustrated in FIG.

[0037] In step ST3, the internal circuit 19 detects the detection signal S output from the determination circuit 17. j Whether or not a failure has occurred in the bypass capacitor 41 is determined based on the result of the comparison. If it is determined that a failure has occurred in the bypass capacitor 41, the process proceeds to step ST4, and if it is determined that no failure has occurred in the bypass capacitor 41, the process returns to step ST1.

[0038] In step ST4, the internal circuit 19 stores failure information indicating that a failure has occurred in the bypass capacitor 41 in the memory circuit 20. After that, the process returns to step ST1. i is repeatedly output at predetermined intervals, and thus the failure detection operation of the bypass capacitor 41 is repeatedly executed at predetermined intervals.

[0039] As described above, the semiconductor device 10 according to this embodiment includes the internal circuit 19, which operates by receiving power from the power supply line L1; the power-on reset circuit 11, which outputs a reset signal S1 indicating the timing of the rise of the power supply voltage VDD applied to the power supply line L1; the test signal output circuit 12, which outputs a test signal S2 indicating the timing specified by the internal circuit 19; the load current control circuit 15, which varies the load current flowing through the power supply line L1 based on the reset signal S1 and the test signal S2; and the determination circuit 17, which determines the level of the power supply voltage VDD. According to the semiconductor device 10 according to this embodiment, before the internal circuit 19 is started up, failure detection of the bypass capacitor 41 is performed using the reset signal S1 output from the power-on reset circuit 11 as a trigger signal. Furthermore, after the internal circuit 19 is started up, failure detection of the bypass capacitor 41 is performed at the timing specified by the internal circuit 19. That is, according to the semiconductor device 10 according to this embodiment, failure detection of the bypass capacitor 41 can be performed not only after the internal circuit 19 is started up but also before the internal circuit 19 is started up.

[0040] Furthermore, since the reset signal S1, which is the output signal of the power-on reset circuit 11, is used as a trigger signal for fault detection before the internal circuit 19 is started up, fault detection of the bypass capacitor 41 before the internal circuit 19 is started up can be realized by utilizing the existing power-on reset circuit 11.

[0041] Furthermore, since the fault detection of the bypass capacitor 41 is performed based on the instantaneous fluctuation of the power supply voltage that accompanies the fluctuation of the load current, the fault detection of the bypass capacitor 41 can be performed without resetting the internal circuit 19.

[0042] Furthermore, since the level of the reference voltage Vref is set to a level higher than the detection level Vd when the power-on reset circuit 11 detects the rising edge of the power supply voltage VDD, it becomes possible to detect a failure of the bypass capacitor 41 before the deterioration of the bypass capacitor 41 progresses to the point where the power-on reset is activated.

[0043] In this embodiment, the test signal output circuit 12 is configured as a circuit separate from the internal circuit 19, but the test signal output circuit 12 may be included in the internal circuit 19. That is, the internal circuit 19 may have a function of outputting the test signal S2. In addition, in this embodiment, the bypass capacitor 11 is provided outside the semiconductor device 10, but the bypass capacitor 11 may be provided inside the semiconductor device 10. In addition, in this embodiment, the fault information is stored in the memory circuit 20 included in the internal circuit 19, but the fault information may be stored in a memory circuit separate from the memory circuit 20 included in the internal circuit 19.

[0044] 6 is a diagram showing an example of the configuration of the reference voltage generating circuit 16 and the determination circuit 17. The reference voltage generating circuit 16 may be configured to include a current source 51 and a resistive element 52. One end of the current source 51 is connected to a power supply line L1, and the other end is connected to one end of the resistive element 52. The other end of the resistive element 52 is connected to a ground line L2. A reference voltage Vref is output from a node n1, which is the connection point between the current source 51 and the resistive element 52. The level of the reference voltage Vref can be set to any level by adjusting the resistance value of the resistive element 52.

[0045] The determination circuit 17 may be configured to include resistance elements 61 and 62 and a comparator 63. One end of the resistance element 61 is connected to a power supply line L1, and the other end is connected to one end of the resistance element 62. The other end of the resistance element 62 is connected to a ground line L2. A voltage obtained by dividing the power supply voltage VDD in accordance with the resistance ratio of these resistance elements is output from a node n2, which is the connection point between the resistance elements 61 and 62.

[0046] One input terminal of the comparator 63 is connected to the node n1, and a reference voltage Vref is input to this input terminal. The other input terminal of the comparator 63 is connected to the node n2, and a voltage obtained by dividing the power supply voltage VDD is input to this input terminal. The output terminal of the comparator 63 outputs a decision signal S indicating the result of comparing the level of the reference voltage Vref with the level of the voltage obtained by dividing the power supply voltage VDD. j In the configuration shown in Fig. 6, the power supply voltage VDD may be either a positive voltage or a negative voltage.

[0047] FIG. 7 is a diagram showing another example of the configuration of the reference voltage generating circuit 16 and the determination circuit 17. The reference voltage generating circuit 16 may be configured to include resistive elements 53 and 54, a switch 55, and a capacitor 56. The resistive element 53 has one end connected to the power supply line L1 and the other end connected to one end of the resistive element 54. The other end of the resistive element 54 is connected to the ground line L2. A voltage obtained by dividing the power supply voltage VDD in accordance with the resistance ratio of these resistive elements is output from a node n3, which is the connection point between the resistive elements 53 and 54. The switch 55 has one end connected to the node n3 and the other end connected to one end of a capacitor 56. The other end of the capacitor 56 is connected to the ground line L2. The switch 55 and the capacitor 56 form a sample-and-hold circuit. The switch 55 is connected to the control signal S output from the AND circuit 13. 12 7. That is, the switch 55 is turned off just before the load current control circuit 15 changes the load current, and remains on at a timing before that. As a result, a voltage obtained by dividing the power supply voltage VDD just before the load current changes is held by the capacitor 56. The held voltage is output as a reference voltage Vref from a node n4, which is the connection point between the switch 55 and the capacitor 56. The configuration of the determination circuit 17 is the same as that shown in FIG. 6, so a description thereof will be omitted. In the configuration shown in FIG. 7, the power supply voltage VDD may be a positive voltage or a negative voltage.

[0048] 8 is a diagram showing another example of the configuration of the reference voltage generating circuit 16 and the determination circuit 17. The reference voltage generating circuit 16 may be configured to include a switch 58 and a capacitor 57. One end of the switch 58 is connected to the power supply line L1, and the other end is connected to one end of the capacitor 57. The other end of the capacitor 57 is connected to the ground line L2. The switch 58 and the capacitor 57 form a sample-and-hold circuit. The switch 58 is connected to the control signal S output from the AND circuit 13. 12That is, switch 58 is turned off just before load current control circuit 15 changes the load current, and remains on at a timing before that. As a result, the power supply voltage VDD at the timing just before the load current changes is held by capacitor 57. The held voltage is output as reference voltage Vref from node n5, which is the connection point between switch 58 and capacitor 57.

[0049] The determination circuit 17 may be configured to include a p-channel transistor 64, a capacitor 65, and a switch 66. The transistor 64 has a source connected to the node n5, a gate connected to the power supply line L1, and a drain connected to one end of the capacitor 65. The other end of the capacitor 65 is connected to the ground line L2. The switch 66 is connected in parallel with the capacitor 65. The switch 66 is connected to the control signal S output from the AND circuit 13. 12 The on / off timing of switch 66 is the same as that of switch 58.

[0050] When the level difference between the power supply voltage VDD supplied to the gate and the reference voltage Vref supplied to the source exceeds the gate threshold voltage of the transistor 64, the transistor 64 turns on and the capacitor 65 is charged. It is preferable that the capacitor 57 that holds the reference voltage Vref has a capacitance sufficient to charge the capacitor 65. The charging voltage of the capacitor 65 is a voltage that is supplied to the determination signal S j is output from a node n6 which is a connection point between the transistor 64 and the capacitor 65. The determination circuit 17 according to this embodiment compares the level of the power supply voltage VDD immediately before the load current fluctuates with the level of the power supply voltage VDD which has dropped as the load current increases, and when the difference between the two exceeds the gate threshold voltage of the transistor 64, the transistor 64 turns on, and a determination signal S j will be output.

[0051] The switch 66 is in the on state until just before the load current changes, so that the charge accumulated in the capacitor 65 is discharged, and the determination signal S j is reset. The switch 66 is turned off just before the load current changes, and the capacitor 65 is placed in a state where it can be charged. The transistor 64 is an example of the "first transistor" in the present invention.

[0052] 8 is based on the assumption that the power supply voltage VDD is a positive voltage. When the power supply voltage VDD is a negative voltage, the transistor 64 is an n-channel transistor.

[0053] FIG. 9 is a diagram showing another example of the configuration of the reference voltage generating circuit 16 and the determination circuit 17. In the configuration shown in FIG. 9, the switch 58 in FIG. 8 is configured with a p-channel transistor 59, and the switch 66 in FIG. 8 is configured with an n-channel transistor 67 and an inverter 68. The gate of the transistor 59 is connected to the output terminal of the AND circuit 13. To prevent the charge stored in the capacitor 57 from leaking to the power supply line L1 through the transistor 59 before the transistor 64 is turned on, the gate threshold voltage of the transistor 59 is preferably higher than the gate threshold voltage of the transistor 64. For example, by making the gate length of the transistor 59 longer than the gate length of the transistor 64, the gate threshold voltage of the transistor 59 can be made higher than the gate threshold voltage of the transistor 64. The transistor 59 is an example of a "second transistor" in the present invention.

[0054] The transistor 67 has a drain connected to the node n6, a source connected to the ground line L2, and a gate connected to the output terminal of the inverter 68. The input terminal of the inverter 68 is connected to the output terminal of the AND circuit 13. [Explanation of symbols]

[0055] 10 Semiconductor devices 11 Power-on reset circuit 12 Test signal output circuit 13 AND Circuit 14 Pulse signal generating circuit 15 Load current control circuit 16 Reference voltage generation circuit 17 Judgment circuit 18 Alarm signal output circuit 19 Internal circuit 20 Memory circuit 21 Fault detection program 31 Resistor element 32 Switch 40 DC power supply 41 Bypass capacitor 51 Current source 52, 53, 54, 61, 62 Resistor elements 55, 58, 66 switches 56, 57, 65 capacitors 59, 64, 67 transistors 63 Comparator 68 Inverter L1 power line L2 Grand Line S1 reset signal S2 test signal S3 alarm signal

Claims

1. an internal circuit that operates by receiving power from the power line; a first signal output circuit that outputs a first signal that indicates the timing of a rise of a power supply voltage applied to the power supply line; a second signal output circuit that outputs a second signal indicating a timing designated by the internal circuit; a load current control circuit that varies a load current flowing through the power supply line based on the first signal and the second signal; a determination circuit for determining the level of the power supply voltage; A semiconductor device comprising:

2. The internal circuit performs a reset operation based on the first signal. The semiconductor device according to claim 1 .

3. a pulse signal generating circuit that generates a pulse signal at a timing when the level of the first signal or the second signal transitions; The load current control circuit varies the load current in response to the pulse signal.

3. The semiconductor device according to claim 1.

4. the load current control circuit includes a series circuit connected to the power supply line and having a resistor element and a switch; When the switch is turned on, the load current increases. The semiconductor device according to claim 1 .

5. The determination circuit outputs a determination signal indicating the result of comparing the level of the power supply voltage with the level of a reference voltage. The semiconductor device according to claim 1 .

6. a third signal output circuit that outputs a third signal generated based on the determination signal; The semiconductor device according to claim 5 .

7. a memory circuit for storing information indicated by the determination signal; 7. The semiconductor device according to claim 5.

8. The load current control circuit includes a reference voltage generation circuit that holds a voltage corresponding to the power supply voltage at a timing immediately before the load current is changed and generates the held voltage as the reference voltage.

8. The semiconductor device according to claim 5, wherein the first insulating film is a semiconductor substrate.

9. The determination circuit a first transistor having a gate to which the power supply voltage is supplied and a source to which the reference voltage is supplied; 9. The semiconductor device according to claim 5, wherein the first insulating film is a semiconductor substrate.

10. The determination circuit a first transistor having a gate to which the power supply voltage is supplied and a source to which the reference voltage is supplied; The reference voltage generating circuit a second transistor having a source connected to the power supply line and a drain connected to the source of the first transistor, the second transistor being turned off immediately before the load current control circuit changes the load current; a capacitor having one end connected to the drain of the second transistor; Including, The threshold voltage of the second transistor is higher than the threshold voltage of the first transistor. The semiconductor device according to claim 8 .

11. the first signal undergoes a level transition when the level at the time of rise of the power supply voltage reaches a predetermined detection level; The level of the reference voltage is higher than the detection level. The semiconductor device according to any one of claims 5 to 10.

12. a bypass capacitor connected to the power supply line The semiconductor device according to claim 1 .

13. A method for detecting a fault in a bypass capacitor connected to a power supply line, comprising: a load current flowing through the power supply line is varied at a timing when a power supply voltage applied to the power supply line rises and at a timing designated by an internal circuit that operates by receiving power from the power supply line; The presence or absence of a fault in the bypass capacitor is determined based on the level of the power supply voltage when the load current is varied. Fault detection methods.

14. The load current is varied based on a first signal indicating the timing of the rise of the power supply voltage and a second signal indicating the timing specified by the internal circuit.

14. The fault detection method of claim 13.

15. If the level of the power supply voltage when the load current is varied is lower than the level of a reference voltage, a third signal indicating that a failure has occurred in the bypass capacitor is output.

15. A fault detection method according to claim 13 or claim 14.

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