Semiconductor device and manufacturing method thereof

Abstract

To provide a technology that can stabilize the characteristics of semiconductor devices.SOLUTION: A semiconductor device has a semiconductor substrate provided with a semiconductor section, which is at least one of a gate insulating film, a pn junction, and a drift layer in a termination region, an insulating film provided over the semiconductor section, a metal electrode having an aperture overlapping the semiconductor section in plan view and provided on the opposite side of the semiconductor section with respect to the insulating film in cross-sectional view, and a plating electrode provided in at least part of the aperture using the metal electrode as a plating material.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] A semiconductor device has been proposed in which an IGBT (Insulated Gate Bipolar Transistor) region and a diode region are provided on a single semiconductor substrate, and in which barrier metal that prevents metal diffusion from the electrodes of the IGBT and the diode is omitted (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2022-56498 Summary of the Invention [Problem to be solved by the invention]

[0004] In semiconductor devices that do not include a barrier metal, high-temperature heat treatment cannot be performed after electrode formation to prevent metal diffusion. This leaves energy levels at the interface between silicon and an insulating film, such as an oxide film, and at pn junctions, such as polysilicon grain boundaries, resulting in unstable semiconductor device characteristics. Even in semiconductor devices that do include a barrier metal, the same problem can occur if the barrier metal's functionality is insufficient due to factors such as a thin barrier metal.

[0005] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique that can stabilize the characteristics of a semiconductor device. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes a semiconductor substrate provided with a semiconductor portion, which is at least one of a gate insulating film, a pn junction portion, and a drift layer in a termination region; an insulating film provided on the semiconductor portion; a metal electrode that overlaps the semiconductor portion in a plan view and has an opening provided on the opposite side of the semiconductor portion with respect to the insulating film in a cross-sectional view; and a plating electrode that uses the metal electrode as a material to be plated and is provided in at least a part of the opening. The semiconductor portion includes the pn junction portion provided in a temperature sensing diode region of the semiconductor substrate, and at least a part of the lower surface of the plating electrode is in direct contact with the insulating film. do. [Effects of the Invention]

[0007] According to the present disclosure, a plating electrode is provided in an opening of a metal electrode that overlaps with a semiconductor portion in a plan view and is provided on the opposite side of the insulating film from the semiconductor portion in a cross-sectional view. With this configuration, it is possible to stabilize the characteristics of the semiconductor device. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 4 is a plan view showing another configuration of the semiconductor device according to the first embodiment. [Figure 3] 2 is a partially enlarged plan view showing the configuration of an IGBT region of the semiconductor device according to the first embodiment. FIG. [Figure 4] 1 is a cross-sectional view showing a configuration of an IGBT region of a semiconductor device according to a first embodiment. [Figure 5] 1 is a cross-sectional view showing a configuration of an IGBT region of a semiconductor device according to a first embodiment. [Figure 6] 2 is a partially enlarged plan view showing the configuration of a diode region of the semiconductor device according to the first embodiment. FIG. [Figure 7] 2 is a cross-sectional view showing the configuration of a diode region of the semiconductor device according to the first embodiment. FIG. [Figure 8] 2 is a cross-sectional view showing the configuration of a diode region of the semiconductor device according to the first embodiment. FIG. [Figure 9]2 is a cross-sectional view showing the configuration of a boundary region between an IGBT region and a diode region of the semiconductor device according to the first embodiment. FIG. [Figure 10] 2 is a cross-sectional view showing the configuration of a termination region of the semiconductor device according to the first embodiment. FIG. [Figure 11] 2 is a cross-sectional view showing the configuration of a termination region of the semiconductor device according to the first embodiment. FIG. [Figure 12] 2A to 2C are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 2A to 2C are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 2A to 2C are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] 2A to 2C are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 16] 2A to 2C are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 17] 2A to 2C are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 18] 3 is a flowchart showing a part of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 19] FIG. 10 is a plan view showing the configuration of a semiconductor device according to a second embodiment. [Figure 20] FIG. 10 is a cross-sectional view showing a configuration of a temperature sensing diode region of a semiconductor device according to a second embodiment. [Figure 21] 10 is a flowchart showing a part of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 22] FIG. 11 is a cross-sectional view showing a configuration of a temperature sensing diode region of a semiconductor device according to a third embodiment. [Figure 23] FIG. 10 is a cross-sectional view showing the configuration of a termination region of a semiconductor device according to a fourth embodiment. [Figure 24] FIG. 11 is a cross-sectional view showing the configuration of a termination region of a semiconductor device according to a fifth embodiment. [Figure 25] FIG. 13 is a cross-sectional view showing the configuration of a termination region of a semiconductor device according to a sixth embodiment. [Figure 26]FIG. 10 is a cross-sectional view showing a configuration of a termination region of a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the accompanying drawings. The features described in each of the following embodiments are merely examples, and not all features are necessarily required. In the following description, similar components in multiple embodiments are denoted by the same or similar reference numerals, and different components will be mainly described. In the following description, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" do not necessarily correspond to the positions and directions in actual implementation. In addition, a portion having a higher concentration than another portion means, for example, that the average concentration of the portion is higher than the average concentration of the other portion. Conversely, a portion having a lower concentration than another portion means, for example, that the average concentration of the portion is lower than the average concentration of the other portion. In the following description, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. In addition, n - indicates that the impurity concentration is lower than n, and n + indicates that the impurity concentration is higher than n. Similarly, p - indicates that the impurity concentration is lower than p, and p + indicates that the impurity concentration is higher than p.

[0010] <First Embodiment> FIG. 1 is a plan view showing a semiconductor device that is an RC-IGBT (Reverse Conducting IGBT). FIG. 2 is a plan view showing another configuration of the semiconductor device that is an RC-IGBT according to the first embodiment. The semiconductor device 100 shown in FIG. 1 has IGBT regions 10 and diode regions 20 arranged side by side in a stripe pattern, and may be referred to simply as a "stripe type" in the following description. The semiconductor device 100 shown in FIG. 2 has a plurality of diode regions 20 arranged vertically and horizontally, and the IGBT regions 10 are arranged around the diode regions 20, and may be referred to simply as an "island type" in the following description.

[0011] <Stripe-type overall planar structure> In FIG. 1 , a semiconductor device 100 includes an IGBT region 10 and a diode region 20. The IGBT region 10 and the diode region 20 extend from one end to the other end of the semiconductor device 100 and are alternately arranged in stripes in a direction perpendicular to the direction in which the IGBT region 10 and the diode region 20 extend. In FIG. 1 , three IGBT regions 10 and two diode regions 20 are shown, and all of the diode regions 20 are sandwiched between the IGBT regions 10. However, the number of IGBT regions 10 and the diode regions 20 is not limited thereto. The number of IGBT regions 10 may be three or more or less, and the number of diode regions 20 may be two or more or less. Alternatively, the positions of the IGBT regions 10 and the diode regions 20 in FIG. 1 may be interchanged, or all of the IGBT regions 10 may be sandwiched between the diode regions 20. Alternatively, one IGBT region 10 and one diode region 20 may be provided adjacent to each other.

[0012] As shown in FIG. 1 , a pad region 40 is provided adjacent to the IGBT region 10 on the lower side of the drawing. The pad region 40 is a region where a control pad 41 for controlling the semiconductor device 100 is provided. In the following description, the IGBT region 10 and the diode region 20 are sometimes collectively referred to as the cell region. A termination region 30 is provided around the combined cell region and pad region 40 to maintain the breakdown voltage of the semiconductor device 100. A well-known breakdown voltage maintaining structure may be appropriately provided in the termination region 30. The breakdown voltage maintaining structure may include, for example, a field limiting ring (FLR) that surrounds the cell region with a p-type termination well layer of a p-type semiconductor, or a variation of lateral doping (VLD) that surrounds the cell region with a p-type well layer with a concentration gradient, provided on the first main surface side, which is the front surface side of the semiconductor device 100. The number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 100. In addition, a p-type termination well layer may be provided over almost the entire area of ​​the pad region 40, and an IGBT cell or a diode cell may be provided in the pad region 40.

[0013] The control pads 41 include, for example, at least one of a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sense diode pads 41d and 41e.

[0014] The current sense pad 41a is a control pad for detecting a current flowing in a cell region of the semiconductor device 100. When a current flows in a cell region of the semiconductor device 100, the current sense pad 41a is electrically connected to the cell region so that a current that is one-several to one-tens-of-thousandths of the current flowing in the entire cell region flows through a portion of the IGBT cells or diode cells in the cell region.

[0015] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage is applied for controlling the on / off of the semiconductor device 100. The Kelvin emitter pad 41b is electrically connected to the p-type base layer of the IGBT cell. The gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer are connected to each other. + The temperature sensing diode pads 41d and 41e may be electrically connected to the anode and cathode of a temperature sensing diode provided in the semiconductor device 100 via a mold contact layer. The temperature sensing diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sensing diode (not shown) provided in the cell region. The voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region is measured via the temperature sensing diode pads 41d and 41e, and the temperature of the semiconductor device 100 is measured based on the voltage.

[0016] <Island-type overall planar structure> 2, the semiconductor device 100 includes an IGBT region 10 and a diode region 20 within the semiconductor device. A plurality of diode regions 20 are arranged side by side in both the vertical and horizontal directions within the semiconductor device 100, and the periphery of each diode region 20 is surrounded by the IGBT region 10. In other words, a plurality of diode regions 20 are arranged in an island shape within the IGBT region 10. FIG. 2 shows a configuration in which the diode regions 20 are arranged in a matrix shape with four columns in the horizontal direction of the page and two rows in the vertical direction of the page. However, the number and arrangement of the diode regions 20 are not limited to this, and it is sufficient that one or a plurality of diode regions 20 are arranged in a scattered manner within the IGBT region 10, and each diode region 20 is surrounded by the IGBT region 10.

[0017] As shown in FIG. 2 , a pad region 40 is provided adjacent to the lower side of the IGBT region 10. The pad region 40 is a region where a control pad 41 for controlling the semiconductor device 100 is provided. In this description, the IGBT region 10 and the diode region 20 are collectively referred to as the cell region. A termination region 30 is provided around the combined region of the cell region and the pad region 40 to maintain the breakdown voltage of the semiconductor device 100. A well-known breakdown voltage support structure may be appropriately provided in the termination region 30. The breakdown voltage support structure may include, for example, an FLR, which surrounds the combined region of the cell region and the pad region 40 with a p-type termination well layer of a p-type semiconductor, or a VLD, which surrounds the cell region with a p-type well layer with a concentration gradient, provided on the first main surface side, which is the front surface side of the semiconductor device 100. The number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 100. In addition, a p-type termination well layer may be provided over almost the entire area of ​​the pad region 40, and an IGBT cell or a diode cell may be provided in the pad region 40.

[0018] The control pads 41 include, for example, at least one of a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sense diode pads 41d and 41e.

[0019] The current sense pad 41a is a control pad for detecting a current flowing in a cell region of the semiconductor device 100. When a current flows in a cell region of the semiconductor device 100, the current sense pad 41a is electrically connected to the cell region so that a current that is one-several to one-tens-of-thousandths of the current flowing in the entire cell region flows through a portion of the IGBT cells or diode cells in the cell region.

[0020] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage for on / off control of the semiconductor device 100 is applied. The Kelvin emitter pad 41b is electrically connected to the p-type base layer and the n+-type source layer of the IGBT cell. The gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer may be electrically connected via a p + type contact layer. The temperature sense diode pads 41d, 41e are control pads electrically connected to the anode and the cathode of the temperature sense diode provided in the semiconductor device 100. The voltage between the anode and the cathode of a temperature sense diode (not shown) provided in the cell region is measured via the temperature sense diode pads 41d, 41e, and the temperature of the semiconductor device 100 is measured based on the voltage.

[0021] <IGBT region 10> FIG. 3 is a partially enlarged plan view showing the configuration of the IGBT region 10 of a semiconductor device that is an RC-IGBT. Specifically, FIG. 3 is a view showing an enlarged view of the region surrounded by the broken line 82 in the semiconductor device 100 shown in FIGS. 1 and 2.

[0022] Also, FIGS. 4 and 5 are cross-sectional views showing the configuration of the IGBT region 10 of a semiconductor device that is an RC-IGBT. Specifically, FIG. 4 is a cross-sectional view taken along the dashed-dotted line A-A of the semiconductor device 100 shown in FIG. 3, and FIG. 5 is a cross-sectional view taken along the dashed-dotted line B-B of the semiconductor device 100 shown in FIG. 3.

[0023] 3, active trench gates 11 and dummy trench gates 12 are provided in a striped pattern in the IGBT region 10. In the semiconductor device 100 of FIG. 1, the active trench gates 11 and dummy trench gates 12 extend in the longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 corresponds to the longitudinal direction of the active trench gates 11 and dummy trench gates 12. On the other hand, in the semiconductor device 100 of FIG. 2, there is no particular distinction between the longitudinal direction and the lateral direction of the IGBT region 10, and the left-right direction on the page may correspond to the longitudinal direction of the active trench gates 11 and dummy trench gates 12, or the up-down direction on the page may correspond to the longitudinal direction of the active trench gates 11 and dummy trench gates 12.

[0024] The active trench gate 11 is configured by providing a gate trench electrode 11a in a trench in a semiconductor substrate via a gate trench insulating film 11b, which is a gate insulating film. The gate trench insulating film 11b is included in the semiconductor portion. The gate trench insulating film 11b is made of, for example, an oxide film. The dummy trench gate 12 is configured by providing a dummy trench electrode 12a in a trench in the semiconductor substrate via a dummy trench insulating film 12b. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c in FIGS. 1 and 2. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 100.

[0025] As shown in Figure 3, n + The source layer 13 is provided on both sides of the active trench gate 11 in the width direction so as to contact the gate trench insulating film 11b. + The source layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+17 / cm 3 ~1.0E+20 / cm 3 n + The p-type source layer 13 is formed along the extension direction of the active trench gate 11. +The p-type contact layer 14 is formed alternately. + The contact layer 14 is provided between two adjacent dummy trench gates 12 in contact with the dummy trench insulating film 12b. + The contact layer 14 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is, for example, 1.0E+15 / cm 3 ~1.0E+20 / cm 3 is.

[0026] As shown in FIG. 3 , in the IGBT region 10 of the semiconductor device 100, three dummy trench gates 12 are arranged next to three active trench gates 11. Next to the three dummy trench gates 12, three other active trench gates 11 are arranged. In this manner, the IGBT region 10 is configured such that pairs of active trench gates 11 and pairs of dummy trench gates 12 are arranged alternately. While the number of active trench gates 11 included in one pair of active trench gates 11 is three in FIG. 3 , it is sufficient that the number is one or more. Furthermore, the number of dummy trench gates 12 included in one pair of dummy trench gates 12 may be one or more, or may be zero. That is, all of the trench gates provided in the IGBT region 10 may be active trench gates 11.

[0027] 4 is a cross-sectional view of the semiconductor device 100 taken along the dashed line AA in FIG. 3, and is a cross-sectional view of the IGBT region 10. The semiconductor device 100 is an n-type semiconductor device made of a semiconductor substrate. - The n-type drift layer 1 is - The drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+12 / cm 3 ~1.0E+15 / cm 3 In addition, the above-mentioned n + The concentration of n-type impurities in the n-type source layer 13 is - The concentration of n-type impurities in the n-type drift layer 1 is higher than that in the n-type drift layer 2.

[0028] The range of the semiconductor substrate is n in FIG. + The source layer 13 and the p + The range is from the p-type contact layer 14 to the p-type collector layer 16. + The source layer 13 and the p + The upper end of the p-type contact layer 14 on the paper surface is called the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the paper surface is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device 100, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 100. In the IGBT region 10 of the cell region, the semiconductor device 100 has an n-type contact layer between the first main surface and the second main surface opposite to the first main surface. - The semiconductor substrate has a type drift layer 1. The semiconductor substrate may be configured to include at least one of a wafer and an epitaxial growth layer. The semiconductor substrate may also include a wide bandgap semiconductor (silicon carbide (SiC), gallium nitride (GaN), or diamond) that can operate stably at high temperatures.

[0029] As shown in FIG. 4, in the IGBT region 10, n - On the first main surface side of the n-type drift layer 1, - The n-type carrier accumulation layer 2 has a higher concentration of n-type impurities than the n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+13 / cm 3 ~1.0E+17 / cm 3 In the semiconductor device 100, the n-type carrier accumulation layer 2 is not provided, and the n-type carrier accumulation layer 2 shown in FIG. - The n-type drift layer 1 may be provided. By providing the n-type carrier accumulation layer 2, it is possible to reduce the current loss when a current flows through the IGBT region 10. - The combined layer and the type drift layer 1 may be called a drift layer.

[0030] The n-type carrier accumulation layer 2 is -n-type impurities are ion-implanted into the semiconductor substrate that constitutes the n-type drift layer 1, and then annealed to convert the implanted n-type impurities into n-type impurities. - The dopant is formed by diffusing it into the semiconductor substrate, which is the type drift layer 1.

[0031] A p-type base layer 15 is provided on the first main surface side of the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+12 / cm 3 ~1.0E+19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11 b of the active trench gate 11 .

[0032] In a part of the first main surface side of the p-type base layer 15, there is provided an n-type insulating film 11b in contact with the gate trench insulating film 11b of the active trench gate 11. + The p-type source layer 13 is provided, and the remaining region of the p-type base layer 15 on the first main surface side is provided with p + A metal contact layer 14 is optionally provided. + The source layer 13 and the p + The p-type contact layer 14 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 14 is a region having a higher concentration of p-type impurities than the p-type base layer 15. + When it is necessary to distinguish between the p-type contact layer 14 and the p-type base layer 15, they may be called individually. + The p-type contact layer 14 and the p-type base layer 15 may be collectively referred to as a p-type base layer.

[0033] In addition, n of the semiconductor device 100 - The second main surface side of the n-type drift layer 1 - The n-type buffer layer 3 has a higher concentration of n-type impurities than the p-type drift layer 1. The n-type buffer layer 3 is provided to prevent a depletion layer extending from the p-type base layer 15 toward the second main surface from punching through when the semiconductor device 100 is in an off state. The n-type buffer layer 3 is doped with, for example, phosphorus (P) or protons (H +) may be formed by injecting phosphorus (P) and protons (H + The n-type buffer layer 3 may be formed by implanting both the n-type impurity and the n-type impurity. The concentration of the n-type impurity in the n-type buffer layer 3 is, for example, 1.0E+12 / cm 3 ~1.0E+18 / cm 3 The semiconductor device 100 does not include the n-type buffer layer 3, and the n-type buffer layer 3 is formed in the region shown in FIG. - The n-type buffer layer 3 and the n-type drift layer 1 may be provided. - The combined layer and the type drift layer 1 may be called a drift layer.

[0034] A p-type collector layer 16 is provided on the second main surface side of the n-type buffer layer 3 of the semiconductor device 100. That is, the p-type collector layer 16 is - The p-type collector layer 16 is provided between the drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is, for example, 1.0E+16 / cm 3 ~1.0E+20 / cm 3 The p-type collector layer 16 forms the second main surface of the semiconductor substrate. The p-type collector layer 16 may be provided not only in the IGBT region 10 but also in the termination region 30. Furthermore, the p-type collector layer 16 may be provided so that a portion of it protrudes from the IGBT region 10 into the diode region 20.

[0035] As shown in FIG. 4, the IGBT region 10 of the semiconductor device 100 includes an n-type junction electrode 14 extending from the first main surface of the semiconductor substrate through the p-type base layer 15. - Trenches are provided that reach the n-type drift layer 1. Gate trench electrodes 11a are provided in some of the trenches via gate trench insulating films 11b, thereby forming active trench gates 11. The gate trench electrodes 11a are connected to the n-type drift layer 1 via the gate trench insulating films 11b. - The n-type drift layer 1 is opposed to the n-type drift layer 1. Dummy trench electrodes 12a are provided in some of the trenches via dummy trench insulating films 12b, thereby forming dummy trench gates 12. The dummy trench electrodes 12a are connected to the n-type drift layer 1 via the dummy trench insulating films 12b.- The semiconductor layer 1 faces the semiconductor layer 2 .

[0036] The gate trench insulating film 11b of the active trench gate 11 is formed on the p-type base layer 15 and the n-type + The active trench gate 11 is in contact with the p-type source layer 13. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11.

[0037] As shown in FIG. 4, an interlayer insulating film 4, which is an insulating film, is provided on the gate trench electrode 11a and gate trench insulating film 11b of the active trench gate 11. For example, an oxide film is used for the interlayer insulating film 4. A barrier metal 5 is provided on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided, and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), and more specifically, may be titanium nitride or TiSi, which is an alloy of titanium and silicon (Si). As shown in FIG. 4, the barrier metal 5 is made of n + Type source layer 13, p + ohmic contact with the contact layer 14 and the dummy trench electrode 12a, + Type source layer 13, p + The barrier metal 5 is electrically connected to the contact layer 14 and the dummy trench electrode 12a. On the other hand, the barrier metal 5 is electrically insulated from the gate trench electrode 11a by the interlayer insulating film 4.

[0038] An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 includes an aluminum electrode 6a, which is a metal electrode, and a plating electrode 6b. The material of the aluminum electrode 6a may be any material that is to be plated, and may be, for example, an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy).

[0039] The aluminum electrode 6a has an opening. The opening in the aluminum electrode 6a overlaps with the gate trench insulating film 11b of the active trench gate 11 in plan view. In plan view, the opening in the aluminum electrode 6a may overlap with the gate trench insulating film 11b and part of the trench, or may be provided along the trench so as to overlap with the entire gate trench insulating film 11b and the trench. In plan view, the opening in the aluminum electrode 6a may be a closed hole or an open hole whose end reaches the end of the aluminum electrode 6a. The above content regarding the opening is similar to other embodiments.

[0040] The opening of the aluminum electrode 6a is provided on the opposite side of the interlayer insulating film 4 from the gate trench insulating film 11b in cross section.

[0041] In the first embodiment, the plating electrode 6b is embedded in the opening of the aluminum electrode 6a, which serves as the material to be plated, and is provided on the aluminum electrode 6a. However, it is sufficient that the plating electrode 6b is provided in at least a portion of the opening of the aluminum electrode 6a. The plating electrode 6b is formed by, for example, electroless plating or electrolytic plating. The material of the plating electrode 6b may be, for example, nickel (Ni), or may contain nickel (Ni) and gold (Au). Nickel formed by electroless plating is sometimes referred to as NiP.

[0042] In the first embodiment, the entire lower surface of the plating electrode 6b in the opening is in direct contact with the interlayer insulating film 4. However, it is sufficient that at least a part of the lower surface of the plating electrode 6b is in direct contact with the interlayer insulating film 4, and for example, a part of the lower surface of the plating electrode 6b may be in direct contact with the interlayer insulating film 4.

[0043] According to the above-described configuration, hydrogen generated during the growth process of the plating electrode 6b and hydrogen in the grown plating electrode 6b pass through the interlayer insulating film 4 and are taken into the gate trench insulating film 11b at the opening of the aluminum electrode 6a. - Since dangling bonds corresponding to the interface state with silicon of the type drift layer 1 are terminated, it is possible to stabilize the threshold voltage (Vth) of the semiconductor device. In addition, by adjusting the aperture ratio of the opening with respect to the active trench gate 11, it is possible to adjust the amount of hydrogen supplied to the gate trench insulating film 11b, and therefore it is possible to adjust the threshold voltage of the semiconductor device.

[0044] Although not shown, a plating electrode 6b may be provided in an opening of the aluminum electrode 6a that overlaps with the dummy trench insulating film 12b of the dummy trench gate 12 in a plan view and is provided on the opposite side of the dummy trench insulating film 12b with respect to the interlayer insulating film 4 in a cross-sectional view.

[0045] If there is a fine region between adjacent interlayer insulating films 4 where the emitter electrode 6 cannot be filled well, a tungsten film, which has better filling properties than the emitter electrode 6, may be disposed in the fine region, and the emitter electrode 6 may be provided on the tungsten film. + Type source layer 13, p + An emitter electrode 6 may be provided on the contact layer 14 and the dummy trench electrode 12a. + The barrier metal 5 may be provided only on the n-type semiconductor layer such as the n-type source layer 13. The barrier metal 5 and the emitter electrode 6 may be collectively called the emitter electrode.

[0046] 4 shows a configuration in which the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12, but in the cross-sectional portion of Fig. 4, the interlayer insulating film 4 may be provided on the dummy trench electrode 12a of the dummy trench gate 12. When the interlayer insulating film 4 is provided on the dummy trench electrode 12a of the dummy trench gate 12 in the cross-sectional portion of Fig. 4, it is sufficient that the emitter electrode 6 and the dummy trench electrode 12a are electrically connected in another cross-sectional portion.

[0047] A collector electrode 7 is provided on the second main surface side of the p-type collector layer 16. Similar to the emitter electrode 6, the collector electrode 7 may be made of an aluminum alloy or multiple layers of an aluminum alloy and a plating film. The collector electrode 7 may have a different configuration from the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0048] 5 is a cross-sectional view of the semiconductor device 100 taken along the dashed line BB in FIG. 3, and is a cross-sectional view of the IGBT region 10. Unlike the cross-sectional portion taken along the dashed line AA in FIG. 4, the cross-sectional portion taken along the dashed line BB in FIG. 5 shows the n-type IGBT region 10, which is in contact with the active trench gate 11 and is provided on the first main surface side of the semiconductor substrate. + There is no n-type source layer 13. + The p-type source layer 13 is selectively provided on the first main surface side of the p-type base layer. + and a mold contact layer 14.

[0049] <Diode region 20> Fig. 6 is a partially enlarged plan view showing the configuration of the diode region 20 of the semiconductor device, which is an RC-IGBT. Specifically, Fig. 6 is an enlarged view of the region surrounded by the dashed line 83 in the semiconductor device 100 shown in Figs. 1 and 2.

[0050] 7 and 8 are cross-sectional views showing the configuration of the diode region 20 of the semiconductor device which is an RC-IGBT. Specifically, Fig. 7 is a cross-sectional view taken along dashed line CC of the semiconductor device 100 shown in Fig. 6, and Fig. 8 is a cross-sectional view taken along dashed line DD of the semiconductor device 100 shown in Fig. 6.

[0051] The diode trench gate 21 extends from one end of the diode region 20 in the cell region to the other opposing end along the first main surface of the semiconductor device 100. The diode trench gate 21 is configured by providing a diode trench electrode 21a in the trench of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a is connected to the n-type MOS transistor 100 via the diode trench insulating film 21b. - The semiconductor layer 1 faces the semiconductor layer 2 .

[0052] Between two adjacent diode trench gates 21, p + The p-type contact layer 24 and the p-type anode layer 25 having a lower concentration of p-type impurities than the p-type contact layer 24 are provided. + The contact layer 24 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is, for example, 1.0E+15 / cm 3 ~1.0E+20 / cm 3 The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+12 / cm 3 ~1.0E+19 / cm 3 p + The p-type contact layers 24 and the p-type anode layers 25 are alternately provided in the longitudinal direction of the diode trench gate 21 .

[0053] 7 is a cross-sectional view of the semiconductor device 100 taken along the dashed line CC in FIG. 6, and is a cross-sectional view of the diode region 20. In the semiconductor device 100, the diode region 20 is also an n-type semiconductor substrate, similar to the IGBT region 10. - The n-type drift layer 1 is formed in the diode region 20. -The n-type drift layer 1 and the IGBT region 10 - The layer 1 and the layer 2 are integrally formed and continuous with each other on the same semiconductor substrate.

[0054] The range of the semiconductor substrate is p + Type contact layer 24 to n + The area extends to the cathode layer 26. + The upper end of the n-type contact layer 24 on the paper surface is called the first main surface of the semiconductor substrate, and + The lower end of the cathode layer 26 in the drawing is called the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are included in the same plane, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are included in the same plane.

[0055] As shown in FIG. 7, in the diode region 20, similarly to the IGBT region 10, n - An n-type carrier accumulation layer 2 is provided on the first main surface side of the n-type drift layer 1, - An n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the diode region 20 may have the same configuration as the n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the IGBT region 10. Note that the n-type carrier accumulation layer 2 does not necessarily have to be provided in the IGBT region 10 and the diode region 20. For example, the n-type carrier accumulation layer 2 may be provided in the IGBT region 10 but not in the diode region 20. Also, like the IGBT region 10, the n-type carrier accumulation layer 2 and n-type buffer layer 3 may be provided in the diode region 20. - The n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 may be collectively referred to as a drift layer.

[0056] A p-type anode layer 25 is provided on the first major surface side of the n-type carrier accumulation layer 2. The p-type anode layer 25 is -The p-type anode layer 25 is provided between the first main surface and the first drift layer 1. The p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously by making the p-type impurity concentration of the p-type anode layer 25 the same as the p-type impurity concentration of the p-type base layer 15 of the IGBT region 10. Alternatively, the p-type impurity concentration of the p-type anode layer 25 may be made lower than the p-type impurity concentration of the p-type base layer 15 of the IGBT region 10 to reduce the number of holes injected into the diode region 20 during diode operation. Reducing the number of holes injected during diode operation can reduce recovery loss during diode operation.

[0057] The first main surface side of the p-type anode layer 25 is + A contact layer 24 is provided. + The concentration of the p-type impurity in the contact layer 24 is + The concentration of the p-type impurity in the contact layer 14 may be the same as or different from that in the p-type contact layer 14. + The p-type contact layer 24 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 24 is a region having a higher concentration of p-type impurities than the p-type anode layer 25. + When it is necessary to distinguish between the p-type contact layer 24 and the p-type anode layer 25, they may be called individually. + The p-type contact layer 24 and the p-type anode layer 25 may be collectively referred to as a p-type anode layer.

[0058] The second main surface side of the n-type buffer layer 3 of the semiconductor device 100 is + A type cathode layer 26 is provided. + The cathode layer 26 is - The n-type drift layer 1 is provided between the n-type drift layer 1 and the second main surface. + The cathode layer 26 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+16 / cm 3 ~1.0E+21 / cm 3 n +The cathode layer 26 is provided on part or all of the diode region 20. + The n-type cathode layer 26 constitutes the second main surface of the semiconductor substrate. + A p-type impurity may be further selectively implanted into a portion of the region where the p-type cathode layer 26 is formed, to provide a p-type cathode layer which is a p-type semiconductor.

[0059] As shown in FIG. 7, the diode region 20 of the semiconductor device 100 includes an n-type anode layer 25 extending from the first main surface of the semiconductor substrate. - A trench is provided in the diode region 20, reaching the n-type drift layer 1. A diode trench electrode 21a is provided in the trench of the diode region 20 via a diode trench insulating film 21b, thereby forming a diode trench gate 21. The diode trench electrode 21a is connected to the n-type drift layer 1 via the diode trench insulating film 21b. - The semiconductor layer 1 faces the semiconductor layer 2 .

[0060] As shown in FIG. 7, the diode trench electrodes 21a and p + A barrier metal 5 is provided on the contact layer 24. The barrier metal 5 is a metal that covers the diode trench electrode 21a and the p + The diode trench electrodes 21a and p + The barrier metal 5 is electrically connected to the contact layer 24. The barrier metal 5 may have the same structure as the barrier metal 5 in the IGBT region .

[0061] An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is configured to be continuous with the emitter electrode 6 provided in the IGBT region 10. Although not shown, similar to the case of the IGBT region 10, the emitter electrode 6 in the diode region 20 may include an aluminum electrode 6a and a plating electrode 6b. The plating electrode 6b may be provided in an opening of the aluminum electrode 6a that overlaps with the diode trench insulating film 21b in a plan view and is provided on the opposite side of the diode trench insulating film 21b with respect to the interlayer insulating film 4 in a cross-sectional view. For convenience, in Figure 7 and subsequent figures, a single emitter electrode 6 may be illustrated regardless of whether the emitter electrode 6 includes the aluminum electrode 6a and the plating electrode 6b. Note that a single emitter electrode 6 may be illustrated without providing the barrier metal 5, and the diode trench electrode 21a and the plating electrode 6b may be provided in an opening of the aluminum electrode 6a that overlaps with the diode trench insulating film 21b in a plan view and is provided on the opposite side of the diode trench insulating film 21b with respect to the interlayer insulating film 4 in a cross-sectional view. + The mold contact layer 24 and the emitter electrode 6 may be in ohmic contact.

[0062] 7 shows a configuration in which the interlayer insulating film 4 as in FIG. 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, but the interlayer insulating film 4 may be provided on the diode trench electrode 21a in the cross-sectional portion of FIG. 7. When the interlayer insulating film 4 is provided on the diode trench electrode 21a of the diode trench gate 21 in the cross-sectional portion of FIG. 7, it is sufficient that the emitter electrode 6 and the diode trench electrode 21a are electrically connected in another cross-sectional portion.

[0063] n + A collector electrode 7 is provided on the second principal surface side of the cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 is an n + ohmic contact with the n-type cathode layer 26, + The cathode layer 26 is electrically connected to the cathode layer 26 .

[0064] FIG. 8 is a cross-sectional view taken along the dash-dotted line D-D in FIG. 6 of the semiconductor device 100 and is a cross-sectional view of the diode region 20. Different from the cross-sectional portion along the dash-dotted line C-C shown in FIG. 7, in the cross-sectional portion along the dash-dotted line D-D in FIG. 8, a p + -type contact layer 24 is not provided between the p-type anode layer 25 and the barrier metal 5, and the p-type anode layer 25 is the first main surface of the semiconductor substrate. That is, the p + -type contact layer 24 shown in FIG. 7 is selectively provided on the first main surface side of the p-type anode layer 25.

[0065] <Configuration of the boundary region between the IGBT region 10 and the diode region 20> FIG. 9 is a cross-sectional view showing the configuration of the boundary region between the IGBT region 10 and the diode region 20 of a semiconductor device that is an RC-IGBT. Specifically, FIG. 9 is a cross-sectional view taken along the dash-dotted line E-E in the semiconductor device 100 shown in FIGS. 1 and 2.

[0066] As shown in FIG. 9, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 and the n + -type cathode layer 26 provided on the second main surface side of the diode region 20 are adjacent to each other in the in-plane direction of the semiconductor substrate. And the p-type collector layer 16 is provided so as to protrude toward the diode region 20 by a distance U1 from the boundary between the IGBT region 10 and the diode region 20.

[0067] Thus, by providing the p-type collector layer 16 to protrude into the diode region 20, the distance between the n + -type cathode layer 26 of the diode region 20 and the active trench gate 11 can be increased. Therefore, even when a gate drive voltage is applied to the gate trench electrode 11a during the operation of the freewheeling diode, current flowing from the channel formed adjacent to the active trench gate 11 of the IGBT region 10 to the n + -type cathode layer 26 can be suppressed. The distance U1 may be, for example, 100 μm. Depending on the application of the semiconductor device 100 that is an RC-IGBT, the distance U1 may be zero or a distance smaller than 100 μm.

[0068] <Terminal area 30> 10 and 11 are cross-sectional views showing the configuration of the termination region 30 of the semiconductor device 100, which is an RC-IGBT. Specifically, Fig. 10 is a cross-sectional view taken along dashed line FF in Fig. 1 or 2, and is a cross-sectional view from the IGBT region 10 to the termination region 30. Fig. 11 is a cross-sectional view taken along dashed line GG in Fig. 1, and is a cross-sectional view from the diode region 20 to the termination region 30.

[0069] As shown in FIGS. 10 and 11, the termination region 30 of the semiconductor device 100 has n-type junctions between the first and second main surfaces of the semiconductor substrate. - The n-type drift layer 1 is formed in the termination region 30. The first and second main surfaces of the termination region 30 are included in the same plane as the first and second main surfaces of the IGBT region 10 and the diode region 20, respectively. - The n-type drift layer 1 is formed in the IGBT region 10 and the diode region 20. - It has the same structure as the drift layer 1 and is integrally formed continuously.

[0070] n - The first main surface of the n-type drift layer 1, i.e., the first main surface of the semiconductor substrate and - A p-type termination well layer 31 is selectively provided between the n-type drift layer 1 and the n-type drift layer 1. The p-type termination well layer 31 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+14 / cm 3 ~1.0E+19 / cm 3 The p-type termination well layer 31 is provided to surround the cell region including the IGBT region 10 and the diode region 20. The p-type termination well layer 31 is provided in a ring shape, and the number of p-type termination well layers 31 provided is appropriately selected depending on the breakdown voltage design of the semiconductor device 100. In addition, on the outer edge side of the p-type termination well layer 31, there is an n + A type channel stopper layer 32 is provided, and an n + The p-type channel stopper layer 32 surrounds the p-type termination well layer 31 in plan view.

[0071] n of the termination region 30 - A p-type termination collector layer 16a is provided between the drift layer 1 and the second main surface of the semiconductor substrate. The p-type termination collector layer 16a is formed integrally and continuously with the p-type collector layer 16 provided in the IGBT region 10 of the cell region. Therefore, the p-type termination collector layer 16a may be collectively referred to as the p-type collector layer.

[0072] 1, in a configuration in which the diode region 20 is provided adjacent to the termination region 30, the end of the p-type termination collector layer 16a on the diode region 20 side is provided so as to protrude into the diode region 20 by a distance U2, as shown in FIG. + This increases the distance between the p-type cathode layer 26 and the p-type termination well layer 31, thereby preventing the p-type termination well layer 31 from functioning as an anode of a diode. The distance U2 may be, for example, 100 μm.

[0073] A collector electrode 7 is provided on the second main surface of the semiconductor substrate. The collector electrode 7 is configured to extend continuously and integrally from the cell region including the IGBT region 10 and the diode region 20 to the termination region 30.

[0074] On the other hand, an emitter electrode 6 continuing from the cell region and a termination electrode 36 structurally separated from the emitter electrode 6 are provided on the first main surface of the semiconductor substrate in the termination region 30. The emitter electrode 6 and the termination electrode 36 are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may be, for example, a semi-insulating silicon nitride (sinSiN) film. The termination electrode 36, the p-type termination well layer 31, and the n-type termination well layer 32 are electrically connected to each other via a semi-insulating film 33. +Each of the trench stopper layers 32 is electrically connected via a contact hole in the interlayer insulating film 4 provided on the first main surface of the termination region 30. Further, the termination region 30 is provided with an emitter electrode 6, a termination electrode 36, and a termination protection film 34 that covers the semi-insulating film 33. The termination protection film 34 is, for example, polyimide.

[0075] <Method of manufacturing an RC-IGBT> Figs. 12 to 17 are cross-sectional views showing a method of manufacturing a semiconductor device that is an RC-IGBT. Figs. 12 to 15 are diagrams showing the process of mainly forming the front surface side of the boundary region of Fig. 9 of the semiconductor device 100, and Figs. 16 and 17 are diagrams showing the process of mainly forming the back surface side of the boundary region of Fig. 9 of the semiconductor device 100. Fig. 18 is a flowchart showing a part of the method of manufacturing the semiconductor device according to Embodiment 1.

[0076] First, as shown in Fig. 12(a), an n - type semiconductor substrate constituting the drift layer 1 is prepared. The semiconductor substrate may be, for example, an FZ wafer manufactured by the FZ (Floating Zone) method or an MCZ wafer manufactured by the MCZ (Magnetic field applied CZochralki) method, or may be an n-type wafer containing n-type impurities. The concentration of the n-type impurities contained in the semiconductor substrate is appropriately selected according to the breakdown voltage of the semiconductor device to be manufactured. For example, in a semiconductor device with a breakdown voltage of 1200V, the concentration of the n - type impurities is adjusted so that the resistivity of the drift layer 1 of the type becomes about 40 to 120 Ω·cm. As shown in Fig. 12(a), in the step of preparing the semiconductor substrate, the entire semiconductor substrate is the n - type drift layer 1. By injecting p-type or n-type impurity ions from the first main surface side or the second main surface side of such a semiconductor substrate and then diffusing them into the semiconductor substrate by heat treatment or the like, a p-type or n-type semiconductor layer is appropriately formed, and the semiconductor device 100 is manufactured.

[0077] As shown in Fig. 12(a), n -The semiconductor substrate constituting the drift layer 1 has regions that will become the IGBT region 10 and the diode region 20. Furthermore, although not shown, regions that will become the termination region 30 and the like are provided around the regions that will become the IGBT region 10 and the diode region 20. The following mainly describes a manufacturing method for the IGBT region 10 and the diode region 20 of the semiconductor device 100, but the termination region 30 and the like of the semiconductor device 100 may also be fabricated by a well-known manufacturing method. For example, when forming an FLR having a p-type termination well layer 31 as a breakdown voltage retention structure in the termination region 30, the FLR may be formed by implanting p-type impurity ions before processing the IGBT region 10 and the diode region 20 of the semiconductor device 100. Alternatively, the FLR may be formed by implanting p-type impurity ions simultaneously with implanting p-type impurity ions into the IGBT region 10 or the diode region 20 of the semiconductor device 100.

[0078] Next, as shown in FIG. 12(b), n-type impurities such as phosphorus (P) are implanted from the first main surface side of the semiconductor substrate to form an n-type carrier accumulation layer 2. Furthermore, p-type impurities such as boron (B) are implanted from the first main surface side of the semiconductor substrate to form a p-type base layer 15 and a p-type anode layer 25. The n-type carrier accumulation layer 2, p-type base layer 15, and p-type anode layer 25 are formed by implanting impurity ions into the semiconductor substrate and then diffusing the impurity ions by heat treatment. The n-type impurity and p-type impurity ion implantation is performed after masking the first main surface of the semiconductor substrate, so that various layers are selectively formed on the first main surface side of the semiconductor substrate. The n-type carrier accumulation layer 2, p-type base layer 15, and p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20 and are connected to a p-type termination well layer 31 in the termination region 30. The masking process involves applying a resist to the semiconductor substrate, forming openings in predetermined regions of the resist using photolithography, and then forming a mask on the semiconductor substrate to perform ion implantation or etching on predetermined regions of the semiconductor substrate through the openings. Through the masking process and ion implantation, the n-type carrier accumulation layer 2, p-type base layer 15, and p-type anode layer 25 are selectively formed on the first principal surface sides of the IGBT region 10 and the diode region 20. Similarly, the p-type termination well layer 31 is selectively formed in the termination region 30.

[0079] The p-type impurities in the p-type base layer 15 and the p-type anode layer 25 may be ion-implanted simultaneously. In this case, the depths and p-type impurity concentrations of the p-type base layer 15 and the p-type anode layer 25 will be the same. Alternatively, the depths and p-type impurity concentrations of the p-type base layer 15 and the p-type anode layer 25 may be made different from each other by ion-implanting the p-type impurities in the p-type base layer 15 and the p-type anode layer 25 separately using a mask process.

[0080] The p-type impurities in the p-type termination well layer 31 and the p-type anode layer 25, which are not shown in FIG. 12(b), may be ion-implanted simultaneously. In this case, the depths and p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25 are the same. Alternatively, the p-type impurities in the p-type termination well layer 31 and the p-type anode layer 25 may be ion-implanted separately using a mask process, thereby making the depths and p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25 different from each other. Alternatively, the p-type impurities in the p-type termination well layer 31 and the p-type anode layer 25 may be ion-implanted simultaneously using masks with different aperture ratios, thereby making the p-type impurities in the p-type termination well layer 31 and the p-type anode layer 25 different from each other. In this case, one or both of the masks may be a mesh mask, and the aperture ratios of the masks may be made different. Similarly, using masks with different aperture ratios, the p-type impurities of the p-type termination well layer 31, the p-type base layer 15, and the p-type anode layer 25 may be ion-implanted simultaneously.

[0081] Next, as shown in FIG. 13(a), n-type impurities are selectively implanted into the first main surface side of the p-type base layer 15 of the IGBT region 10 by mask processing. + The n-type source layer 13 is formed. The n-type impurity to be implanted may be, for example, arsenic (As) or phosphorus (P). Furthermore, a mask process is used to implant p-type impurities into the first main surface side of the p-type base layer 15 of the IGBT region 10 to form p + A p-type contact layer 14 is formed, and p-type impurities are selectively implanted into the first main surface side of the p-type anode layer 25 in the diode region 20 to form a p + A p-type contact layer 24 is formed. The implanted p-type impurity may be, for example, boron or aluminum.

[0082] Next, as shown in FIG. 13(b), a semiconductor substrate is formed from the first main surface side thereof through the p-type base layer 15 and the p-type anode layer 25, and n - A trench 8 is formed in the IGBT region 10, reaching the n-type drift layer 1. + The sidewalls of the trenches 8 penetrating the n-type source layer 13 +In the IGBT region 10, a part of the p + The sidewalls of the trenches 8 penetrating the contact layer 14 are p + In the diode region 20, p + The sidewalls of the trenches 8 penetrating the contact layer 24 are p + It includes a part of the mold contact layer 24 .

[0083] For example, the trenches 8 are formed by depositing an oxide film such as SiO2 on the semiconductor substrate, forming openings in the oxide film at the portions where the trenches 8 are to be formed by masking, and then etching the semiconductor substrate using the oxide film with the openings as a mask. In FIG. 13(b), the trenches 8 are formed with the same pitch in the IGBT region 10 and the diode region 20, but the pitch of the trenches 8 may be different between the IGBT region 10 and the diode region 20. The pitch and planar pattern of the trenches 8 can be changed as appropriate by changing the mask pattern used in the masking process.

[0084] Next, as shown in FIG. 14(a), the semiconductor substrate is heated in an atmosphere containing oxygen to form an oxide film 9 on the inner walls of the trenches 8 and on the first main surface of the semiconductor substrate. The oxide film 9 formed in the trenches 8 in the IGBT region 10 is the gate trench insulating film 11b of the active trench gate 11 and the dummy trench insulating film 12b of the dummy trench gate 12. Furthermore, the oxide film 9 formed in the trenches 8 in the diode region 20 is the diode trench insulating film 21b. As a result, the gate trench insulating film 11b is substantially provided on the semiconductor substrate (see step S1 in FIG. 18). The oxide film 9 formed on the first main surface of the semiconductor substrate will be removed in a later step except for the portion formed in the trenches 8.

[0085] Next, as shown in FIG. 14(b), polysilicon doped with n-type or p-type impurities is deposited on the oxide film 9 in the trench 8 by CVD (chemical vapor deposition) or the like to form a gate trench electrode 11a, a dummy trench electrode 12a, and a diode trench electrode 21a.

[0086] Next, as shown in FIG. 15(a), an interlayer insulating film 4 is formed on the gate trench electrode 11a of the active trench gate 11 in the IGBT region 10 and on the gate trench insulating film 11b of the oxide film 9 (see step S1 in FIG. 18). The interlayer insulating film 4 may be, for example, SiO2. By forming contact holes in the insulating film that will become the deposited interlayer insulating film 4 and removing the oxide film 9 formed on the first main surface of the semiconductor substrate using a mask process, the interlayer insulating film 4 and the like shown in FIG. 15(a) are formed. The contact holes in the interlayer insulating film 4 are formed by n + On type source layer 13, p + On the contact layer 14, + It is formed on the mold contact layer 24, the dummy trench electrode 12a, and the diode trench electrode 21a.

[0087] 15(b), a barrier metal 5 is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 4. The barrier metal 5 is formed by depositing titanium nitride by physical vapor deposition (PDV) or CVD.

[0088] Then, an emitter electrode 6 is formed on the barrier metal 5. In the IGBT region 10, an emitter electrode 6 including an aluminum electrode 6a and a plated electrode 6b is formed as shown in FIGS. 4 and 5. Here, the emitter electrode 6 in the IGBT region 10 will be described. First, an aluminum silicon alloy (Al-Si alloy) is deposited on the barrier metal 5 by PVD such as sputtering or vapor deposition to form the aluminum electrode 6a (see step S2 in FIG. 18). Then, an opening in the aluminum electrode 6a, i.e., an opening that overlaps with the gate trench insulating film 11b in a plan view, is formed by masking the aluminum electrode 6a (see step S3 in FIG. 18).

[0089] Next, electroless plating or electrolytic plating is performed on the aluminum electrode 6a as the material to be plated. As a result, plating grows laterally from the sidewalls of the opening of the aluminum electrode 6a, i.e., from the sidewalls of the aluminum electrode 6a, and a plating electrode 6b is formed in at least a part of the opening of the aluminum electrode 6a (see step S4 in FIG. 18). Note that if the width of the opening of the aluminum electrode 6a is smaller than the thickness of the plating electrode 6b, the plating electrode 6b will be embedded in the opening of the aluminum electrode 6a.

[0090] Forming the emitter electrode 6 including the aluminum electrode 6a and the plated electrode 6b in this manner stabilizes the characteristics of the semiconductor device, as described above. Furthermore, since a thick metal film can be easily formed as the emitter electrode 6, the heat capacity of the emitter electrode 6 can be increased, thereby improving its heat resistance. When forming the emitter electrode 6 made of an aluminum-silicon alloy by PVD and then further forming a nickel alloy by plating, the plating for forming the nickel alloy may be performed after processing the second main surface of the semiconductor substrate.

[0091] 16(a), the second main surface side of the semiconductor substrate is ground to thin the semiconductor substrate to a predetermined designed thickness. The thickness of the semiconductor substrate after grinding may be, for example, 80 μm to 200 μm.

[0092] Next, as shown in FIG. 16(b), n-type impurities are implanted from the second main surface side of the semiconductor substrate to form an n-type buffer layer 3. Furthermore, p-type impurities are implanted from the second main surface side of the semiconductor substrate to form a p-type collector layer 16. The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20, the termination region 30, etc., or may be formed only in the IGBT region 10 or the diode region 20. The n-type buffer layer 3 may be formed by implanting, for example, phosphorus (P) ions, or by implanting protons (H +), or may be formed by implanting both protons and phosphorus. Protons can be implanted deep from the second main surface of the semiconductor substrate with a relatively low acceleration energy. Furthermore, the depth to which protons are implanted can be changed relatively easily by changing the acceleration energy. Therefore, when forming the n-type buffer layer 3 with protons, if the protons are implanted multiple times while changing the acceleration energy, an n-type buffer layer 3 that is thicker in the thickness direction of the semiconductor substrate than when formed with phosphorus can be formed.

[0093] Furthermore, since phosphorus can have a higher activation rate as an n-type impurity than protons, forming the n-type buffer layer 3 with phosphorus can suppress punch-through of the depletion layer even in a thinned semiconductor substrate. To further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 3 by implanting both protons and phosphorus, and in this case, the protons are implanted deeper from the second main surface than the phosphorus.

[0094] The p-type collector layer 16 may be formed by implanting boron (B), for example. The p-type collector layer 16 is also formed in the termination region 30, and the p-type collector layer 16 in the termination region 30 becomes the p-type termination collector layer 16a. After ion implantation from the second main surface side of the semiconductor substrate, the implanted boron is activated by irradiating the second main surface with a laser for laser annealing, thereby forming the p-type collector layer 16. At this time, the phosphorus implanted relatively shallow from the second main surface of the semiconductor substrate is also activated at the same time. On the other hand, since protons are activated at a relatively low annealing temperature of 350°C to 500°C, care must be taken to prevent the entire semiconductor substrate from being heated to a temperature higher than 350°C to 500°C after the proton implantation, except during the process for activating the protons. Because laser annealing can heat only the vicinity of the second main surface of the semiconductor substrate to a high temperature, it can be used to activate n-type impurities and p-type impurities even after the proton implantation.

[0095] Next, as shown in FIG. 17(a), an n + Form the cathode layer 26. +17(a), the p-type cathode layer 26 is formed at a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20. + n-type impurities are selectively implanted from the second main surface side by mask processing so that the boundary with the n-type cathode layer 26 is located. + The amount of n-type impurities implanted to form the n-type cathode layer 26 is greater than the amount of p-type impurities implanted to form the p-type collector layer 16. In FIG. 17(a), the p-type collector layer 16 and the n-type + The depth of the cathode layer 26 is shown to be the same as that of the n + The depth of the n-type cathode layer 26 is equal to or greater than the depth of the p-type collector layer 16. + The region where the cathode layer 26 is to be formed must be made into an n-type semiconductor by implanting n-type impurities into the region where p-type impurities have been implanted. + The concentration of n-type impurities is higher than the concentration of p-type impurities implanted in the entire region where the cathode layer 26 is formed.

[0096] Next, as shown in FIG. 17(b), a collector electrode 7 is formed on the second main surface of the semiconductor substrate. The collector electrode 7 is formed over the entire surfaces of the IGBT region 10, the diode region 20, the termination region 30, etc. on the second main surface. Alternatively, the collector electrode 7 may be formed over the entire surface of the second main surface of an n-type wafer, which is the semiconductor substrate. The collector electrode 7 may be formed by depositing an aluminum silicon alloy (Al-Si alloy), titanium (Ti), or the like by physical vapor deposition (PVD) such as sputtering or vapor deposition, or by laminating multiple metals such as an aluminum silicon alloy, titanium, nickel, or gold. Alternatively, the collector electrode 7 may be formed by forming an additional metal film by electroless plating or electrolytic plating on a metal film formed by PVD.

[0097] The semiconductor device 100 is manufactured through the above-described process. A plurality of semiconductor devices 100, 100 are manufactured in a matrix-like integrated state on a semiconductor substrate such as a single n-type wafer. For this reason, the semiconductor device 100 is cut into individual semiconductor devices 100 by laser dicing or blade dicing.

[0098] <Summary of the First Embodiment> In the semiconductor device according to the first embodiment described above, the plating electrode 6b is provided in the opening of the aluminum electrode 6a, which overlaps the gate trench insulating film 11b in plan view and is provided on the opposite side of the interlayer insulating film 4 from the gate trench insulating film 11b in cross-sectional view. This configuration allows dangling bonds to be terminated by hydrogen in the plating electrode 6b, thereby stabilizing the threshold voltage (Vth) characteristics of the semiconductor device. This is effective when the function of the barrier metal 5 is insufficient, for example, because the barrier metal 5 is thin, and is even more effective in a semiconductor device in which the barrier metal 5 is not provided.

[0099] Furthermore, in the first embodiment, the entire lower surface of the plating electrode 6b in the opening is in direct contact with the interlayer insulating film 4. With this configuration, dangling bonds due to hydrogen in the plating electrode 6b can be easily terminated.

[0100] <Embodiment 2> 19 is a plan view showing the configuration of a semiconductor device that is an RC-IGBT according to the second embodiment. The second embodiment is similar to the configuration shown in FIGS. 1 and 2, except that a temperature sensing diode region 62 for monitoring temperature, a current sensing region 63 for monitoring current, and a protection diode region 64 for protecting the semiconductor device are provided. The temperature sensing diode region 62 is provided adjacent to the IGBT region 10, and the current sensing region 63 and protection diode region 64 are provided adjacent to the pad region 40.

[0101] Fig. 20 is a cross-sectional view showing the configuration of the temperature sensing diode region 62 according to the second embodiment, specifically a cross-sectional view taken along the dashed dotted line HH of the semiconductor device 100 shown in Fig. 19. Note that although the second embodiment does not provide a barrier metal 5, the barrier metal 5 may be provided as in the first embodiment.

[0102] In the temperature sensing diode region 62, n - A p-type well layer 51 similar to the p-type termination well layer 31 is provided on the drift layer 1. An interlayer insulating film 4 is provided on the p-type well layer 51, and a pn junction 50 is provided inside the interlayer insulating film 4. The pn junction 50 is included in the semiconductor portion. The pn junction 50 according to the second embodiment is an n + a polysilicon cathode layer 50a and a p - type polysilicon anode layer 50b and p + and a polysilicon anode contact layer 50c.

[0103] The electrode 56 is insulated from the emitter electrode 6 by a protective film 54 made of, for example, polyimide. In the second embodiment, the electrode 56 includes an aluminum electrode 56a, which is a metal electrode, and a plated electrode 56b, similar to the emitter electrode 6 of the first embodiment. However, in the second embodiment, the opening of the aluminum electrode 56a overlaps with the pn junction 50 provided in the temperature sensing diode region 62 in plan view. In plan view, the opening overlaps with the pn junction 50 provided in the temperature sensing diode region 62. + The polysilicon cathode layers 50a and p - The junction with the polysilicon anode layer 50b, or - The polysilicon anode layer 50b and p + The insulating layer 52 may be provided along the junction with the mold polysilicon anode contact layer 50c, or may be provided overlapping a part of the junction.

[0104] The opening of the aluminum electrode 56a is provided on the opposite side of the pn junction 50 with respect to the upper part of the interlayer insulating film 4 in cross section.

[0105] In the second embodiment, the plating electrode 56b is embedded in the opening of the aluminum electrode 56a, with the aluminum electrode 56a serving as the material to be plated, and is provided on the aluminum electrode 56a. However, it is sufficient that the plating electrode 56b is provided in at least a portion of the opening of the aluminum electrode 56a. Also, in the second embodiment, the entire lower surface of the plating electrode 56b in the opening is in direct contact with the interlayer insulating film 4. However, it is sufficient that at least a portion of the lower surface of the plating electrode 56b is in direct contact with the interlayer insulating film 4; for example, a portion of the lower surface of the plating electrode 56b may be in direct contact with the interlayer insulating film 4.

[0106] With the above-described configuration, hydrogen generated during the growth process of the plating electrode 56b and hydrogen within the grown plating electrode 56b pass through the interlayer insulating film 4 and are incorporated into the polysilicon of the p-n junction 50 at the opening of the aluminum electrode 56a. The incorporated hydrogen terminates dangling bonds corresponding to the interface states at the grain boundaries of the polysilicon, thereby stabilizing the forward voltage (VFAK) of the temperature sensing diode region 62. Furthermore, by adjusting the aperture ratio of the opening relative to the p-n junction 50, the amount of hydrogen supplied to the p-n junction 50 can be adjusted, thereby adjusting the forward voltage of the semiconductor device.

[0107] <Manufacturing method> FIG. 21 is a flowchart showing a part of a method for manufacturing a semiconductor device according to the second embodiment, and the manufacturing method in FIG. 21 corresponds to the manufacturing method in FIG.

[0108] In step S11, the lower part of the interlayer insulating film 4 is formed on the p-type well layer 51, and the pn junction 50 is formed on the lower part. Then, the upper part of the interlayer insulating film 4 is formed on the pn junction 50, and an opening that partially exposes the pn junction 50 is provided in the upper part of the interlayer insulating film 4.

[0109] In step S12, an aluminum silicon alloy (Al--Si ​​alloy) is deposited on the interlayer insulating film 4 and the like by PVD such as sputtering or vapor deposition to form the aluminum electrode 56a.

[0110] In step S13, an opening in the aluminum electrode 56a, that is, an opening that overlaps the pn junction 50 in a plan view, is formed by masking the aluminum electrode 56a.

[0111] In step S14, electroless plating or electrolytic plating is performed on the aluminum electrode 56a as the plating target, causing the plating to grow laterally from the sidewall of the opening of the aluminum electrode 56a, i.e., from the sidewall of the aluminum electrode 56a, to form a plating electrode 56b in at least a portion of the opening of the aluminum electrode 56a.

[0112] <Summary of the second embodiment> In the semiconductor device according to the second embodiment, the plating electrode 56b is provided in the opening of the aluminum electrode 56a, which overlaps the pn junction 50 in plan view and is provided on the opposite side of the interlayer insulating film 4 from the pn junction 50 in cross section. With this configuration, dangling bonds are terminated by hydrogen in the plating electrode 56b, thereby stabilizing the forward voltage (VFAK) characteristics of the semiconductor device. This is particularly effective in a semiconductor device that does not include a barrier metal 5.

[0113] Furthermore, in the second embodiment, the entire lower surface of the plating electrode 56b in the opening is in direct contact with the interlayer insulating film 4. With this configuration, dangling bonds due to hydrogen in the plating electrode 56b can be easily terminated.

[0114] <Third Embodiment> Fig. 22 is a cross-sectional view showing the configuration of a temperature sensing diode region 62 according to the present embodiment 3. The configuration according to the present embodiment 3 shown in Fig. 22 is similar to the configuration according to the embodiment 2 shown in Fig. 20, except that the polyimide protective film 54 is changed to a semi-insulating protective film 58.

[0115] The plating electrode 56b is formed in the opening of the aluminum electrode 56a in a portion other than the protective film 58. In other words, the protective film 58 is provided within the opening of the aluminum electrode 56a and separates the plating electrode 56b. In the third embodiment, the plating electrode 56b is provided on the side wall of the opening of the aluminum electrode 56a by the protective film 58. The protective film 58 is formed of n + The polysilicon cathode layers 50a and p - The junction with the polysilicon anode layer 50b, or - The polysilicon anode layer 50b and p + The polysilicon anode contact layer 50c may be patterned to conform to the junction with the polysilicon anode contact layer 50c.

[0116] In the third embodiment, the entire lower surface of the plating electrode 56b in the opening is in direct contact with the interlayer insulating film 4. However, it is sufficient that at least a part of the lower surface of the plating electrode 56b is in direct contact with the interlayer insulating film 4; for example, a part of the lower surface of the plating electrode 56b may be in direct contact with the interlayer insulating film 4.

[0117] <Summary of the Third Embodiment> In the semiconductor device according to the third embodiment, the protective film 58 is provided in the opening of the aluminum electrode 56a and separates the plating electrodes 56b. With this configuration, the protective film 58 partially prevents the growth of the plating electrodes 56b, allowing the shape of the plating electrodes 56b to be made complex.

[0118] Furthermore, in the third embodiment, the entire lower surface of the plating electrode 56b in the opening is in direct contact with the interlayer insulating film 4. With this configuration, dangling bonds due to hydrogen in the plating electrode 56b can be easily terminated.

[0119] <Fourth Embodiment> Fig. 23 is a cross-sectional view showing the configuration of termination region 30 of semiconductor device 100, which is an RC-IGBT according to the fourth embodiment, and is a cross-sectional view taken along dashed line GG of semiconductor device 100 shown in Fig. 1. Fig. 23 shows termination region 30 having an FLR structure. Note that although barrier metal 5 is not provided in the fourth embodiment, barrier metal 5 may be provided as in the first embodiment.

[0120] In the fourth embodiment, n - The semiconductor portion includes the drift layer 1. In the fourth embodiment, the emitter electrode 6 includes an aluminum electrode 6a, which is a metal electrode, and a plated electrode 6b, and the termination electrode 36 includes an aluminum electrode 36a, which is a metal electrode, and a plated electrode 36b. The openings of the aluminum electrodes 6a and 36a are located in the n-type region of the termination region 30 in a plan view. - The n-type drift layer 1 overlaps the n-type drift layer 1, and the n-type drift layer 1 overlaps the n-type drift layer 1. - The openings in the aluminum electrodes 6a and 36a are provided on the opposite side from the type drift layer 1. The openings in the aluminum electrodes 6a and 36a here include at least one of the openings between the aluminum electrodes 6a and 36a, the openings between the aluminum electrodes 6a, and the openings between the aluminum electrodes 36a.

[0121] The plating electrodes 6b, 36b are provided on the sidewalls of the openings of the aluminum electrodes 6a, 36a, with the aluminum electrodes 6a, 36a serving as the plating target, and are also provided on the aluminum electrodes 6a, 36a. However, it is sufficient that the plating electrodes 6b, 36b are provided in at least a portion of the openings of the aluminum electrodes 6a, 36a. In the fourth embodiment, the entire lower surface of each of the plating electrodes 6b, 36b in the openings is in direct contact with the interlayer insulating film 4. However, it is sufficient that at least a portion of the lower surface of each of the plating electrodes 6b, 36b is in direct contact with the interlayer insulating film 4; for example, it is also possible that a portion of the lower surface of each of the plating electrodes 6b, 36b is in direct contact with the interlayer insulating film 4.

[0122] In the manufacturing method according to the fourth embodiment, the gate trench insulating film 11b and the pn junction 50 are formed in the n-type semiconductor layer 11 in the first and second embodiments. - Since it is the same as the one replacing the type drift layer 1, its description will be omitted here.

[0123] <Summary of the Fourth Embodiment> According to the semiconductor device of the fourth embodiment, n - The n-type drift layer 1 overlaps with the interlayer insulating film 4 in cross section. - The plating electrodes 6b, 36b are provided in the openings of the aluminum electrodes 6a, 36a provided on the opposite side of the n-type drift layer 1. With this configuration, hydrogen generated during the growth process of the plating electrodes 6b, 36b and hydrogen in the grown plating electrodes 6b, 36b pass through the interlayer insulating film 4 and are transferred to the n-type drift layer 1. - The hydrogen is trapped at the interface with the n-type drift layer 1. The trapped hydrogen causes the n-type drift layer 1 to - Since dangling bonds corresponding to the interface states with the type drift layer 1 are terminated, the characteristics related to withstand voltage creep during avalanche, i.e., the characteristics related to fluctuations in withstand voltage, can be stabilized. This is particularly effective in semiconductor devices that do not have a barrier metal 5.

[0124] Furthermore, in the fourth embodiment, the entire lower surfaces of the plating electrodes 6b, 36b in the openings are in direct contact with the interlayer insulating film 4. With this configuration, dangling bonds due to hydrogen in the plating electrodes 6b, 36b can be easily terminated.

[0125] <Fifth Embodiment> Fig. 24 is a cross-sectional view showing the configuration of termination region 30 of semiconductor device 100, which is an RC-IGBT according to present embodiment 5. The configuration according to present embodiment 5 shown in Fig. 24 is similar to the configuration according to embodiment 4 shown in Fig. 23, in which semi-insulating protective film 38 and insulating protective film 39 are added.

[0126] The plating electrodes 6b, 36b are formed in the openings of the aluminum electrodes 6a, 36a except for the protective film 38. In other words, the protective film 38 is provided in the openings of the aluminum electrodes 6a, 36a and separates the plating electrodes 6b, 36b. The separation of the plating electrodes 6b, 36b here includes at least one of the separation between the plating electrodes 6b and 36b, the separation between the plating electrodes 6b, and the separation between the plating electrodes 36b.

[0127] Semi-insulating protective film 38 may be a semi-insulating silicon nitride film such as sinSiN. Then, protective film 39, which is an insulating silicon nitride film, may be provided on semi-insulating protective film 38. With this configuration, the potential between p-type termination well layers 31 can be fixed by protective film 38 or the like, thereby stabilizing the breakdown voltage.

[0128] In the fifth embodiment, the entire lower surface of each of the plating electrodes 6b, 36b in the opening is in direct contact with the interlayer insulating film 4. However, it is sufficient that at least a part of the lower surface of each of the plating electrodes 6b, 36b is in direct contact with the interlayer insulating film 4; for example, a part of the lower surface of each of the plating electrodes 6b, 36b may be in direct contact with the interlayer insulating film 4.

[0129] <Summary of the Fifth Embodiment> In the semiconductor device according to the fifth embodiment, the protective film 38 is provided in the openings of the aluminum electrodes 6a and 36a to separate the plating electrodes 6b and 36b. This configuration allows the protective film 38, which partially prevents the growth of the plating electrodes 6b and 36b, to make the shapes of the plating electrodes 6b and 36b more complex. Furthermore, since the potential between the p-type termination well layers 31 can be fixed, stabilization of the breakdown voltage can also be expected.

[0130] Furthermore, in the fifth embodiment, the entire lower surfaces of the plating electrodes 6b, 36b in the openings are in direct contact with the interlayer insulating film 4. With this configuration, dangling bonds due to hydrogen in the plating electrodes 6b, 36b can be easily terminated.

[0131] <Sixth Embodiment> Fig. 25 is a cross-sectional view showing the configuration of termination region 30 of semiconductor device 100, which is an RC-IGBT according to the sixth embodiment, and is a cross-sectional view taken along dashed line GG of semiconductor device 100 shown in Fig. 1. Fig. 25 shows termination region 30 having an FLR structure. Note that although barrier metal 5 is not provided in the sixth embodiment, barrier metal 5 may be provided as in the first embodiment.

[0132] In the sixth embodiment, similarly to the first embodiment, n - A p-type termination well layer 31 is provided on the n-type drift layer 1. - A pn junction between the p-type drift layer 1 and the p-type termination well layer 31 is provided in the semiconductor substrate. This pn junction is included in the semiconductor portion.

[0133] In the sixth embodiment, similarly to the fourth embodiment, the emitter electrode 6 includes an aluminum electrode 6a, which is a metal electrode, and a plated electrode 6b, and the termination electrode 36 includes an aluminum electrode 36a, which is a metal electrode, and a plated electrode 36b. The openings of the aluminum electrodes 6a, 36a overlap the p-n junction provided in the termination region 30 in a plan view and are provided on the opposite side of the interlayer insulating film 4 from the p-n junction in a cross-sectional view. The openings of the aluminum electrodes 6a, 36a here include at least one of the openings between the aluminum electrodes 6a and 36a, the openings between the aluminum electrodes 6a, and the openings between the aluminum electrodes 36a. Note that, in a plan view, the openings may be provided along the p-n junction or may be provided overlapping a portion of it.

[0134] The plating electrodes 6b, 36b are embedded in the openings of the aluminum electrodes 6a, 36a, with the aluminum electrodes 6a, 36a serving as the plating target, and are provided on the aluminum electrodes 6a, 36a. However, it is sufficient that the plating electrodes 6b, 36b are provided in at least a portion of the openings of the aluminum electrodes 6a, 36a. In the sixth embodiment, the entire lower surface of each of the plating electrodes 6b, 36b in the openings is in direct contact with the interlayer insulating film 4. However, it is sufficient that at least a portion of the lower surface of each of the plating electrodes 6b, 36b is in direct contact with the interlayer insulating film 4; for example, it is also possible that a portion of the lower surface of each of the plating electrodes 6b, 36b is in direct contact with the interlayer insulating film 4.

[0135] <Summary of the Sixth Embodiment> In the semiconductor device according to the sixth embodiment, the plating electrodes 6b, 36b are provided in the openings of the aluminum electrodes 6a, 36a, which overlap the pn junction of the termination region 30 in a plan view and are provided on the opposite side of the pn junction with respect to the interlayer insulating film 4 in a cross-sectional view. This configuration allows the hydrogen in the plating electrodes 6b to terminate the dangling bonds of the pn junction of the termination region 30, thereby reducing leakage current and stabilizing leakage current characteristics. This is particularly effective in semiconductor devices that do not include a barrier metal 5.

[0136] Furthermore, in the sixth embodiment, the entire lower surfaces of the plating electrodes 6b, 36b in the openings are in direct contact with the interlayer insulating film 4. With this configuration, dangling bonds due to hydrogen in the plating electrodes 6b, 36b can be easily terminated.

[0137] <Modifications of Embodiments 1 to 6> The first to sixth embodiments may be combined as appropriate. That is, the gate trench insulating film 11b of the IGBT region 10, the pn junction 50 of the temperature sensing diode region 62, the n-type terminal region 30, and the n-type terminal region 30 may be combined as appropriate. -19. Alternatively, the pn junction of the semiconductor device may be configured so that hydrogen from the plating electrode is taken in by at least one of the pn junctions of the drift layer 1 and the termination region 30. A configuration similar to that of the first embodiment may be applied to the current sense region 63 in FIG. 19, and the aperture ratio of the openings may be different between the cell region and the current sense region 63. A configuration similar to that of the second embodiment may be applied to the protection diode region 64 made of polysilicon in FIG. 19.

[0138] In addition, in the fourth to sixth embodiments, both the emitter electrode 6 and the terminal electrode 36 are configured to include an aluminum electrode and a plated electrode, but this is not limiting. For example, one of the emitter electrode 6 and the terminal electrode 36 may be configured to include an aluminum electrode and a plated electrode, and the other may be configured to include an aluminum electrode without including a plated electrode.

[0139] Furthermore, in the fourth to sixth embodiments, termination region 30 has an FLR structure, but this is not limited thereto and may have, for example, a VLD structure. As an example, Fig. 26 shows a VLD structure that combines the fourth to sixth embodiments. As shown in Fig. 26, the occupancy rate per area of ​​the opening of aluminum electrodes 6a, 36a may be increased as the boundary of the pn junction becomes deeper.

[0140] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0141] Various aspects of the present disclosure are summarized below as appendices.

[0142] (Appendix 1) a semiconductor substrate provided with a semiconductor portion that is at least one of a gate insulating film, a pn junction, and a drift layer in a termination region; an insulating film provided on the semiconductor portion; a metal electrode that overlaps the semiconductor portion in a plan view and has an opening that is provided on the opposite side of the insulating film from the semiconductor portion in a cross-sectional view; a plating electrode provided in at least a part of the opening, the metal electrode being used as a plating material; A semiconductor device comprising:

[0143] (Appendix 2) the semiconductor portion includes the gate insulating film provided on an active trench gate in an IGBT region of the semiconductor substrate, 2. The semiconductor device according to claim 1, wherein at least a portion of the lower surface of the plating electrode is in direct contact with the insulating film.

[0144] (Appendix 3) 3. The semiconductor device according to claim 2, wherein the entire lower surface of the plating electrode in the opening is in direct contact with the insulating film.

[0145] (Appendix 4) the semiconductor portion includes the pn junction portion provided in a temperature sensing diode region of the semiconductor substrate, 4. The semiconductor device according to claim 1, wherein at least a portion of a lower surface of the plating electrode is in direct contact with the insulating film.

[0146] (Appendix 5) 5. The semiconductor device according to claim 4, wherein the entire lower surface of the plating electrode in the opening is in direct contact with the insulating film.

[0147] (Appendix 6) 6. The semiconductor device according to claim 4, further comprising a semi-insulating protective film provided in the opening and isolating the plating electrodes.

[0148] (Appendix 7) the plating electrode is provided on a side wall of the opening, 7. The semiconductor device according to claim 6, wherein the entire lower surface of the plating electrode in the opening is in direct contact with the insulating film.

[0149] (Appendix 8) the semiconductor portion includes the drift layer provided in the termination region, 8. The semiconductor device according to claim 1, wherein at least a portion of a lower surface of the plating electrode is in direct contact with the insulating film.

[0150] (Appendix 9) the plating electrode is provided on a side wall of the opening, 9. The semiconductor device according to claim 8, wherein the entire lower surface of the plating electrode in the opening is in direct contact with the insulating film.

[0151] (Appendix 10) 10. The semiconductor device according to claim 8, further comprising a semi-insulating protective film provided in the opening and isolating the plating electrodes.

[0152] (Appendix 11) the semiconductor portion includes the pn junction portion provided in the termination region, 11. The semiconductor device according to claim 1, wherein at least a portion of a lower surface of the plating electrode is in direct contact with the insulating film.

[0153] (Appendix 12) 12. The semiconductor device according to claim 11, wherein the entire lower surface of the plating electrode in the opening is in direct contact with the insulating film.

[0154] (Appendix 13) forming a semiconductor portion, which is at least one of a gate insulating film, a pn junction portion, and a drift layer in a termination region, provided on a semiconductor substrate, and an insulating film provided on the semiconductor portion; forming a metal electrode that overlaps the semiconductor portion in a plan view and has an opening that is provided on the opposite side of the insulating film from the semiconductor portion in a cross-sectional view; forming a plating electrode in at least a part of the opening using the metal electrode as a material to be plated; A method for manufacturing a semiconductor device, comprising: [Explanation of symbols]

[0155] 1n -Drift layer, 4 interlayer insulating film, 6a, 36a, 56a aluminum electrode, 6b, 36b, 56b plated electrode, 10 IGBT region, 11 active trench gate, 11b gate trench insulating film, 30 termination region, 38, 52 passivation film, 50 junction, 62 temperature sense diode region.

Claims

1. a semiconductor substrate provided with a semiconductor portion, which is at least one of a gate insulating film, a pn junction, and a drift layer in a termination region; an insulating film provided on the semiconductor portion; a metal electrode that overlaps the semiconductor portion in a plan view and has an opening that is provided on the opposite side of the insulating film from the semiconductor portion in a cross-sectional view; a plating electrode provided in at least a part of the opening, the metal electrode being used as a plating material; Equipped with the semiconductor portion includes the pn junction portion provided in a temperature sensing diode region of the semiconductor substrate, At least a portion of the lower surface of the plating electrode is in direct contact with the insulating film.

2. a semiconductor substrate provided with a semiconductor portion, which is at least one of a gate insulating film, a pn junction, and a drift layer in a termination region; an insulating film provided on the semiconductor portion; a metal electrode that overlaps the semiconductor portion in a plan view and has an opening that is provided on the opposite side of the insulating film from the semiconductor portion in a cross-sectional view; a plating electrode provided in at least a part of the opening, the metal electrode being used as a plating material; Equipped with the semiconductor portion is provided in the termination region and includes the drift layer in direct contact with the insulating film, At least a portion of the lower surface of the plating electrode is in direct contact with the insulating film.

3. 3. The semiconductor device according to claim 1, the semiconductor portion further includes the gate insulating film provided on an active trench gate in an IGBT region of the semiconductor substrate.

4. 3. The semiconductor device according to claim 1, The semiconductor device has a lower surface of the plating electrode in the opening that is in direct contact with the insulating film.

5. 2. The semiconductor device according to claim 1, The semiconductor device further comprises a semi-insulating protective film provided in the opening and isolating the plating electrodes.

6. 2. The semiconductor device according to claim 1, the plating electrode is provided on a side wall of the opening, The semiconductor device has a lower surface of the plating electrode in the opening that is in direct contact with the insulating film.

7. 3. The semiconductor device according to claim 2, the plating electrode is provided on a side wall of the opening, The semiconductor device has a lower surface of the plating electrode in the opening that is in direct contact with the insulating film.

8. 3. The semiconductor device according to claim 2, The semiconductor device further comprises a semi-insulating protective film provided in the opening and isolating the plating electrodes.

9. 3. The semiconductor device according to claim 1, The semiconductor device, wherein the semiconductor portion further includes the pn junction portion provided in the termination region.

10. forming a semiconductor portion, which is at least one of a gate insulating film, a pn junction, and a drift layer in a termination region, provided on a semiconductor substrate, and an insulating film provided on the semiconductor portion; forming a metal electrode that overlaps the semiconductor portion in a plan view and has an opening that is provided on the opposite side of the insulating film from the semiconductor portion in a cross-sectional view; forming a plating electrode in at least a part of the opening using the metal electrode as a material to be plated; Equipped with the semiconductor portion includes the pn junction portion provided in a temperature sensing diode region of the semiconductor substrate, At least a portion of the lower surface of the plating electrode is in direct contact with the insulating film.

11. forming a semiconductor portion, which is at least one of a gate insulating film, a pn junction, and a drift layer in a termination region, provided on a semiconductor substrate, and an insulating film provided on the semiconductor portion; forming a metal electrode that overlaps the semiconductor portion in a plan view and has an opening that is provided on the opposite side of the insulating film from the semiconductor portion in a cross-sectional view; forming a plating electrode in at least a part of the opening using the metal electrode as a material to be plated; Equipped with the semiconductor portion is provided in the termination region and includes the drift layer in direct contact with the insulating film, At least a portion of the lower surface of the plating electrode is in direct contact with the insulating film.

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