Semiconductor device and manufacturing method thereof

Abstract

To improve the performance of a semiconductor device.SOLUTION: In a semiconductor substrate SB, an n-type source region SR, an n-type drain region DR, a p-type semiconductor region PR, and a p-type semiconductor region PB surrounding the n-type source region SR and the p-type semiconductor region PR are formed. A gate electrode GE is formed between the n-type source region SR and the n-type drain region DR over the semiconductor substrate SB through an insulating film GF. In the semiconductor substrate SB, a depressed part KB is formed so as to penetrate the n-type source region SR. The p-type semiconductor region PR is formed under the depressed part KB.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and can be suitably used, for example, in a semiconductor device having an LDMOSFET and a manufacturing method thereof. [Background technology]

[0002] The laterally diffused metal-oxide-semiconductor field effect transistor (LDMOSFET) is a type of MISFET (Metal Insulator Semiconductor Field Effect Transistor). LDMOSFETs have a high drain breakdown voltage.

[0003] Japanese Patent Application Laid-Open No. 2021-190548 (Patent Document 1) describes a technology related to a semiconductor device having an LDMOSFET. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-190548 Summary of the Invention [Problem to be solved by the invention]

[0005] It is desirable to improve the performance of semiconductor devices having MISFETs as much as possible.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] According to one embodiment, a semiconductor device includes a semiconductor substrate, a source region of a first conductivity type and a drain region of the first conductivity type formed in the semiconductor substrate and spaced apart from each other, a gate electrode formed on the semiconductor substrate between the source region and the drain region with a gate insulating film interposed therebetween, and a recess formed in the semiconductor substrate so as to penetrate the source region. The semiconductor device further includes a first semiconductor region of a second conductivity type provided below the recess, and a second semiconductor region of the second conductivity type formed so as to surround the source region and the first semiconductor region.

[0008] According to one embodiment, a method for manufacturing a semiconductor device includes: (a) preparing a semiconductor substrate; (b) forming a conductive film for a gate electrode on the semiconductor substrate via a gate insulating film; (c) after step (b), etching the conductive film to form a first pattern made of the conductive film and expose a first upper surface of the semiconductor substrate. The method for manufacturing a semiconductor device further includes: (d) after step (c), forming a source region of a first conductivity type in the first upper surface by ion implantation; (e) after step (d), etching the first upper surface to form a recessed portion so as to penetrate the source region; and (f) after step (e), forming a first semiconductor region of a second conductivity type in the semiconductor substrate below the recessed portion by ion implantation. [Effects of the Invention]

[0009] According to one embodiment, the performance of a semiconductor device can be improved. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention; [Figure 2] 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention; [Figure 3] 1 is a plan view of a main part of a semiconductor device according to an embodiment; [Figure 4] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to a modified example. [Figure 5] 1 is a cross-sectional view of a main part of a semiconductor device during a manufacturing process according to an embodiment of the present invention; [Figure 6] 6 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process, continued from FIG. 5. [Figure 7] 7 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 6. [Figure 8] 8 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process, continued from FIG. 7. [Figure 9] 9 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 8. [Figure 10] 10 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 9. [Figure 11] 11 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 10. [Figure 12] 12 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 11. [Figure 13] 13 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 12. [Figure 14] 14 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 13. [Figure 15] 15 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 14. [Figure 16] 16 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 15. [Figure 17] FIG. 17 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 16. [Figure 18] FIG. 18 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. [Figure 19] FIG. 19 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 18. [Figure 20] FIG. 20 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 19. [Figure 21] FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a study example. [Figure 22] FIG. 1 is a plan view of a main part of a semiconductor device according to a study example. [Figure 23] 10A and 10B are cross-sectional views of a main part of a semiconductor device during a manufacturing process of the semiconductor device according to the study example. [Figure 24] FIG. 24 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 23. [Figure 25] FIG. 25 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 24. [Figure 26] FIG. 26 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 25. [Figure 27] FIG. 27 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 26. [Figure 28] FIG. 28 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 27. [Figure 29] FIG. 29 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 28. [Figure 30] FIG. 30 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process following FIG. 29. [Figure 31] FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a study example. [Figure 32] 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention; [Figure 33] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to another embodiment. [Figure 34] FIG. 10 is a cross-sectional view of a main part of a semiconductor device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the following embodiments, the description will be divided into multiple sections or embodiments for convenience, as necessary. However, unless otherwise specified, they are not unrelated to one another, and one is a partial or complete modification, detail, supplementary explanation, etc., of the other. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or clearly limited to a specific number in principle. Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential, unless otherwise specified or clearly considered essential in principle. Similarly, in the following embodiments, when the shape, positional relationship, etc. of components, etc. are mentioned, it is intended to include those that are substantially similar to or similar to the shape, etc., unless otherwise specified or clearly considered not to be essential in principle. The same applies to the above numerical values ​​and ranges.

[0012] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0013] In the drawings used in the embodiments, hatching may be omitted even in cross-sectional views to make the drawings easier to see, and hatching may be added even in plan views to make the drawings easier to see.

[0014] (Embodiment 1) <About the structure of semiconductor devices> A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. Figures 1 and 2 are cross-sectional views of a main portion of the semiconductor device according to this embodiment, and Figure 3 is a plan view of a main portion of the semiconductor device according to this embodiment. Figures 1 and 2 show cross sections substantially parallel to the gate length direction, with the cross-sectional view taken along line A1-A1 in Figure 3 substantially corresponding to Figure 1, and the cross-sectional view taken along line A2-A2 in Figure 3 substantially corresponding to Figure 2. Figures 1 to 3 show two LDMOSFETs that share an n-type source region SR and a p-type semiconductor region PR.

[0015] FIG. 3 also shows the X direction and the Y direction. The X direction is the direction along the gate length direction of the gate electrode GE, and therefore the direction along the channel length direction. The Y direction is the gate width direction of the gate electrode GE. The Y direction is the direction intersecting the X direction, more specifically, the direction perpendicular to the X direction. Hereinafter, the gate length direction of the gate electrode GE will be simply referred to as the "gate length direction," and the gate width direction of the gate electrode GE will be simply referred to as the "gate width direction."

[0016] The semiconductor device of this embodiment is a semiconductor device having a MISFET (Metal Insulator Semiconductor Field Effect Transistor), and in this case, the semiconductor device has an LDMOSFET (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor) as the MISFET.

[0017] In this application, the term MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or LDMOSFET includes not only MISFETs that use an oxide film (silicon oxide film) as the gate insulating film, but also MISFETs that use an insulating film other than an oxide film (silicon oxide film) as the gate insulating film. LDMOSFET is a type of MISFET element.

[0018] Hereinafter, the structure of the semiconductor device according to the present embodiment will be specifically described with reference to FIGS. 1 to 3.

[0019] As shown in FIGS. 1 to 3, as a MISFET, a LDMOSFET is formed on the main surface of a semiconductor substrate SB. The semiconductor substrate SB includes a substrate body SB1 made of, for example, a p-type single crystal silicon into which a p-type impurity such as boron (B) is introduced, an n-type buried layer (semiconductor layer) NBL formed on the substrate body SB1, and an epitaxial layer (semiconductor layer) EP made of, for example, p-type single crystal silicon formed on the buried layer NBL. Therefore, the semiconductor substrate SB is a so-called epitaxial wafer. The impurity concentration (p-type impurity concentration) of the substrate body SB1 is higher than the impurity concentration (p-type impurity concentration) of the epitaxial layer EP. The epitaxial layer EP and the buried layer NBL can also be regarded as part of the semiconductor substrate SB.

[0020] On the main surface of the semiconductor substrate SB, an element isolation region (not shown) made of an insulator (insulating film) is formed using, for example, the STI (Shallow Trench Isolation) method or the LOCOS (Local Oxidization of Silicon) method.

[0021] Referring to FIGS. 1 and 2, an n-type semiconductor region (n-type drift layer, n-type well) ND and a p-type semiconductor region (p-type body region, p-type well) PB are formed in the upper part (upper layer part) of the semiconductor substrate SB, that is, in the upper part (upper layer part) of the epitaxial layer EP. The n-type semiconductor region ND is an n-type semiconductor region.

[0022] <<p-type semiconductor region PB>> The p-type semiconductor region PB is a p-type semiconductor region. The n-type semiconductor region ND and the p-type semiconductor region PB are adjacent to each other. The impurity concentration (p-type impurity concentration) of the p-type body region PB is higher than the impurity concentration (p-type impurity concentration) of the epitaxial layer EP. The p-type semiconductor region PB is formed so as to surround the n-type source region SR and the p-type semiconductor region PR described later. More specifically, the p-type semiconductor region PB is in contact with the bottom surface and the side surface of the p-type semiconductor region PR. Further, the p-type semiconductor region PB is in contact with the bottom surface of the n-type source region SR and the side surfaces other than the side on the recessed portion KB side described later.

[0023] The p-type semiconductor region PB can function as a back gate. The p-type semiconductor region PB can also have a function as a punch-through stopper that suppresses the extension of the depletion layer from the drain to the source of the LDMOSFET. Between the n-type source region SR and the n-type drain region DR, the upper part (upper layer part) of the p-type semiconductor region PB located under the gate electrode GE becomes the channel formation region of the LDMOSFET.

[0024] <<n-type source region SR>> An n-type source region (n-type semiconductor region) SR is formed in the p-type semiconductor region PB. The n-type source region SR is an n-type semiconductor region that functions as the source region of the LDMOSFET. The n-type source region SR is adjacent to the recessed portion KB described later. In the present embodiment, referring to FIG. 1, the n-type source regions SR are arranged on the left and right of the recessed portion KB in the cross section. Therefore, one of the side surfaces of the n-type source region SR is in contact with the recessed portion KB. The n-type source PR is formed in the semiconductor substrate SB. The upper surface of the n-type source region PR is at the same height as the upper surface of the semiconductor substrate SB.

[0025] <<recessed portion KB>> On the main surface (upper surface) of the semiconductor substrate SB, that is, on the main surface (upper surface) of the epitaxial layer EP, a recessed portion KB is formed. The recessed portion KB has a concave shape that is dug in the thickness direction of the semiconductor substrate SB. The recessed portion KB is constituted by a space that penetrates from the upper surface to the lower surface inside the n-type source region SR. In FIG. 1, the recessed portion KB penetrates the center of the n-type source region SR. The recessed portion KB further forms a space that reaches into the p-type semiconductor region PB below the n-type source region SR.

[0026] Referring now to FIG. 3. In plan view, the recessed portion KB is included in the n-type source region SR. That is, in plan view, the recessed portion KB is surrounded by the n-type source region SR. The n-type source region SR is in contact with the recessed portion KB so as to surround the recessed portion KB. As shown in FIG. 1, one side surface of the n-type source region SR, that is, the side surface other than the side surface adjacent to the recessed portion KB, and the bottom surface of the n-type source region SR are covered with the p-type semiconductor region PB.

[0027] <<p-type semiconductor region PR>> In the p-type semiconductor region PB, a p-type semiconductor region PR is also formed. The p-type semiconductor region PR is formed under the bottom (bottom surface) of the recessed portion KB. The impurity concentration (p-type impurity concentration) of the p-type semiconductor region PR is higher than the impurity concentration (p-type impurity concentration) of the p-type semiconductor region PB. The side surface and the bottom surface of the p-type semiconductor region PR are in contact with the p-type semiconductor region PB. The p-type semiconductor region PR is covered with the p-type semiconductor region PB except for its upper surface. Therefore, the p-type semiconductor region PB is formed so as to surround the p-type semiconductor region PR together with the n-type source region SR. The p-type semiconductor region PR can function as a contact of the p-type semiconductor region PB.

[0028] In this embodiment, the upper surface of the p-type semiconductor region PR is located below the bottom surface of the n-type source region SR. In other words, the height position of the upper surface of the p-type semiconductor region PR is lower than the height position of the bottom surface of the n-type source region SR. The side surface of the p-type semiconductor region PR lies in the same plane as the side surface of the recessed portion KB. Similarly, the side surface of the p-type semiconductor region PR also lies in the same plane as the side surface of the n-type source region SR. The length of the p-type semiconductor region PR in the gate length direction is the same as the length of the recessed portion KB. Here, referring also to FIG. 32, the length of the p-type semiconductor region PR is indicated as the width L1. Also, referring to FIG. 11, the length of the recessed portion KB is indicated as the width L3.

[0029] As a modification, as shown in FIG. 4, the length of the p-type semiconductor region PR can be made wider than the length of the recessed portion KB. Thereby, the contact area between the p-type semiconductor region PR and the p-type semiconductor region PB can be widened. Here, FIG. 4 is a cross-sectional view of a main part showing a modification of the semiconductor device of this embodiment, and a cross-section corresponding to FIG. 1 is shown. FIG. 4 shows a case where the length of the p-type semiconductor region PR in the gate length direction is longer than the length of the recessed portion KB in the gate length direction.

[0030] Also, in FIG. 3, when viewed in plan, the p-type semiconductor region PR is arranged in an island shape within the p-type semiconductor region PB. The p-type semiconductor region PR can be arranged in a plurality of island shapes within the p-type semiconductor region PB.

[0031] <<n-type semiconductor region ND>> Referring again to FIG. 1. In the gate length direction (X direction), the n-type semiconductor region ND is adjacent to the p-type semiconductor region PB. Among the n-type semiconductor region ND and the p-type semiconductor region PB, the n-type semiconductor region ND is located on the drain side and the p-type semiconductor region PB is located on the source side. The boundary between the n-type semiconductor region ND and the p-type semiconductor region PB is located below the gate electrode GE and extends in the gate width direction (Y direction) of the gate electrode GE.

[0032] <<n-type drain region DR>> An n-type drain region (n-type semiconductor region) DR is formed in the n-type semiconductor region ND. The n-type semiconductor region ND is formed so as to surround the n-type drain region DR. In other words, the bottom and side surfaces of the n-type drain region DR are covered with the n-type semiconductor region ND. The n-type drain region DR is an n-type semiconductor region that functions as the drain region of the LDMOSFET. The impurity concentration (n-type impurity concentration) of the n-type drain region DR is higher than the impurity concentration (n-type impurity concentration) of the n-type semiconductor region ND. The n-type drain region DR and the n-type source region SR are spaced apart from each other in the gate length direction (X direction) of the gate electrode GE.

[0033] In the gate length direction (X direction) of the gate electrode GE, an n-type semiconductor region ND having a lower impurity concentration (n-type impurity concentration) than the n-type drain region DR is interposed between the p-type semiconductor region PB and the n-type drain region DR. Therefore, an n-type semiconductor region ND having a lower impurity concentration than the n-type drain region DR exists between the channel formation region of the LDMOSFET and the n-type drain region DR, and this n-type semiconductor region ND can function as an n-type drift region. Therefore, in the gate length direction (X direction) of the gate electrode GE, a channel formation region and an n-type semiconductor region ND (n-type drift region) exist between the n-type source region SR and the n-type drain region DR, with the channel formation region located on the n-type source region SR side and the n-type semiconductor region ND located on the n-type drain region DR side. The channel formation region is adjacent to the n-type source region SR and the n-type semiconductor region ND, and is interposed between the n-type source region SR and the n-type semiconductor region ND in the X direction. The p-type epitaxial layer EP remaining under the n-type semiconductor region ND and the p-type semiconductor region PB can function as a resurf layer (resurf region). Although an epitaxial layer is used in this embodiment, the present invention is not limited to this, and a layer formed by ion implantation can also be used.

[0034] <<Gate electrode GE>> On the main surface (upper surface) of the semiconductor substrate SB, i.e., on the main surface (upper surface) of the epitaxial layer EP, a gate electrode GE of the LDMOSFET is formed via an insulating film (gate insulating film) GF. An n-type source region SR and an n-type drain region DR are formed in the epitaxial layer EP of the semiconductor substrate SB. A gate electrode GE is formed on the epitaxial layer EP between the n-type source region SR and the n-type drain region DR via an insulating film GF. The insulating film GF is the gate insulating film of the LDMOSFET. The width of the n-type source region SR is the same as the gate width of the gate electrode GE. That is, in the Y direction, the width of the source region SR and the width of the gate electrode GE are the same.

[0035] The gate electrode GE is made of, for example, a single film of polycrystalline silicon film (doped polysilicon film) or a laminated film of a polycrystalline silicon film and a metal silicide layer. The insulating film GF is made of, for example, a silicon oxide film. Sidewall spacers (sidewall insulating films) SW1 made of insulating films (for example, silicon oxide films) are formed on both side surfaces (side walls) of the gate electrode GE.

[0036] The gate electrode GE is disposed between the n-type source region SR and the n-type drain region DR. When a voltage equal to or greater than the threshold voltage is applied to the gate electrode GE, an n-type inversion layer is formed in the upper part (upper layer) of the p-type semiconductor region PB located under the gate electrode GE. The n-type inversion layer becomes a channel. The n-type source region SR and the n-type drain region DR are electrically connected via the channel and the n-type semiconductor region ND.

[0037] A part of the p-type semiconductor region PB is located below the gate electrode GE, and a part of the n-type semiconductor region ND is located below the gate electrode GE. The boundary between the p-type semiconductor region PB and the n-type semiconductor region ND forms a PN junction surface. This boundary is located midway along the gate electrode GE in the X direction.

[0038] <<Sidewall insulating film SW2>> A sidewall insulating film SW2 made of an insulating film is formed on the side surface of the recess portion KB. For example, the sidewall insulating film SW2 is made of a silicon oxide film. The sidewall insulating film SW2 has a sidewall spacer shape. Referring to FIG. 1, the sidewall insulating film SW2 is provided so as to cover the side surface of the recess portion KB in the thickness direction of the semiconductor (the height direction in the figure), starting from the height of the position of the metal silicide SL on the n-type source region SR and reaching the bottom of the recess portion KB, i.e., the upper surface of the first semiconductor region PR. The sidewall insulating film SW2 covers the n-type source region SR and the second semiconductor region PB facing the recess portion KB.

[0039] <<Metal silicide layer SL>> A metal silicide layer SL is formed on each of the upper portions (upper layer portions) of the n-type drain region DR, the n-type source region SR, the p-type semiconductor region PR, and the gate electrode GE. The metal silicide layer SL is made of, for example, a cobalt silicide layer, a nickel silicide layer, or a platinum-added nickel silicide layer, and can be formed using salicide (Self Aligned Silicide) technology. Although it is preferable to form the metal silicide layer SL, it can be omitted if unnecessary.

[0040] <<Interlayer insulating film IL>> An interlayer insulating film IL is formed as an insulating film on the main surface (top surface) of the semiconductor substrate SB, i.e., on the main surface (top surface) of the epitaxial layer EP, so as to cover the gate electrode GE and the sidewall spacer SW1. The interlayer insulating film IL is made of, for example, a silicon oxide film. The interlayer insulating film IL can also be formed of a stacked film of a relatively thin silicon nitride film and a relatively thick silicon oxide film on the silicon nitride. The top surface of the interlayer insulating film IL is flattened. The interlayer insulating film IL is also formed in the recessed portion KB. That is, the interlayer insulating film IL is formed on the main surface of the semiconductor substrate SB (epitaxial layer EP) so as to cover the gate electrode GE and the sidewall spacer SW1 and to fill the recessed portion KB.

[0041] Contact holes (through holes) are formed in the interlayer insulating film IL, and conductive plugs (contact plugs) PG made mainly of a tungsten (W) film are embedded in the contact holes. The plugs PG penetrate the interlayer insulating film IL. The plugs PG are formed on the n-type source region SR, the n-type drain region DR, and the p-type semiconductor region PR, respectively.

[0042] <<Plug PG>> Here, the plug PG formed on the n-type source region SR and electrically connected to the n-type source region SR will be referred to as a plug PGS. Furthermore, the plug PG formed on the n-type drain region DR and electrically connected to the n-type drain region DR will be referred to as a plug PGD. Furthermore, the plug PG formed on the p-type semiconductor region PR and electrically connected to the p-type semiconductor region PR will be referred to as a plug PGP. The plug PG can also be formed on the gate electrode GE, but the plug PG on the gate electrode GE is not shown in the cross-sectional views of FIGS. 1 and 2.

[0043] The plug PGP is electrically connected to the p-type semiconductor region PR. The plug PGP penetrates the interlayer insulating film IL, passes between the recessed portions KB, and reaches their bottom surfaces. At this time, the plug PGP passes between the sidewall insulating films SW2 provided in the recessed portions KB. The plug PGP reaches the bottom of the recessed portions KB, in other words, the upper surface of the p-type semiconductor region PR.

[0044] The plug PGP is in contact with the metal silicide layer SL formed on the upper part of the p-type semiconductor region PR and is electrically connected to the metal silicide layer SL. As a result, the plug PGP is electrically connected to the p-type semiconductor region PR through the metal silicide layer SL formed on the upper part of the p-type semiconductor region PR. Furthermore, the plug PGP is electrically connected to the p-type semiconductor region PB through the p-type semiconductor region PR. When the metal silicide layer SL is not formed on the upper part of the p-type semiconductor region PR, the plug PGP is in direct contact with the p-type semiconductor region PR and is electrically connected to the p-type semiconductor region PR.

[0045] Referring to FIG. 2, the plug PGS is electrically connected to the n-type source region SR. The plug PGS penetrates the interlayer insulating film IL and reaches the upper surface of the n-type source region SR. In this embodiment, the plug PGS is in contact with a metal silicide layer SL formed on the upper part of the n-type source region SR and is electrically connected to the metal silicide layer SL. The plug PGS is electrically connected to the n-type source region SR via the metal silicide layer SL. If the metal silicide layer SL is not formed on the upper part of the n-type source region SR, the plug PGS is in direct contact with the n-type source region SR and is electrically connected to the n-type source region SR.

[0046] Referring to FIG. 3, in plan view, the plug PGP is contained in the recessed portion KB. The lower part of the plug PGP is located within the recessed portion KB. Even within the recessed portion KB, the side surface (periphery) of the plug PGP is surrounded (covered) by the interlayer insulating film IL. The plugs PGP and the plugs PGS are aligned on a straight line in the gate width direction. On this straight line, there is a location where the boundary between the recessed portion KB and the source region SR is sandwiched between the plugs PGP and the plugs PGS. In this embodiment, when the plugs PG are observed on a straight line in plan view, one plug PGS is aligned next to two plugs PGP. This arrangement pattern of the plugs PGS and the plugs PGP may be repeated on a straight line. The number of plugs PGS and plugs PGP can be changed as necessary.

[0047] As described above, the sidewall insulating film SW2 having a sidewall spacer shape is formed on the side surface of the recessed portion KB. The plug PGP does not contact the side surface of the recessed portion KB. The sidewall insulating film SW2 can more effectively prevent the plug PGP from contacting the epitaxial layer EP exposed from the side surface of the recessed portion KB. The plug PGP is electrically insulated from the source region SR by the sidewall insulating film SW2.

[0048] On the interlayer insulating film IL in which the plugs PG are buried, there is formed a wiring (first layer wiring) M1 made of a conductive film mainly made of aluminum (Al) or an aluminum alloy, etc. The wiring M1 is preferably an aluminum wiring, but may also be a wiring made of other metal materials, such as a tungsten wiring or a copper wiring.

[0049] The wiring M1 has a source wiring M1S electrically connected to the n-type source region SR via the plug PGS and a drain wiring M1D electrically connected to the n-type drain region DR via the plug PGD. The source wiring M1S is also electrically connected to the p-type semiconductor region PR via the plug PGP. That is, the source wiring M1S is electrically connected to both the plug PGS and the plug PGD. Therefore, the potential supplied to the n-type source region SR from the plug PGS is the same as the potential supplied to the p-type semiconductor region PR via the plug PGP. Therefore, the same potential as the potential (source potential) supplied to the n-type source region SR from the source wiring M1S via the plug PGS is supplied from the source wiring M1S to the p-type semiconductor region PR via the plug PGP, and is further supplied from the p-type semiconductor region PR to the p-type semiconductor region PB. The wiring M1 may further have a gate wiring electrically connected to the gate electrode GE via the plug PG, but the gate wiring is not shown in the cross-sectional views of FIGS. 1 and 2.

[0050] The illustration and description of the structure above the interlayer insulating film IL and the wiring M1 will be omitted here.

[0051] When a voltage (potential) equal to or greater than the threshold voltage is applied to the gate electrode GE, a channel (n-type inversion layer) is formed in the upper portion (upper layer) of the p-type semiconductor region PB located under the gate electrode GE. When the channel is formed, the n-type source region SR and the n-type drain region DR are electrically connected via the channel and the n-type semiconductor region ND. In this state, if a large current flows between the n-type source region SR and the n-type drain region DR, the n-type source region SR may have a higher potential than the p-type semiconductor region PB, causing the parasitic bipolar transistor to operate (become ON). However, by supplying the same potential as that supplied to the n-type source region SR from the plug PGD via the p-type semiconductor region PR to the p-type semiconductor region PB when a large current flows between the n-type source region SR and the n-type drain region DR, the n-type source region SR can be prevented from becoming higher in potential than the p-type semiconductor region PB. This prevents the parasitic bipolar transistor from operating. The parasitic bipolar transistor is an NPN bipolar transistor formed by an n-type semiconductor region ND, a p-type semiconductor region PB, and an n-type source region SR.

[0052] The on-state breakdown voltage is the voltage that must be applied between the n-type source region SR and the n-type drain region DR before the parasitic bipolar transistor operates. By providing a p-type semiconductor region PR and supplying the same potential as that supplied to the source region SR to the p-type semiconductor region PB via the p-type semiconductor region PR, the on-state breakdown voltage of the LDMOSFET can be increased.

[0053] <<Combination of recessed portion KB and p-type semiconductor region PR>> As can be seen from FIG. 3, the epitaxial layer EP of the semiconductor substrate SB has a plurality of pairs of recessed portions KB and underlying p-type semiconductor regions PR. These pairs are arranged at a distance from one another in the Y direction (gate width direction). That is, a plurality of recessed portions KB are formed so as to penetrate one n-type source region SR, and these recessed portions KB are arranged at a distance from one another in the Y direction (gate width direction). A p-type semiconductor region PR is formed below each recessed portion KB. As a result, an n-type source region SR exists between recessed portions KB adjacent to one another in the Y direction. Therefore, a plug PGS can be disposed on the n-type source region SR between recessed portions KB adjacent to one another in the Y direction. The plug PGS can be electrically connected to the n-type source region SR. At least one plug PGP is disposed for each recessed portion KB. In the case of FIG. 3, two plugs PGP are disposed for each recessed portion KB. The number of plugs PGP disposed for each recessed portion KB may be one or may be three or more.

[0054] <About the manufacturing process of semiconductor devices> Next, the manufacturing process of the semiconductor device of this embodiment will be described with reference to the drawings. Figures 5 to 20 are cross-sectional views of the main part of the semiconductor device during the manufacturing process of this embodiment, and show cross sections corresponding to the above-mentioned Figure 1.

[0055] To manufacture a semiconductor device, first, a semiconductor substrate SB is prepared. For example, as shown in Fig. 5, a semiconductor substrate SB is prepared that includes a substrate body SB1 made of p-type single crystal silicon or the like, an n-type buried layer (semiconductor layer) NBL formed on the main surface (top surface) of the substrate body SB1, and an epitaxial layer EP made of p-type single crystal silicon or the like formed on the main surface (top surface) of the buried layer NBL. In this case, the main surface (top surface) of the semiconductor substrate SB and the main surface (top surface) of the epitaxial layer EP are synonymous, so hereinafter, "the main surface of the semiconductor substrate SB" can also be read as "the main surface of the epitaxial layer EP," and "the main surface of the epitaxial layer EP" can also be read as "the main surface of the semiconductor substrate SB."

[0056] Next, an element isolation region (not shown) is formed on the main surface of the semiconductor substrate SB by using, for example, an STI method or a LOCOS method.

[0057] 6, an n-type semiconductor region ND is formed in the upper part (upper layer) of the epitaxial layer EP of the semiconductor substrate SB by introducing an n-type impurity using an ion implantation method or the like. The n-type semiconductor region ND is formed to a predetermined depth from the main surface (upper surface) of the epitaxial layer EP.

[0058] Next, after cleaning the main surface of the semiconductor substrate SB, an insulating film GF is formed on the main surface of the semiconductor substrate SB as shown in Fig. 7. The insulating film GF is made of a silicon oxide film or the like, and can be formed using a thermal oxidation method or the like.

[0059] 7, a silicon film PS is formed on the main surface of the semiconductor substrate SB, that is, on the insulating film GF, as a conductive film (conductor film) for the gate electrode GE. The silicon film PS is made of, for example, a polysilicon film, and can be formed by using a CVD (Chemical Vapor Deposition) method or the like.

[0060] Next, as shown in FIG. 8, a photoresist pattern (resist pattern) RP1 is formed on the silicon film PS using photolithography. Then, using the photoresist pattern RP1 as an etching mask, the silicon film PS is etched. As a result, the silicon film PS on the source side is removed, forming a pattern made of the silicon film PS. An opening OPS is formed in the pattern made of the silicon film PS. A side surface (sidewall) GEa is formed in the silicon film PS as the side surface of the pattern. This side surface GEa becomes the side surface (sidewall) of the gate electrode GE on the source side. FIG. 8 shows this stage. In plan view, the opening OPS in the silicon film PS approximately coincides with the opening in the photoresist pattern RP1. In the region where the silicon film PS has been removed by etching, the insulating film GF is exposed. After etching the silicon film PS, if the exposed insulating film GF that is not covered by the silicon film PS is further etched and removed, the main surface (top surface) of the semiconductor substrate SB is exposed.

[0061] Next, as shown in FIG. 9, using the photoresist pattern RP1 and the silicon film PS as a mask (ion implantation element mask), p-type impurities are introduced into the epitaxial layer EP of the semiconductor substrate SB by ion implantation, thereby forming a p-type semiconductor region PB in the epitaxial layer EP of the semiconductor substrate SB. Oblique ion implantation is used as the ion implantation for forming the p-type semiconductor region PB. As a result, a portion of the p-type semiconductor region PB overlaps with the gate electrode GE in a planar view. Therefore, a portion of the p-type semiconductor region PB exists below the gate electrode GE. The p-type semiconductor region PB is formed to a predetermined depth from the main surface (upper surface) of the epitaxial layer EP. When the p-type semiconductor region PB is formed, the p-type semiconductor region PB is adjacent to the n-type semiconductor region ND.

[0062] Next, as shown in FIG. 9, using the photoresist pattern RP1 and the silicon film PS as a mask (ion implantation element mask), an n-type impurity is introduced into the epitaxial layer EP of the semiconductor substrate SB by ion implantation, thereby forming an n-type source region SR in the epitaxial layer EP of the semiconductor substrate SB. The n-type source region SR is formed by ion implanting n-type impurities into the semiconductor substrate SB through the openings OPS of the pattern made of the silicon film PS. Vertical ion implantation is used as the ion implantation method for forming the n-type source region SR. As a result, the n-type source region SR is formed in self-alignment with the side surface GEa of the silicon film PS. That is, the n-type source region SR is formed in the portion of the semiconductor substrate SB that is not covered with the silicon film PS. The n-type source region SR is formed to a predetermined depth from the main surface (top surface) of the epitaxial layer EP. In the epitaxial layer EP of the semiconductor substrate SB, the n-type source region SR is formed in the p-type semiconductor region PB. The depth of the n-type source region SR is shallower than the depth of the p-type semiconductor region PB. The bottom and side surfaces of the formed n-type source region SR are covered with the p-type semiconductor region PB. Thereafter, the photoresist pattern RP1 is removed by ashing or the like.

[0063] Next, as shown in FIG. 10, a photoresist pattern (resist pattern) RP2 is formed on the main surface of the semiconductor substrate SB using photolithography technology so as to cover the silicon film PS in the portion that will become the gate electrode GE and a portion of the n-type source region SR. The photoresist pattern RP2 has an opening OP1 that exposes a portion of the n-type source region SR (a region where the recessed portion KB is to be formed). The opening OP1 in the photoresist pattern RP2 is an opening for forming the recessed portion KB. The opening OP1 in the photoresist pattern RP2 is contained within the n-type source region SR in a planar view. Furthermore, the opening OP1 in the photoresist pattern RP2 is contained within the opening OPS of the pattern made of the silicon film PS in a planar view. Therefore, the opening OP1 in the photoresist pattern RP2 exposes a portion of the opening OPS of the pattern made of the silicon film PS in a planar view. The n-type source region SR other than the region where the recessed portion KB is to be formed is covered with the photoresist pattern RP2. In this embodiment, an opening OP1 of the photoresist pattern PR2 is provided in the center of the n-type source region SR in the gate length direction. The photoresist pattern PR2 covers the n-type source region SR on both sides of the opening OP1. The silicon film PS in the portion that will become the gate electrode GE is covered with the photoresist pattern RP2. The silicon film PS in the portion that will not become the gate electrode GE is exposed and not covered with the photoresist pattern RP2. In the gate length direction, the length (width L2) of the opening OP1 of the photoresist pattern PR2 is smaller than the length of the opening of the photoresist pattern RP1. In the gate length direction, the length of the opening OP1 of the photoresist pattern PR2 is smaller than the length of the opening OPS of the pattern made of the silicon film PS.

[0064] Next, as shown in FIG. 11, the silicon film PS and the epitaxial layer EP are etched using the photoresist pattern RP2 as an etching mask. By etching the exposed portion of the silicon film PS that is not covered by the photoresist pattern RP2, the drain-side silicon film PS is removed, forming a side surface (sidewall) GEb of the silicon film PS. This side surface GEb becomes the drain-side side surface (sidewall) of the gate electrode GE. Furthermore, by etching the insulating film GF exposed at the bottom of the opening OP1 in the photoresist pattern RP2 and the underlying semiconductor substrate SB (epitaxial layer EP), a recessed portion KB is formed in the semiconductor substrate SB (epitaxial layer EP). The depth of the recessed portion KB is shallower than the depth of the p-type semiconductor region PB, and the p-type semiconductor region PB exists below the bottom surface of the recessed portion KB. Thereafter, as shown in FIG. 12, the photoresist pattern RP2 is removed by ashing or the like.

[0065] The silicon film PS is patterned by etching using the photoresist pattern RP1 (etching in FIG. 8) and etching using the photoresist pattern RP2 (etching in FIG. 11) to form a gate electrode GE. The gate electrode GE is made of the patterned silicon film PS, and the source-side side of the gate electrode GE is a side GEa formed by etching using the photoresist pattern RP1, and the drain-side side of the gate electrode GE is a side GEb formed by etching using the photoresist pattern RP2. The insulating film GF remaining under the gate electrode GE becomes the gate insulating film of the LDMOSFET. The gate electrode GE is formed on the epitaxial layer EP of the semiconductor substrate SB via the insulating film GF.

[0066] Furthermore, the insulating film GF and the semiconductor substrate SB (epitaxial layer EP) are etched at the bottom of the opening OP1 of the photoresist pattern RP2 to form a recessed portion KB, which is aligned with the opening OP1 of the photoresist pattern RP2. The depth of the recessed portion KB is deeper than the depth of the n-type source region SR (i.e., the bottom surface of the recessed portion KB is located deeper than the bottom surface of the n-type source region SR), and the recessed portion KB is formed to penetrate the n-type source region SR. The formed recessed portion KB is contained in the n-type source region SR in plan view and is surrounded by the n-type source region SR. The photoresist pattern RP2 serves as both an etching mask for patterning the silicon film PS and an etching mask for forming the recessed portion KB.

[0067] Next, as shown in FIG. 13, sidewall spacers SW1 are formed on both side surfaces (GEa, GEb) of the gate electrode GE. For example, an insulating film (e.g., a silicon oxide film) for forming sidewall spacers is formed on the main surface of the semiconductor substrate SB (including the bottom and side surfaces of the recessed portion KB) by a CVD method or the like so as to cover the gate electrode GE, and then the insulating film is etched back by an anisotropic etching technique, thereby forming the sidewall spacers SW1. When the sidewall spacers SW1 are formed on both side surfaces of the gate electrode GE, sidewall insulating films SW2 in the form of sidewall spacers may be formed on the side surfaces (sidewalls) of the recessed portion KB. The sidewall spacers SW1 and the sidewall insulating films SW2 are formed in the same process.

[0068] 14, a photoresist pattern (resist pattern) RP3 is formed on the main surface of the semiconductor substrate SB by photolithography so as to cover the gate electrode GE, the sidewall spacer SW1, the n-type source region SR, and the recessed portion KB. The region where the n-type drain region DR is to be formed is not covered with the photoresist pattern RP3.

[0069] Next, as shown in Figure 14, using the photoresist pattern RP3 as a mask (ion implantation element mask), n-type impurities are introduced into the epitaxial layer EP of the semiconductor substrate SB by ion implantation, thereby forming an n-type drain region DR in the epitaxial layer EP of the semiconductor substrate SB. In the epitaxial layer EP of the semiconductor substrate SB, the n-type drain region DR is formed in the n-type semiconductor region ND. Figure 14 shows this stage. Thereafter, the photoresist pattern RP3 is removed by ashing or the like.

[0070] 15, a photoresist pattern (resist pattern) RP4 is formed on the main surface of the semiconductor substrate SB using photolithography to cover the gate electrode GE, the sidewall spacer SW1, and the n-type drain region DR. The photoresist pattern RP4 has an opening OP2 for forming the p-type semiconductor region PR. The opening OP2 of the photoresist pattern RP4 overlaps with the recessed portion KB in plan view. Therefore, at least a portion of the recessed portion KB of the semiconductor substrate SB (epitaxial layer EP) is exposed from the opening OP2 of the photoresist pattern RP4.

[0071] Next, as shown in FIG. 15, using the photoresist pattern RP4 as a mask (ion implantation element mask), p-type impurities are introduced into the epitaxial layer EP of the semiconductor substrate SB by ion implantation, thereby forming a p-type semiconductor region PR in the epitaxial layer EP of the semiconductor substrate SB. In this ion implantation, the p-type impurities are implanted into the portion of the semiconductor substrate SB (epitaxial layer EP) exposed from the opening OP2 of the photoresist pattern RP4, so that the p-type semiconductor region PR is formed below the recessed portion KB. In the epitaxial layer EP of the semiconductor substrate SB, the p-type semiconductor region PR is formed to a predetermined depth from the bottom surface of the recessed portion KB. The bottom surface and side surfaces of the p-type semiconductor region PR are covered with the p-type semiconductor region PB. The impurity concentration (p-type impurity concentration) of the p-type semiconductor region PR is higher than the impurity concentration (p-type impurity concentration) of the p-type semiconductor region PB. Thereafter, as shown in FIG. 16, the photoresist pattern RP4 is removed by ashing or the like.

[0072] When the opening OP2 of the photoresist pattern RP4 is contained within the recess KB in plan view (including the case where the opening OP2 of the photoresist pattern RP4 coincides with the recess KB), the n-type source region SR is not exposed from the opening OP2 of the photoresist pattern RP4. In this case, during ion implantation using the photoresist pattern RP4 (ion implantation for forming the p-type semiconductor region PR), almost no p-type impurities are implanted into the n-type source region SR near the recess KB.

[0073] Furthermore, in plan view, a part of the opening OP2 of the photoresist pattern RP4 may protrude from the recessed portion KB. In this case, during ion implantation using the photoresist pattern RP4 (ion implantation for forming the p-type semiconductor region PR), p-type impurities are implanted into the portion of the n-type source region SR exposed from the opening OP2 of the photoresist pattern RP4 near the recessed portion KB. In this case, the ion implantation using the photoresist pattern RP4 (ion implantation for forming the p-type semiconductor region PR) may partially reduce the effective n-type impurity concentration of the n-type source region SR near the recessed portion KB, but this does not cause any particular problem with the function of the n-type source region SR as a source region.

[0074] Therefore, in plan view, not only can the opening OP2 of the photoresist pattern RP4 be contained within the recess KB, but also a part of the opening OP2 of the photoresist pattern RP4 can be tolerated protruding from the recess KB, so a margin for the formation position of the opening OP2 of the photoresist pattern RP4 can be ensured. This makes it easier to form the photoresist pattern RP4 and makes it easier to manage the process of forming the photoresist pattern RP4.

[0075] Next, activation annealing is performed, which is a heat treatment for activating the impurities that have been introduced (implanted) up to this point.

[0076] Next, the metal silicide layer SL is formed. Specifically, the metal silicide layer SL can be formed as follows.

[0077] 17, an insulating film (silicide block film) ZM for preventing the formation of a metal silicide layer SL is formed. This insulating film ZM can be formed, for example, by forming an insulating film on the main surface of the semiconductor substrate SB so as to cover the gate electrode GE, the sidewall spacer SW1, and the sidewall insulating film SW2, and then patterning the insulating film.

[0078] Then, a metal film (metal film for forming a metal silicide layer SL) is formed over the entire main surface of the semiconductor substrate SB, including the upper surfaces (surfaces) of the n-type drain region DR, the n-type source region SR, the p-type semiconductor region PR, and the gate electrode GE, so as to cover the gate electrode GE and the sidewall spacer SW1. The metal film for forming the metal silicide layer SL is made of, for example, a cobalt (Co) film, a nickel (Ni) film, or a nickel-platinum alloy film, and can be formed by a sputtering method or the like. Then, the semiconductor substrate SB is subjected to a heat treatment, so that the upper layer portions (surface portions) of the n-type drain region DR, the n-type source region SR, the p-type semiconductor region PR, and the gate electrode GE react with the metal film for forming the metal silicide layer SL. As a result, as shown in FIG. 18 , the metal silicide layer SL is formed on the upper portions (upper surface, surface, upper layer portions) of the n-type drain region DR, the n-type source region SR, the p-type semiconductor region PR, and the gate electrode GE, respectively. The metal silicide layer SL is made of, for example, a cobalt silicide layer, a nickel silicide layer, or a platinum-added nickel silicide layer. Thereafter, the unreacted metal film (the metal film for forming the metal silicide layer SL) is removed by wet etching or the like. This step is shown in FIG. 18. After the unreacted metal film is removed, a heat treatment may be further performed.

[0079] In this way, by performing a so-called salicide (Self Aligned Silicide) process, a metal silicide layer SL is formed on the n-type drain region DR, the n-type source region SR, the p-type semiconductor region PR, and the gate electrode GE, thereby reducing the diffusion resistance and contact resistance. By using the salicide process, the metal silicide layer SL can be formed in a self-aligned manner on each of the n-type drain region DR, the n-type source region SR, the p-type semiconductor region PR, and the gate electrode GE. Note that the formation of the metal silicide layer SL can be omitted.

[0080] 19, an interlayer insulating film IL is formed on the main surface of the semiconductor substrate SB, i.e., on the epitaxial layer EP, by using a CVD method or the like so as to cover the gate electrode GE and the sidewall spacer SW1. The interlayer insulating film IL is also formed in the recessed portion KB. After the interlayer insulating film IL is formed, the upper surface of the interlayer insulating film IL can be polished and flattened by using a CMP (Chemical Mechanical Polishing) method or the like.

[0081] Next, as shown in Figure 20, the interlayer insulating film IL is etched using a photoresist pattern (not shown) formed on the interlayer insulating film IL as an etching mask to form contact holes (through holes) in the interlayer insulating film IL, and then conductive plugs PG are formed in the contact holes as connecting conductor portions.

[0082] For example, after a barrier conductor film is formed on the interlayer insulating film IL including the bottom and side surfaces of the contact hole, a main conductor film (e.g., a tungsten film) is formed on the barrier conductor film so as to fill the contact hole, and then unnecessary main conductor film and barrier conductor film outside the contact hole are removed by CMP etc. This allows the plug PG to be formed.

[0083] The plugs PG include a plug PGS electrically connected to the n-type source region SR, a plug PGD electrically connected to the n-type drain region DR, a plug PGP electrically connected to the p-type semiconductor region PR, and a plug (not shown) electrically connected to the gate electrode GE.

[0084] The plug PGS is in contact with the metal silicide layer SL formed on the upper part of the n-type source region SR, is electrically connected to the metal silicide layer SL, and is electrically connected to the n-type source region SR through the metal silicide layer SL. The plug PGD is in contact with the metal silicide layer SL formed on the upper part of the n-type drain region DR, is electrically connected to the metal silicide layer SL, and is electrically connected to the n-type drain region DR through the metal silicide layer SL.

[0085] The contact hole for the plug PGP is formed so as to be contained in the recess portion KB. Therefore, the metal silicide layer SL formed on the upper part of the p-type semiconductor region PR is exposed at the bottom of the contact hole for the plug PGP. The plug PGP embedded in the contact hole for the plug PGP penetrates the interlayer insulating film IL, passes between the sidewall insulating films SW2 provided in the recess portion KB, and reaches the bottom surface of the recess portion KB. The plug PGP comes into contact with and is electrically connected to the metal silicide layer SL formed on the upper part of the p-type semiconductor region PR. As a result, the plug PGP is electrically connected to the p-type semiconductor region PR via the metal silicide layer SL formed on the upper part of the p-type semiconductor region PR, and is further electrically connected to the p-type semiconductor region PB via the p-type semiconductor region PR.

[0086] 1 and 2, a wiring M1 is formed on the interlayer insulating film IL in which the plug PG is buried. For example, a conductive film (metal film) for forming the wiring M1 is formed on the interlayer insulating film IL in which the plug PG is buried, and then this conductive film is patterned using photolithography and etching techniques, thereby forming the wiring M1 made of the patterned conductive film. A damascene wiring can also be used as the wiring M1.

[0087] The subsequent steps will not be illustrated or explained here.

[0088] <About the study example> Fig. 21 is a cross-sectional view of a main part of a semiconductor device of an example studied by the present inventors, and Fig. 22 is a plan view of a main part of the semiconductor device of an example studied by the present inventors. Fig. 21 shows a cross section approximately parallel to the gate length direction, and the cross-sectional view taken along line B1-B1 in Fig. 22 corresponds approximately to Fig. 21.

[0089] The following describes the differences between the structure of the semiconductor device of the study example shown in FIGS. 21 and 22 and the structure of the semiconductor device of the first embodiment (FIGS. 1 to 3).

[0090] 21 and 22, nothing equivalent to the recessed portion KB or the sidewall insulating film SW2 is formed. A p-type semiconductor region PR101 equivalent to the p-type semiconductor region PR is formed in the upper portion (surface layer portion) of the semiconductor substrate SB (epitaxial layer EP) so as to be adjacent to the n-type source region SR101 in the gate length direction (X direction). The n-type source region SR101 and the p-type semiconductor region PR101 each extend in the Y direction. In the thickness direction of the semiconductor substrate SB, the n-type source region SR101 and the p-type semiconductor region PR101 are located at approximately the same position.

[0091] The n-type source region SR101 corresponds to the above-mentioned n-type source region SR, but is made up of a lightly doped semiconductor region SR101a and a heavily doped semiconductor region SR101b. The heavily doped semiconductor region SR101b has a higher n-type impurity concentration than the lightly doped semiconductor region SR101a. In the gate length direction (X direction), the lightly doped semiconductor region SR101a is disposed between the heavily doped semiconductor region SR101b and the channel formation region. The lightly doped semiconductor region SR101a is located below a sidewall spacer SW101 formed on the side surface of the gate electrode GE on the source side.

[0092] A metal silicide layer SL101 corresponding to the metal silicide layer SL is formed on an upper portion of the high-concentration region SR101b of the n-type source region SR101 and on an upper portion of the p-type semiconductor region PR101, and the metal silicide layers SL101 are connected to each other. A plug PGP101 corresponding to the plug PGP is located on the p-type semiconductor region PR101 and is electrically connected to the p-type semiconductor region PR101 via the metal silicide layer SL101, and is further electrically connected to a p-type semiconductor region PB101 corresponding to the p-type semiconductor region PB via the p-type semiconductor region PR101. The plug PGP101 is also electrically connected to the high-concentration region SR101b of the n-type source region SR101 via the metal silicide layer SL101.

[0093] As for other aspects, the structure of the semiconductor device of the study example in FIGS. 21 and 22 is similar to the structure of the semiconductor device of the first embodiment (FIGS. 1 to 3), and therefore a repeated description thereof will be omitted here.

[0094] Next, the manufacturing process of the semiconductor device of the study example will be described with reference to Figures 23 to 30. Figures 23 to 30 are cross-sectional views of the main part of the semiconductor device of the study example during the manufacturing process, and show the cross section corresponding to Figure 21 above.

[0095] In the case of the examined example, after obtaining the structure shown in Fig. 7 as described above, a photoresist pattern RP101 is formed on the silicon film PS, and then the silicon film PS is etched using the photoresist pattern RP101 as an etching mask, as shown in Fig. 23. This removes the silicon film PS on the source side.

[0096] Next, as shown in FIG. 24, using the photoresist pattern RP101 and the silicon film PS as an ion implantation element mask, oblique ion implantation of p-type impurities is performed to form p-type semiconductor regions PB101 in the epitaxial layer EP of the semiconductor substrate SB.

[0097] 24, n-type impurity ions are implanted using the photoresist pattern RP101 and the silicon film PS as an ion implantation element mask to form a low-concentration semiconductor region SR101a in the epitaxial layer EP of the semiconductor substrate SB. The n-type impurity concentration of the low-concentration semiconductor region SR101a is lower than the n-type impurity concentration of the n-type source region SR101. Thereafter, the photoresist pattern RP101 is removed.

[0098] 25, a photoresist pattern RP102 is formed on the silicon film PS. The photoresist pattern RP102 does not have an opening corresponding to the opening OP1 of the photoresist pattern RP2, and the entire low-concentration semiconductor region SR101a is covered with the photoresist pattern RP102. Furthermore, the portion of the silicon film PS that will become the gate electrode GE101 is covered with the photoresist pattern RP102, but the portion of the silicon film PS that will not become the gate electrode GE101 is not covered with the photoresist pattern RP102 and is exposed.

[0099] Next, as shown in FIG. 26, the silicon film PS is etched using the photoresist pattern RP102 as an etching mask. This removes the silicon film PS on the drain side. In the case of the examined example, no portion corresponding to the recessed portion KB is formed. Thereafter, the photoresist pattern RP102 is removed.

[0100] The silicon film PS is patterned by etching using the photoresist pattern RP101 and etching using the photoresist pattern RP102 to form a gate electrode GE101.

[0101] 27, sidewall spacers SW1 are formed on both side surfaces of the gate electrode GE101. In the case of the examined example, since nothing equivalent to the recessed portion KB is formed, nothing equivalent to the sidewall insulating film SW2 is also formed.

[0102] 27, a photoresist pattern RP103 is formed on the main surface of the semiconductor substrate SB. The region where the p-type semiconductor region PR101 is to be formed is covered with the photoresist pattern RP103, but the region where the n-type drain region DR101 is to be formed and the region where the high-concentration semiconductor region SR101b is to be formed are not covered with the photoresist pattern RP103.

[0103] Next, as shown in Fig. 27, n-type impurities are ion-implanted using the photoresist pattern RP103 as an ion-implantation element mask, thereby forming an n-type drain region DR101 and a heavily doped semiconductor region SR101b in the epitaxial layer EP of the semiconductor substrate SB. This stage is shown in Fig. 27. Thereafter, the photoresist pattern RP103 is removed.

[0104] 28, a photoresist pattern RP104 is formed on the main surface of the semiconductor substrate SB. The gate electrode GE101, the n-type drain region DR101, and the heavily doped semiconductor region SR101b are covered with the photoresist pattern RP104. The region where the p-type semiconductor region PR101 is to be formed is not covered with the photoresist pattern RP104.

[0105] 28, p-type impurities are ion-implanted using the photoresist pattern RP104 as an ion-implantation element mask, thereby forming a p-type semiconductor region PR101 in the epitaxial layer EP of the semiconductor substrate SB. Thereafter, as shown in FIG. 29, the photoresist pattern RP104 is removed.

[0106] Next, activation annealing is performed, which is a heat treatment for activating the impurities that have been introduced (implanted) up to this point.

[0107] Next, as shown in FIG. 30, an insulating film (silicide block film) ZM for preventing the formation of a metal silicide layer SL101 is formed, and then the metal silicide layer SL101 is formed using a salicide technique.

[0108] Thereafter, as shown in FIG. 21, an interlayer insulating film IL is formed on the main surface of the semiconductor substrate SB, a contact hole is formed in the interlayer insulating film IL, a plug PG101 is formed in the contact hole, and a wiring M101 is formed on the interlayer insulating film IL101 in which the plug PG101 is embedded.

[0109] Fig. 31 is a cross-sectional view of a main part of the semiconductor device of the study example, and shows an enlarged portion of Fig. 21. According to the study by the present inventors, it has been found that the following problems arise in the case of the study example.

[0110] When a voltage equal to or greater than the threshold voltage is applied to the gate electrode GE101, a channel (n-type inversion layer) is formed in the upper part of the p-type semiconductor region PB101 located under the gate electrode GE101. When the channel is formed, the n-type source region SR101 and the n-type drain region DR101 are electrically connected via the channel and the n-type semiconductor region ND.

[0111] When a current flows between the n-type source region SR101 and the n-type drain region DR101, holes (positive holes) HL101 tend to accumulate at the position shown in FIG. 31. That is, holes HL101 tend to accumulate from the channel formation region above the p-type semiconductor region PB101 to the vicinity of the PN junction surface between the n-type source region SR101 and the p-type semiconductor region PB101. The increased amount of holes accumulated near the PN junction surface between the n-type source region SR101 and the p-type semiconductor region PB101 tends to generate a potential difference between the n-type source region SR101 and the p-type semiconductor region PB101, which acts to increase the potential difference. As a result, when a large current flows between the n-type source region SR101 and the n-type drain region DR101, the parasitic bipolar transistor tends to operate, and the on-breakdown voltage of the LDMOSFET decreases. This leads to a decrease in the manufacturing yield of the semiconductor device. In order to improve the performance of a semiconductor device, it is desirable to prevent the parasitic bipolar transistor from operating as much as possible and to improve the on-state breakdown voltage of the LDMOSFET.

[0112] Furthermore, in the case of the studied example, it is difficult to reduce the width (dimension) L101 (see FIGS. 21 and 28) of the p-type semiconductor region PR101 in the gate length direction (X direction). This is disadvantageous for miniaturizing the semiconductor device. The reason why it is difficult to reduce the width L101 of the p-type semiconductor region PR101 will be explained below.

[0113] In the case of the examined example, a lightly doped semiconductor region SR101a for the n-type source region SR101 is formed in the step of Fig. 23, a heavily doped semiconductor region SR101b for the n-type source region SR101 is formed in the step of Fig. 27, and a p-type semiconductor region PR101 is formed in the step of Fig. 28. When forming the heavily doped semiconductor region SR101b for the source region SR101 in the step of Fig. 27, a photoresist pattern RP103 is used as a mask, and the photoresist pattern RP103 includes a photoresist pattern RP103a that covers a region where the p-type semiconductor region PR101 is to be formed. The photoresist pattern RP103a is provided to prevent n-type impurities from being implanted into the region where the p-type semiconductor region PR101 is to be formed in the ion implantation step of forming the heavily doped semiconductor region SR101b for the source region SR101. The width (dimension) L102 (see FIG. 27) of the photoresist pattern RP103a in the gate length direction (X direction) is set to be approximately the same as the width L101 of the p-type semiconductor region PR101 formed in the step of FIG.

[0114] Here, assume that the photoresist pattern RP103 does not have the photoresist pattern RP103a in the step of FIG. 27. In this case, in the ion implantation step of forming the high-concentration semiconductor region SR101b for the source region SR101, n-type impurities are also implanted at a high concentration into the region where the p-type semiconductor region PR101 is to be formed. If n-type impurities are implanted at a high concentration into the region where the p-type semiconductor region PR101 is to be formed, when the p-type semiconductor region PR101 is formed by ion implantation of p-type impurities in the step of FIG. 28, it becomes difficult to control the effective p-type impurity concentration of the formed p-type semiconductor region PR101, making it difficult to form the p-type semiconductor region PR101 with a desired impurity concentration. For this reason, in the step of FIG. 27, the photoresist pattern RP103 needs to have the photoresist pattern RP103a to prevent n-type impurities from being implanted into the region where the p-type semiconductor region PR101 is to be formed.

[0115] However, there is a limit to how small the width L102 of the photoresist pattern RP103a can be. This is because, if the width L102 of the photoresist pattern RP103a is reduced, the photoresist pattern RP103a becomes a narrow pattern, reducing stability and making the photoresist pattern RP103a more likely to collapse during processing. For this reason, the width L102 of the photoresist pattern RP103a needs to be increased to some extent, and as a result, the width L101 of the p-type semiconductor region PR101 needs to be increased to some extent. For this reason, it is difficult to suppress the width L101 of the p-type semiconductor region PR101.

[0116] Also, assume that the high-concentration semiconductor region SR101b is not formed. In this case, the photoresist pattern RP103 can cover the entire low-concentration semiconductor region SR101a, and therefore the photoresist pattern RP103 does not have the photoresist pattern RP103a. However, in this case, the source region SR101 is formed of the low-concentration semiconductor region SR101a, and therefore the n-type impurity concentration of the low-concentration semiconductor region SR101a needs to be set to a high n-type impurity concentration appropriate for the source region SR101. That is, when the low-concentration semiconductor region SR101a is formed by ion implantation using the photoresist pattern RP101 in the process of FIG. 24, the n-type impurity concentration of the low-concentration semiconductor region SR101a needs to be set to a high n-type impurity concentration similar to that of the high-concentration semiconductor region SR101b. In this case, in order to prevent high concentration implantation of n-type impurities into the region where the p-type semiconductor region PR101 is to be formed, the photoresist pattern RP101 needs to have a photoresist pattern RP103a that covers the region where the p-type semiconductor region PR101 is to be formed. Since the width L102 of the photoresist pattern RP103a of the photoresist pattern RP101 needs to be large to some extent, it is still difficult to suppress the width L101 of the p-type semiconductor region PR101.

[0117] <Main features and effects> FIG. 32 is a cross-sectional view of a main part of the semiconductor device of this embodiment, showing an enlarged view of a part of FIG.

[0118] When a current is passed between the n-type source region SR and the n-type drain region DR, holes (positive holes) HL ​​tend to accumulate at the position schematically shown in Fig. 32. That is, holes HL tend to accumulate from the channel formation region above the p-type semiconductor region PB to the p-type semiconductor region PR below the recessed portion KB.

[0119] In this embodiment, a recessed portion KB is provided in the semiconductor substrate SB, and a p-type semiconductor region PR is formed below the recessed portion KB. Therefore, although the n-type source region SR and the p-type semiconductor region PR are adjacent to each other in a planar view, they are offset from each other in the thickness direction of the semiconductor substrate SB, with the p-type semiconductor region PR being formed at a deeper position than the n-type source region SR. Reflecting this, the accumulation position of holes HL is somewhat separated from the PN junction surface between the n-type source region SR and the p-type semiconductor region PB, thereby suppressing the amount of holes accumulated near the PN junction surface between the n-type source region SR and the p-type semiconductor region PB. That is, in the case of the study example (FIG. 31), the amount of holes accumulated is large near the PN junction surface between the n-type source region SR101 and the p-type semiconductor region PB101. In comparison, in this embodiment (FIG. 32), the amount of holes accumulated near the PN junction surface between the n-type source region SR and the p-type semiconductor region PB can be suppressed.

[0120] An increase in the amount of holes accumulated near the PN junction surface between the n-type source region SR and the p-type semiconductor region PB facilitates the generation of a potential difference between the n-type source region SR and the p-type semiconductor region PB, thereby increasing the potential difference. In this embodiment, by providing a recessed portion KB in the semiconductor substrate SB and forming a p-type semiconductor region PR below the recessed portion KB, the amount of holes accumulated near the PN junction surface between the n-type source region SR and the p-type semiconductor region PB can be suppressed when a large current flows between the n-type source region SR and the n-type drain region DR. As a result, when a large current flows between the n-type source region SR and the n-type drain region DR, the potential difference between the n-type source region SR and the p-type semiconductor region PB can be suppressed, preventing the parasitic bipolar transistor from operating. This improves the on-state breakdown voltage of the LDMOSFET. This, in turn, improves the performance of the semiconductor device.

[0121] Furthermore, in this embodiment, by providing a recessed portion KB in the semiconductor substrate SB and forming a p-type semiconductor region PR below the recessed portion KB, it is possible to suppress the width (dimension) L1 (see FIG. 32) of the p-type semiconductor region PR in the gate length direction (X direction) to be small. This makes it possible to reduce the size (area) of the semiconductor device. The reduction in cell size also makes it possible to reduce the resistance of the semiconductor.

[0122] The reason why the width L1 of the p-type semiconductor region PR can be reduced will be explained below.

[0123] As described above, in the semiconductor device of this embodiment, a recessed portion KB is formed in the semiconductor substrate SB, and a p-type semiconductor region PR is formed below the recessed portion KB. Reflecting this, the manufacturing process of the semiconductor device of this embodiment includes the steps of forming an n-type source region SR in the semiconductor substrate SB by using an ion implantation method, then etching the semiconductor substrate SB to form the recessed portion KB so as to penetrate the n-type source region SR, and then forming the p-type semiconductor region PR in the semiconductor substrate SB below the recessed portion KB by using an ion implantation method.

[0124] After forming an n-type source region SR in the semiconductor substrate SB by ion implantation (see FIG. 9), the semiconductor substrate SB is etched to form a recessed portion KB (see FIG. 11). The recessed portion KB is formed so as to penetrate the n-type source region SR, and thus the recessed portion KB is formed by removing a portion of the n-type source region SR by etching. Therefore, when the recessed portion KB is formed, the region below the recessed portion KB in the semiconductor substrate SB is a region into which almost no n-type impurities were implanted when the n-type source region SR was formed by ion implantation. Then, when a p-type semiconductor region PR is formed below the recessed portion KB by ion implantation (see FIG. 15), the p-type semiconductor region PR can be formed in the region into which almost no n-type impurities were implanted when the n-type source region SR was formed by ion implantation. This makes it possible to set the n-type impurity concentration of the n-type source region SR to an impurity concentration appropriate for the source region of an LDMOSFET, and to suppress or prevent the n-type impurities implanted when forming the n-type source region SR from affecting the effective impurity concentration of the p-type semiconductor region PR. Therefore, the effective p-type impurity concentration of the formed p-type semiconductor region PR101 can be accurately controlled, and the p-type semiconductor region PR101 having a desired impurity concentration can be accurately formed.

[0125] In this embodiment, after the n-type source region SR is formed by ion implantation, the recessed portion KB is formed by etching, and then the p-type semiconductor region PR is formed below the recessed portion KB by ion implantation. Therefore, the photoresist pattern RP1 used when forming the n-type source region SR by ion implantation does not need to cover the region where the p-type semiconductor region PR is to be formed (see FIG. 8). Therefore, ion implantation to form the n-type source region SR can be performed in a state where the region where the p-type semiconductor region PR is to be formed is not covered by the photoresist pattern RP1 and is exposed from the photoresist pattern RP1. Therefore, the photoresist pattern RP1 used when forming the n-type source region SR does not have anything equivalent to the photoresist pattern RP103a (a photoresist pattern covering the region where the p-type semiconductor region PR is to be formed).

[0126] Furthermore, the photoresist pattern RP2 used to form the recessed portion KB has an opening OP1 exposing the region where the recessed portion KB is to be formed. The recessed portion KB can be formed by etching the semiconductor substrate SB at the bottom of the opening OP1 of the photoresist pattern RP2. The photoresist pattern RP4 used to form the p-type semiconductor region PR has an opening OP2 exposing the region where the p-type semiconductor region PR is to be formed. The p-type semiconductor region PR can be formed by ion-implanting p-type impurities into the semiconductor substrate SB through the opening OP2 of the photoresist pattern RP2. Even if the width (dimension) L2 (see FIG. 10) of the opening OP1 in the gate length direction (X direction) is reduced, the stability of the photoresist pattern RP2 is not affected, and the photoresist pattern RP2 does not collapse during formation. Even if the width (dimension) L4 (see FIG. 15) of the opening OP2 in the gate length direction (X direction) is reduced, the stability of the photoresist pattern RP4 is not affected, and the photoresist pattern RP4 does not collapse during formation. Therefore, since the width L2 of the opening OP1 and the width L4 of the opening OP2 can be reduced, it is possible to reduce the width (dimension) L3 (see FIG. 11) of the recess portion KB in the gate length direction (X direction), and it is also possible to reduce the width L1 (see FIG. 32) of the p-type semiconductor region PR in the gate length direction (X direction). The photoresist pattern RP103a needs to have a width L102 that is relatively large, which makes it difficult to suppress the width L101 of the p-type semiconductor region PR101, but in this embodiment, such a restriction does not arise.

[0127] As described above, in this embodiment, it is possible to reduce the width L1 of the p-type semiconductor region PR in the gate length direction, and therefore it is possible to reduce the size (area) of the semiconductor device.

[0128] For example, in the case of the study example (FIGS. 21 to 31), the width L101 of the p-type semiconductor region PR101 in the gate length direction is, for example, about 0.5 μm, but in the case of this embodiment (FIGS. 1 to 20 and 32), the width L3 of the recessed portion KB and the width L1 of the p-type semiconductor region PR in the gate length direction can be, for example, about 0.2 to 0.3 μm. Also, the n-type impurity concentration of the n-type source region SR is, for example, 1E19 to 1E21 / cm 3 It can be about.

[0129] Furthermore, since multiple plugs PGP and PGS can be aligned in a straight line in the gate width direction, the plugs PGP and PGS can be arranged efficiently. Therefore, from this perspective as well, the semiconductor device can be miniaturized in the gate length direction, thereby reducing the area of ​​the semiconductor device. Furthermore, since the p-type semiconductor region PR, the p-type semiconductor region PB, and the plug PGP are enclosed within the n-type source region SR, it is possible to arrange the n-type source region SR over the entire width of the gate electrode GE. Therefore, a large effective gate width area ratio can be ensured.

[0130] (Embodiment 2) 33 and 34 are cross-sectional views of a main part of a semiconductor device according to the present embodiment 2. Fig. 33 shows a cross section corresponding to Fig. 1, and Fig. 34 shows a cross section corresponding to Fig. 2.

[0131] The semiconductor device of the second embodiment shown in FIGS. 33 and 34 differs from the semiconductor device of the first embodiment (FIGS. 1 to 3) in the following points.

[0132] That is, in the second embodiment, the p-type semiconductor region PB is made up of a p-type semiconductor region PBa and a p-type semiconductor region PBb having a higher impurity concentration (p-type impurity concentration) than the p-type semiconductor region PBa. The p-type semiconductor region PR formed below the recessed portion KB is surrounded by the p-type semiconductor region PBb. That is, the bottom and side surfaces of the p-type semiconductor region PR are covered with the p-type semiconductor region PBb. The p-type semiconductor region PR has a higher impurity concentration (p-type impurity concentration) than the p-type semiconductor region PBb. The p-type semiconductor region PBb exists below the p-type semiconductor region PR and below the n-type source region SR. The p-type semiconductor region PBa is adjacent to the p-type semiconductor region PBb (more specifically, adjacent to it in the X direction), and the channel of the LDMOSFET is formed in the p-type semiconductor region PBa. That is, the channel formation region of the LDMOSFET is located within the p-type semiconductor region PBa.

[0133] Other than that, the semiconductor device of the second embodiment is almost the same as the semiconductor device of the first embodiment, so a repeated description thereof will be omitted here.

[0134] The manufacturing process of the semiconductor device according to the second embodiment differs from that according to the first embodiment in the p-type semiconductor region PB forming process shown in FIG. 9 . That is, in the case of the second embodiment, the p-type semiconductor region PB forming process includes a process of forming a p-type semiconductor region PBa by ion implantation of p-type impurities and a process of forming a p-type semiconductor region PBb by ion implantation of p-type impurities, both of which can be performed using the photoresist pattern RP1 as an ion implantation element mask. The ion implantation for forming the p-type semiconductor region PBb has a deeper implantation depth and a larger dose than the ion implantation for forming the p-type semiconductor region PBa. Furthermore, although the ion implantation for forming the p-type semiconductor region PBa uses oblique ion implantation, the ion implantation for forming the p-type semiconductor region PBb may be vertical ion implantation. In the p-type semiconductor region PR forming process, the p-type semiconductor region PR is formed in the p-type semiconductor region PBb.

[0135] In the second embodiment, the p-type semiconductor region PB is composed of a p-type semiconductor region PBb with a high impurity concentration surrounding the p-type semiconductor region PR, and a p-type semiconductor region PBa adjacent to the p-type semiconductor region PBb and having a lower p-type impurity concentration than the p-type semiconductor region PBb. This makes it easier to form the p-type semiconductor region PR with a high impurity concentration below the recessed portion KB. Furthermore, the p-type semiconductor region PR and the p-type semiconductor region PB can be electrically connected with lower resistance. Furthermore, the p-type semiconductor region PBa can be set independently of the impurity concentration of the p-type semiconductor region PBb, and the channel of the LDMOSFET is formed in the p-type semiconductor region PBa. Therefore, even if the impurity concentration of the p-type semiconductor region PBb is increased, the characteristics of the LDMOSFET do not deteriorate.

[0136] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. Appendix 1: The method for manufacturing a semiconductor device including a MISFET as described above can be summarized as follows.

[0137] (a) providing a semiconductor substrate; (b) forming a conductive film for a gate electrode of the MISFET on the semiconductor substrate via a gate insulating film; (c) forming a first resist pattern on the conductive film after the step (b); (d) after the step (c), etching the conductive film using the first resist pattern as an etching mask to form a side surface of the gate electrode on the source side; (e) after the step (d), performing ion implantation using the first resist pattern as a mask to form a source region of the first conductivity type for the MISFET in the semiconductor substrate; (f) removing the first resist pattern after the step (e); (g) after the step (f), forming a second resist pattern on the semiconductor substrate so as to cover a part of the conductive film; wherein the second resist pattern has a first opening that is included in the source region in a plan view; (h) after the step (g), etching the semiconductor substrate using the second resist pattern as an etching mask to form a recessed portion that penetrates the source region, and etching the conductive film using the second resist pattern as an etching mask to form a side surface of the gate electrode on the drain side, thereby forming the gate electrode; (i) after the step (h), removing the second resist pattern; (j) after the step (i), forming a third resist pattern on the semiconductor substrate so as to cover the gate electrode; (k) after the step (j), forming a drain region of the first conductivity type for the MISFET in the semiconductor substrate by ion implantation using the third resist pattern as a mask; (l) after the step (k), removing the third resist pattern; (m) after the step (i), forming a fourth resist pattern on the semiconductor substrate so as to cover the gate electrode; wherein the fourth resist pattern has a second opening at a position overlapping the recessed portion in a plan view; (n) after the step (m), forming a first semiconductor region of a second conductivity type opposite to the first conductivity type under the recessed portion by ion implantation using the fourth resist pattern as a mask; (o) After the step (n), the step of removing the fourth resist pattern. [Explanation of symbols]

[0138] DR, DR101 n-type drain region EP epitaxial layer GE,GE101 gate electrode GF insulating film IL,IL101 insulating film KB recess M1, M101 wiring M1D drain wiring M1S source wiring NBL buried layer ND n-type semiconductor region OP1,OP2 opening PB,PB101 p-type semiconductor region PG, PG101, PGD, PGP, PGP101, PGS plugs PR, PR101 p-type semiconductor region SB1 board body SL,SL101 Metal silicide layer SR, SR101 n-type source region SR101a Low concentration semiconductor region SR101b High concentration semiconductor region SB semiconductor substrate SW1, SW101 Sidewall spacer SW2 sidewall insulating film ZM, ZM101 insulating film

Claims

1. a semiconductor substrate; a source region of a first conductivity type of a MISFET and a drain region of the first conductivity type of the MISFET formed in the semiconductor substrate and spaced apart from each other; a gate electrode of the MISFET formed on the semiconductor substrate between the source region and the drain region via a gate insulating film; a recess formed in the semiconductor substrate that penetrates the source region; a first semiconductor region of a second conductivity type opposite to the first conductivity type provided under the recess; a second semiconductor region of the second conductivity type formed in the semiconductor substrate so as to surround the source region and the first semiconductor region; an interlayer insulating film provided on the semiconductor substrate; a first contact plug electrically connected to the first semiconductor region; a sidewall insulating film formed on a side surface of the recessed portion, The first contact plug penetrates the interlayer insulating film, passes between the sidewall insulating films, and reaches an upper surface of the first semiconductor region.

2. 2. The semiconductor device according to claim 1, a second semiconductor region in contact with a bottom surface and a side surface of the first semiconductor region, and further in contact with a bottom surface and a side surface of the source region other than the side facing the recessed portion;

3. 2. The semiconductor device according to claim 1, In a plan view, the recessed portion is surrounded by the source region.

4. 4. The semiconductor device according to claim 3, a width of the source region and a width of the gate electrode in a gate width direction of the gate electrode, the width being the same as that of the gate electrode;

5. 2. The semiconductor device according to claim 1, A semiconductor device, wherein an upper surface of the first semiconductor region is located below a bottom surface of the source region in the semiconductor substrate.

6. 6. The semiconductor device according to claim 5, a length of the first semiconductor region in a gate length direction of the gate electrode being longer than a length of the recessed portion;

7. 2. The semiconductor device according to claim 1, A semiconductor device, wherein the first semiconductor region is arranged in an island shape in the second semiconductor region in a plan view.

8. 8. The semiconductor device according to claim 7, A semiconductor device, wherein a plurality of the first semiconductor regions are provided in the second semiconductor region.

9. 2. The semiconductor device according to claim 1, a second contact plug that penetrates the interlayer insulating film and is electrically connected to the source region; the first contact plug and the second contact plug are aligned in a straight line in the gate width direction in a plan view, and the boundary between the recessed portion and the source region is sandwiched between the first contact plug and the second contact plug.

10. 10. The semiconductor device according to claim 9, a potential supplied from the first contact plug to the first semiconductor region and a potential supplied from the second contact plug to the source region are the same;

11. 2. The semiconductor device according to claim 1, an upper portion of the second semiconductor region between the source region and the drain region is a channel formation region of the MISFET, A semiconductor device, wherein the first semiconductor region has a higher impurity concentration than the second semiconductor region.

12. 2. The semiconductor device according to claim 1, a third semiconductor region of the first conductivity type interposed between the first semiconductor region and the drain region in a gate length direction of the gate electrode, The semiconductor device, wherein the impurity concentration of the third semiconductor region is lower than the impurity concentration of the drain region.

13. 12. The semiconductor device according to claim 11, the second semiconductor region has a fourth semiconductor region of the second conductivity type surrounding the first semiconductor region and a fifth semiconductor region of the second conductivity type adjacent to the fourth semiconductor region, the fourth semiconductor region has an impurity concentration higher than the impurity concentration of the fifth semiconductor region; The channel formation region is located in the fifth semiconductor region.

14. 2. The semiconductor device according to claim 1, a plurality of pairs of the recessed portion and the first semiconductor region thereunder are provided in the semiconductor substrate; The plurality of sets are spaced apart from each other in a gate width direction of the gate electrode.

15. A method for manufacturing a semiconductor device including a MISFET, comprising the steps of: (a) providing a semiconductor substrate; (b) forming a conductive film on the semiconductor substrate via a gate insulating film; (c) after the step (b), etching the conductive film to form a first pattern made of the conductive film; (d) after the step (c), forming a source region of the first conductivity type of the MISFET in the semiconductor substrate that is not covered with the first pattern by using an ion implantation method; (e) after the step (d), etching the semiconductor substrate to form a recess that penetrates the source region; (f) after the step (e), forming a sidewall insulating film on the side surface of the recessed portion; (g) after the step (f), forming a first semiconductor region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate below the recessed portion by ion implantation; (h) after the step (g), forming an interlayer insulating film on the semiconductor substrate; (i) after the step (h), forming a contact plug in the interlayer insulating film; In the step (i), the contact plug is formed so as to penetrate the interlayer insulating film, pass through the sidewall insulating film, and reach the upper surface of the first semiconductor region.

16. 16. The method for manufacturing a semiconductor device according to claim 15, (b1) forming a first resist pattern on the conductive film after the step (b) and before the step (c); and In the step (c), the conductive film is etched using the first resist pattern as an etching mask to form the first pattern having a first opening; In the step (d), the source region is formed in the semiconductor substrate by implanting ions through the first opening using the first resist pattern as a mask; (d1) removing the first resist pattern after the step (d) and before the step (e); The method for manufacturing a semiconductor device further comprises:

17. 17. The method for manufacturing a semiconductor device according to claim 16, (e1) after the step (d1) and before the step (e), forming a second resist pattern on the semiconductor substrate while covering a part of the first pattern that will become a gate electrode; and In the step (e), the semiconductor substrate is etched using the second resist pattern as an etching mask to form the recessed portion so as to penetrate the source region; (e2) removing the second resist pattern after the step (e) and before the step (f); The method for manufacturing a semiconductor device further comprises:

18. 18. The method for manufacturing a semiconductor device according to claim 17, the second resist pattern has a second opening that is included in the source region in a plan view; In the step (e), the recessed portion is formed by etching the semiconductor substrate at the bottom of the second opening.

19. 18. The method for manufacturing a semiconductor device according to claim 17, In the step (e), the semiconductor substrate is etched using the second resist pattern as an etching mask to form the recessed portion so as to penetrate the source region, and the conductive film is etched using the second resist pattern as an etching mask to form the gate electrode.

20. 20. The method of manufacturing a semiconductor device according to claim 19, (g1) after the step (f) and before the step (g), forming a third resist pattern on the semiconductor substrate so as to cover the gate electrode; and the third resist pattern has a third opening at a position overlapping the recessed portion in a plan view; In the step (g), the first semiconductor region is formed below the recessed portion by ion implantation using the third resist pattern as a mask.

21. 18. The method for manufacturing a semiconductor device according to claim 17, the second resist pattern has a second opening that exposes the first opening in a plan view; a length of the second opening in a gate length direction of the gate electrode being shorter than a length of the first opening;

22. 18. The method for manufacturing a semiconductor device according to claim 17, the second resist pattern is formed on the conductive film and on a part of the source region.

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