Solid-state imaging device and manufacturing method thereof

Abstract

[Problem] To provide: a solid-state imaging device that can form a photoelectric conversion unit and a floating diffusion unit in a semiconductor substrate and, when a channel semiconductor layer of a transistor is formed within a semiconductor layer different from this semiconductor substrate, can form a suitable transistor; and a method for manufacturing the solid-state imaging device. [Solution] A solid-state imaging device of the present disclosure comprises: a first semiconductor substrate that includes a photoelectric conversion unit and a floating diffusion unit; and a first transistor that includes a first semiconductor layer that is disposed over the first semiconductor substrate, a first insulating film that is disposed on a lower surface, an upper surface, and a side surface of the first semiconductor layer, and a first electrode that is disposed on a lower surface, an upper surface, and a side surface of the first insulating film. The first insulating film on the lower surface of the first semiconductor layer is thicker than the first insulating film on the upper surface or the side surface of the first semiconductor layer.

Description

[Technical Field]

[0001] The present disclosure relates to a solid-state imaging device and a manufacturing method thereof. [Background technology]

[0002] When manufacturing a solid-state imaging device, a photoelectric conversion unit and a floating diffusion unit may be formed within a semiconductor substrate, and a channel semiconductor layer of a pixel transistor may be formed within a semiconductor layer separate from the semiconductor substrate. For example, a solid-state imaging device may be manufactured by forming a photoelectric conversion unit, a floating diffusion unit, wiring, etc. on a first semiconductor substrate, and a channel semiconductor layer of a pixel transistor on a second semiconductor substrate, and then bonding the first and second semiconductor substrates together. In this case, since the wiring is disposed on the first semiconductor substrate, it is possible to arrange pixel transistors on the second semiconductor substrate with ample space, enabling the solid-state imaging device to be miniaturized.

[0003] In such solid-state imaging devices, in order to increase the effective channel length of the pixel transistor, a trench may be formed in the second semiconductor substrate, and the gate insulating film and gate electrode of the pixel transistor may be formed in the trench, thereby improving the noise characteristics of the pixel transistor.

[0004] In this case, it is conceivable to further improve the noise characteristics of the pixel transistor by deepening the trench. However, as the trench becomes deeper, it becomes more difficult to inject impurity atoms into the channel semiconductor layer and source / drain regions of the pixel transistor, resulting in a lower impurity concentration in these locations. As a result, when a voltage is applied to the wiring, noise from the wiring is more likely to affect the pixel transistor, deteriorating the noise characteristics of the pixel transistor. This makes it difficult to further miniaturize solid-state imaging devices. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Patent Application Publication No. WO2020 / 075583 Summary of the Invention [Problem to be solved by the invention]

[0006] Therefore, it is conceivable to form a gate insulating film and gate electrode with a GAA (Gate All Around) structure around the channel semiconductor layer of the pixel transistor to protect the channel semiconductor layer from noise using the GAA structure. When the GAA structure is applied to the above-mentioned solid-state imaging device, the gate insulating film and gate electrode are formed, for example, by combining an insulating film and electrode on the first semiconductor substrate with an insulating film and electrode on the second semiconductor substrate. However, when bonding the first and second semiconductor substrates, plasma damage may be applied to the insulating film on the first semiconductor substrate during bonding, which may prevent the formation of a high-performance gate insulating film. As a result, the GAA structure may not be able to sufficiently improve the noise characteristics of the pixel transistor.

[0007] Therefore, the present disclosure provides a solid-state imaging device and a manufacturing method thereof that are capable of forming suitable transistors when a photoelectric conversion section and a floating diffusion section are formed within a semiconductor substrate and the channel semiconductor layer of the transistor is formed within a semiconductor layer separate from this semiconductor substrate. [Means for solving the problem]

[0008] A solid-state imaging device according to a first aspect of the present disclosure includes a first semiconductor substrate including a photoelectric conversion section and a floating diffusion section, a first semiconductor layer provided above the first semiconductor substrate, a first insulating film provided on a lower surface, an upper surface, and a side surface of the first semiconductor layer, and a first transistor including a first electrode provided on the lower surface, an upper surface, and a side surface of the first insulating film, wherein the thickness of the first insulating film on the lower surface of the first semiconductor layer is thicker than the thickness of the first insulating film on the upper surface or the side surface of the first semiconductor layer. This makes it possible, for example, to suitably protect the first semiconductor layer by the thick first insulating film on the lower surface of the first semiconductor layer, thereby realizing a suitable first transistor.

[0009] In addition, in this first aspect, the thickness of the first insulating film on the lower surface of the first semiconductor layer may be at least twice the thickness of the first insulating film on the upper surface or side surface of the first semiconductor layer, which makes it possible, for example, to more suitably protect the first semiconductor layer with a sufficiently thick first insulating film on the lower surface of the first semiconductor layer, thereby realizing a more suitable first transistor.

[0010] In addition, in this first aspect, the first semiconductor layer, the first insulating film, and the first electrode may extend in a first direction parallel to the surface of the first semiconductor substrate, and the first insulating film and the first electrode may have a tubular shape surrounding the first semiconductor layer, thereby realizing, for example, a GAA structure or a pseudo GAA structure.

[0011] In this first aspect, the first semiconductor layer may be a part of a second semiconductor substrate provided above the first semiconductor substrate, which makes it possible to manufacture a solid-state imaging device by bonding the first semiconductor substrate and the second semiconductor substrate together, for example.

[0012] In this first aspect, the first transistor may be an amplifier transistor, a select transistor, a reset transistor, or a switch transistor, thereby making it possible to realize, for example, a suitable pixel transistor.

[0013] In addition, in this first aspect, the first insulating film may include a first film provided on the lower surface of the first semiconductor layer and a second film provided on the upper surface and side surfaces of the first semiconductor layer, which makes it possible to form, for example, the first insulating film (first film) on the lower surface of the first semiconductor layer and the first insulating film (second film) on the upper surface and side surfaces of the first semiconductor layer in separate processes.

[0014] In addition, in this first aspect, the first insulating film may further include a third film provided on the lower surface of the first film, which makes it possible to form the first insulating film by combining, for example, the third film on the first semiconductor substrate side and the first film on the first semiconductor layer (e.g., the second semiconductor substrate) side.

[0015] In addition, in this first side surface, the first electrode may include a first layer provided on the lower surface of the first insulating film and a second layer provided on the upper surface and side surfaces of the first insulating film, which makes it possible to form, for example, the first electrode (first layer) on the lower surface of the first insulating film and the first electrode (second layer) on the upper surface and side surfaces of the first insulating film in separate processes.

[0016] The solid-state imaging device of the first aspect may further include a second insulating film having the same thickness as the first electrode on the lower surface of the first insulating film and provided laterally of the first electrode on the lower surface of the first insulating film. This makes it possible, for example, to form the first insulating film on the first semiconductor substrate with the second insulating film interposed therebetween, then remove part of the second insulating film, and then form part of the first electrode between the first semiconductor substrate and the first insulating film.

[0017] The solid-state imaging device according to the first aspect may further include a first wiring provided on an upper surface of the first electrode and electrically connecting the first electrode and the floating diffusion region, which makes it possible to form the first wiring after forming the first transistor, for example.

[0018] The solid-state imaging device according to the first aspect may further include a second semiconductor layer provided above the first semiconductor substrate, and a second wiring electrically connecting the first semiconductor substrate and the second semiconductor layer, thereby making it possible to prevent the potential of the second semiconductor layer from floating, for example.

[0019] In this first aspect, the second semiconductor layer may be part of a second semiconductor substrate provided above the first semiconductor substrate, which makes it possible to electrically connect a second transistor on the first semiconductor substrate to a second semiconductor substrate different from the first semiconductor substrate, for example.

[0020] The solid-state imaging device according to the first aspect may further include a third wiring provided on a lower surface of the first electrode and electrically connecting the first electrode and the floating diffusion region, which makes it possible to form the first wiring before forming the first transistor, for example.

[0021] The solid-state imaging device according to the first aspect may further include a fourth wiring provided on a side surface of the first electrode and electrically connecting the first electrode and the floating diffusion region, which makes it possible to form the first wiring after forming the first transistor, for example.

[0022] A method for manufacturing a solid-state imaging device according to a second aspect of the present disclosure includes forming a photoelectric conversion section and a floating diffusion section in a first semiconductor substrate, and forming a first transistor including a first semiconductor layer provided above the first semiconductor substrate, a first insulating film provided on a lower surface, an upper surface, and a side surface of the first semiconductor layer, and a first electrode provided on the lower surface, an upper surface, and a side surface of the first insulating film, wherein the thickness of the first insulating film on the lower surface of the first semiconductor layer is set to be thicker than the thickness of the first insulating film on the upper surface or the side surface of the first semiconductor layer. This makes it possible, for example, to suitably protect the first semiconductor layer with the thick first insulating film on the lower surface of the first semiconductor layer, thereby realizing a suitable first transistor.

[0023] In addition, in this second aspect, the first semiconductor layer may be formed by bonding the first semiconductor substrate and a second semiconductor substrate together and processing the second semiconductor substrate through the first semiconductor layer, thereby making it possible to manufacture a solid-state imaging device by bonding the first semiconductor substrate and the second semiconductor substrate together, for example.

[0024] In addition, in this second aspect, the first insulating film may include a first film provided on the lower surface of the first semiconductor layer and a second film provided on the upper surface and side surfaces of the first semiconductor layer, and the first semiconductor substrate and the second semiconductor substrate may be bonded together via the first film provided on the lower surface of the second semiconductor substrate. This makes it possible, for example, to form the first insulating film (first film) on the lower surface of the first semiconductor layer and the first insulating film (second film) on the upper surface and side surfaces of the first semiconductor layer in separate processes.

[0025] In addition, in this second aspect, the first insulating film may further include a third film provided on a lower surface of the first film, and the first semiconductor substrate and the second semiconductor substrate may be bonded together via the third film provided on an upper surface of the first semiconductor substrate. This makes it possible to form a first insulating film by combining, for example, the third film on the first semiconductor substrate side and the first film on the second semiconductor substrate side.

[0026] In addition, in this second aspect, the first electrode may include a first layer provided on the lower surface of the first insulating film and a second layer provided on the upper surface and side surfaces of the first insulating film, and the first semiconductor substrate and the second semiconductor substrate may be bonded together via the first layer provided on the upper surface of the first semiconductor substrate. This makes it possible, for example, to form the first electrode (first layer) on the lower surface of the first insulating film and the first electrode (second layer) on the upper surface and side surfaces of the first insulating film in separate processes.

[0027] In this second aspect, the first semiconductor substrate and the second semiconductor substrate may be further bonded together via a second insulating film provided on a lower surface of the first film, and the first electrode may be formed by removing a portion of the second insulating film from between the first semiconductor substrate and the second semiconductor substrate after the bonding, and then forming a portion of the first electrode between the first semiconductor substrate and the second semiconductor substrate after the removal. This makes it possible to form, for example, the first electrode on the lower surface of the first insulating film and the first electrode on the upper surface and side surfaces of the first insulating film in the same process. [Brief explanation of the drawings]

[0028] [Figure 1] 1 is a block diagram showing a configuration of a solid-state imaging device according to a first embodiment. [Figure 2] FIG. 1 is a plan view showing the structure of a solid-state imaging device according to a first embodiment. [Figure 3] 1 is a circuit diagram showing a configuration of a solid-state imaging device according to a first embodiment. [Figure 4] 1 is a cross-sectional view showing the structure of a solid-state imaging device according to a first embodiment. [Figure 5] 1 is a cross-sectional view showing the structure of an amplifying transistor according to a first embodiment. [Figure 6] FIG. 2 is a perspective view illustrating the structure of the amplifying transistor of the first embodiment. [Figure 7] FIG. 10 is a cross-sectional view for explaining a problem of a solid-state imaging device as a comparative example of the first embodiment. [Figure 8] 1A and 1B are cross-sectional views (1 / 6) illustrating a method for manufacturing the solid-state imaging device according to the first embodiment. [Figure 9] 10A and 10B are cross-sectional views (2 / 6) illustrating a method for manufacturing the solid-state imaging device according to the first embodiment. [Figure 10] 3A and 3B are cross-sectional views (3 / 6) illustrating a method for manufacturing the solid-state imaging device according to the first embodiment. [Figure 11] 4 is a cross-sectional view (4 / 6) illustrating a method for manufacturing the solid-state imaging device according to the first embodiment. [Figure 12] 5A and 5B are cross-sectional views (5 / 6) illustrating a method for manufacturing the solid-state imaging device according to the first embodiment. [Figure 13] 6 is a cross-sectional view (6 / 6) illustrating the method for manufacturing the solid-state imaging device according to the first embodiment. [Figure 14] FIG. 2 is a cross-sectional view showing the structure of a solid-state imaging device according to a first modified example of the first embodiment. [Figure 15] FIG. 4 is a cross-sectional view showing a structure of the amplifying transistor of the first modified example. [Figure 16] FIG. 10 is a cross-sectional view (1 / 3) illustrating a method for manufacturing the solid-state imaging device of the first modified example. [Figure 17] FIG. 10 is a cross-sectional view (2 / 3) illustrating a method for manufacturing the solid-state imaging device of the first modified example. [Figure 18] FIG. 10 is a cross-sectional view (3 / 3) illustrating a method for manufacturing the solid-state imaging device of the first modified example. [Figure 19] FIG. 10 is a cross-sectional view showing the structure of a solid-state imaging device according to a second modified example of the first embodiment. [Figure 20] FIG. 10 is a cross-sectional view (1 / 2) illustrating a method for manufacturing the solid-state imaging device of the second modified example. [Figure 21] FIG. 10 is a cross-sectional view (2 / 2) illustrating a method for manufacturing the solid-state imaging device of the second modified example. [Figure 22] FIG. 10 is a cross-sectional view showing the structure of a solid-state imaging device according to a third modified example of the first embodiment. [Figure 23] FIG. 11 is a cross-sectional view (1 / 2) illustrating a method for manufacturing the solid-state imaging device of the third modified example. [Figure 24] FIG. 11 is a cross-sectional view (1 / 2) illustrating a method for manufacturing the solid-state imaging device of the third modified example. [Figure 25] FIG. 10 is a cross-sectional view showing the structure of a solid-state imaging device according to a second embodiment. [Figure 26] FIG. 10 is a cross-sectional view showing the structure of an amplifying transistor according to a second embodiment. [Figure 27] 10 is a cross-sectional view (1 / 5) illustrating a method for manufacturing a solid-state imaging device according to a second embodiment. [Figure 28] 10 is a cross-sectional view (2 / 5) illustrating a method for manufacturing the solid-state imaging device according to the second embodiment. [Figure 29] 10 is a cross-sectional view (3 / 5) illustrating a method for manufacturing the solid-state imaging device according to the second embodiment. [Figure 30] 10 is a cross-sectional view (4 / 5) illustrating a method for manufacturing the solid-state imaging device according to the second embodiment. [Figure 31] 5 is a cross-sectional view (5 / 5) illustrating a method for manufacturing the solid-state imaging device according to the second embodiment. [Figure 32] FIG. 10 is a cross-sectional view showing the structure of a solid-state imaging device according to a modified example of the second embodiment. [Figure 33] 10 is a cross-sectional view (1 / 2) illustrating a method for manufacturing the solid-state imaging device of the modified example. [Figure 34] 10 is a cross-sectional view (2 / 2) illustrating a method for manufacturing the solid-state imaging device of the modified example. [Figure 35]FIG. 1 is a block diagram illustrating an example of the configuration of an electronic device. [Figure 36] FIG. 1 is a block diagram showing an example of the configuration of a mobile object control system. [Figure 37] 37 is a plan view showing a specific example of the setting position of the imaging unit in FIG. 36. FIG. [Figure 38] FIG. 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 39] FIG. 2 is a block diagram showing an example of the functional configuration of a camera head and a CCU. DETAILED DESCRIPTION OF THE INVENTION

[0029] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0030] (First embodiment) FIG. 1 is a block diagram showing the configuration of a solid-state imaging device according to the first embodiment.

[0031] The solid-state imaging device of FIG. 1 is a CMOS (Complementary Metal Oxide Semiconductor) type image sensor, and includes a pixel array region 2 having a plurality of pixels 1, a control circuit 3, a vertical drive circuit 4, a plurality of column signal processing circuits 5, a horizontal drive circuit 6, an output circuit 7, a plurality of vertical signal lines 8, and a horizontal signal line 9.

[0032] Each pixel 1 includes a photodiode that functions as a photoelectric conversion unit and a MOS transistor that functions as a pixel transistor. Examples of the pixel transistor include a transfer transistor, an amplification transistor, a selection transistor, a reset transistor, and a switch transistor. These pixel transistors may be shared by several pixels 1.

[0033] The pixel array region 2 has a plurality of pixels 1 arranged in a two-dimensional array. The pixel array region 2 includes an effective pixel region that receives light, performs photoelectric conversion, and outputs signal charges generated by the photoelectric conversion, and a black reference pixel region that outputs optical black, which serves as a reference for the black level. Generally, the black reference pixel region is arranged on the periphery of the effective pixel region.

[0034] The control circuit 3 generates various signals that serve as references for the operation of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on a vertical synchronization signal, a horizontal synchronization signal, a master clock, etc. The signals generated by the control circuit 3 are, for example, clock signals and control signals, and are input to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0035] The vertical drive circuit 4 includes, for example, a shift register, and vertically scans each pixel 1 in the pixel array region 2 row by row. The vertical drive circuit 4 further supplies pixel signals based on signal charges generated by each pixel 1 to a column signal processing circuit 5 through vertical signal lines 8.

[0036] The column signal processing circuits 5 are arranged, for example, for each column of pixels 1 in the pixel array region 2, and perform signal processing for each column of signals output from one row of pixels 1 based on signals from the black reference pixel region. Examples of this signal processing include noise reduction and signal amplification.

[0037] The horizontal drive circuit 6 includes, for example, a shift register, and supplies pixel signals from each column signal processing circuit 5 to a horizontal signal line 9 .

[0038] The output circuit 7 processes the signals supplied from each column signal processing circuit 5 through the horizontal signal line 9, and outputs the processed signals.

[0039] FIG. 2 is a plan view showing the structure of the solid-state imaging device of the first embodiment.

[0040] 2 illustrates four pixels 1 and nine floating diffusions FD in the pixel array region 2. Each pixel 1 includes four transfer transistors TG, an amplifier transistor AMP, a selection transistor SEL, a reset transistor RST, and a switch transistor SWI. Each floating diffusion FD is provided at a corner of four adjacent pixels 1.

[0041] Each transfer transistor TG is used to transfer signal charges from the photodiode in each pixel 1 to the corresponding floating diffusion FD. Each floating diffusion FD converts the signal charges from the photodiode into a voltage signal and outputs it. The amplifier transistor AMP amplifies the voltage signal read out from the corresponding floating diffusion FD. The select transistor SEL has the function of selecting the corresponding pixel 1. The reset transistor RST resets the potential of the corresponding floating diffusion FD. The switch transistor SWI has the function of switching the state of the corresponding floating diffusion FD.

[0042] FIG. 3 is a circuit diagram showing the configuration of the solid-state imaging device of the first embodiment.

[0043] Each pixel 1 of this embodiment includes a photodiode PD, a transfer transistor TG, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, a switch transistor SWI, and a floating diffusion FD, as shown in Fig. 3. One transfer transistor TG shown in Fig. 3 collectively represents the four transfer transistors TG of each pixel 1 shown in Fig. 2.

[0044] The anode of the photodiode PD is electrically connected to the ground wiring GND. The cathode of the photodiode PD is electrically connected to the floating diffusion region FD via the transfer transistor TG. The floating diffusion region FD is electrically connected to the gate of the amplification transistor AMP. The amplification transistor AMP and the selection transistor SEL are connected in series between the power supply wiring VDD and the vertical signal line 8. The reset transistor RST and the switch transistor SWI are connected in series between the power supply wiring VDD and the floating diffusion region FD.

[0045] When the switch transistor SWI is turned off, the floating diffusion FD is electrically isolated from the reset transistor RST, and the capacitance of the floating diffusion FD decreases. When the capacitance of the floating diffusion FD decreases, the potential of the floating diffusion FD drops significantly with a small number of signal electrons, and a highly sensitive voltage signal is output from the floating diffusion FD. On the other hand, when there are a large number of signal electrons, the signal charge overflows from the floating diffusion FD, making it impossible to obtain a voltage signal corresponding to the amount of light incident on the photodiode PD.

[0046] When the switch transistor SWI is turned on, the floating diffusion FD is electrically connected to the reset transistor RST, and the capacitance of the floating diffusion FD increases. When the capacitance of the floating diffusion FD increases, the floating diffusion FD can receive more electrons, but the sensitivity of the floating diffusion FD decreases.

[0047] Therefore, the solid-state imaging device of this embodiment can output an image obtained by reading out signal charges in the high-sensitivity operation mode and an image obtained by reading out signal charges in the low-sensitivity operation mode by switching on and off the switch transistor SWI. The solid-state imaging device of this embodiment can realize an expansion of the dynamic range by combining these images.

[0048] FIG. 4 is a cross-sectional view showing the structure of the solid-state imaging device of the first embodiment.

[0049] FIG. 4 shows one pixel 1 of the solid-state imaging device of this embodiment. As shown in FIG. 4, the solid-state imaging device of this embodiment includes a first semiconductor substrate 11, a gate insulating film 12, a gate electrode 13, a first interlayer insulating film 14, wiring 15, a second interlayer insulating film 16, an electrode 17, a third interlayer insulating film 18, a second semiconductor substrate 21, an insulating film 22, a fourth interlayer insulating film 23, an insulating film 24, an electrode 25, a fifth interlayer insulating film 26, and wiring 31. The first semiconductor substrate 11 includes an n-type region 11a, a p-type region 11b, and an n-type region 11c. FIG. 4 also shows an insulating film 18a that is part of the third interlayer insulating film 18 and a semiconductor layer 21a that is part of the second semiconductor substrate 21.

[0050] FIG. 4 shows X, Y, and Z axes that are perpendicular to each other. The X and Y directions correspond to the lateral (horizontal) direction, and the Z direction corresponds to the longitudinal (vertical) direction. The +Z direction corresponds to the upward direction, and the -Z direction corresponds to the downward direction. The -Z direction may or may not strictly coincide with the direction of gravity.

[0051] The solid-state imaging device of this embodiment is manufactured by bonding a first substrate S1 including a first semiconductor substrate 11 and the like and a second substrate S2 including a second semiconductor substrate 21 and the like. FIG. 4 shows the bonding surface S of the first substrate S1 and the second substrate S2. In FIG. 4, the X direction and Y direction are parallel to the upper surface of the first semiconductor substrate 11 and the bonding surface S, and the Z direction is perpendicular to the upper surface of the first semiconductor substrate 11 and the bonding surface S. The second semiconductor substrate 21 is disposed above the first semiconductor substrate 11, i.e., in the +Z direction of the first semiconductor substrate 11.

[0052] The first semiconductor substrate 11 is, for example, a silicon substrate. As shown in FIG. 4, the first semiconductor substrate 11 includes a photodiode PD and a floating diffusion region FD. The photodiode PD is formed by a pn junction between an n-type region 11a and a p-type region 11b, and functions as a photoelectric conversion region that converts light into electric charges. In FIG. 4, the p-type region 11b is formed around the n-type region 11a. The floating diffusion region FD is formed by an n-type region 11c near the top surface of the first semiconductor substrate 11.

[0053] The gate insulating film 12 and the gate electrode 13 are formed in this order on the first semiconductor substrate 11 to form one transfer transistor TG. The gate insulating film 12 is, for example, a silicon oxide film. The gate electrode 13 is, for example, a polysilicon layer. The other three transfer transistors TG in the pixel 1 shown in FIG. 4 may also have a structure similar to that of the transfer transistor TG shown in FIG. 4.

[0054] The first interlayer insulating film 14 is formed on the first semiconductor substrate 11 and covers the gate insulating film 12 and the gate electrode 13. The wiring 15 is formed on the first interlayer insulating film 14. The wiring 15 is, for example, a polysilicon wiring.

[0055] The second interlayer insulating film 16 is formed on the first interlayer insulating film 14 and covers the wiring 15. The electrode 17 is formed on the second interlayer insulating film 16 and forms the amplifier transistor AMP. The electrode 17 is, for example, a polysilicon electrode. The amplifier transistor AMP is an example of a first transistor of the present disclosure, and the electrode 17 is an example of a first layer in the first electrode of the present disclosure.

[0056] The third interlayer insulating film 18 is formed on the second interlayer insulating film 16 and covers the electrode 17. As described above, the third interlayer insulating film 18 includes the insulating film 18a. The insulating film 18a is formed on the electrode 17 and forms the amplifying transistor AMP. The insulating film 18a is, for example, a silicon oxide film. The insulating film 18a is an example of a third film in the first insulating film of the present disclosure.

[0057] The second semiconductor substrate 21 is, for example, a silicon substrate. As described above, the second semiconductor substrate 21 includes the semiconductor layer 21a. The semiconductor layer 21a is formed on the insulating film 18a via the insulating film 22. The insulating film 22 is, for example, a silicon oxide film. In FIG. 4, the insulating film 22 is provided on the lower surface of the semiconductor layer 21a, the insulating film 18a is provided on the lower surface of the insulating film 22, and the electrode 17 is provided on the lower surface of the insulating film 18a. The semiconductor layer 21a is an example of a first semiconductor layer of the present disclosure, and the insulating film 22 is an example of a first film in the first insulating film of the present disclosure.

[0058] The fourth interlayer insulating film 23 is formed on the third interlayer insulating film 18. The insulating film 24 is formed on the upper surface of the semiconductor layer 21a, the side surfaces of the semiconductor layer 21a, the insulating film 22, and the insulating film 18a, and the upper surface of the electrode 17, thereby forming the amplification transistor AMP. The insulating film 24 is, for example, a silicon oxide film. The electrode 25 is formed on the upper surface of the insulating film 24, the side surfaces of the insulating film 24, and the upper surface of the electrode 17, thereby forming the amplification transistor AMP. The electrode 25 is, for example, a polysilicon electrode. The insulating film 24 is an example of a second film in the first insulating film of the present disclosure, and the electrode 25 is an example of a second layer in the first electrode of the present disclosure.

[0059] The fifth interlayer insulating film 26 is formed on the fourth interlayer insulating film 23, and covers the amplification transistor AMP together with the third interlayer insulating film 18 and the fourth interlayer insulating film 23.

[0060] The wiring 31 is formed in the first interlayer insulating film 14, the second interlayer insulating film 16, the third interlayer insulating film 18, the fourth interlayer insulating film 23, and the fifth interlayer insulating film 26, and electrically connects the floating diffusion FD and the electrode 25. One end of the wiring 31 is provided on the upper surface of the floating diffusion FD, and the other end of the wiring 31 is provided on the upper surface of the electrode 25. The wiring 31 is, for example, a metal wiring or a semiconductor wiring. The wiring 31 is an example of the first wiring of the present disclosure.

[0061] The solid-state imaging device of this embodiment further includes a color filter and an on-chip lens (not shown) on the lower surface of the first semiconductor substrate 11 in this order.

[0062] 5 and 6 are a cross-sectional view and a perspective view showing the structure of the amplification transistor AMP of the first embodiment.

[0063] As shown in FIGS. 5 and 6 , the amplification transistor AMP of this embodiment includes a columnar semiconductor layer 41 having a columnar shape extending in the Y direction, a tubular insulating film 42 having a tubular shape extending in the Y direction, and a tubular electrode 43 having a tubular shape extending in the Y direction. The columnar semiconductor layer 41 is formed of the semiconductor layer 21a described above ( FIG. 5 ). The tubular insulating film 42 is formed of the insulating films 18a, 22, and 24 described above ( FIG. 5 ). The tubular electrode 43 is formed of the electrodes 17 and 25 described above ( FIG. 5 ). The columnar semiconductor layer 41 is an example of the first semiconductor layer of the present disclosure, the tubular insulating film 42 is an example of the first insulating film of the present disclosure, and the tubular electrode 43 is an example of the first electrode of the present disclosure. The Y direction is an example of the first direction of the present disclosure.

[0064] The tubular insulating film 42 is formed on the lower surface, upper surface, and side surfaces of the columnar semiconductor layer 41, and extends in a tubular shape in the Y direction. Therefore, the tubular insulating film 42 is formed in a tubular shape around the columnar semiconductor layer 41 so as to surround the columnar semiconductor layer 41. Similarly, the tubular electrode 43 is formed on the lower surface, upper surface, and side surfaces of the tubular insulating film 42, and extends in a tubular shape in the Y direction. Therefore, the tubular electrode 43 is formed in a tubular shape around the tubular insulating film 42 so as to surround the columnar semiconductor layer 41 and the tubular insulating film 42.

[0065] 5 shows a thickness T1 of the tubular insulating film 42 on the lower surface of the pillar-shaped semiconductor layer 41, a thickness T2 of the tubular insulating film 42 on the upper surface of the pillar-shaped semiconductor layer 41, and a thickness T3 of the tubular insulating film 42 on the side surface of the pillar-shaped semiconductor layer 41. The thickness T1 is equal to the sum of the thickness of the insulating film 18a and the thickness of the insulating film 22. The thickness T2 is equal to the thickness of the insulating film 24 on the upper surface of the pillar-shaped semiconductor layer 41. The thickness T3 is equal to the thickness of the insulating film 24 on the side surface of the pillar-shaped semiconductor layer 41.

[0066] In this embodiment, the insulating film 24 has a substantially uniform thickness. Therefore, the thickness T2 of this embodiment is substantially equal to the thickness T3 (T2=T3). On the other hand, the thickness T1 of this embodiment is thicker than the thicknesses T2 and T3 (T1>T2, T1>T3), and is, for example, at least twice the thicknesses T2 and T3 (T1≧2×T2, T1≧2×T3). Therefore, according to this embodiment, the thick tubular insulating film 42 on the lower surface of the pillar-shaped semiconductor layer 41 can suitably protect the pillar-shaped semiconductor layer 41. The effect of such a tubular insulating film 42 will be described in further detail later. The thickness T2 may be different from the thickness T3 (T2≠T3).

[0067] When the columnar semiconductor layer 41, the tubular insulating film 42, and the tubular electrode 43 function as the channel semiconductor layer, gate insulating film, and gate electrode of the amplifying transistor AMP as a whole, the tubular insulating film 42 and the tubular electrode 43 become the gate insulating film and gate electrode of the GAA structure described above. In the GAA structure, the gate insulating film and gate electrode are formed in a tubular shape around the channel semiconductor layer so as to surround the channel semiconductor layer.

[0068] However, in the tubular insulating film 41 of this embodiment, the thickness T1 is greater than the thicknesses T2 and T3. Therefore, if the thickness T1 is sufficiently greater than the thicknesses T2 and T3, the channel in the columnar semiconductor layer 41 will occur only near the top surface and side surfaces of the columnar semiconductor layer 41, and will not occur near the bottom surface of the columnar semiconductor layer 41. In this case, the tubular insulating film 42 and the tubular electrode 43 on the top surface and side surfaces of the columnar semiconductor layer 41 correspond to the gate insulating film and gate electrode, but the tubular insulating film 42 and the tubular electrode 43 on the bottom surface of the columnar semiconductor layer 41 do not correspond to the gate insulating film and gate electrode. As a result, the tubular insulating film 42 and the tubular electrode 43 do not correspond to the gate insulating film and gate electrode of the GAA structure. Therefore, the tubular insulating film 42 and the tubular electrode 43 of this embodiment are not referred to as the gate insulating film and gate electrode.

[0069] In this embodiment, the entire columnar semiconductor layer 41, the tubular insulating film 42, and the tubular electrode 43 may function as the channel semiconductor layer, the gate insulating film, and the gate electrode, or only portions of the columnar semiconductor layer 41, the tubular insulating film 42, and the tubular electrode 43 may function as the channel semiconductor layer, the gate insulating film, and the gate electrode. For example, when the thickness T1 is sufficiently close to the thicknesses T2 and T3, the former gate insulating film and gate electrode have a GAA structure. On the other hand, when the thickness T1 is sufficiently thicker than the thicknesses T2 and T3, the latter gate insulating film and gate electrode do not have a GAA structure. In the latter case, the tubular insulating film 42 and the tubular electrode 43 can be said to have a pseudo-GAA structure. That is, the tubular insulating film 42 and the tubular electrode 43 of this embodiment may have a GAA structure or a pseudo-GAA structure.

[0070] The source region and drain region of the amplifying transistor AMP of this embodiment are formed in the ±Y direction of the columnar semiconductor layer 41, the tubular insulating film 42, and the tubular electrode 43, as shown in FIG.

[0071] The structure of the amplifier transistor AMP of this embodiment is also applicable to the select transistor SEL, reset transistor RST, and switch transistor SWI. The gate insulating film and gate electrode of at least one of the select transistor SEL, reset transistor RST, and switch transistor SWI of this embodiment may have the same GAA structure as the amplifier transistor AMP or a pseudo GAA structure.

[0072] FIG. 7 is a cross-sectional view for explaining a problem with a solid-state imaging device as a comparative example of the first embodiment.

[0073] The solid-state imaging device of this comparative example has a structure similar to that of the solid-state imaging device of the first embodiment, but does not include the insulating film 22. Therefore, the thickness T1 of the tubular insulating film 42 of this comparative example is approximately equal to the thicknesses T2 and T3 of the tubular insulating film 42 (T1 = T2 = T3). For definitions of the tubular insulating film 42 and the thicknesses T1, T2, and T3, see FIG. 5.

[0074] 7 schematically shows noise generated from the wiring 15. When a voltage is applied to the wiring 15, noise may be generated from the wiring 15. If this noise reaches the semiconductor layer 21a of the amplifier transistor AMP, the operation of the amplifier transistor AMP may be adversely affected (bias interference) by this noise.

[0075] Therefore, the amplification transistor AMP of this comparative example is provided with an insulating film 18a and an electrode 17 on the lower surface of the semiconductor layer 21a, and as a result, is provided with a gate insulating film (tubular insulating film 42) and a gate electrode (tubular electrode 43) of a GAA structure. Therefore, according to this comparative example, the insulating film 18a and the electrode 17 on the lower surface of the semiconductor layer 21a can protect the semiconductor layer 21a from noise.

[0076] The gate insulating film (tubular insulating film 42) and gate electrode (tubular electrode 43) of this comparative example are formed, for example, as follows. First, an electrode 17 and a third interlayer insulating film 18 (including an insulating film 18a) are formed on a first semiconductor substrate 11, and the first semiconductor substrate 11 and a second semiconductor substrate 21 are bonded together with the electrode 17 and the third interlayer insulating film 18 interposed therebetween. Next, the second semiconductor substrate 21 is etched into a semiconductor layer 21a (columnar semiconductor layer 41), and an insulating film 24 and an electrode 25 are formed on the top and side surfaces of the semiconductor layer 21a. In this manner, a gate insulating film and a gate electrode having a GAA structure are formed.

[0077] In this case, when bonding the first semiconductor substrate 11 and the second semiconductor substrate 21, plasma damage may be inflicted on the insulating film 18a on the first semiconductor substrate 11 side during bonding, which may prevent the formation of a high-performance gate insulating film. FIG. 7 schematically shows plasma damage inflicted on the insulating film 18a. Such plasma damage may prevent the noise characteristics of the amplifier transistor AMP from being sufficiently improved by the GAA structure. This is because such plasma damage may cause undesirable channels to be generated near the bottom surface of the semiconductor layer 21a. In other words, the gate insulating film and gate electrode on the bottom surface of the semiconductor layer 21a may adversely affect the operation of the amplifier transistor AMP.

[0078] Therefore, in this embodiment, the thickness T1 of the tubular insulating film 42 is set to be thicker than the thicknesses T2 and T3 of the tubular insulating film 42 (T1>T2, T1>T3). As a result, the tubular insulating film 42 and the tubular electrode 43 on the lower surface of the pillar-shaped semiconductor layer 41 contribute little or no contribution to the operation of the amplifier transistor AMP. As a result, it is possible to realize an amplifier transistor AMP having desired current-voltage characteristics while protecting the pillar-shaped semiconductor layer 41 from noise from the wiring 15. Furthermore, according to this embodiment, the effective channel length of the amplifier transistor AMP can be increased by increasing the dimension of the pillar-shaped semiconductor layer 41 in the Z direction.

[0079] It is desirable that the tubular insulating film 42 and the tubular electrode 43 on the lower surface of the pillar-shaped semiconductor layer 41 contribute as little as possible to the operation of the amplifying transistor AMP. Therefore, it is desirable that the thickness T1 of the tubular insulating film 42 in this embodiment be as thick as possible than the thicknesses T2 and T3 of the tubular insulating film 42. For example, it is desirable that the thickness T1 in this embodiment be at least twice the thicknesses T2 and T3 (T1≧2×T2, T1≧2×T3).

[0080] 8 to 13 are cross-sectional views showing a method for manufacturing the solid-state imaging device of the first embodiment.

[0081] First, n-type region 11a, p-type region 11b, and n-type region 11c are formed in first semiconductor substrate 11 by ion implantation (FIG. 8A). As a result, photodiode PD and floating diffusion FD are formed in first semiconductor substrate 11. N-type region 11a, p-type region 11b, and n-type region 11c are formed, for example, by implanting p-type impurity ions into p-type region 11b and n-type impurity ions into n-type region 11c.

[0082] Next, a gate insulating film 12 is formed on the first semiconductor substrate 11, and a gate electrode 13 is formed on the gate insulating film 12 (A in FIG. 8). As a result, a transfer transistor TG is formed on the first semiconductor substrate 11. The gate insulating film 12 and the gate electrode 13 are formed, for example, by forming a silicon oxide film that will become the gate insulating film 12 on the first semiconductor substrate 11, depositing a polysilicon layer that will become the gate electrode 13 on the silicon oxide film by thermal CVD (Chemical Vapor Deposition), and processing the polysilicon layer by photolithography and dry etching. By this dry etching, the gate electrode 13 is formed from the polysilicon layer, and the gate insulating film 12 is formed from the silicon oxide film.

[0083] Next, a first interlayer insulating film 14 is formed on the first semiconductor substrate 11 via the gate insulating film 12 and the gate electrode 13 (B in FIG. 8). The first interlayer insulating film 14 is formed, for example, by depositing the first interlayer insulating film 14 on the first semiconductor substrate 11 by plasma CVD and planarizing the surface of the first interlayer insulating film 14 by CMP (Chemical Mechanical Polishing).

[0084] Next, wiring 15 is formed on the first interlayer insulating film 14, and a second interlayer insulating film 16 is formed on the first interlayer insulating film 14 with the wiring 15 interposed therebetween (FIG. 9A). The wiring 15 is formed, for example, by depositing a polysilicon layer that will become the wiring 15 on the first interlayer insulating film 14 by thermal CVD, and then processing the polysilicon layer by photolithography and dry etching. The second interlayer insulating film 16 is formed, for example, by depositing a second interlayer insulating film 16 on the first interlayer insulating film 14 by plasma CVD, and then planarizing the surface of the second interlayer insulating film 16 by CMP.

[0085] Next, an electrode 17 is formed on the second interlayer insulating film 16, and a third interlayer insulating film 18 is formed on the second interlayer insulating film 16 with the electrode 17 interposed therebetween (FIG. 9B). The electrode 17 is formed, for example, by depositing a polysilicon layer that will become the electrode 17 on the second interlayer insulating film 16 by thermal CVD, and then processing the polysilicon layer by photolithography and dry etching. The third interlayer insulating film 18 is formed, for example, by depositing the third interlayer insulating film 18 on the second interlayer insulating film 16 by plasma CVD, and then planarizing the surface of the third interlayer insulating film 18 by CMP.

[0086] Next, an insulating film 22 is formed on the upper surface of the second semiconductor substrate 21, the second semiconductor substrate 21 is turned upside down, and the second semiconductor substrate 21 is bonded to the first semiconductor substrate 11 (A in FIG. 10). As a result, the first semiconductor substrate 11 and the second semiconductor substrate 21 are bonded together via the first interlayer insulating film 14, the second interlayer insulating film 16, the third interlayer insulating film 18, the insulating film 22, etc. The insulating film 22 is formed, for example, by depositing the insulating film 22 on the second semiconductor substrate 21 by plasma CVD. The second semiconductor substrate 21 is bonded to the first semiconductor substrate 11 by, for example, plasma bonding.

[0087] Next, the second semiconductor substrate 21 and the insulating film 22 are processed by photolithography and dry etching (B in FIG. 10). As a result, a part of the second semiconductor substrate 21 is processed into the semiconductor layer 21a. Furthermore, the insulating film 22 is processed so that the insulating film 22 remains on the lower surface of the semiconductor layer 21a.

[0088] Next, a fourth interlayer insulating film 23 is formed on the third interlayer insulating film 18 (FIG. 11A). The fourth interlayer insulating film 23 is formed, for example, by depositing the fourth interlayer insulating film 23 on the third interlayer insulating film 18 via the second semiconductor substrate 21 and the insulating film 22 by plasma CVD, and then planarizing the surface of the fourth interlayer insulating film 23 by CMP. This CMP is performed until the upper surface of the second semiconductor substrate 21 is exposed on the upper surface of the fourth interlayer insulating film 23.

[0089] Next, an opening H1 is formed in the fourth interlayer insulating film 23 and the third interlayer insulating film 18 by photolithography and dry etching (FIG. 11B). The opening H1 is formed on the electrode 17 so as to be adjacent to the semiconductor layer 21a, and the upper surface of the electrode 17 and the side surface of the semiconductor layer 21a are exposed in the opening H1. The opening H1 is formed in a region where the insulating film 24 and the electrode 25 are to be formed. As a result, the third interlayer insulating film 18 below the insulating film 22 is processed into the insulating film 18a.

[0090] Next, the insulating film 24 is formed by thermal oxidation (A in FIG. 12). The insulating film 24 is formed inside and outside the opening H1, specifically, on the upper surface of the semiconductor layer 21a and on the side surfaces of the semiconductor layer 21a, the insulating film 22, and the insulating film 18a. In this embodiment, the thickness of the insulating film 24 is set to be thinner than the total thickness of the insulating film 22 and the insulating film 18a. This makes it possible to achieve the above-mentioned conditions "T1>T2, T1>T3" and "T1≧2×T2, T1≧2×T3" (see FIG. 5).

[0091] Next, the electrode 25 is formed by thermal CVD (B in FIG. 12). The electrode 25 is formed inside and outside the opening H1, specifically, on the upper surface of the insulating film 24, the side surfaces of the insulating film 24, and the upper surface of the electrode 17. As a result, the amplification transistor AMP including the columnar semiconductor layer 41, the tubular insulating film 42, and the tubular electrode 43 shown in FIG. 5 is formed.

[0092] Next, a fifth interlayer insulating film 26 is formed on the fourth interlayer insulating film 23 so as to cover the amplifying transistor AMP (A in FIG. 13). The fifth interlayer insulating film 26 is formed, for example, by depositing the fifth interlayer insulating film 26 on the fourth interlayer insulating film 23 by plasma CVD and planarizing the surface of the fifth interlayer insulating film 26 by CMP.

[0093] Next, a first opening is formed in the fifth interlayer insulating film 26, and second openings are formed in the first interlayer insulating film 14, the second interlayer insulating film 16, the third interlayer insulating film 18, the fourth interlayer insulating film 23, and the fifth interlayer insulating film 26, and wiring 31 is formed in the first and second openings and on the fifth interlayer insulating film 26 (FIG. 13B). The first opening is formed in the upper surface of the electrode 25. The second opening is formed in the upper surface of the floating diffusion FD. As a result, the electrode 25 and the floating diffusion FD are electrically connected by the wiring 31. The first and second openings are formed by photolithography and dry etching.

[0094] Thereafter, a color filter and an on-chip lens (not shown) are formed on the lower surface of the first semiconductor substrate 11. In this manner, the solid-state imaging device of this embodiment is manufactured.

[0095] (First Modification of the First Embodiment) FIG. 14 is a cross-sectional view showing the structure of a solid-state imaging device according to a first modified example of the first embodiment.

[0096] The solid-state imaging device of this modification includes wiring 51 in addition to the components of the solid-state imaging device of the first embodiment. The wiring 51 includes a contact electrode 52 and a vertical wiring 53. The solid-state imaging device of this modification further includes a semiconductor layer 21b that is part of the second semiconductor substrate 21. On the other hand, the solid-state imaging device of this modification does not include the insulating film 22.

[0097] The wiring 51 is formed in the first interlayer insulating film 14, the second interlayer insulating film 16, and the third interlayer insulating film 18, and electrically connects the first semiconductor substrate 11 and the semiconductor layer 21b. Specifically, the wiring 51 includes a contact electrode 52 formed on the first semiconductor substrate 11 and a vertical wiring 53 formed on the contact electrode 52, and the contact electrode 52 and the vertical wiring 53 are provided on the upper surface of the first semiconductor substrate 11 and the lower surface of the semiconductor layer 21b, respectively. The contact electrode 52 is, for example, a polysilicon electrode. The vertical wiring 53 is, for example, a polysilicon wiring. The wiring 51 is an example of the second wiring of the present disclosure.

[0098] The second semiconductor substrate 21 includes a semiconductor layer 21a and a semiconductor layer 21b. Because the solid-state imaging device of this modification does not include the insulating film 22, the semiconductor layer 21a is formed directly on the insulating film 18a. The thickness of the insulating film 18a of this modification is greater than the thickness of the insulating film 24. Therefore, even though the solid-state imaging device of this modification does not include the insulating film 22, the above-mentioned conditions "T1>T2, T1>T3" and "T1≧2×T2, T1≧2×T3" are also realized in this modification (see FIG. 5). On the other hand, the semiconductor layer 21b is formed on the third interlayer insulating film 18 and the wiring 51 and is electrically connected to the wiring 51. The semiconductor layer 21b of this modification is separated from the semiconductor layer 21a. The semiconductor layer 21b is an example of the second semiconductor layer of the present disclosure.

[0099] The semiconductor layer 21b forms, for example, some kind of device. Examples of such devices are a capacitor or a resistor. In such devices, it may be undesirable for the potential of the semiconductor layer 21b to become floating. According to this modification, by electrically connecting the semiconductor layer 21b to the first semiconductor substrate 11 via the wiring 51, it is possible to prevent the potential of the semiconductor layer 21b from becoming floating.

[0100] FIG. 15 is a cross-sectional view showing the structure of the amplifying transistor AMP of this modification.

[0101] Similar to the amplifier transistor AMP of the first embodiment, the amplifier transistor AMP of this modification includes a columnar semiconductor layer 41 having a columnar shape extending in the Y direction, a tubular insulating film 42 having a tubular shape extending in the Y direction, and a tubular electrode 43 having a tubular shape extending in the Y direction. However, whereas the tubular insulating film 42 of the first embodiment is formed of the insulating films 18a, 22, and 24, the tubular insulating film 42 of this modification is formed of the insulating films 18a and 24.

[0102] 15 shows the thickness T1 of the tubular insulating film 42 on the lower surface of the columnar semiconductor layer 41, the thickness T2 of the tubular insulating film 42 on the upper surface of the columnar semiconductor layer 41, and the thickness T3 of the tubular insulating film 42 on the side surface of the columnar semiconductor layer 41. As in the first embodiment, the thickness T1 of this modification is thicker than the thicknesses T2 and T3 (T1>T2, T1>T3), and is, for example, at least twice the thicknesses T2 and T3 (T1≧2×T2, T1≧2×T3). Therefore, according to this modification, the thick tubular insulating film 42 on the lower surface of the columnar semiconductor layer 41 can suitably protect the columnar semiconductor layer 41.

[0103] 16 to 18 are cross-sectional views showing a method for manufacturing the solid-state imaging device of this modified example.

[0104] First, an n-type region 11a, a p-type region 11b, and an n-type region 11c are formed by ion implantation in a first semiconductor substrate 11 (FIG. 16A). As a result, a photodiode PD and a floating diffusion FD are formed in the first semiconductor substrate 11.

[0105] Next, a gate insulating film 12 is formed on the first semiconductor substrate 11, a gate electrode 13 is formed on the gate insulating film 12, and a contact electrode 52 is formed on the first semiconductor substrate 11 (A in FIG. 16). As a result, a transfer transistor TG is formed on the first semiconductor substrate 11. The gate electrode 13 and the contact electrode 52 may be formed from, for example, the same polysilicon layer.

[0106] Next, a first interlayer insulating film 14 is formed on the first semiconductor substrate 11 with a gate insulating film 12, a gate electrode 13, and a contact electrode 52 interposed therebetween (FIG. 16B). Next, wiring 15 is formed on the first interlayer insulating film 14, and a second interlayer insulating film 16 is formed on the first interlayer insulating film 14 with the wiring 15 interposed therebetween (FIG. 16B). Next, an electrode 17 is formed on the second interlayer insulating film 16, and a third interlayer insulating film 18 is formed on the second interlayer insulating film 16 with the electrode 17 interposed therebetween (FIG. 16B).

[0107] Next, openings are formed in the first interlayer insulating film 14, the second interlayer insulating film 16, and the third interlayer insulating film 18, and vertical wiring 53 is formed in these openings (A in FIG. 17). Because these openings are formed on the upper surfaces of the contact electrodes 52, the vertical wiring 53 is formed on the contact electrodes 52. These openings are formed by photolithography and dry etching. The vertical wiring 53 is formed, for example, by depositing a polysilicon layer in these openings by thermal CVD and then removing the polysilicon layer outside the openings by CMP. In this way, wiring 51 is formed on the first semiconductor substrate 11.

[0108] Next, the second semiconductor substrate 21 is bonded to the first semiconductor substrate 11 (B in FIG. 17). As a result, the second semiconductor substrate 21 is disposed on the first semiconductor substrate 21 with the first interlayer insulating film 14, the second interlayer insulating film 16, the third interlayer insulating film 18, etc. interposed therebetween. The second semiconductor substrate 21 is bonded to the first semiconductor substrate 11 by, for example, plasma bonding. The second semiconductor substrate 21 of this modification is electrically connected to the wiring 51.

[0109] Next, the second semiconductor substrate 21 is processed by photolithography and dry etching (A in FIG. 18). As a result, a part of the second semiconductor substrate 21 is processed into a semiconductor layer 21a, and another part of the second semiconductor substrate 21 is processed into a semiconductor layer 21b. The semiconductor layer 21b is formed on the wiring 51.

[0110] Next, a fourth interlayer insulating film 23 is formed on the third interlayer insulating film 18, openings are formed in the fourth interlayer insulating film 23 and the third interlayer insulating film 18, an insulating film 24 and an electrode 25 are formed in the openings, and a fifth interlayer insulating film 26 is formed on the fourth interlayer insulating film 23 (FIG. 18A). This process is performed in the same manner as the processes shown in FIGS. 11A to 13A. Therefore, the opening formed in this process is formed in the same manner as the opening H1 shown in FIG. 11B. As a result, the insulating film 18a and the amplifying transistor AMP are formed in this process. In this modification, the thickness of the insulating film 24 is set thinner than the thickness of the insulating film 18a. This makes it possible to achieve the above-mentioned conditions "T1>T2, T1>T3" and "T1≧2×T2, T1≧2×T3" (see FIG. 15).

[0111] Next, a first opening is formed in the fifth interlayer insulating film 26, and second openings are formed in the first interlayer insulating film 14, the second interlayer insulating film 16, the third interlayer insulating film 18, the fourth interlayer insulating film 23, and the fifth interlayer insulating film 26, and wiring 31 is formed in the first and second openings and on the fifth interlayer insulating film 26 (B in FIG. 18). The first opening is formed in the upper surface of the electrode 25. The second opening is formed in the upper surface of the floating diffusion FD. As a result, the electrode 25 and the floating diffusion FD are electrically connected by the wiring 31. In this manner, the solid-state imaging device of this modified example is manufactured.

[0112] (Second Modification of the First Embodiment) FIG. 19 is a cross-sectional view showing the structure of a solid-state imaging device according to a second modified example of the first embodiment.

[0113] The solid-state imaging device of this modification includes wiring 54 in addition to the components of the solid-state imaging device of the first embodiment. On the other hand, the solid-state imaging device of this modification does not include the wiring 31.

[0114] The wiring 54 is formed in the first interlayer insulating film 14 and the second interlayer insulating film 16, and electrically connects the floating diffusion FD and the electrode 17. One end of the wiring 54 is provided on the upper surface of the floating diffusion FD, and the other end of the wiring 54 is provided on the lower surface of the electrode 17. The wiring 54 is, for example, a metal wiring or a semiconductor wiring. The wiring 54 is an example of a third wiring of the present disclosure.

[0115] According to this modification, by using the wiring 54 instead of the wiring 31, it is possible to electrically connect the floating diffusion region FD and the tubular electrode 43 with the short wiring 54. This makes it possible to reduce the capacitance between the wirings in this modification.

[0116] 20 and 21 are cross-sectional views showing a method for manufacturing the solid-state imaging device of this modification.

[0117] First, an n-type region 11a, a p-type region 11b, and an n-type region 11c are formed by ion implantation in a first semiconductor substrate 11 (FIG. 20A). As a result, a photodiode PD and a floating diffusion FD are formed in the first semiconductor substrate 11.

[0118] Next, a gate insulating film 12 is formed on the first semiconductor substrate 11, and a gate electrode 13 is formed on the gate insulating film 12 (A in FIG. 20). As a result, a transfer transistor TG is formed on the first semiconductor substrate 11.

[0119] Next, a first interlayer insulating film 14 is formed on the first semiconductor substrate 11 via a gate insulating film 12 and a gate electrode 13 (FIG. 20A). Next, wiring 15 is formed on the first interlayer insulating film 14, and a second interlayer insulating film 16 is formed on the first interlayer insulating film 14 via the wiring 15 (FIG. 20A).

[0120] Next, openings are formed in the first interlayer insulating film 14 and the second interlayer insulating film 16, and wiring 54 is formed in these openings (A in FIG. 20). Since these openings are formed on the top surface of the floating diffusion region FD, the wiring 54 is formed on the floating diffusion region FD. These openings are formed by photolithography and dry etching.

[0121] Next, an electrode 17 is formed on the second interlayer insulating film 16, and a third interlayer insulating film 18 is formed on the second interlayer insulating film 16 with the electrode 17 interposed therebetween (FIG. 20B). The electrode 17 in this modification is formed on the wiring 54.

[0122] Next, an insulating film 22 is formed on the upper surface of the second semiconductor substrate 21, the second semiconductor substrate 21 is turned upside down, and the second semiconductor substrate 21 is bonded to the first semiconductor substrate 11 (A in FIG. 21). As a result, the first semiconductor substrate 11 and the second semiconductor substrate 21 are bonded together with the first interlayer insulating film 14, the second interlayer insulating film 16, the third interlayer insulating film 18, the insulating film 22, etc. interposed therebetween.

[0123] Next, the second semiconductor substrate 21 and the insulating film 22 are processed by photolithography and dry etching (B in FIG. 21). As a result, a portion of the second semiconductor substrate 21 is processed into the semiconductor layer 21a. Furthermore, the insulating film 22 is processed so that the insulating film 22 remains on the lower surface of the semiconductor layer 21a.

[0124] Next, a fourth interlayer insulating film 23 is formed on the third interlayer insulating film 18, an opening is formed in the fourth interlayer insulating film 23 and the third interlayer insulating film 18, an insulating film 24 and an electrode 25 are formed in the opening, and a fifth interlayer insulating film 26 is formed on the fourth interlayer insulating film 23 (FIG. 21B). This process is performed in the same manner as the processes shown in FIGS. 11A to 13A. Therefore, the opening formed in this process is formed in the same manner as the opening H1 shown in FIG. 11B. As a result, the insulating film 18a and the amplifying transistor AMP are formed in this process. In this modification, the thickness of the insulating film 24 is set thinner than the sum of the thicknesses of the insulating films 22 and 18a. This makes it possible to achieve the above-mentioned conditions "T1>T2, T1>T3" and "T1≧2×T2, T1≧2×T3" (see FIG. 5). In this manner, the solid-state imaging device of this modification is manufactured.

[0125] (Third Modification of the First Embodiment) FIG. 22 is a cross-sectional view showing the structure of a solid-state imaging device according to a third modified example of the first embodiment.

[0126] The solid-state imaging device of this modification includes wiring 55 in addition to the components of the solid-state imaging device of the first embodiment. On the other hand, the solid-state imaging device of this modification does not include the wiring 31.

[0127] The wiring 55 is formed in the first interlayer insulating film 14, the second interlayer insulating film 16, the third interlayer insulating film 18, and the fourth interlayer insulating film 23, and electrically connects the floating diffusion FD and the electrode 17. One end of the wiring 55 is provided on the upper surface of the floating diffusion FD, and the other end of the wiring 55 is provided on the side surface of the electrodes 17 and 25. The wiring 55 is, for example, a metal wiring or a semiconductor wiring. The wiring 55 is an example of a fourth wiring of the present disclosure.

[0128] According to this modification, by using the wiring 55 instead of the wiring 31, it is possible to electrically connect the floating diffusion region FD and the tubular electrode 43 with a short wiring 54. This makes it possible to reduce the capacitance between the wirings in this modification.

[0129] 23 and 24 are cross-sectional views showing a method for manufacturing the solid-state imaging device of this modified example.

[0130] First, an n-type region 11a, a p-type region 11b, and an n-type region 11c are formed by ion implantation in a first semiconductor substrate 11 (FIG. 23A). As a result, a photodiode PD and a floating diffusion FD are formed in the first semiconductor substrate 11.

[0131] Next, a gate insulating film 12 is formed on the first semiconductor substrate 11, and a gate electrode 13 is formed on the gate insulating film 12 (A in FIG. 23). As a result, a transfer transistor TG is formed on the first semiconductor substrate 11.

[0132] Next, a first interlayer insulating film 14 is formed on the first semiconductor substrate 11 with a gate insulating film 12 and a gate electrode 13 interposed therebetween (FIG. 23A). Next, wiring 15 is formed on the first interlayer insulating film 14, and a second interlayer insulating film 16 is formed on the first interlayer insulating film 14 with the wiring 15 interposed therebetween (FIG. 23A). Next, an electrode 17 is formed on the second interlayer insulating film 16, and a third interlayer insulating film 18 is formed on the second interlayer insulating film 16 with the electrode 17 interposed therebetween (FIG. 23A).

[0133] Next, an insulating film 22 is formed on the upper surface of the second semiconductor substrate 21, the second semiconductor substrate 21 is turned upside down, and the second semiconductor substrate 21 is bonded to the first semiconductor substrate 11 (A in FIG. 23). As a result, the first semiconductor substrate 11 and the second semiconductor substrate 21 are bonded together with the first interlayer insulating film 14, the second interlayer insulating film 16, the third interlayer insulating film 18, the insulating film 22, etc. interposed therebetween.

[0134] Next, the second semiconductor substrate 21 and the insulating film 22 are processed by photolithography and dry etching (B in FIG. 23). As a result, a part of the second semiconductor substrate 21 is processed into the semiconductor layer 21a. Furthermore, the insulating film 22 is processed so that the insulating film 22 remains on the lower surface of the semiconductor layer 21a.

[0135] Next, a fourth interlayer insulating film 23 is formed on the third interlayer insulating film 18, and openings are formed in the fourth interlayer insulating film 23 and the third interlayer insulating film 18. An insulating film 24 and an electrode 25 are formed in the openings (FIG. 23B). This process is performed in the same manner as the processes shown in FIGS. 11A to 12B. Therefore, the opening formed in this process is formed in the same manner as the opening H1 shown in FIG. 11B. As a result, the insulating film 18a and the amplifying transistor AMP are formed in this process. In this modification, the thickness of the insulating film 24 is set thinner than the sum of the thicknesses of the insulating films 22 and 18a. This makes it possible to achieve the above-mentioned conditions "T1>T2, T1>T3" and "T1≧2×T2, T1≧2×T3" (see FIG. 5).

[0136] Next, openings are formed in the first interlayer insulating film 14, the second interlayer insulating film 16, the third interlayer insulating film 18, and the fourth interlayer insulating film 23, and wiring 55 is formed in these openings (A in FIG. 24). Because these openings are formed on the top surface of the floating diffusion region FD, wiring 55 is formed on the floating diffusion region FD. Furthermore, because these openings are formed on the side surfaces of the electrodes 17 and 25, wiring 55 is formed on the side surfaces of the electrodes 17 and 25. These openings are formed by photolithography and dry etching.

[0137] Next, a fifth interlayer insulating film 26 is formed on the fourth interlayer insulating film 23 (B in FIG. 24). In this manner, the solid-state imaging device of this modified example is manufactured.

[0138] As described above, the tubular insulating film 42 of this embodiment and its modified examples is formed so that the thickness T1 of the tubular insulating film 42 on the lower surface of the pillar-shaped semiconductor layer 41 is greater than the thicknesses T2 and T3 of the tubular insulating film 42 on the upper surface and side surface of the pillar-shaped semiconductor layer 41. Therefore, according to this embodiment and its modified examples, it is possible to realize a suitable amplification transistor AMP, for example, by suitably protecting the pillar-shaped semiconductor layer 41 with the thick tubular insulating film 42 on the lower surface of the pillar-shaped semiconductor layer 41.

[0139] Note that, instead of making the thickness T1 thicker than both the thicknesses T2 and T3, the thickness T1 may be thicker than only one of the thicknesses T2 and T3. Furthermore, such a relationship between the thicknesses T1 to T3 may be applied to pixel transistors other than the amplification transistor AMP.

[0140] (Second embodiment) FIG. 25 is a cross-sectional view showing the structure of the solid-state imaging device of the second embodiment.

[0141] The solid-state imaging device of this embodiment includes an insulating film 56 and an electrode 57 in addition to the components of the solid-state imaging device of the first embodiment. On the other hand, the solid-state imaging device of this embodiment does not include the electrode 17, the third interlayer insulating film 18, or the electrode 25.

[0142] The insulating film 56 is formed on the second interlayer insulating film 16 and is interposed between the second interlayer insulating film 16 and the fourth interlayer insulating film 23. The insulating film 56 is, for example, a silicon nitride film. The insulating film 56 is an example of the second insulating film of the present disclosure.

[0143] The electrode 57 is formed on the second interlayer insulating film 16 and forms the amplifier transistor AMP of this embodiment. The electrode 57 is, for example, a polysilicon electrode. In this embodiment, the insulating film 22 is provided on the lower surface of the semiconductor layer 21a, and the insulating film 24 is provided on the upper surface of the semiconductor layer 21a and on side surfaces of the semiconductor layer 21a and the insulating film 22. The insulating films 22 and 24, together with the semiconductor layer 21a and the electrode 57, form the amplifier transistor AMP of this embodiment. The electrode 57 is provided on the upper surface of the insulating film 24, on the side surfaces of the insulating film 24, and on the lower surfaces of the insulating films 22 and 24. In this embodiment, the wiring 31 is provided on the floating diffusion layer FD and the electrode 57. The electrode 57 is an example of a first electrode of the present disclosure.

[0144] The insulating film 56 in this embodiment has the same thickness as the electrode 57 on the underside of the insulating film 22, and is provided to the side of the electrode 57 on the underside of the insulating film 22. The reason for this is that the electrode 57 on the underside of the insulating film 22 is formed by sequentially forming the insulating film 56 and the insulating film 22 on the second interlayer insulating film 16, removing the insulating film 56 from between the second interlayer insulating film 16 and the insulating film 22, and then forming the electrode 57 between the second interlayer insulating film 16 and the insulating film 22. In other words, the electrode 57 is embedded in the space created by removing the insulating film 56. This makes it possible to form the tubular electrode 43 using only the electrode 57.

[0145] According to this embodiment, by manufacturing a solid-state imaging device using the insulating film 56 instead of the third interlayer insulating film 18, it is possible to shorten the distance between the first semiconductor substrate 11 and the second semiconductor substrate 21. This makes it possible to shorten the wiring 31, thereby reducing the inter-wiring capacitance of this embodiment. Furthermore, according to this embodiment, it is possible to reduce the aspect ratio of the wiring 31 on the floating diffusion layer FD.

[0146] FIG. 26 is a cross-sectional view showing the structure of the amplifying transistor of the second embodiment.

[0147] Similar to the amplifier transistor AMP of the first embodiment, the amplifier transistor AMP of the present embodiment includes a columnar semiconductor layer 41 having a columnar shape extending in the Y direction, a tubular insulating film 42 having a tubular shape extending in the Y direction, and a tubular electrode 43 having a tubular shape extending in the Y direction. However, whereas the tubular insulating film 42 of the first embodiment is formed of the insulating films 18a, 22, and 24, the tubular insulating film 42 of the present embodiment is formed of the insulating films 22 and 24. Furthermore, whereas the tubular electrode 43 of the first embodiment is formed of the electrodes 17 and 25, the tubular electrode 43 of the present embodiment is formed of the electrode 57.

[0148] 26 shows the thickness T1 of the tubular insulating film 42 on the lower surface of the columnar semiconductor layer 41, the thickness T2 of the tubular insulating film 42 on the upper surface of the columnar semiconductor layer 41, and the thickness T3 of the tubular insulating film 42 on the side surface of the columnar semiconductor layer 41. As in the first embodiment, the thickness T1 of this embodiment is thicker than the thicknesses T2 and T3 (T1>T2, T1>T3), and is, for example, at least twice the thicknesses T2 and T3 (T1≧2×T2, T1≧2×T3). Therefore, according to this embodiment, the thick tubular insulating film 42 on the lower surface of the columnar semiconductor layer 41 can suitably protect the columnar semiconductor layer 41.

[0149] 27 to 31 are cross-sectional views showing a method for manufacturing the solid-state imaging device of the second embodiment.

[0150] First, an n-type region 11a, a p-type region 11b, and an n-type region 11c are formed by ion implantation in a first semiconductor substrate 11 (FIG. 27A). As a result, a photodiode PD and a floating diffusion FD are formed in the first semiconductor substrate 11.

[0151] Next, a gate insulating film 12 is formed on the first semiconductor substrate 11, and a gate electrode 13 is formed on the gate insulating film 12 (A in FIG. 27). As a result, a transfer transistor TG is formed on the first semiconductor substrate 11.

[0152] Next, a first interlayer insulating film 14 is formed on the first semiconductor substrate 11 via a gate insulating film 12 and a gate electrode 13 (B in FIG. 27). Next, wiring 15 is formed on the first interlayer insulating film 14, and a second interlayer insulating film 16 is formed on the first interlayer insulating film 14 via the wiring 15 (B in FIG. 27).

[0153] Next, insulating film 22 and insulating film 56 are formed in this order on the upper surface of second semiconductor substrate 21, and second semiconductor substrate 21 is then turned upside down and bonded to first semiconductor substrate 11 (A in FIG. 28). As a result, first semiconductor substrate 11 and second semiconductor substrate 21 are bonded together via first interlayer insulating film 14, second interlayer insulating film 16, insulating film 56, insulating film 22, etc. The second semiconductor substrate 21 is bonded to first semiconductor substrate 11 by, for example, plasma bonding.

[0154] Next, the second semiconductor substrate 21 and the insulating film 22 are processed by photolithography and dry etching (B in FIG. 28). As a result, a part of the second semiconductor substrate 21 is processed into the semiconductor layer 21a. Furthermore, the insulating film 22 is processed so that the insulating film 22 remains on the lower surface of the semiconductor layer 21a.

[0155] Next, a fourth interlayer insulating film 23 is formed on the second interlayer insulating film 16, and an opening H2 is formed in the fourth interlayer insulating film 23 (FIG. 29A). This step is performed in the same manner as the steps shown in FIGS. 11A and 11B. Thus, the opening H2 is formed in the same manner as the opening H1 shown in FIG. 11B.

[0156] Next, the insulating film 56 exposed in the opening H2 is removed by wet etching using hot phosphoric acid (B in FIG. 29). In this step, a portion of the insulating film 56 is removed; specifically, the insulating film 56 is removed from the bottom of the opening H2 and between the second interlayer insulating film 16 and the insulating film 22. As a result, the opening H2 extends from the region in the fourth interlayer insulating film 23 to the region in the insulating film 56. In this embodiment, the insulating film 56 is a silicon nitride film, and the other insulating films exposed in the opening H2 are silicon oxide films. Therefore, the insulating film 56 can be selectively etched with hot phosphoric acid.

[0157] Next, the insulating film 24 is formed by thermal oxidation (A in FIG. 30). The insulating film 24 is formed inside and outside the opening H2, specifically, on the upper surface of the semiconductor layer 21a and on the side surfaces of the semiconductor layer 21a and the insulating film 22. In this embodiment, the thickness of the insulating film 24 is set to be thinner than the thickness of the insulating film 22. This makes it possible to achieve the above-mentioned conditions "T1>T2, T1>T3" and "T1≧2×T2, T1≧2×T3" (see FIG. 26).

[0158] Next, the electrode 57 is formed by thermal CVD (B in FIG. 30). The electrode 57 is formed inside and outside the opening H2, specifically, on the upper surface of the insulating film 24, the side surfaces of the insulating film 24, and the lower surfaces of the insulating films 22 and 24. As a result, the amplifying transistor AMP including the columnar semiconductor layer 41, the tubular insulating film 42, and the tubular electrode 43 shown in FIG. 26 is formed.

[0159] Next, a fifth interlayer insulating film 26 is formed on the fourth interlayer insulating film 23 so as to cover the amplification transistor AMP (A in FIG. 31).

[0160] Next, a first opening is formed in fifth interlayer insulating film 26, and a second opening is formed in first interlayer insulating film 14, second interlayer insulating film 16, insulating film 56, fourth interlayer insulating film 23, and fifth interlayer insulating film 26, and wiring 31 is formed in the first and second openings and on fifth interlayer insulating film 26 (FIG. 31B). The first opening is formed in the upper surface of electrode 57. The second opening is formed in the upper surface of floating diffusion FD. As a result, electrode 57 and floating diffusion FD are electrically connected by wiring 31.

[0161] Thereafter, a color filter and an on-chip lens (not shown) are formed on the lower surface of the first semiconductor substrate 11. In this manner, the solid-state imaging device of this embodiment is manufactured.

[0162] (Modification of the second embodiment) FIG. 32 is a cross-sectional view showing the structure of a solid-state imaging device according to a modification of the second embodiment.

[0163] The solid-state imaging device of this modification includes wiring 58 in addition to the components of the solid-state imaging device of the second embodiment. On the other hand, the solid-state imaging device of this modification does not include the wiring 31.

[0164] The wiring 58 has a structure similar to that of the wiring 54 of the second modified example of the first embodiment. Specifically, the wiring 58 is formed in the first interlayer insulating film 14 and the second interlayer insulating film 16, and electrically connects the floating diffusion FD and the electrode 57. One end of the wiring 58 is provided on the upper surface of the floating diffusion FD, and the other end of the wiring 58 is provided on the lower surface of the electrode 57. The wiring 58 is, for example, a metal wiring or a semiconductor wiring. Like the wiring 54, the wiring 58 is an example of the third wiring of the present disclosure.

[0165] According to this modification, by using the wiring 58 instead of the wiring 31, it is possible to electrically connect the floating diffusion region FD and the tubular electrode 43 with the short wiring 58. This makes it possible to reduce the capacitance between the wirings in this modification.

[0166] 33 and 34 are cross-sectional views showing a method for manufacturing the solid-state imaging device of this modification.

[0167] First, an n-type region 11a, a p-type region 11b, and an n-type region 11c are formed by ion implantation in a first semiconductor substrate 11 (FIG. 33A). As a result, a photodiode PD and a floating diffusion FD are formed in the first semiconductor substrate 11.

[0168] Next, a gate insulating film 12 is formed on the first semiconductor substrate 11, and a gate electrode 13 is formed on the gate insulating film 12 (A in FIG. 33). As a result, a transfer transistor TG is formed on the first semiconductor substrate 11.

[0169] Next, a first interlayer insulating film 14 is formed on the first semiconductor substrate 11 via a gate insulating film 12 and a gate electrode 13 (FIG. 33A). Next, wiring 15 is formed on the first interlayer insulating film 14, and a second interlayer insulating film 16 is formed on the first interlayer insulating film 14 via the wiring 15 (FIG. 33A).

[0170] Next, openings are formed in the first interlayer insulating film 14 and the second interlayer insulating film 16, and wiring 58 is formed in these openings (A in FIG. 33). Since these openings are formed on the top surface of the floating diffusion region FD, the wiring 58 is formed on the floating diffusion region FD. These openings are formed by photolithography and dry etching.

[0171] Next, insulating film 22 and insulating film 56 are formed in this order on the upper surface of second semiconductor substrate 21, and second semiconductor substrate 21 is turned upside down and bonded to first semiconductor substrate 11 (B in FIG. 33). As a result, first semiconductor substrate 11 and second semiconductor substrate 21 are bonded together with first interlayer insulating film 14, second interlayer insulating film 16, insulating film 56, insulating film 22, etc. interposed therebetween.

[0172] Next, the second semiconductor substrate 21 and the insulating film 22 are processed by photolithography and dry etching (A in FIG. 34). As a result, a part of the second semiconductor substrate 21 is processed into the semiconductor layer 21a. Furthermore, the insulating film 22 is processed so that the insulating film 22 remains on the lower surface of the semiconductor layer 21a.

[0173] Next, a fourth interlayer insulating film 23 is formed on the second interlayer insulating film 16, an opening H2 is formed in the fourth interlayer insulating film 23, and the insulating film 56 exposed in the opening H2 is removed by wet etching using hot phosphoric acid (FIG. 34A). This step is performed in the same manner as the steps shown in FIGS. 29A and 29B. Therefore, this opening H2 is formed in the same manner as the opening H2 shown in FIG. 29B.

[0174] Next, the insulating film 24 and the electrode 57 are formed in the opening H2, and the fifth interlayer insulating film 26 is formed on the fourth interlayer insulating film 23 (B in FIG. 34). This process is performed in the same manner as the processes shown in A in FIG. 30 to A in FIG. 31. Therefore, the insulating film 24 and the electrode 57 are formed in the same manner as the insulating film 24 and the electrode 57 shown in A in FIG. 31, and as a result, the amplifying transistor AMP is formed. In this modification, the thickness of the insulating film 24 is set thinner than the thickness of the insulating film 22. This makes it possible to realize the above-mentioned conditions "T1>T2, T1>T3" and "T1≧2×T2, T1≧2×T3" (see FIG. 26). In this manner, the solid-state imaging device of this modification is manufactured.

[0175] As described above, the tubular insulating film 42 of this embodiment and its modified examples is formed so that the thickness T1 of the tubular insulating film 42 on the lower surface of the pillar-shaped semiconductor layer 41 is greater than the thicknesses T2 and T3 of the tubular insulating film 42 on the upper surface and side surface of the pillar-shaped semiconductor layer 41. Therefore, according to this embodiment and its modified examples, it is possible to realize a suitable amplification transistor AMP, for example, by suitably protecting the pillar-shaped semiconductor layer 41 with the thick tubular insulating film 42 on the lower surface of the pillar-shaped semiconductor layer 41.

[0176] (Application example) 35 is a block diagram showing an example of the configuration of an electronic device. The electronic device shown in FIG.

[0177] Camera 100 includes optical unit 101 including a lens group and the like, imaging device 102 which is the solid-state imaging device of the first or second embodiment, DSP (Digital Signal Processor) circuit 103 which is a camera signal processing circuit, frame memory 104, display unit 105, recording unit 106, operation unit 107, and power supply unit 108. DSP circuit 103, frame memory 104, display unit 105, recording unit 106, operation unit 107, and power supply unit 108 are connected to each other via bus line 109.

[0178] The optical unit 101 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging device 102. The imaging device 102 converts the amount of incident light formed on the imaging surface by the optical unit 101 into an electrical signal on a pixel-by-pixel basis and outputs the signal as a pixel signal.

[0179] The DSP circuit 103 performs signal processing on the pixel signals output by the imaging device 102. The frame memory 104 is a memory for storing one frame of a moving image or still image captured by the imaging device 102.

[0180] The display unit 105 includes a panel-type display device such as a liquid crystal panel or an organic EL panel, and displays moving images or still images captured by the imaging device 102. The recording unit 106 records the moving images or still images captured by the imaging device 102 on a recording medium such as a hard disk or semiconductor memory.

[0181] An operation unit 107, under the operation of a user, issues operation commands for various functions of the camera 100. A power supply unit 108 appropriately supplies various types of power to the DSP circuit 103, frame memory 104, display unit 105, recording unit 106, and operation unit 107 as operating power sources to these devices.

[0182] By using the solid-state imaging device of the first or second embodiment as the imaging device 102, it is possible to expect to obtain a good image.

[0183] The solid-state imaging device can be applied to various other products, for example, the solid-state imaging device may be mounted on various moving objects such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0184] 36 is a block diagram showing an example of the configuration of a mobile object control system. The mobile object control system shown in FIG.

[0185] The vehicle control system 200 includes a plurality of electronic control units connected via a communication network 201. In the example shown in Fig. 36, the vehicle control system 200 includes a drive system control unit 210, a body system control unit 220, an outside-vehicle information detection unit 230, an inside-vehicle information detection unit 240, and an integrated control unit 250. Fig. 36 further shows a microcomputer 251, an audio / video output unit 252, and an in-vehicle network I / F (Interface) 253 as components of the integrated control unit 250.

[0186] The drivetrain control unit 210 controls the operation of devices related to the vehicle's drivetrain in accordance with various programs. For example, the drivetrain control unit 210 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor that generates drive force for the vehicle, a drive force transmission mechanism that transmits drive force to the wheels, a steering mechanism that adjusts the steering angle of the vehicle, a braking device that generates braking force for the vehicle, etc.

[0187] Body system control unit 220 controls the operation of various devices mounted on the vehicle body in accordance with various programs. For example, body system control unit 220 functions as a control device for a smart key system, a keyless entry system, a power window device, various lamps (e.g., head lamps, backup lamps, brake lamps, blinkers, fog lamps), etc. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to body system control unit 220. Body system control unit 220 receives input of such radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0188] The outside-vehicle information detection unit 230 detects information outside the vehicle equipped with the vehicle control system 200. For example, an imaging unit 231 is connected to the outside-vehicle information detection unit 230. The outside-vehicle information detection unit 230 causes the imaging unit 231 to capture images outside the vehicle and receives the captured images from the imaging unit 231. The outside-vehicle information detection unit 230 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0189] The imaging unit 231 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The imaging unit 231 can output the electrical signal as an image, or can output it as distance measurement information. The light received by the imaging unit 231 may be visible light or invisible light such as infrared light. The imaging unit 231 includes the solid-state imaging device of the first or second embodiment.

[0190] The in-vehicle information detection unit 240 detects information about the inside of a vehicle equipped with the vehicle control system 200. For example, a driver state detection unit 241 that detects the state of the driver is connected to the in-vehicle information detection unit 240. For example, the driver state detection unit 241 includes a camera that captures an image of the driver, and the in-vehicle information detection unit 240 may calculate the degree of fatigue or concentration of the driver or determine whether the driver is dozing off based on the detection information input from the driver state detection unit 241. This camera may include the solid-state imaging device of the first or second embodiment, and may be, for example, the camera 100 shown in FIG. 35 .

[0191] The microcomputer 251 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 230 or the inside-vehicle information detection unit 240, and output control commands to the drivetrain control unit 210. For example, the microcomputer 251 can perform cooperative control aimed at realizing functions of an ADAS (Advanced Driver Assistance System), such as vehicle collision avoidance, impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, collision warning, and lane departure warning.

[0192] In addition, the microcomputer 251 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without being operated by the driver, by controlling the driving force generating device, steering mechanism, or braking device based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 230 or the inside vehicle information detection unit 240.

[0193] Furthermore, the microcomputer 251 can output a control command to the body system control unit 220 based on the information about the outside of the vehicle acquired by the outside information detection unit 230. For example, the microcomputer 251 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 230, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0194] The audio / video output unit 252 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 36, an audio speaker 261, a display unit 262, and an instrument panel 263 are shown as such output devices. The display unit 262 may include, for example, an on-board display or a head-up display.

[0195] FIG. 37 is a plan view showing a specific example of the setting position of the imaging unit 231 in FIG.

[0196] 37 includes imaging units 301, 302, 303, 304, and 305 as imaging unit 231. Imaging units 301, 302, 303, 304, and 305 are provided, for example, at positions such as the front nose of vehicle 300, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin.

[0197] The imaging unit 301 provided on the front nose mainly acquires images of the front of the vehicle 300. The imaging unit 302 provided on the left side mirror and the imaging unit 303 provided on the right side mirror mainly acquire images of the sides of the vehicle 300. The imaging unit 304 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 300. The imaging unit 305 provided on the top of the windshield inside the vehicle mainly acquires images of the front of the vehicle 300. The imaging unit 305 is used to detect, for example, leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0198] FIG. 37 shows an example of the imaging ranges of imaging units 301, 302, 303, and 304 (hereinafter referred to as "imaging units 301-304"). Imaging range 311 indicates the imaging range of imaging unit 301 provided on the front nose. Imaging range 312 indicates the imaging range of imaging unit 302 provided on the left side mirror. Imaging range 313 indicates the imaging range of imaging unit 303 provided on the right side mirror. Imaging range 314 indicates the imaging range of imaging unit 304 provided on the rear bumper or back door. For example, by overlaying the image data captured by imaging units 301-304, an overhead image of vehicle 300 viewed from above can be obtained. Hereinafter, imaging ranges 311, 312, 313, and 314 will be referred to as "imaging ranges 311-314."

[0199] At least one of the imaging units 301 to 304 may have a function of acquiring distance information. For example, at least one of the imaging units 301 to 304 may be a stereo camera including multiple imaging devices, or an imaging device having pixels for detecting a phase difference.

[0200] For example, the microcomputer 251 (FIG. 36) calculates the distance to each three-dimensional object within the imaging ranges 311-314 and the change in this distance over time (relative speed with respect to the vehicle 300) based on the distance information obtained from the imaging units 301-304. Based on these calculation results, the microcomputer 251 can extract, as a preceding vehicle, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 300 and that is traveling in approximately the same direction as the vehicle 300 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 251 can set a vehicle-to-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, according to this example, cooperative control can be performed for the purpose of automatic driving, which autonomously travels without the driver's operation.

[0201] For example, based on the distance information obtained from the imaging units 301 to 304, the microcomputer 251 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and can use the data for automatic obstacle avoidance. For example, the microcomputer 251 distinguishes obstacles around the vehicle 300 into obstacles that are visible to the driver of the vehicle 300 and obstacles that are difficult to see. The microcomputer 251 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 251 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 261 or the display unit 262, or by performing forced deceleration or avoidance steering via the drivetrain control unit 210.

[0202] At least one of the image capturing units 301-304 may be an infrared camera that detects infrared rays. For example, the microcomputer 251 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 301-304. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 301-304 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 251 determines that a pedestrian is present in the images captured by the image capturing units 301-304 and recognizes the pedestrian, the audio / video output unit 252 controls the display unit 262 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / video output unit 252 may also control the display unit 262 to display an icon or the like representing the pedestrian at a desired position.

[0203] FIG. 38 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0204] 38 shows a state in which an operator (doctor) 531 is performing surgery on a patient 532 on a patient bed 533 using an endoscopic surgery system 400. As shown in the figure, the endoscopic surgery system 400 is composed of an endoscope 500, other surgical tools 510 such as an insufflation tube 511 and an energy treatment tool 512, a support arm device 520 that supports the endoscope 500, and a cart 600 on which various devices for endoscopic surgery are mounted.

[0205] The endoscope 500 is composed of a lens barrel 501, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 532, and a camera head 502 connected to the base end of the lens barrel 501. In the example shown in the figure, the endoscope 500 is configured as a so-called rigid lens barrel having a rigid lens barrel 501, but the endoscope 500 may also be configured as a so-called flexible lens barrel having a flexible lens barrel.

[0206] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 501. A light source device 603 is connected to the endoscope 500, and light generated by the light source device 603 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 501, and is irradiated via the objective lens towards an observation target inside the body cavity of the patient 532. Note that the endoscope 500 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0207] An optical system and an image sensor are provided inside the camera head 502, and light reflected from the object of observation (observation light) is collected by the optical system onto the image sensor. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 601 as RAW data.

[0208] The CCU 601 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 500 and the display device 602. Furthermore, the CCU 601 receives an image signal from the camera head 502 and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0209] Under the control of the CCU 601 , the display device 602 displays an image based on an image signal that has been subjected to image processing by the CCU 601 .

[0210] The light source device 603 is configured from a light source such as an LED (Light Emitting Diode), and supplies the endoscope 500 with irradiation light when photographing an operation site or the like.

[0211] The input device 604 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 400 via the input device 604. For example, the user inputs an instruction to change the imaging conditions (type of irradiating light, magnification, focal length, etc.) of the endoscope 500.

[0212] The treatment tool control device 605 controls the driving of an energy treatment tool 512 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 606 sends gas into the body cavity of the patient 532 via the insufflation tube 511 to ensure a clear field of view for the endoscope 500 and a working space for the surgeon. The recorder 607 is a device capable of recording various types of information related to the surgery. The printer 608 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0213] The light source device 603, which supplies illumination light to the endoscope 500 when photographing the surgical site, can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 603. In this case, it is also possible to capture images corresponding to each RGB color in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 502 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0214] Furthermore, the light source device 603 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 502 in synchronization with the timing of the change in the light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0215] The light source device 603 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto body tissues and observing the fluorescence from the tissues (autofluorescence observation), or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 603 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0216] FIG. 39 is a block diagram showing an example of the functional configuration of the camera head 502 and the CCU 601 shown in FIG.

[0217] The camera head 502 has a lens unit 701, an imaging unit 702, a drive unit 703, a communication unit 704, and a camera head control unit 705. The CCU 601 has a communication unit 711, an image processing unit 712, and a control unit 713. The camera head 502 and the CCU 601 are connected to each other via a transmission cable 700 so that they can communicate with each other.

[0218] Lens unit 701 is an optical system provided at the connection point with lens barrel 501. Observation light taken in from the tip of lens barrel 501 is guided to camera head 502 and enters lens unit 701. Lens unit 701 is configured by combining multiple lenses including a zoom lens and a focus lens.

[0219] The imaging unit 702 is configured with an imaging element. The imaging element constituting the imaging unit 702 may be one (a so-called single-chip type) or multiple (a so-called multi-chip type). When the imaging unit 702 is configured with a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and the image signals may be combined to obtain a color image. Alternatively, the imaging unit 702 may be configured with a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. 3D display enables the surgeon 531 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 702 is configured with a multi-chip type, multiple lens units 701 may be provided corresponding to each imaging element. The imaging unit 702 is, for example, the solid-state imaging device of the first or second embodiment.

[0220] Furthermore, the imaging unit 702 does not necessarily have to be provided in the camera head 502. For example, the imaging unit 702 may be provided inside the lens barrel 501, immediately behind the objective lens.

[0221] The driving unit 703 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 701 by a predetermined distance along the optical axis under the control of the camera head control unit 705. This allows the magnification and focus of the image captured by the imaging unit 702 to be adjusted appropriately.

[0222] The communication unit 704 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 601. The communication unit 704 transmits the image signal obtained from the imaging unit 702 to the CCU 601 via the transmission cable 700 as RAW data.

[0223] Furthermore, the communication unit 704 receives a control signal for controlling the driving of the camera head 502 from the CCU 601 and supplies it to the camera head control unit 705. The control signal includes information relating to the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0224] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 713 of the CCU 601 based on the acquired image signal. In the latter case, the endoscope 500 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0225] The camera head control unit 705 controls the driving of the camera head 502 based on a control signal received from the CCU 601 via the communication unit 704 .

[0226] The communication unit 711 is configured by a communication device for transmitting and receiving various types of information to and from the camera head 502. The communication unit 711 receives an image signal transmitted from the camera head 502 via the transmission cable 700.

[0227] Furthermore, the communication unit 711 transmits to the camera head 502 a control signal for controlling the driving of the camera head 502. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0228] The image processing unit 712 performs various image processing operations on the image signal, which is RAW data sent from the camera head 502 .

[0229] The control unit 713 performs various controls related to the imaging of the surgical site, etc. by the endoscope 500 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 713 generates a control signal for controlling the driving of the camera head 502.

[0230] Furthermore, the control unit 713 causes the display device 602 to display the captured image showing the surgical site, etc., based on the image signal that has been image processed by the image processing unit 712. At this time, the control unit 713 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 713 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 512, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 602, the control unit 713 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 531, the burden on the surgeon 531 can be reduced and the surgeon 531 can proceed with the surgery reliably.

[0231] The transmission cable 700 connecting the camera head 502 and the CCU 601 is an electric signal cable for communication of electric signals, an optical fiber for optical communication, or a composite cable of these.

[0232] In the illustrated example, communication is performed by wire using the transmission cable 700, but communication between the camera head 502 and the CCU 601 may also be performed wirelessly.

[0233] Although the embodiments of the present disclosure have been described above, these embodiments may be implemented with various modifications within the scope of the gist of the present disclosure. For example, two or more embodiments may be implemented in combination.

[0234] The present disclosure may also be configured as follows.

[0235] (1) a first semiconductor substrate including a photoelectric conversion portion and a floating diffusion portion; a first transistor including a first semiconductor layer provided above the first semiconductor substrate, a first insulating film provided on a lower surface, an upper surface, and a side surface of the first semiconductor layer, and a first electrode provided on a lower surface, an upper surface, and a side surface of the first insulating film; A solid-state imaging device, wherein the thickness of the first insulating film on the lower surface of the first semiconductor layer is greater than the thickness of the first insulating film on the upper surface or side surface of the first semiconductor layer.

[0236] (2) The solid-state imaging device according to (1), wherein the thickness of the first insulating film on the lower surface of the first semiconductor layer is at least twice the thickness of the first insulating film on the upper surface or side surface of the first semiconductor layer.

[0237] (3) the first semiconductor layer, the first insulating film, and the first electrode extend in a first direction parallel to a surface of the first semiconductor substrate; The solid-state imaging device according to (1), wherein the first insulating film and the first electrode have a tubular shape surrounding the first semiconductor layer.

[0238] (4) The solid-state imaging device according to (1), wherein the first semiconductor layer is a part of a second semiconductor substrate provided above the first semiconductor substrate.

[0239] (5) The solid-state imaging device according to (1), wherein the first transistor is an amplification transistor, a selection transistor, a reset transistor, or a switch transistor.

[0240] (6) The solid-state imaging device according to (1), wherein the first insulating film includes a first film provided on the lower surface of the first semiconductor layer and a second film provided on the upper surface and side surfaces of the first semiconductor layer.

[0241] (7) The solid-state imaging device according to (6), wherein the first insulating film further includes a third film provided on a lower surface of the first film.

[0242] (8) The solid-state imaging device according to (1), wherein the first electrode includes a first layer provided on the lower surface of the first insulating film and a second layer provided on the upper surface and side surfaces of the first insulating film.

[0243] (9) The solid-state imaging device described in (1) further comprises a second insulating film having the same thickness as the first electrode on the lower surface of the first insulating film and provided to the side of the first electrode on the lower surface of the first insulating film.

[0244] (10) The solid-state imaging device according to (1), further comprising a first wiring provided on an upper surface of the first electrode and electrically connecting the first electrode and the floating diffusion region.

[0245] (11) a second semiconductor layer provided above the first semiconductor substrate; a second wiring that electrically connects the first semiconductor substrate and the second semiconductor layer; The solid-state imaging device according to (1) further comprises:

[0246] (12) The solid-state imaging device according to (11), wherein the second semiconductor layer is a part of a second semiconductor substrate provided above the first semiconductor substrate.

[0247] (13) The solid-state imaging device according to (1), further comprising a third wiring provided on a lower surface of the first electrode and electrically connecting the first electrode and the floating diffusion region.

[0248] (14) The solid-state imaging device according to (1), further comprising a fourth wiring provided on a side surface of the first electrode and electrically connecting the first electrode and the floating diffusion portion.

[0249] (15) forming a photoelectric conversion region and a floating diffusion region in a first semiconductor substrate; forming a first transistor including a first semiconductor layer provided above the first semiconductor substrate, a first insulating film provided on a lower surface, an upper surface, and a side surface of the first semiconductor layer, and a first electrode provided on a lower surface, an upper surface, and a side surface of the first insulating film; This includes: A method for manufacturing a solid-state imaging device, wherein the thickness of the first insulating film on the lower surface of the first semiconductor layer is set to be thicker than the thickness of the first insulating film on the upper surface or side surface of the first semiconductor layer.

[0250] (16) The method for manufacturing a solid-state imaging device described in (15), wherein the first semiconductor layer is formed by bonding the first semiconductor substrate and a second semiconductor substrate together and processing the second semiconductor substrate to form the first semiconductor layer.

[0251] (17) the first insulating film includes a first film provided on a lower surface of the first semiconductor layer and a second film provided on an upper surface and a side surface of the first semiconductor layer; The method for manufacturing a solid-state imaging device according to (16), wherein the first semiconductor substrate and the second semiconductor substrate are bonded together via the first film provided on the underside of the second semiconductor substrate.

[0252] (18) the first insulating film further includes a third film provided on a lower surface of the first film, The method for manufacturing a solid-state imaging device according to (17), wherein the first semiconductor substrate and the second semiconductor substrate are further bonded together via the third film provided on the upper surface of the first semiconductor substrate.

[0253] (19) the first electrode includes a first layer provided on a lower surface of the first insulating film and a second layer provided on an upper surface and a side surface of the first insulating film; The method for manufacturing a solid-state imaging device according to (16), wherein the first semiconductor substrate and the second semiconductor substrate are bonded together via the first layer provided on the upper surface of the first semiconductor substrate.

[0254] (20) the first semiconductor substrate and the second semiconductor substrate are further bonded together via a second insulating film provided on a lower surface of the first film; The method for manufacturing a solid-state imaging device described in (17), wherein the first electrode is formed by removing a portion of the second insulating film from between the first semiconductor substrate and the second semiconductor substrate after the bonding, and forming a portion of the first electrode between the first semiconductor substrate and the second semiconductor substrate after the removal. [Explanation of symbols]

[0255] 1: pixel, 2: pixel array area, 3: control circuit, 4: vertical drive circuit, 5: column signal processing circuit, 6: horizontal drive circuit, 7: output circuit, 8: vertical signal line, 9: horizontal signal line, 11: first semiconductor substrate, 11a: n-type region, 11b: p-type region, 11c: n-type region, 12: gate insulating film; 13: gate electrode; 14: first interlayer insulating film; 15: wiring; 16: second interlayer insulating film, 17: electrode, 18: third interlayer insulating film, 18a: insulating film, 21: second semiconductor substrate, 21a: semiconductor layer, 21b: semiconductor layer, 22: insulating film, 23: fourth interlayer insulating film, 24: insulating film, 25: electrode, 26: fifth interlayer insulating film, 31: wiring, 41: columnar semiconductor layer, 42: tubular insulating film, 43: tubular electrode, 51: wiring, 52: contact electrode, 53: vertical wiring, 54: wiring, 55: wiring, 56: insulating film, 57: electrode, 58: wiring

Claims

1. a first semiconductor substrate including a photoelectric conversion portion and a floating diffusion portion; a pixel transistor including a first semiconductor layer provided above the first semiconductor substrate, a first insulating film provided on a lower surface, an upper surface, and a side surface of the first semiconductor layer, and a first electrode provided on a lower surface, an upper surface, and a side surface of the first insulating film; the first insulating film and the first electrode have a tubular shape surrounding the first semiconductor layer, a thickness of the first insulating film on the lower surface of the first semiconductor layer is thicker than a thickness of the first insulating film on the upper surface or side surface of the first semiconductor layer; the first insulating film on at least the top surface and side surfaces of the first semiconductor layer functions as a gate insulating film of the pixel transistor; At least the first electrode on the upper surface and side surfaces of the first insulating film functions as a gate electrode of the pixel transistor. Solid-state imaging device.

2. 2. The solid-state imaging device according to claim 1, wherein the thickness of the first insulating film on the lower surface of the first semiconductor layer is at least twice as large as the thickness of the first insulating film on the upper surface or side surface of the first semiconductor layer.

3. The solid-state imaging device according to claim 1 , wherein the first semiconductor layer, the first insulating film, and the first electrode extend in a first direction parallel to a surface of the first semiconductor substrate.

4. The solid-state imaging device according to claim 1 , wherein the first semiconductor layer is a part of a second semiconductor substrate provided above the first semiconductor substrate.

5. The solid-state imaging device according to claim 1 , wherein the pixel transistor is an amplification transistor, a selection transistor, a reset transistor, or a switch transistor.

6. 2. The solid-state imaging device according to claim 1, wherein the first insulating film includes a first film provided on a lower surface of the first semiconductor layer and a second film provided on an upper surface and a side surface of the first semiconductor layer.

7. 7. The solid-state imaging device according to claim 6, wherein the first insulating film further includes a third film provided on a lower surface of the first film.

8. 2. The solid-state imaging device according to claim 1, wherein the first electrode includes a first layer provided on a lower surface of the first insulating film and a second layer provided on an upper surface and a side surface of the first insulating film.

9. 2. The solid-state imaging device according to claim 1, further comprising a second insulating film having the same thickness as the first electrode on the lower surface of the first insulating film and provided on the side of the first electrode on the lower surface of the first insulating film.

10. The solid-state imaging device according to claim 1 , further comprising a first wiring provided on an upper surface of the first electrode, electrically connecting the first electrode and the floating diffusion region.

11. a second semiconductor layer provided above the first semiconductor substrate; a second wiring that electrically connects the first semiconductor substrate and the second semiconductor layer; The solid-state imaging device according to claim 1 , further comprising:

12. The solid-state imaging device according to claim 11 , wherein the second semiconductor layer is a part of a second semiconductor substrate provided above the first semiconductor substrate.

13. The solid-state imaging device according to claim 1 , further comprising a third wiring provided on a lower surface of the first electrode, electrically connecting the first electrode and the floating diffusion region.

14. The solid-state imaging device according to claim 1 , further comprising a fourth wiring provided on a side surface of the first electrode, electrically connecting the first electrode and the floating diffusion region.

15. forming a photoelectric conversion region and a floating diffusion region in a first semiconductor substrate; forming a pixel transistor including a first semiconductor layer provided above the first semiconductor substrate, a first insulating film provided on a lower surface, an upper surface, and a side surface of the first semiconductor layer, and a first electrode provided on a lower surface, an upper surface, and a side surface of the first insulating film; This includes: the first insulating film and the first electrode are formed to have a tubular shape surrounding the first semiconductor layer; a thickness of the first insulating film on the lower surface of the first semiconductor layer is set to be thicker than a thickness of the first insulating film on the upper surface or side surface of the first semiconductor layer; the first insulating film on at least the top surface and side surfaces of the first semiconductor layer functions as a gate insulating film of the pixel transistor; At least the first electrode on the upper surface and side surfaces of the first insulating film functions as a gate electrode of the pixel transistor. A method for manufacturing a solid-state imaging device.

16. The method for manufacturing a solid-state imaging device according to claim 15 , wherein the first semiconductor layer is formed by bonding the first semiconductor substrate and a second semiconductor substrate together and processing the first semiconductor layer on the second semiconductor substrate.

17. the first insulating film includes a first film provided on a lower surface of the first semiconductor layer and a second film provided on an upper surface and a side surface of the first semiconductor layer; The method for manufacturing a solid-state imaging device according to claim 16 , wherein the first semiconductor substrate and the second semiconductor substrate are bonded together via the first film provided on the lower surface of the second semiconductor substrate.

18. the first insulating film further includes a third film provided on a lower surface of the first film, The method for manufacturing a solid-state imaging device according to claim 17 , wherein the first semiconductor substrate and the second semiconductor substrate are further bonded together via the third film provided on the top surface of the first semiconductor substrate.

19. the first electrode includes a first layer provided on a lower surface of the first insulating film and a second layer provided on an upper surface and a side surface of the first insulating film; The method for manufacturing a solid-state imaging device according to claim 16 , wherein the first semiconductor substrate and the second semiconductor substrate are bonded together via the first layer provided on the upper surface of the first semiconductor substrate.

20. the first semiconductor substrate and the second semiconductor substrate are further bonded together via a second insulating film provided on a lower surface of the first film; 18. The method for manufacturing a solid-state imaging device according to claim 17, wherein the first electrode is formed by removing a portion of the second insulating film from between the first semiconductor substrate and the second semiconductor substrate after the bonding, and forming a portion of the first electrode between the first semiconductor substrate and the second semiconductor substrate after the removal.

Images