SiC semiconductor device

Abstract

To provide an SiC semiconductor device with which a source region can be source-grounded appropriately, in a structure that includes a source trench.SOLUTION: Provided is an SiC semiconductor device 1 including an SiC semiconductor layer 2 having a first main surface 3, a source trench 31 formed in the first main surface 3 and having a side wall and a bottom wall, a source electrode 33 embedded in the source trench 31 and having a side wall contact portion 39 in contact with an opening side of the source trench 31 at a region of the side wall of the source trench 31, and a source region 42 electrically connected to the side wall contact portion 39 in a surface layer portion of the first main surface 3.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] This relates to a SiC semiconductor device with a source trench. [Background technology]

[0002] Patent Document 1 describes a SiC semiconductor substrate, a source trench, a source insulating layer, a source electrode, a body The present invention discloses a SiC semiconductor device including a source region and a source trench. The source insulating layer is formed on the main surface of the iC semiconductor substrate. The source electrode is buried in the source trench with a source insulating layer sandwiched between them. The source region is a surface layer of the main surface of the SiC semiconductor substrate, sandwiching a source insulating layer. The source region is located in the surface layer of the body region, sandwiching the source insulating layer. It faces the source electrode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2016 / 006696A1 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment provides a SiC semiconductor device that can appropriately ground a source region in a structure having a source trench. One embodiment provides a SiC semiconductor device capable of improving the breakdown voltage of the peripheral portion of the active region. [Means for solving the problem]

[0005] One embodiment includes a first conductivity type SiC semiconductor layer having a main surface, and a side surface formed on the main surface. a source trench having a wall and a bottom wall; a sidewall contact portion that contacts a region on the sidewall of the trench on the opening side of the source trench; and a source electrode formed in a surface layer portion of the main surface in a region along the source trench. a second conductive type body region formed in front of the source electrode in a surface layer portion of the body region; a source region of a first conductivity type electrically connected to the sidewall contact portion, A conductor device is provided.

[0006] According to this SiC semiconductor device, the source region is a silicon dioxide film exposed from the sidewall of the source trench. This allows the source region to be properly grounded. It is possible to provide a SiC semiconductor device that can

[0007] One embodiment provides a SiC semiconductor device including: a SiC semiconductor layer of a first conductivity type having a main surface; an active region having a plurality of trench gate structures formed on the main surface; a first impurity region of a second conductivity type formed in a region in a surface layer portion of the main surface between a peripheral portion of the active region and a peripheral edge of the SiC semiconductor layer, the first impurity region having a flat first bottom along the main surface; and a second impurity region of a second conductivity type formed in a region in the surface layer portion of the main surface between an outer edge of the first impurity region and the peripheral edge of the SiC semiconductor layer, the second impurity region being continuous with the first impurity region, the second impurity region having a flat second bottom along the main surface and located closer to the main surface than the first bottom. The above and other objects, features and advantages will become more apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a perspective view of a SiC semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a plan view of the SiC semiconductor device shown in FIG. [Figure 3] FIG. 3 is a plan view of the structure shown in FIG. 2, with the structure above the first principal surface electrode removed. [Figure 4] FIG. 4 is an enlarged plan view showing the internal structure of region IV shown in FIG. [Figure 5] FIG. 5 is a cross-sectional view taken along line VV shown in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. [Figure 7]FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. [Figure 8] FIG. 8 is an enlarged view of region VIII shown in FIG. [Figure 9] FIG. 9 is an enlarged view of region IX shown in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along the line XX shown in FIG. [Figure 11A] FIG. 11A is an enlarged cross-sectional view showing an example of a method for manufacturing the SiC semiconductor device shown in FIG. [Figure 11B] FIG. 11B is an enlarged cross-sectional view showing a step subsequent to that shown in FIG. 11A. [Figure 11C] FIG. 11C is an enlarged cross-sectional view showing a step subsequent to FIG. 11B. [Figure 11D] FIG. 11D is an enlarged cross-sectional view showing a step subsequent to FIG. 11C. [Figure 11E] FIG. 11E is an enlarged cross-sectional view showing a step subsequent to FIG. 11D. [Figure 11F] FIG. 11F is an enlarged cross-sectional view showing a step subsequent to FIG. 11E. [Figure 11G] FIG. 11G is an enlarged cross-sectional view showing a step subsequent to FIG. 11F. [Figure 11H] FIG. 11H is an enlarged cross-sectional view showing a step subsequent to FIG. 11G. [Figure 11I] FIG. 11I is an enlarged cross-sectional view showing a step subsequent to FIG. 11H. [Figure 11J] FIG. 11J is an enlarged cross-sectional view showing a step subsequent to FIG. 11I. [Figure 11K] FIG. 11K is an enlarged cross-sectional view showing a step subsequent to FIG. 11J. [Figure 11L] FIG. 11L is an enlarged cross-sectional view showing a step subsequent to FIG. 11K. [Figure 11M] FIG. 11M is an enlarged cross-sectional view showing a step subsequent to FIG. 11L. [Figure 11N] FIG. 11N is an enlarged cross-sectional view showing a step subsequent to FIG. 11M. [Figure 11O] FIG. 11O is an enlarged cross-sectional view showing a step subsequent to FIG. 11N. [Figure 11P] FIG. 11P is an enlarged cross-sectional view showing a step subsequent to FIG. 11O. [Figure 11Q] FIG. 11Q is an enlarged cross-sectional view showing a step subsequent to FIG. 11P. [Figure 11R] FIG. 11R is an enlarged cross-sectional view showing a step subsequent to FIG. 11Q. [Figure 11S] FIG. 11S is an enlarged cross-sectional view showing a step subsequent to FIG. 11R. [Figure 12] FIG. 12 is an enlarged view of a region corresponding to FIG. 8, and is a view partially showing the SiC semiconductor device according to the second embodiment of the present invention. [Figure 13A] FIG. 13A is an enlarged cross-sectional view showing an example of a method for manufacturing the SiC semiconductor device shown in FIG. [Figure 13B] FIG. 13B is an enlarged cross-sectional view showing a step subsequent to that of FIG. 13A. [Figure 13C] FIG. 13C is an enlarged cross-sectional view showing a step subsequent to FIG. 13B. [Figure 13D] FIG. 13D is an enlarged cross-sectional view showing a step subsequent to FIG. 13C. [Figure 13E] FIG. 13E is an enlarged cross-sectional view showing a step subsequent to FIG. 13D. [Figure 13F] FIG. 13F is an enlarged cross-sectional view showing a step subsequent to FIG. 13E. [Figure 14] FIG. 14 is an enlarged view of a region corresponding to FIG. 8, and is a view partially showing the SiC semiconductor device according to the third embodiment of the present invention. [Figure 15A] FIG. 15A is an enlarged cross-sectional view showing an example of a method for manufacturing the SiC semiconductor device shown in FIG. [Figure 15B] FIG. 15B is an enlarged cross-sectional view showing a step subsequent to that of FIG. 15A. [Figure 16] FIG. 16 is an enlarged view of a region corresponding to FIG. 8, and is a view partially showing the SiC semiconductor device according to the fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] FIG. 1 is a perspective view of a SiC semiconductor device 1 according to a first embodiment of the present invention. 3 is a plan view of the SiC semiconductor device 1 shown in FIG. 1 is a plan view in which the structure above the surface electrode 71 and the source main surface electrode 81 (first main surface electrode) is removed. FIG. 4 is an enlarged plan view showing the internal structure of region IV shown in FIG. 3. FIG. 5 is an enlarged plan view showing the internal structure of region IV shown in FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 4. FIG. 7 is a cross-sectional view taken along line VI-VI shown in FIG. Fig. 8 is a cross-sectional view taken along line VII-VII shown in Fig. 4. Fig. 8 is an enlarged view of region VIII shown in Fig. 5. 9 is an enlarged view of region IX shown in FIG. 6. FIG. 10 is a cross-sectional view taken along line XX shown in FIG. is.

[0010] 1 to 10, a SiC semiconductor device 1 includes a SiC semiconductor layer 2. The conductor layer 2 includes a SiC single crystal made of a hexagonal crystal. Depending on the arrangement period, 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H- The SiC semiconductor layer 2 has a plurality of polytypes including SiC single crystal. In this embodiment, the 4H-SiC single crystal is used, but other polytypes are excluded. It's not something like that.

[0011] The thickness of the SiC semiconductor layer 2 may be 40 μm or more and 300 μm or less. The thickness of the body layer 2 is 40 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200μm or less, 200μm or more and 250μm or less, or 250μm or more and 30 The thickness of the SiC semiconductor layer 2 may be 60 μm or more and 150 μm or less. It is preferable that there is.

[0012] The SiC semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and a The first main surface 3 and the second main surface 4 are connected to each other through side surfaces 5A to 5D. The first main surface 3 and the second main surface 5A include a first side surface 5B, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D. The main surfaces 4 are, in plan view as viewed from the normal direction Z thereof (hereinafter simply referred to as "plan view"). The electrode is formed in a quadrangular shape (rectangular in this embodiment).

[0013] In this embodiment, the first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal. The first main surface 3 faces the silicon surface ((0001) surface) of the SiC single crystal. The second main surface 4 is a non-mounting surface. The second main surface 4 faces the carbon surface ((000-1) surface) of the SiC single crystal. The first principal surface 3 and the second principal surface 4 are inclined at a predetermined angle in the off-direction with respect to the c-plane. The off-axis direction is the a-axis direction ([11-20] direction) of the SiC single crystal. When the crystal has an off-axis angle, it is preferable that the c-axis of the SiC single crystal (the

[0001] direction) is The direction of the crystal grains is inclined by an off angle with respect to the normal direction Z.

[0014] The off angle may be more than 0° and not more than 10°. The off angle is preferably 0° or more and not more than 6°. The off angle may be 0° or more and 2° or less, 2° or more and 4° or less, or 4° or more and 6° or less. The off angle is preferably greater than 0° and equal to or less than 4.5°. In this case, the off angle may be 3° or more and 4.5° or less. The off angle is preferably 1.5° or more and 3° or less. In this case, the off angle may be 1.5° or more and 2° or less, or 2° or more and 2. It is preferable that the angle is 5° or less.

[0015] The second main surface 4 has either grinding marks or annealing marks (specifically, laser irradiation marks) or The annealing marks may consist of amorphized SiC and a rough surface having both. and / or containing SiC (specifically Si) silicided (alloyed) with metal The second main surface 4 is preferably an ohmic surface having at least annealing marks. It's nice.

[0016] The first side surface 5A and the second side surface 5B extend in a first direction X and intersect with the first direction X (specifically, The first side surface 5A and the second side surface 5B face each other in a second direction Y (which is perpendicular to the first side surface 5A). The third side surface 5C and the fourth side surface 5D form the short sides of the SiC semiconductor layer 2. The third side surface 5C and the fourth side surface 5D extend in the two directions Y and face each other in the first direction X. 2. The long side of the SiC semiconductor layer 2 is formed in this manner.

[0017] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal. The second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. The side surface 5A and the second side surface 5B are formed by the a-plane of the SiC single crystal. The third side surface 5C and the fourth side surface 5D are opposed to each other in the a-axis direction. The side surfaces 5A to 5D are formed so as to face each other in the m-axis direction of the SiC single crystal. The length of each of the side surfaces 5A to 5D may be 0.1 mm or more and 10 mm or less. It is preferable that the thickness is 2.5 mm or less.

[0018] The side surfaces 5A to 5D may be cleaved or ground surfaces. In this embodiment, the first side surface 5A and the second side surface 5B are cleaved. When the SiC single crystal is tilted toward the c-axis direction (0001) of the SiC single crystal with respect to the normal direction Z, An inclined surface may be formed.

[0019] When the normal direction Z is set to 0°, the first side surface 5A and the second side surface 5B are The angle corresponding to the off angle may be equal to the off angle. Alternatively, the angle may be greater than 0° and less than the off angle. The four side surfaces 5D extend planarly along the second direction Y (a-axis direction) and the normal direction Z. Specifically, the third side surface 5C and the fourth side surface 5D are It is formed substantially vertically.

[0020] The SiC semiconductor layer 2 is + The drain region 6 includes an n-type impurity concentration Degree is 1 x 10 18 cm -3 More than 1×10 20 cm -3 The drain area may be: The drain region 6 is formed in the surface layer of the second main surface 4 and forms the second main surface 4. , in this form, n + The semiconductor substrate 7 is made of SiC.

[0021] The thickness of the drain region 6 may be 40 μm or more and 250 μm or less. The thickness of 6 is 40 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm The thickness may be from 200 μm to 200 μm, or from 200 μm to 250 μm. The thickness of the drain region 6 is preferably 40 μm or more and 150 μm or less. By thinning the drain region 6, the resistance value of the drain region 6 can be reduced.

[0022] The SiC semiconductor layer 2 includes an n-type drift region 8. The drift region 8 is a drain region The n-type impurity concentration of the drift region 8 is less than the n-type impurity concentration of the Degrees are 1.0 x 10 15 cm -3 Over 1.0 x 10 18 cm -3 The following may be used: The lift region 8 is formed in the surface layer of the first main surface 3, and forms the first main surface 3. Region 8 is electrically connected to drain region 6. Drain region 6 and drift region The boundary of the region 8 extends parallel to the first main surface 3. In this embodiment, the drift region 8 is , an n-type SiC epitaxial layer 9 formed on a SiC semiconductor substrate 7.

[0023] The thickness of the drift region 8 may be 1 μm or more and 50 μm or less. The thickness is 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15μm or more and 20μm or less, 20μm or more and 30μm or less, 30μm or more and 40μm or less, or Alternatively, the thickness of the drift region 8 may be 40 μm or more and 50 μm or less. It is preferably 15 μm or less.

[0024] In this embodiment, the drift region 8 has different n-type impurity concentrations along the normal direction Z. The drift region 8 has a plurality of regions. Specifically, the drift region 8 has a high concentration region 10 and a low concentration region 11. The high concentration region 10 has a relatively high n-type impurity concentration and is The low concentration region 11 has an n-type impurity concentration lower than that of the high concentration region 10. It has an impurity concentration and is formed in a region on the second main surface 4 side with respect to the high concentration region 10.

[0025] The peak value of the n-type impurity concentration in the high concentration region 10 is 1.0×10 16 cm -3 Over 1.0 x10 18 cm -3 The peak value of the n-type impurity concentration of the low concentration region 11 may be equal to or less than 1000 kJ / cm. , 1.0×10 15 cm -3 Over 1.0 x 10 16 cm -3 It may be less than 10 ... The thickness of the region 11 is greater than the thickness of the high concentration region 10. In other words, the thickness of the high concentration region 10 is less than the thickness of the low concentration region 11 and less than half the total thickness of the drift region 8. Of course, the drift region 8 may be formed to have a uniform n-type impurity concentration.

[0026] The SiC semiconductor layer 2 includes an active region 12 and an outer region 13. 12 is MISFET (Metal Insulator Semiconductor Field Effect Transistor) The active area 12 is an area formed inward from the side surfaces 5A to 5D in a plan view. The active region 12 is formed in the center of the SiC semiconductor layer 2 with a gap therebetween. In this embodiment, the shape is a rectangle having four sides parallel to the side surfaces 5A to 5D in plan view (in this embodiment, The outer region 13 is a region outside the active region 12. The outer region 13 is formed in the region between the side surfaces 5A to 5D and the periphery of the active region 12. The outer region 13 is an annular (more specifically, circular) region surrounding the active region 12 in a plan view. Specifically, it is formed in an endless shape.

[0027] The SiC semiconductor device 1 has a plurality of transistors formed on the first main surface 3 in the active region 12. The trench gate structures 18 are formed as strips extending in a first direction X. The trench gates are formed in a shape similar to that of the trench gates 100 and 102, and are spaced apart in the second direction Y. The dot structure 18 is formed in a stripe shape as a whole in a plan view.

[0028] In this embodiment, the plurality of trench gate structures 18 are formed on one side of the active region 12. It extends in a strip shape from the peripheral edge of the third side surface 5C to the peripheral edge of the other side (fourth side surface 5D). The plurality of trench gate structures 18 are formed on the peripheral edge of the active region 12 on one side. and across the middle between the periphery on the other side.

[0029] The length of each trench gate structure 18 may be between 1 mm and 10 mm. The length of the anti-gate structure 18 is 1 mm or more and 2 mm or less, 2 mm or more and 4 mm or less, 4 mm or less It may be 6mm or less, 6mm to 8mm, or 8mm to 10mm. The length of each trench gate structure 18 is preferably 2 mm or more and 6 mm or less. The total length per unit area of ​​the trench gate structure 18 is 0.5 μm / μm 2 Over 0. 75μm / μm 2 It may be the following:

[0030] Each trench gate structure 18 includes an active trench portion 19 and a contact trench portion 19. The active trench portion 19 is a portion along the channel of the MISFET. The contact trench portion 20 is a portion outside the channel of the MISFET. The trench portion 20 is the end of the trench gate structure 18 and is primarily intended for external connection.

[0031] Each trench gate structure 18 includes a gate trench 21, a gate insulating layer 22, and a gate electrode. 4, the gate insulating layer 22 and the gate electrode 23 are indicated by hatching. is shown.

[0032] The gate trench 21 is formed in the drift region 8. The gate trench 21 has a side The sidewalls forming the long sides of the gate trench 21 are made of a-plane SiC single crystal. The sidewalls that form the short sides of the gate trench 21 are made of SiC single crystal. It is formed by m-planes.

[0033] The sidewalls of the gate trench 21 may extend along the normal direction Z. In this case, The sidewalls of the trench 21 may be formed substantially perpendicular to the first main surface 3. The angle formed by the sidewall of the gate trench 21 in the semiconductor layer 2 with respect to the first main surface 3 is 90°. The angle may be greater than or equal to 95° and less than or equal to 95° (for example, greater than or equal to 91° and less than or equal to 93°). The wrench 21 is formed in a tapered shape in which the opening width narrows from the first main surface 3 toward the bottom wall. Good too.

[0034] The bottom wall of the gate trench 21 is located in the high concentration region 10. The bottom wall of the gate trench 21 faces the c-plane of the SiC single crystal. The off-axis angle is tilted in the [11-20] direction relative to the (0001) plane. The bottom wall of the trench 21 may be formed parallel to the first main surface 3. Gate trench The bottom wall of 21 may be curved toward the second main surface 4.

[0035] The width of the gate trench 21 along the second direction Y may be 0.1 μm or more and 2 μm or less. The width of the gate trench 21 is 0.1 μm or more and 0.5 μm or less, and 0.5 μm or more and 1.0 μm or less. μm or less, 1.0 μm to 1.5 μm or 1.5 μm to 2 μm Good too.

[0036] The gate trench 21 has a first depth D1. The first depth D1 is 0.5 μm or more. The first depth D1 may be 0.5 μm or more and 1.0 μm or less, and 1. 0μm or more and 1.5μm or less, 1.5μm or more and 2.0μm or less, 2.0μm or more and 2.5μm It may be 2.5 μm or less, or 2.5 μm or more and 3.0 μm or less.

[0037] The opening edge of the gate trench 21 extends from the first main surface 3 toward the inside of the gate trench 21. The opening edge of the gate trench 21 includes a sloped portion that slopes downward. and the portion connecting the sidewall of the gate trench 21. The inclined portion of the gate trench 21 is The gate trench 21 is formed in a curved shape directed inward of the SiC semiconductor layer 2. The gate trench 21 may be formed in a curved shape toward the inside of the gate trench 21. The inclined portion of the gate trench 21 reduces the concentration of the electric field at the opening edge of the gate trench 21.

[0038] The gate insulating layer 22 may be made of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, or the like. The gate insulating layer 22 includes at least one of silicon oxide and tantalum oxide. The gate electrode may have a laminated structure in which a silicon layer and a silicon nitride layer are laminated in any order. The insulating layer 22 may have a single layer structure made of a silicon oxide layer or a silicon nitride layer. In this embodiment, the gate insulating layer 22 has a single layer structure made of a silicon oxide layer. do.

[0039] The gate insulating layer 22 is formed in a film shape along the inner wall of the gate trench 21. The gate insulating layer 22 defines a recess space in the trench 21. The gate insulating layer 22 includes a first region 24, a second region 25, a third region 26, a fourth region 27, a fifth region 28, a sixth region 29 ... The first region 24 includes a second region 25 and a third region 26. The first region 24 is formed along the sidewall of the gate trench 21. The second region 25 is formed along the bottom wall of the gate trench 21. The third region 26 is formed along the first main surface 3 .

[0040] The thickness of the first region 24 is less than the thickness of the second region 25 and the thickness of the third region 26. The thickness of the first region 24 may be 0.01 μm or more and 0.2 μm or less. The thickness may be 0.05 μm or more and 0.5 μm or less. The thickness of the third region 26 is 0. It may be 0.05 μm or more and 0.5 μm or less.

[0041] The gate insulating layer 22 has a bulge that bulges toward the inside of the gate trench 21 at the opening edge portion. The bulging portion 27 is formed between the first region 24 and the third region 26 of the gate insulating layer 22. The bulging portion 27 is formed in a curved shape toward the inside of the gate trench 21. The bulging portion 27 narrows the opening of the gate trench 21 at the opening edge portion. The gate insulating layer 22 may be formed without the bulging portion 27. A gate insulating layer 22 may be formed.

[0042] The gate electrode 23 is buried in the gate trench 21 with the gate insulating layer 22 sandwiched therebetween. Specifically, the gate electrode 23 is formed in the gate trench 21 by the gate insulating layer 22. The gate electrode 23 is embedded in a recess space partitioned by the gate trench 21. The electrode surface of the gate electrode 23 is exposed from the opening of the gate trench 21. The electrode surface of the gate electrode 23 is formed in a curved shape recessed toward the bottom wall. It is narrowed by a bulge 27 in layer 22 .

[0043] The gate electrode 23 is made of a conductive material other than a metal material. The gate electrode 23 is preferably made of silicon. In this embodiment, the gate electrode 23 is p-doped. The p-type impurity concentration of the gate electrode 23 is 1.0×10 18 cm -3 Over 1.0 x 10 22 cm -3 The p-type impurity of the gate electrode 23 may be The article contains at least one of boron, aluminum, indium, and gallium. The sheet resistance of the gate electrode 23 may be 10 Ω / □ or more and 500 Ω / □ or less (this The thickness of the gate electrode 23 may be 0.5 μm or more. It may be 3 μm or less.

[0044] The SiC semiconductor device 1 has a gate electrode formed on the first main surface 3 in the active region 12. In FIG. 4, the gate wiring 28 is shown by hatching. Specifically, the gate wiring 28 is formed on the third region 26 of the gate insulating layer 22. The port wiring 28 is formed on the first side surface 5A, the third side surface 5C, and the fourth side surface 5D in the active region 12. The area formed along the surface 5D and having the plurality of trench gate structures 18 formed therein is viewed from three directions. It is divided into sections.

[0045] The gate wiring 28 is exposed from the contact trench portion 20 of the trench gate structure 18. In this embodiment, the gate wiring 28 is connected to the gate electrode 23. 1 and the lead portion of the gate electrode 23 led out onto the first main surface 3. The electrode surface of the gate wiring 28 is connected to the electrode surface of the gate electrode 23 .

[0046] The SiC semiconductor device 1 includes a first low resistance layer 29 that covers the gate electrode 23. The resistive layer 29 includes a conductive material having a sheet resistance less than the sheet resistance of the gate electrode 23. The sheet resistance of the low resistance layer 29 may be 0.01 Ω / □ or more and 10 Ω / □ or less. The thickness of the first low-resistance layer 29 in the linear direction Z is less than the thickness of the gate electrode 23. The thickness of the first low-resistivity layer 29 may be 0.01 μm or more and 3 μm or less.

[0047] The first low-resistance layer 29 covers the gate electrode 23 in the gate trench 21. The first low resistance layer 29 forms a part of the trench gate structure 18. The first low-resistance layer 29 also covers the gate wiring 28. The portion covering the gate electrode 23 is formed integrally with the portion of the first low resistance layer 29 that covers the gate electrode 23. As a result, the first low resistance layer 29 is formed over the entire area of ​​the gate electrode 23 and the gate wiring 28. It covers the entire area.

[0048] Specifically, the first low resistance layer 29 includes a polycide layer. The surface layer of the gate wiring 28 and the surface layer of the gate wiring 23 are made of a metal material and a silicide layer. That is, the polycide layer is formed on the gate electrode 23 (p-type polysilicon) and the gate wiring 28 ( It consists of a p-type polycide layer containing p-type impurities added to p-type polysilicon. The electrode surface of the gate electrode 23 and the electrode surface of the gate wiring 28 are formed by a first low resistance layer 29. The polycide layer has a resistivity of 10 μΩ·cm or more and 110 μΩ·cm or less. It is preferable that

[0049] The sheet in the gate trench 21 in which the gate electrode 23 and the first low-resistance layer 29 are buried The resistance is equal to or less than the sheet resistance of the gate electrode 23 alone. The resistance is preferably equal to or less than the sheet resistance of n-type polysilicon doped with n-type impurities. The sheet resistance in the gate trench 21 is approximated to the sheet resistance of the first low resistance layer 29. The sheet resistance in the gate trench 21 may be 0.01 Ω / □ or more and 10 Ω / □ or less. The sheet resistance in the gate trench 21 is preferably less than 10 Ω / □.

[0050] The first low resistance layer 29 is made of TiSi, TiSi2, NiSi, CoSi, CoSi2, or Mo It may contain at least one of Si2 and WSi2. Among the species, NiSi, CoSi2, and TiSi2 have relatively high resistivity and temperature dependence. Since it is relatively small, it is suitable as a polycide layer for forming the first low resistance layer 29. The low resistance layer 29 is preferably made of CoSi2, which has the property of being less likely to diffuse into other regions. preferable.

[0051] The first low-resistance layer 29 includes a contact portion that contacts the gate insulating layer 22. Specifically, the contact portion is in contact with the third region 26 (bulge portion 27) of the gate insulating layer 22. This makes it possible to suppress the current path between the first low-resistance layer 29 and the drift region 8. In particular, The contact portion of the first low resistance layer 29 is connected to a relatively thick corner portion of the gate insulating layer 22. The meter is effective in reducing the risk of current paths.

[0052] P-type polysilicon, which has a different work function from n-type polysilicon, is placed in gate trench 2. By embedding it in 1, the gate threshold voltage Vth can be increased by about 1V. However, the sheet resistance of p-type polysilicon is several tens of times (approximately 20 times) higher than that of n-type polysilicon. Therefore, p-type polysilicon is used as the material for the gate electrode 23. When the gate resistance is adopted as the gate resistance, the parasitic resistance in the gate trench 21 (hereinafter simply referred to as the “gate resistance”) As the temperature increases, the energy loss increases.

[0053] Therefore, in the SiC semiconductor device 1, a first low-temperature insulating film is formed on the gate electrode 23 (p-type polysilicon). The first low-resistivity layer 29 is formed as a resistive layer (p-type polycide). The sheet resistance in the gate trench 21 can be reduced while allowing an increase in the voltage Vth. For example, a structure having the first low resistance layer 29 has a different effect from a structure not having the first low resistance layer 29. The sheet resistance can be reduced to 1 / 100 or less compared to the first low resistance layer. The structure having 29 has a sheet resistance lower than that of the gate electrode 23 including n-type polysilicon. The resistance can be reduced by more than five times.

[0054] This reduces the gate resistance, allowing current to flow efficiently along the trench gate structure 18. That is, the first low resistance layer 29 can be diffused efficiently in the gate trench 21. It is formed as a current diffusion layer that diffuses current. In the case of a gate trench 21 having a length of 1 mm or more, it takes time for the current to be transmitted. The first low-resistance layer 29 can appropriately suppress switching delay. According to the structure having the p-type impurity in the drift region 8, the gate threshold voltage Vth can be increased. Therefore, the gate threshold voltage can be increased while suppressing the increase in channel resistance. The threshold voltage Vth can be increased appropriately.

[0055] The SiC semiconductor device 1 has a plurality of trench gate structures 18 adjacent to each other. Each of the trench source structures 30 includes a plurality of trench source structures 30 formed therein. are formed at intervals in the second direction Y in a manner that one trench gate structure 18 is sandwiched between them. The plurality of trench source structures 30 are each formed in a strip shape extending in the first direction X. The plurality of trench source structures 30 are arranged in a stripe pattern as a whole in a plan view. It is formed.

[0056] In the second direction Y, the pitch PS between the center portions of the adjacent trench source structures 30 is The pitch PS may be 1 μm or more and 5 μm or less. The thickness may be 1 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, or 4 μm or more and 5 μm or less. The pitch PS is preferably 1.5 μm or more and 3 μm or less.

[0057] Each trench source structure 30 includes a source trench 31, a source insulating layer 32, and a source electrode. 4, the source insulating layer 32 and the source electrode 33 are indicated by hatching. The source trench 31 is formed in the drift region 8. The sidewalls forming the long sides of the source trench 31 are made of SiC. The sidewalls of the source trench 31 are made of a single crystal a-plane. It is formed by the m-plane of an iC single crystal.

[0058] The bottom wall of the source trench 31 is located in the high concentration region 10. The bottom wall of the source trench 31 faces the c-plane of the SiC single crystal. The off-axis angle is tilted in the [11-20] direction relative to the (0001) plane. The bottom wall of the trench 31 may be formed parallel to the first main surface 3. Source Trench The bottom wall of 31 may be curved toward the second main surface 4.

[0059] The bottom wall of the source trench 31 is a region on the second main surface 4 side with respect to the bottom wall of the gate trench 21. The bottom wall of the source trench 31 is located at the gate trench 2 The source trench 31 is located in the region between the bottom wall of the source trench 31 and the low concentration region 11. The first depth D2 is greater than the first depth D1 of the gate trench 21. The ratio DS / DG of the second depth D2 to 1 is The ratio DS / DG may be 1.5 or more, provided that the ratio is 2 or more. It is preferable.

[0060] The second depth D2 may be 0.5 μm or more and 10 μm or less. The second depth D2 may be 0. 5μm or more and 1μm or less, 1μm or more and 2μm or less, 2μm or more and 4μm or less, 4μm or more and 6μm It may be 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. Even if the source trench 31 is formed with a second depth D2 that is approximately equal to the first depth D1, good.

[0061] In this embodiment, the source trench 31 includes a first trench portion 34 and a second trench portion 35. The first trench portion 34 is formed on the opening side of the source trench 31. The trench portion 34 has a first width W1 in the second direction Y. The first trench portion 34 has The first width W1 may be tapered from the first main surface 3 toward the bottom wall side. The first trench portion 34 is a first trench that crosses the bottom wall of the gate trench 21 in the normal direction Z. The first trench portion 34 may be formed as a trench portion 34. That is, the depth of the first trench portion 34 may be The depth may exceed the first depth D1 of the gate trench 21.

[0062] The first trench portion 34 is formed in a region on the first main surface 3 side with respect to the bottom wall of the gate trench 21. That is, the depth of the first trench portion 34 is preferably set to be equal to or larger than the depth of the gate trench 21. The depth of the first trench portion 34 is preferably less than the first depth D1. The depth of the first trench portion 34 may be 0.1 μm or more and 0.5 μm or less. or less, 0.5 μm to 1 μm, 1 μm to 1.5 μm, or 1.5 μm or more It may be 2 μm or less.

[0063] The first width W1 of the first trench portion 34 may be equal to or greater than the width of the gate trench 21, The first width W1 may be less than the width of the gate trench 21. The first width W1 may be equal to or greater than 0.1 μm and equal to or less than 2 μm. The first width W1 is 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more It may be 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0064] The second trench portion 35 is formed on the bottom wall side of the source trench 31. The portion 35 is located between the first trench portion 34 and the bottom of the drift region 8 in the normal direction Z. The first region is formed in the normal direction Z and crosses the bottom wall of the gate trench 21. The depth of the second trench portion 35 based on the trench portion 34 is 1 / 2 the first depth of the gate trench 21. It is preferable that the thickness exceeds D1.

[0065] The second trench portion 35 has a second width W2 in the second direction Y that is less than the first width W1. The second width W2 is equal to or greater than the width of the gate trench 21, provided that the second width W2 is less than the first width W1. The second width W2 may be 0.1 μm or less than the width of the gate trench 21. The second width W2 may be 0.1 μm or more and less than 2 μm. 5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and less than 2 μm Of course, the second trench portion 3 may have a second width W2 that is approximately equal to the first width W1. 5 may be formed.

[0066] The opening width of the source trench 31 including the first trench portion 34 and the second trench portion 35 is It is preferable that the opening width of the source trench 21 is approximately the same as that of the gate trench 21. The opening width of the source trench 31 is approximately the same as the opening width of the gate trench 21. This means that the opening width is within a range of ±20% of the opening width of the gate trench 21.

[0067] The sidewall of the second trench portion 35 may extend along the normal direction Z. SiC semiconductor layer 2, the angle formed by the sidewall of the second trench portion 35 with respect to the first main surface 3 is 90° or more. The angle may be 5° or less (for example, 91° or more and 93° or less). The second trench portion 35 may be formed substantially perpendicular to the first main surface 3. Even if the trench portion 34 is formed in a tapered shape in which the second width W2 narrows from the trench portion 34 toward the bottom wall side, good.

[0068] The source insulating layer 32 is made of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, or the like. The source insulating layer 32 contains at least one of silicon oxide and tantalum oxide. The silicon nitride layer may have a laminated structure in which the silicon layer and the silicon nitride layer are laminated in any order. The insulating layer 32 may have a single layer structure made of a silicon oxide layer or a silicon nitride layer. In this embodiment, the source insulating layer 32 has a single layer structure made of a silicon oxide layer. do.

[0069] The source insulating layer 32 is formed in a film shape along the inner wall of the source trench 31. The source insulating layer 32 defines a recess space within the trench 31. Specifically, the source insulating layer 32 is The second trench portion 35 is formed in a film shape along the inner wall thereof so as to expose the trench portion 34. As a result, the source insulating layer 32 has a sidewall window portion 33 exposing the first trench portion 34. 6, which defines a recess space in the second trench portion 35.

[0070] The source insulating layer 32 includes a first region 37 and a second region 38. The first region 37 is The second region 38 is formed along the sidewall of the source trench 31. The first region 37 is formed along the bottom wall. The thickness of the first region 37 is less than the thickness of the second region 38. The thickness of the first region 37 may be 0.01 μm or more and 0.2 μm or less. The thickness of the first region 37 may be 0.05 μm or more and 0.5 μm or less. The thickness of the second region 38 may be approximately equal to the thickness of the first region 24 of the gate insulating layer 22. The thickness of the source insulating layer 22 may be approximately equal to the thickness of the second region 25 of the source insulating layer 22. An insulating layer 32 may be formed.

[0071] The source electrode 33 is buried in the source trench 31 with the source insulating layer 32 sandwiched therebetween. Specifically, the source electrode 33 is formed in the first trench of the source trench 31 with the source insulating layer 32 interposed therebetween. The source electrode 33 is buried in the trench portion 34 and the second trench portion 35. The second trench portion 35 is embedded in the recess space defined by the bottom wall of the trench 31. The source electrode 33 is exposed from a sidewall window 36 on the opening side of the source trench 31. The first trench portion 34 has a sidewall contact portion 39 that contacts the sidewall of the first trench portion 34 .

[0072] The source electrode 33 has an electrode surface exposed from the opening of the source trench 31. The electrode surface of the source electrode 33 is formed in a curved shape recessed toward the bottom wall of the source trench 31. The electrode surface of the source electrode 33 may be formed parallel to the first main surface 3.

[0073] The thickness of the source electrode 33 in the normal direction Z is 0.5 μm or more and 10 μm or less. The thickness of the source electrode 33 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm It may be 10 μm or more.

[0074] The source electrode 33 is made of a conductive material other than a metal material. The source electrode 33 is preferably made of silicon. In this embodiment, the source electrode 33 is p-doped. The source electrode 33 includes p-type polysilicon. The p-type impurity concentration of the source electrode 33 is 1.0×10 18 cm -3 Over 1.0 x 10 22 cm -3 The p-type impurity of the source electrode 33 may be less than or equal to the above. The impurity concentration of the source electrode 22 is preferably equal to the p-type impurity concentration of the gate electrode 23. The sheet resistance of electrode 33 is 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this form). The p-type impurity of the source electrode 33 may be boron, aluminum, indium, or the like. The material may contain at least one of aluminum and gallium.

[0075] The SiC semiconductor device 1 includes a second low resistance layer 40 that covers the source electrode 33. The resistance layer 40 covers the source electrode 33 in the source trench 31. The layer 40 forms part of the trench source structure 30. The second low resistance layer 40 is The second low resistance layer 40 includes a conductive material having a sheet resistance lower than that of the electrode 33. The port resistance may be 0.01 Ω / □ or more and 10 Ω / □ or less. With respect to the normal direction Z, The thickness of the second low-resistance layer 40 is preferably less than the thickness of the source electrode 33. The thickness of the anti-friction layer 40 may be 0.01 μm or more and 3 μm or less.

[0076] Specifically, the second low resistance layer 40 includes a polycide layer. The surface layer of 33 is made of a metal material and a silicide layer. The source electrode 33 is made of a p-type polycide layer containing p-type impurities. The electrode surface of 33 is formed by the second low resistance layer 40. The polycide layer has a resistance of 10 μΩ It is preferable that the resistivity is 100 μΩ·cm or more and 110 μΩ·cm or less.

[0077] The sheet in the source trench 31 in which the source electrode 33 and the second low resistance layer 40 are buried The resistance is equal to or less than the sheet resistance of the source electrode 33 alone. The resistance is preferably equal to or less than the sheet resistance of n-type polysilicon doped with n-type impurities. The sheet resistance in the source trench 31 is approximated to the sheet resistance of the second low resistance layer 40. The sheet resistance in the source trench 31 may be 0.01 Ω / □ or more and 10 Ω / □ or less. The sheet resistance in the source trench 31 is preferably less than 10 Ω / □.

[0078] The second low resistance layer 40 is made of TiSi, TiSi2, NiSi, CoSi, CoSi2, Mo It may contain at least one of Si2 and WSi2. Among the species, NiSi, CoSi2, and TiSi2 have relatively high resistivity and temperature dependence. Since it is relatively small, it is suitable as a polycide layer for forming the second low resistance layer 40. The low resistance layer 40 is preferably made of CoSi2, which has the property of being less likely to diffuse into other regions. It is preferable that the second low-resistance layer 40 is made of the same conductive material as the first low-resistance layer 29. It's nice.

[0079] The SiC semiconductor device 1 has a p-type body region formed in the surface layer portion of the first main surface 3 in the active region 12. (Second impurity region) The body region 41 defines the active region 12. The p-type impurity concentration of the body region 41 is lower than the p-type impurity concentration of the gate electrode 23. The p-type impurity concentration of the body region 41 is lower than the p-type impurity concentration of the source electrode 33. The peak value of the p-type impurity concentration of the body region 41 is 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 It may be the following:

[0080] The body region 41 is formed on the surface of the first main surface 3, and is connected to the sidewalls and the sole of the gate trench 21. The body region 41 covers the sidewall of the gate trench 31. The body region 41 is formed in a region on the first main surface 3 side relative to the gate insulating layer 22. The gate electrode 23 is opposed to the gate electrode 23 on either side.

[0081] The body region 41 is further formed to have a first trench portion 35 of the source trench 31 . The body region 41 is formed in the region on the trench portion 34 side of the source trench 31. The body region 41 covers the source trench 31. The source electrode 33 is connected to the sidewall contact portion 39 of the source electrode 33 exposed from the first trench portion 34. The body region 41 is connected to a source ground in the SiC semiconductor layer 2. The body region 41 may cover a part of the second trench portion 35. In this case, the body region 41 may face the source electrode 33 with a part of the source insulating layer 32 interposed therebetween.

[0082] The SiC semiconductor device 1 has an n-type + Type source region 42 The source region 42 is spaced from the contact trench portion 20 of the gate trench 21. The source is formed along the active trench portion 19 of the gate trench 21. The peak value of the n-type impurity concentration in the region 42 is equal to the peak value of the n-type impurity concentration in the high concentration region 10. The peak value of the n-type impurity concentration in the source region 42 exceeds 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 It may be the following:

[0083] The source region 42 is formed on the sidewall of the gate trench 21 and the surface of the body region 41. The source region 42 covers the sidewall of the source trench 31. The source region 42 is formed by sandwiching the gate insulating layer 22. The source region 42 faces the gate electrode 23 at the first low It is preferable that it faces the resistive layer 29 .

[0084] The source region 42 is further formed by forming a first trench with respect to the second trench portion 35 of the source trench 31. The source region 42 is formed in the trench portion 34 side region. The source region 42 covers the first trench of the source trench 31. The contact portion 39 of the source electrode 33 is connected to the sidewall contact portion 39 of the source electrode 33 exposed from the contact portion 34. The source region 42 is connected to source ground within the SiC semiconductor layer 2 .

[0085] The portion of the source region 42 along the sidewall of the gate trench 21 is located within the body region 41. The channel of the MISFET is defined between the high concentration region 10 and the ON region of the channel. / OFF is controlled by the gate electrode 23 .

[0086] The SiC semiconductor device 1 has a surface layer formed on the first main surface 3 in the active region 12. p + The contact region 43 includes a plurality of p-type contact regions 43. The peak value exceeds the peak value of the p-type impurity concentration of the body region 41. The peak value of the p-type impurity concentration of 43 is 1.0 × 10 18 cm -3 Over 1.0 x 10 21 c m -3 It may be the following:

[0087] The plurality of contact regions 43 are formed in regions along the plurality of source trenches 31, respectively. Specifically, the plurality of contact regions 43 are connected to a corresponding one of the source trenches 3. The contact regions 43 are formed in a one-to-many correspondence with the corresponding The contacts are formed at intervals along one source trench 31. The gate regions 43 are formed at intervals from the gate trenches 21 .

[0088] Each contact region 43 covers the first trench portion 34 of the corresponding source trench 31. Each contact region 43 is connected to the first trench portion 34 of the corresponding source trench 31. In this case, a semiconductor layer is interposed between the sidewall contact portion 39 of the source electrode 33 and the source region 42. Each contact region 43 further includes a first trench portion 31a of the corresponding source trench 31. 4, a gate electrode 34 is interposed between the sidewall contact portion 39 of the source electrode 33 and the body region 41. are.

[0089] As a result, each contact region 43 is connected to a source ground in the SiC semiconductor layer 2. In addition, each contact region 43 is connected to the source electrode 33, the boron The gate electrode 41 is electrically connected to the source region 42 .

[0090] The portion of each contact region 43 that covers the first trench portion 34 is the gate trench In each contact region 43, the first contact of the source trench 31 is drawn out toward the first contact region 21. The portion covering the trench portion 34 is a region on the first main surface 3 side with respect to the bottom of the body region 41. The portion of each contact region 43 that covers the first trench portion 34 is , may extend to the intermediate region between the gate trench 21 and the source trench 31.

[0091] Each contact region 43 further includes a second trench portion 35 of the corresponding source trench 31. Each contact region 43 covers the second trench of the corresponding source trench 31. The contact portion 35 faces the source electrode 33 with the source insulating layer 32 interposed therebetween. The contact region 43 also covers the bottom wall of the corresponding source trench 31. The source region 43 faces the source electrode 33 across the bottom wall of the corresponding source trench 31. The bottom of each contact region 43 is parallel to the bottom wall of the corresponding source trench 31. It may be formed.

[0092] The SiC semiconductor device 1 has a surface layer formed on the first main surface 3 in the active region 12. The deep well region 44 includes a plurality of p-type deep well regions 44. The p-type impurity concentration of each deep well region 44 is The peak value of the concentration of the p-type impurity in each of the deep regions 41 and 42 is less than the peak value of the concentration of the p-type impurity in the contact region 43. The peak value of the p-type impurity concentration in the well region 44 is the peak value of the p-type impurity concentration in the body region 41. The peak value of the p-type impurity concentration in the body region 41 may be equal to or greater than the peak value. The peak value of the p-type impurity concentration of each deep well region 44 is 1.0×10 17 c m -3 Over 1.0 x 10 19 cm -3 It may be the following:

[0093] The deep well regions 44 are arranged in one-to-one correspondence with the source trenches 31. Each deep well region 44 is formed in a corresponding source trench in plan view. Each deep well region 44 is formed in a strip shape extending along the trench 31. Each deep well region 44 is formed in the body region 41. Each deep well region 44 is formed in a region on the surface 4 side. are.

[0094] Each deep well region 44 covers the second trench portion 35 of the corresponding source trench 31. Each deep well region 44 includes a corresponding contact region 43 therebetween. The deep well region includes a portion covering the second trench portion 35 of the source trench 31. Each of the deep trenches 44 further includes a portion covering the bottom wall of the corresponding source trench 31. The well region 44 covers the bottom wall of the corresponding source trench 31 with the contact region 43 interposed therebetween. Includes the covering part.

[0095] Each deep well region 44 is located on the second main surface 4 side with respect to the bottom wall of the gate trench 21. The bottom of each deep well region 44 is aligned with the bottom of each source trench 31. The plurality of deep well regions 44 may be formed parallel to the wall. Each deep well region 44 is preferably formed between the high concentration region 10 and From this pn junction, depletion The depletion layer may overlap the bottom wall of the gate trench 21.

[0096] The SiC semiconductor device 1 has a plurality of p-type peripheral well regions formed in the surface layer of the first main surface 3 in the peripheral portion of the active region 12. (1st impurity region) The peak value of the p-type impurity concentration of each peripheral well region 45 is less than the peak value of the p-type impurity concentration of the contact region 43.

[0097] The peak value of the p-type impurity concentration of each peripheral well region 45 is the p-type impurity concentration of the body region 41. The p-type impurity concentration of the body region 41 may be equal to or greater than the peak value of the p-type impurity concentration of the body region 41. The peak value of the p-type impurity concentration of each peripheral well region 45 may be 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 The p-type of the peripheral well region 45 may be The impurity concentration is preferably approximately equal to the p-type impurity concentration of the deep well region 44 .

[0098] The peripheral well region 45 is formed in a one-to-one correspondence with the plurality of trench gate structures 18. The peripheral well regions 45 are formed as contacts for the corresponding trench gate structures 18. The peripheral well region 20 is covered, and the active trench region 19 is exposed. The region 45 is formed on the sidewall of the gate trench 21 and the corresponding contact trench portion 20. The bottom of the peripheral well region 45 covers the bottom wall of the deep well region 44. Each peripheral well region 45 is located on the first main surface 3 side. The semiconductor substrate 40 is electrically connected to the ground well region 44 .

[0099] In a SiC semiconductor device having only a pn junction diode, a trench is not provided. Due to this structure, there is little problem of electric field concentration in the SiC semiconductor layer 2. 44 brings the trench gate type MISFET closer to the structure of a pn junction diode. In the trench gate type MISFET, the electric field in the SiC semiconductor layer 2 is It can be alleviated.

[0100] Further, a deep well having a bottom on the second main surface 4 side with respect to the bottom wall of the gate trench 21 The region 44 provides a depletion layer that appropriately relieves the electric field concentration in the gate trench 21. The pins between the adjacent source trenches 31 (deep well regions 44) can be Narrowing the pitch PS is effective in alleviating electric field concentration and improving the breakdown voltage.

[0101] The deep well regions 44 are preferably formed to a uniform depth. As a result, the breakdown voltage (for example, breakdown resistance) of the SiC semiconductor layer 2 is increased by each deep well region 44. Since the restriction due to the peripheral well can be suppressed, the pressure resistance can be appropriately improved. The deep well region 45 also provides the same effect as the deep well region 44 .

[0102] By utilizing the source trench 31, a diffusion layer is formed in a relatively deep region of the SiC semiconductor layer 2. The deep well region 44 can be appropriately formed. Since the deep well regions 44 can be formed, the depths of the plurality of deep well regions 44 do not vary. This can appropriately suppress the

[0103] In this embodiment, a part of the high concentration region 10 is formed by a plurality of deep wells adjacent to each other. The deep wells 44 are interposed between the adjacent deep wells 44. In the region between the regions 44, the JFET (Junction Field Effect Transistor) resistance is reduced. It can be reduced.

[0104] In this embodiment, the bottom of each deep well region 44 is located in the high concentration region 10. As a result, in the region immediately below each deep well region 44 in the high concentration region 10, As a result, a current path can be formed in the lateral direction parallel to the first main surface 3. As a result, the current spreading resistance In such a structure, the low concentration region 11 can reduce the breakdown voltage of the SiC semiconductor layer 2. Increase.

[0105] Referring to FIG. 10, the active area 12 is an active main surface forming a part of the first main surface 3. The active principal surface 51 and the outer principal surface 52 are aligned with the c-plane of the SiC single crystal. The active principal surface 51 and the outer principal surface 52 are (00) of the SiC single crystal. 01) plane, each has an off-angle tilted in the [11-20] direction.

[0106] The outer region 13 has an outer major surface 52 that forms part of the first major surface 3. 2 is connected to the side surfaces 5A to 5D. The outer region 13 is connected to the drift region 8 (SiC epitaxial layer). It is formed by digging down the taxial layer 9) toward the second main surface 4. The outer main surface 52 is formed in a region recessed toward the second main surface 4 side with respect to the active main surface 51. The outer main surface 52 is located on the second main surface 4 side with respect to the bottom wall of the gate trench 21. It is preferable.

[0107] In this embodiment, the outer main surface 52 is located at a depth substantially equal to the bottom wall of each source trench 31. The outer main surface 52 is located on approximately the same plane as the bottom wall of each source trench 31. The outer main surface 52 is spaced apart from the bottom wall of each source trench 31 by 0 μm or more and 1 μm or less. The outer main surface 52 may be located on the second main surface 4 side within the range below. I'm making them release it.

[0108] In this embodiment, the active area 12 is an active area divided into plateaus by the outer area 13. The active plateau 53 extends upward from the outer main surface 52. The active plateau 53 connects the active principal surface 51 and the outer principal surface 52. The active sidewalls 54 are formed between the active area 12 and the outer area The first main surface 3 defines a boundary area between the active main surface 51 and the outer main surface 5 2 and active sidewall 54.

[0109] In this embodiment, the active sidewall 54 is formed in a direction normal to the active principal surface 51 (outer principal surface 52). The active sidewall 54 extends along the Z direction. The active sidewall 54 is formed by the m-plane and the a-plane of the SiC single crystal. The active sidewall 54 is formed from the active main surface 51 toward the outer main surface 52. The active sidewall 54 may have a downwardly sloping surface. The active sidewalls 54 may expose the body region 41.

[0110] The SiC semiconductor device 1 has a p + Type diode region 5 The peak value of the p-type impurity concentration in the diode region 55 is the p-type impurity concentration in the body region 41. The peak value of the p-type impurity concentration in the diode region 55 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The following may be used: The peak value of the p-type impurity concentration in the contact region 55 is higher than the peak value of the p-type impurity concentration in the contact region 43. It may be approximately equal to the value.

[0111] The diode region 55 is formed in the high concentration region 10. The diode region 5 is formed in the region between the active sidewall 54 and the side surfaces 5A to 5D. 5 is formed at a distance from the active sidewall 54 and the side surfaces 5A to 5D. The die region 55 extends in a strip shape along the active region 12 in a plan view. In this embodiment, the electrode region 55 is an annular ( More specifically, it is formed in an endless shape.

[0112] The diode region 55 is located on the second main surface 4 side with respect to the bottom wall of the gate trench 21. The bottom of the diode region 55 is located on the second main surface 4 side with respect to the bottom wall of each source trench 31. The bottom of the diode region 55 is located at a depth approximately equal to the bottom of the contact region 43. The insulating film 11 may be formed at a position closer to the insulating film 11 than the insulating film 11 .

[0113] The bottom of the diode region 55 is located on approximately the same plane as the bottom of the contact region 43. The bottom of the diode region 55 is closer to the second main surface than the bottom of the contact region 43. The bottom of the diode region 55 may be located on the bottom of the contact region 43. In contrast, it may be located on the second main surface 4 side within a range of 0 μm or more and 1 μm or less.

[0114] The diode region 55 forms a pn junction with the high concentration region 10. The diode region 55 serves as the anode and the high concentration region 10 serves as the cathode, forming a pn junction diode. An ode is formed.

[0115] The SiC semiconductor device 1 has a p-type outer well region 56 formed in the surface layer of the outer principal surface 52. The peak value of the p-type impurity concentration in the outer well region 56 is 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 The p-type impurity concentration of the outer well region 56 may be The peak value of the concentration may be less than the peak value of the p-type impurity concentration of the diode region 55. The peak value of the p-type impurity concentration in the outer well region 56 is greater than the p-type impurity concentration in the deep well region 44. It may be approximately equal to the peak value of the concentration of the substance.

[0116] The outer well region 56 is formed by the active sidewall 54 and the diode region 55 in a plan view. The outer well region 56 is formed in the region between the active region 1 and the 2. In this embodiment, the outer well region 56 is The conductive layer 14 is formed in a ring shape (more specifically, endless shape) surrounding the active region 12 .

[0117] The outer well region 56 is formed in the high concentration region 10. The outer well region 56 is The bottom of the outer well region 56 is located on the second main surface 4 side with respect to the bottom wall of the outer well trench 21. The outer well region is located on the second main surface 4 side of the bottom wall of each source trench 31. The bottom of the region 56 is located on the second main surface 4 side relative to the bottom of the diode region 55. The bottom of the well region 56 is formed at a depth substantially equal to the bottom of the deep well region 44. It may also be used.

[0118] The inner periphery of the outer well region 56 is at a corner connecting the active sidewall 54 and the outer major surface 52. The inner periphery of the outer well region 56 is further formed along the active sidewall 54. The inner periphery of the outer well region 56 is connected to the body region 41. The insulating film 54 may be formed at an interval from the sidewall 54 toward the diode region 55 .

[0119] The outer periphery of the outer well region 56 covers the diode region 55 from the second main surface 4 side. The outer well region 56 is electrically connected to the diode region 55. The outer well region 56 may form part of a pn junction diode. The edge may be spaced apart from the diode region 55 toward the active sidewall 54. stomach.

[0120] The SiC semiconductor device 1 has a field limiting structure 57 (FL structure) formed on the surface layer of the outer main surface 52. The FL structure 57 includes a diode region 55 and a side surface In this embodiment, the FL structure 57 is formed in the region between the side surfaces 5A to 5D. The FL structure 57 is formed at an interval from the diode region 55 side. It is formed in a concentration region 10.

[0121] The FL structure 57 includes one or more (for example, 2 to 20) p-type FL regions 5 8 (field limit region). In this embodiment, the FL structure 57 includes five FL regions 58 FL regions 58A to 58E. E are formed in this order at intervals along the direction away from the diode region 55. .

[0122] The FL regions 58A to 58E are arranged in a strip shape along the periphery of the active region 12 in a plan view. Specifically, the FL regions 58A to 58E are active regions in a plan view. The FL region is formed in an annular shape (more specifically, endless shape) surrounding the FL region 12. 58A to 58E are also referred to as FLR regions (field limiting ring regions). .

[0123] The entire FL regions 58A to 58E are located on the second main surface 4 side with respect to the bottom wall of the gate trench 21. The bottoms of the FL regions 58A to 58E are located at the third position with respect to the bottom of the diode region 55. The bottoms of the FL regions 58A to 58E are located on the main surface 4 side. The FL region 58A is located on the second main surface 4 side of the wall. The region 58A covers the diode region 55 from the second main surface 4 side. Region 58A is electrically connected to diode region 55. FL region 58A is a pn It may form part of a junction diode.

[0124] The FL structure 57 relieves the electric field concentration in the outer region 13. The depth, p-type impurity concentration, etc. can take various values ​​depending on the electric field to be relaxed. 7 is formed in the region between the active sidewall 54 and the diode region 55 in a plan view. The FL region 58 may include one or more FL regions 58.

[0125] The SiC semiconductor device 1 includes an outer insulating layer 61 that covers the outer principal surface 52. The outer insulating layer 61 may comprise silicon oxide. The outer insulating layer 61 may comprise other insulating materials such as silicon nitride. In this embodiment, the outer insulating layer 61 may have the same insulating properties as the gate insulating layer 22. It is formed by edge material species.

[0126] The outer insulating layer 61 is formed in a film shape along the active sidewall 54 and the outer main surface 52. The outer insulating layer 61 is formed on the active main surface 51 so as to cover the gate insulating layer 22 (third region The outer insulating layer 61 is continuous with the diode region 55 in the outer region 13. It covers the outer well region 56 and the FL structure 57 .

[0127] The peripheral edge of the outer insulating layer 61 is exposed from the side surfaces 5A to 5D. In this embodiment, the outer insulating layer 61 is continuous with the side surfaces 5A to 5D. In this case, the outer insulating layer 61 may be formed at a distance inward from the outer The main surface 52 is exposed.

[0128] The SiC semiconductor device 1 further includes a sidewall structure 62 covering the active sidewall 54. The sidewall structure 62 protects the active plateau 53 from the outer region 13 side. The sidewall structure 62 also reinforces the active principal surface 51 and the outer principal surface 52. A step reduction structure is formed to reduce the step formed therebetween.

[0129] An upper layer structure (covering layer) covering the boundary area between the active area 12 and the outer area 13 When formed, the upper layer structure covers the sidewall structure 62. The sidewall structure 62 enhances the flatness of the upper layer structure. The sidewall structure may have an inclined surface that slopes downward from the outer main surface 52. The inclined surface of the structure 62 can appropriately reduce the step.

[0130] The inclined surface of the sidewall structure 62 is curved and recessed toward the SiC semiconductor layer 2 side. The inclined surface of the sidewall structure 62 may be formed on the side opposite to the SiC semiconductor layer 2. The slope of the sidewall structure 62 may be curved toward the active It may extend in a plane from the inner main surface 51 side toward the outer main surface 52 side.

[0131] The sidewall structure 62 is formed along the active sidewall 54. In this embodiment, the hole structure 62 has an annular shape (or a circular shape) surrounding the active region 12 in a plan view. The sidewall structure 62 is formed of polysilicon (this In this case, the gate electrode 23 and the source The sidewall structure 62 can be formed simultaneously with the electrode 33 .

[0132] The SiC semiconductor device 1 includes an interlayer insulating layer 63 (insulating layer) formed on the first main surface 3. The interlayer insulating layer 63 may include silicon oxide or silicon nitride. 63 shows a USG (Undoped Silicate Glass) layer as an example of silicon oxide, a PSG (Ph of the BPSG (Boron Phosphor Silicate Glass) layer and the BPSG (Boron Phosphor Silicate Glass) layer. In this embodiment, the interlayer insulating layer 63 may include at least one of the first insulating layer 6 The first insulating layer 64 has a laminated structure including a USG layer and a second insulating layer 65. The second insulating layer 65 is made of a BPSG layer.

[0133] An interlayer insulating layer 63 covers the active area 12 and the outer area 13. The layer 63 is formed in a film shape along the active principal surface 51 and the outer principal surface 52. The insulating layer 63 is formed on the side in the boundary region between the active area 12 and the outer area 13. The interlayer insulating layer 63 is formed along the sidewall structure 62. It forms part of the upper structure covering the

[0134] The periphery of the interlayer insulating layer 63 is exposed from the side surfaces 5A to 5D. The periphery of the interlayer insulating layer 63 extends inward from the side surfaces 5A to 5D. In this case, the interlayer insulating layer 63 is formed on the outer main surface 52 (the outer The insulating layer 61) is exposed.

[0135] The interlayer insulating layer 63 covers the source region 42 in the active region 12. The insulating layer 63 further covers the contact region 43. Specifically, the interlayer insulating layer 63 is The interlayer insulating film 41 covers the entire area of ​​the source region 42 in a cross-sectional view along the second direction Y. The layer 63 covers the entire source region 42 in plan view. The interlayer insulating layer 63 covers the entire contact region 43 in plan view. The entire contact region 43 is covered.

[0136] More specifically, the interlayer insulating layer 63 is formed between the source trench 3 in the active region 12. The interlayer insulating layer 63 covers the source electrode 33 across the first trench portion 34 of the first insulating layer 63. The sidewall contact portion 39 of the source electrode 33 is covered on the first main surface 3 .

[0137] The interlayer insulating layer 63 includes a gate hole 66, a source hole 67, and a diode hole 68. The gate hole 66 exposes the gate wiring 28 in the active region 12. The gate hole 66 may be formed in a strip shape along the gate wiring 28. is formed in a curved shape that points toward the inside of the gate hole 66.

[0138] The source hole 67 exposes the source electrode 33 in the active region 12. The source hole 67 may be formed in a strip shape extending along the trench source structure 30. The opening edge of the source hole 67 is curved toward the inside of the source hole 67 .

[0139] Specifically, the source hole 67 is formed by the source trench 31 (first trench portion 3 The source hole 67 is formed in a region surrounded by the sidewalls of the source trench 4). The source trench 31 is spaced apart from the sidewall of the first trench portion 34 toward the inside of the source trench 31. The source electrode 33 is exposed through the source hole 67. .

[0140] The electrode surface of the source electrode 33 has a recess 69 recessed toward the bottom wall of the source trench 31. The recess 69 is formed in a strip shape extending along the trench source structure 30. The recess 69 may be formed in the source trench 31 (first trench portion 31) in a plan view. 4) is formed within the area surrounded by the sidewalls.

[0141] The recess 69 extends from the sidewall of the source trench 31 (first trench portion 34) to the source trench 31. The recess 69 is formed inward of the second low resistance layer 40 with a gap therebetween. The recess 69 may penetrate the second low-resistance layer 40. The source hole 67 is The recess 69 of the electrode 33 is in communication with the recess 69 .

[0142] The diode hole 68 exposes the diode region 55 in the outer region 13. The diode hole 68 is formed in a strip shape (specifically, endless) extending along the diode region 55. The diode hole 68 may be formed in the outer well region 56 and / or the FL structure 5 The opening edge of the diode hole 68 may be exposed. It is formed in a curved shape.

[0143] The SiC semiconductor device 1 includes a gate electrode 71 formed on the first main surface 3. Specifically, the gate electrode 71 is formed on the interlayer insulating layer 63. A gate voltage is applied to 71. The gate voltage is 10V or more and 50V or less (for example, 3 0V).

[0144] The gate electrode 71 is formed in the active region 12. , a gate pad 72 and a gate finger 73. The gate pad 72 has a The gate pad 72 is formed in the area on the first side surface 5A side. The gate pad 72 is formed along a region along the center of the first side surface 5A. is formed in a region along a corner connecting any two of the side surfaces 5A to 5D in a plan view. The gate pad 72 may be formed in a quadrangular shape in plan view. stomach.

[0145] The gate finger 73 is led out from the gate pad 72 and extends through the active area 1 In this embodiment, the gate finger 73 extends in a strip shape along the periphery of the first side surface 2. 5A, the third side surface 5C and the fourth side surface 5D, and surrounds the active area 12 from three sides. It is divided from both sides.

[0146] The gate finger 73 has a pair of open ends 74, 75. 75 is formed in an area facing the gate pad 72 across the inside of the active area 12. In this embodiment, the pair of open ends 74, 75 are aligned along the second side surface 5B in a plan view. are formed in the area.

[0147] The gate finger 73 extends from above the interlayer insulating layer 63 into the gate hole 66. The gate finger 73 is connected to the gate wiring 28 within the gate hole 66. As a result, an electrical signal from the gate pad 72 is transmitted to the gate electrode via the gate finger 73. 23 and the gate wiring 28.

[0148] The gate electrode 71 contains a conductive material different from that of the gate electrode 23 (gate wiring 28). Specifically, the gate electrode 71 is made of a metal material. The gate electrode 23 (gate electrode 71) made of conductive polysilicon is It is electrically connected to wiring 28).

[0149] The gate electrode 71 is formed by stacking a first barrier layer 76 in this order from the SiC semiconductor layer 2 side. and a first main body layer 77. The first barrier layer 76 has a laminated structure including a Ti layer and The first barrier layer 76 preferably includes at least one of a SiC semiconductor and a TiN layer. The layer structure includes a Ti layer and a TiN layer laminated in this order from the conductor layer 2 side. The first barrier layer 76 preferably has a single layer structure made of a Ti layer or a TiN layer. That's fine.

[0150] The thickness of the first barrier layer 76 may be 0.01 μm or more and 6 μm or less. The thickness of the layer 76 is 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 2 μm or less, 2 μm or less It may be from 4 μm to 4 μm, or from 4 μm to 6 μm.

[0151] The first main body layer 77 has a resistance value less than the resistance value of the first barrier layer 76. 77 is a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer. The thickness of the first body layer 77 exceeds the thickness of the first barrier layer 76. The thickness of the first main layer 77 may be 0.05 μm or more and 10 μm or less. The thickness of 77 is 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 1 μm or less, 1 μm or less Upper 2μm or less, 2μm or more and 4μm or less, 4μm or more and 6μm or less, 6μm or more and 8μm or less, Alternatively, it may be 8 μm or more and 10 μm or less.

[0152] The SiC semiconductor device 1 is formed on the first main surface 3 at a distance from the gate main surface electrode 71. The source electrode 81 is specifically formed on the interlayer insulating layer 63. A source voltage is applied to the source main surface electrode 81. The source voltage is , may be a reference voltage (for example, a GND voltage).

[0153] The source main surface electrode 81 is formed in the active region 12 and the outer region 13. The source main surface electrode 81 includes a source pad 82, a source wiring 83, and a source connection portion 84. The source pad 82 is formed in the active region 12 at a distance from the gate main surface electrode 71. The source pad 82 is a C-shaped region defined by the gate electrode 71. It is formed in a C-shape in plan view so as to cover the entire area.

[0154] The source pad 82 includes a source connection electrode 85 and a source covering electrode 86. The source connection electrode 85 is buried in the source hole 67. The source connection electrode 85 is connected to the source electrode 33 in the source hole 67. It is connected only to the source electrode 33 .

[0155] The source covering electrode 86 covers the interlayer insulating layer 63 in the region outside the source hole 67. In this embodiment, the source covering electrode 86 is integrally formed with the source connecting electrode 85. As a result, the source pad 82 is connected to the body region 41 and the source electrode 33 via the source electrode 33. It is electrically connected to region 42 and contact region 43 .

[0156] The source wiring 83 is formed in the outer region 13. The source wiring 83 is formed in the active region The source wiring 83 extends in a strip shape along the active region 12 in a plan view. The source wiring 83 is formed in a ring shape (more specifically, endless shape) surrounding the source wiring 83. The source wiring 83 penetrates into the diode hole 68 from above the edge layer 63. In 68, it is electrically connected to the diode region 55.

[0157] The source connector 84 connects the source pad 82 and the source wiring 83. The connection 84 extends from the source pad 82 across the open ends 74, 75 of the gate fingers 73. , and is connected to the source wiring 83. The source connection portion 84 is connected to the active region 12. The source connection portion 84 is extended across the side wall structure 62 to the outer region 13. It forms part of an upper structure that covers the sidewall structure 62 .

[0158] The source principal surface electrode 81 includes a conductive material different from that of the source electrode 33. Specifically, the source 1 is made of a metal material. The principal surface electrode 81 is electrically connected to the source electrode 33 made of conductive polysilicon.

[0159] The source main surface electrode 81 is formed by stacking a second barrier layer 87 in this order from the SiC semiconductor layer 2 side. and a second main body layer 88. The second barrier layer 87 has a laminated structure including a Ti layer and The second barrier layer 87 preferably includes at least one of a SiC semiconductor and a TiN layer. The layer structure includes a Ti layer and a TiN layer laminated in this order from the conductor layer 2 side. The second barrier layer 87 preferably has a single layer structure made of a Ti layer or a TiN layer. That's fine.

[0160] The thickness of the second barrier layer 87 may be 0.01 μm or more and 6 μm or less. The thickness of the layer 87 is 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 2 μm or less, 2 μm It may be from 4 μm to 4 μm, or from 4 μm to 6 μm.

[0161] The second body layer 88 has a resistance value less than the resistance value of the second barrier layer 87. 88 is a layer of pure Al, AlSi alloy, AlCu alloy and AlSiCu alloy. The thickness of the second body layer 88 exceeds the thickness of the second barrier layer 87. The thickness of the second body layer 88 may be 0.05 μm or more and 10 μm or less. The thickness of 88 is 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 1 μm or less, 1 μm or less Upper 2μm or less, 2μm or more and 4μm or less, 4μm or more and 6μm or less, 6μm or more and 8μm or less, Alternatively, it may be 8 μm or more and 10 μm or less.

[0162] The MISFET formed in the active region 12 has an npn-type parasitic transistor due to its structure. The avalanche current generated in the outer region 13 flows into the active region 12. In this case, the parasitic transistor is turned on. Therefore, in the SiC semiconductor device 1, the structure of the source main surface electrode 81 is This is used to form an avalanche current absorption structure.

[0163] The avalanche current generated in the outer region 13 flows through the diode region 55 to the source wiring 8 The avalanche current absorbed by the source wiring 83 is absorbed by the source The source pad 82 is connected to the connecting portion 84 by a bonding wire or the like. If the conductor is electrically connected, the avalanche current will reach the outside through the conductor. This makes it possible to suppress the driving of the parasitic transistor caused by the avalanche current. Since latch-up can be suppressed, the stability of the MISFET can be improved.

[0164] The SiC semiconductor device 1 includes an insulating layer 91 formed on the interlayer insulating layer 63. In FIG. The insulating layer 91 is shown by hatching. The periphery of the insulating layer 91 is As a result, the insulating layer 91 is formed inwardly from the The periphery of the iC semiconductor layer 2 (specifically, the interlayer insulating layer 63) is exposed.

[0165] The periphery of the insulating layer 91 defines a dicing street DS between the side surfaces 5A to 5D. According to Dicing Street DS, the SiC semiconductor device 1 is cut out from the SiC wafer. This eliminates the need to physically cut the insulating layer 91 when cutting the SiC semiconductor from the SiC wafer. The body device 1 can be smoothly cut out, and at the same time, peeling and deterioration of the insulating layer 91 can be suppressed. As a result, the insulating layer 91 isolates the SiC semiconductor layer 2, the gate electrode 71, and the source electrode 72 from each other. This allows for proper protection of objects to be protected, such as the pole 81.

[0166] The width of the dicing street DS may be 1 μm or more and 25 μm or less. The width of the dicing street DS is the width in the direction perpendicular to the direction in which the dicing street DS extends. The width of the dicing street DS is 1 μm or more and 5 μm or less, and 5 μm or more and 10 μm or less. Below, 10 μm to 15 μm, 15 μm to 20 μm, or 20 μm to 25 It may be less than μm.

[0167] The insulating layer 91 selectively covers the gate electrode 71 and the source electrode 81. The insulating layer 91 includes a gate pad opening 92 and a source pad opening 93. The gate pad opening 92 exposes the gate pad 72. The source pad opening 93 exposes the source pad 72. The gate pad opening 92 may have any planar shape. The planar shape of the head opening 93 is arbitrary.

[0168] In this embodiment, the insulating layer 91 is a passivation layer laminated in this order from the SiC semiconductor layer 2 side. The passivation layer 94 has a laminated structure including a passivation layer 94 and a resin layer 95. The insulating layer may include at least one of a silicon oxide layer and a silicon nitride layer. The passivation layer 94 is a layer of silicon oxide and silicon nitride stacked in any order. The passivation layer 94 may have a laminated structure. The passivation layer 94 may have a single layer structure consisting of an interlayer insulating layer. Preferably, the passivation layer 94 comprises a different insulating material than the insulating material 63. has a single layer structure made of a silicon nitride layer.

[0169] The passivation layer 94 is formed in a film shape along the interlayer insulating layer 63. The insulation layer 94 covers the active region 12 and the outer region 13 with the interlayer insulating layer 63 sandwiched therebetween. The passivation layer 94 covers the sidewall structure 6 from the active region 12. 2 and is extended to the outer region 13. The passivation layer 94 is It forms part of the upper structure that covers the roof structure 62.

[0170] The passivation layer 94 has a first gate opening 96 and a first source opening 97. The first gate opening 96 exposes the gate pad 72. The first source opening 97 , exposing the source pad 82. The first gate opening 96 may have any planar shape. The first source opening 97 may have any planar shape.

[0171] The thickness of the passivation layer 94 may be 0.1 μm or more and 20 μm or less. The thickness of the saturation layer 94 is 0.1 μm or more and 1 μm or less, 1 μm or more and 5 μm or less, 5 μm or more and 5 μm or less. m or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less It's okay to have it.

[0172] The resin layer 95 may contain a photosensitive resin. The photosensitive resin may be a negative type or The resin layer 95 may be of a positive type. The resin layer 95 may contain at least one of the following compounds: In some embodiments, the polymer comprises polybenzoxazole.

[0173] The resin layer 95 is formed in a film shape along the main surface of the passivation layer 94. 95 extends from the active region 12 across the sidewall structure 62 to the outer region 13. The resin layer 95 forms part of the upper layer structure that covers the sidewall structure 62. In this embodiment, the periphery of the resin layer 95 exposes the periphery of the passivation layer 94. The periphery of the insulating layer 91 is aligned with the periphery of the resin layer 95 and the periphery of the passivation layer 94. The resin layer 95 covers the periphery of the passivation layer 94. Good too.

[0174] The resin layer 95 has a second gate opening 98 and a second source opening 99. The gate opening 98 communicates with the first gate opening 96 in the passivation layer 94 , and the first gate opening 96 forms a gate pad opening 92. The second source opening 99 is formed by The source pad 94 is connected to the first source opening 97 of the connection layer 94. An opening 93 is formed.

[0175] The inner wall of the second gate opening 98 may be formed flush with the inner wall of the first gate opening 96. The inner wall of the second gate opening 98 is located outside the first gate opening 96 in a plan view. The inner wall of the second gate opening 98 is located within the first gate opening 96 in a plan view. In other words, the resin layer 95 may cover the inner wall of the first gate opening 96.

[0176] The inner wall of the second source opening 99 may be formed flush with the inner wall of the first source opening 97. The inner wall of the second source opening 99 is located outside the first source opening 97 in a plan view. The inner wall of the second source opening 99 is located within the first source opening 97 in a plan view. In other words, the resin layer 95 may cover the inner wall of the first source opening 97.

[0177] The thickness of the resin layer 95 may be 1 μm or more and 50 μm or less. 1μm or more and 10μm or less, 10μm or more and 20μm or less, 20μm or more and 30μm or less, 30 It may be 40 μm or more and 40 μm or less, or 50 μm or more and 40 μm or less.

[0178] The SiC semiconductor device 1 has an uneven structure 101 (Uneven Structure Specifically, the concave-convex structure 101 includes an interlayer insulating layer 63 that covers the outer main surface 52. The uneven structure 101 includes unevenness formed by using a layer. The interlayer insulating layer 63 includes an anchor hole 102 formed therein.

[0179] The anchor hole 102 is formed by digging down a portion of the interlayer insulating layer 63 that covers the outer region 13. The anchor hole 102 is formed by arranging the diode region 5 in a plan view. The anchor holes 102 may be formed in the area between the side surfaces 5A to 5D. In the embodiment, the FL structure 57 is formed in the region between the side surfaces 5A to 5D in a plan view. do.

[0180] The anchor holes 102 may be partitioned by an interlayer insulating layer 63. In this embodiment, the outer major surface 52 of the base 2 is exposed. The anchor holes 102 are formed on the outer major surface 52 of the base 2. The opening edge of the anchor hole 102 may be dug down toward the second main surface 4. It is formed in a curved shape that points toward the inside of the anchor hole 102.

[0181] The anchor holes 102 extend in a strip shape along the active region 12 in a plan view. In this embodiment, the anchor holes 102 are annular in shape surrounding the active area 12 in a plan view. (More specifically, endless) The number of anchor holes 102 is arbitrary. The anchor hole 102 may be formed in the interlayer insulating layer 63, or a plurality of anchor holes 10 2 may be formed on the interlayer insulating layer 63.

[0182] The resin layer 95 has an anchor portion 103 that engages with the anchor hole 102. In this configuration, the anchor hole 102 is mated with the passivation layer 94 . Specifically, the passivation layer 94 is formed by inserting the insulating interlayer 63 into the anchor hole 102. The passivation layer 94 is embedded in the anchor holes 102 on the outer major surface 52. The portion of the main surface of the passivation layer 94 that covers the anchor hole 102 is in contact with the A recess 104 recessed toward the anchor hole 102 is formed.

[0183] A portion of the resin layer 95 is formed in the recess 104 of the passivation layer 94 to form the anchor portion 105. This increases the connection strength of the resin layer 95 to the first main surface 3. Therefore, peeling of the resin layer 95 can be appropriately suppressed.

[0184] The SiC semiconductor device 1 has a drain electrode formed on the second main surface 4 of the SiC semiconductor layer 2. The drain electrode 105 is electrically connected to the drain region 6. The inner electrode 105 is made of at least one of a Ti layer, a Ni layer, a Pd layer, a Au layer, an Ag layer, and an Al layer. The drain electrode 105 forms an ohmic contact with the second main surface 4. It is preferable that the Ti layer is included.

[0185] The drain electrode 105 is made of at least a Ti layer, a Ni layer, and a The drain electrode 105 preferably has a laminated structure including a first layer and a second layer. 2. A laminated structure including a Ti layer, a Ni layer, a Au layer, and an Ag layer laminated in this order from the main surface 4 side. It is more preferable that the Pd layer is interposed between the Ni layer and the Au layer. The Al layer may be disposed in any layer in the laminated structure.

[0186] As described above, the SiC semiconductor device 1 has the sidewall contact portion 39 exposed from the sidewall window portion 36. The source region 42 includes a source electrode 33 formed in the SiC semiconductor layer 2. The sidewall contact portion 39 of the source electrode 33 is electrically connected to the sidewall contact portion 39. This allows the source region 42 to be properly grounded within the SiC semiconductor layer 2. It can be done.

[0187] Furthermore, according to the SiC semiconductor device 1, the body region 41 is formed in the SiC semiconductor layer 2. The sidewall contact portion 39 of the source electrode 33 exposed from the sidewall of the source trench 31 is electrically connected to the This allows the body region 41 to be properly connected within the SiC semiconductor layer 2. The source can be grounded.

[0188] Furthermore, according to the SiC semiconductor device 1, the body region 41 and the The contact region 43 is interposed between the sidewall contact portion 39 and the contact region 43. The source electrode 33 is exposed from the sidewall of the source trench 31 in the SiC semiconductor layer 2. The contact region 43 is electrically connected to the sidewall contact portion 39. Therefore, the source can be appropriately grounded in the SiC semiconductor layer 2.

[0189] Furthermore, according to the SiC semiconductor device 1, the source region 42 is formed in the SiC semiconductor layer 2. Since the source is grounded, the interlayer insulating layer covering the source region 42 on the first main surface 3 In addition, an interlayer insulating layer 63 can be formed to cover the entire area of ​​the source region 42 in a cross-sectional view. In addition, the interlayer insulating layer 63 that covers the entire source region 42 in plan view can be formed. Furthermore, a sidewall contact portion 3 of the source electrode 33 can be formed on the first main surface 3. An interlayer insulating layer 63 can be formed to cover the semiconductor device 9 .

[0190] Furthermore, according to the SiC semiconductor device 1, the source region 42 is formed in the SiC semiconductor layer 2. Since the source is grounded, the opening width of the source hole 67 that exposes the source electrode 33 can be narrowed. This allows the alignment margin of the source hole 67 to be widened. That is, it is possible to provide a SiC semiconductor device 1 that is resistant to misalignment of the source holes 67.

[0191] Furthermore, according to the SiC semiconductor device 1, the source hole 67 that exposes only the source electrode 33 is formed. At the same time, the source connection electrode 85 connected only to the source electrode 33 can be formed. As a result, the source region 42 can be properly grounded, and at the same time, the source Fluctuations in electrical characteristics caused by misalignment of the connection electrode 85 (source hole 67) can be appropriately suppressed. .

[0192] The source electrode 33 is preferably made of a conductive material other than a metal material. It is particularly preferable that the source main surface electrode 81 is made of conductive polysilicon. The source main surface electrode 81 is preferably made of a conductive material different from that of the electrode 33. It is particularly preferable that the composition is:

[0193] According to this structure, the source electrode 33 can be appropriately buried in the source trench 31. At the same time, the source main surface electrode 81 can be properly connected to the source electrode 33. In such a structure, the opening width of the source trench 31 is the same as the opening width of the gate trench 21. and the source trench 31 exceeds the first depth D1 of the gate trench 21. This is particularly effective when the depth D2 is 2.

[0194] The source trench 31 may be filled with a metal material. The depth of the trench 31 is limited, and at the same time, the opening width of the gate trench 21 is increased. Therefore, it is necessary to form the source trench 31 having an opening width that is much larger than the SiC It should be noted that this is contrary to the demand for high breakdown voltage and miniaturization of the semiconductor device 1. The conductor device 1 can solve this problem.

[0195] 11A to 11S are enlarged cross-sectional views showing an example of a method for manufacturing the SiC semiconductor device 1 shown in FIG. 11A to 11S are enlarged views of the area corresponding to FIG.

[0196] First, referring to FIG. 11A, the n-type GaN layer that becomes the base of the drain region 6 (SiC semiconductor substrate 7) + Next, a mold SiC wafer 111 is prepared. The SiC epitaxial layer 112 is the base of the soft region 8 (SiC epitaxial layer 9). The SiC epitaxial layer 112 is formed by epitaxial growth of SiC. It is formed on the main surface of the wafer 111 .

[0197] In this step, the doping amount of n-type impurities is adjusted to form the high concentration region 10 and the low concentration region 11. The SiC epitaxial layer 112 having the concentration region 11 is formed. The SiC semiconductor layer 2 is formed, including the gate region 6 and the drift region 8. The description will be given using the body layer 2, the first main surface 3 and the second main surface 4.

[0198] Next, referring to FIG. 11B, a p-type body region 41 is formed in the surface layer portion of first main surface 3. The body region 41 is formed over the entire surface layer of the first main surface 3. The body region 41 is formed by introducing p-type impurities into the main surface 3. n + The source region 42 is formed in the surface layer of the body region 41. The source region 42 is formed in the region where the channel of the MISFET is to be formed. It is formed by introducing n-type impurities into the surface layer of the region 41 .

[0199] Next, referring to FIG. 11C, a hard mask 1 having a predetermined pattern is formed on the first main surface 3. The hard mask 113 is formed on the first main surface 3 so as to cover the gate trench 21 and the silicon dioxide film 13. A plurality of openings 114 are formed to expose the area where the trench 31 and the outer region 13 are to be formed. The hard mask 113 may include silicon oxide. 13 is formed by CVD (chemical vapor deposition) or thermal oxidation. In this step, the hard mask 113 is formed by a thermal oxidation process.

[0200] Next, the SiC epitaxial layer 1 is formed by etching through the hard mask 113. The unnecessary portion of 12 is removed. The etching method may be a wet etching method and / or The etching method may be a dry etching method. This is preferable. A trench 31 is formed. In addition, an outer recessed portion on the second main surface 4 side with respect to the active region 12 Region 13 is formed. Hard mask 113 is then removed.

[0201] Next, referring to FIG. 11D, a mask 115 having a predetermined pattern is placed on the first main surface 3. The mask 115 is formed by a plurality of masks that expose the source trench 31 and the outer region 13. The mask 115 has an opening 116. In this step, the mask 115 is formed by a polysilicon layer 117 and a and an insulating layer 118. The insulating layer 118 contains silicon oxide. The silicon layer 117 may be formed by a CVD method. The insulating layer 118 may be formed by a CVD method. Alternatively, the insulating layer 118 may be formed by a thermal oxidation process. It is formed by thermal oxidation treatment of silicon layer 117 .

[0202] Next, the SiC epitaxial layer 112 is etched using a mask 115. The unwanted parts are removed. The etching method can be wet etching and / or dry etching. The etching method may be an etching method. The etching method is preferably a dry etching method. As a result, the source trench 31 and the outer region 13 are further extended toward the second main surface 4. Can be dug up.

[0203] Next, referring to FIG. 11E, the deep well region 44, the peripheral well region 45 and the outer A well region 56 is formed in the surface layer portion of the first main surface 3. The well region 45 and the outer well region 56 are formed by introducing p-type impurities into the first main surface 3. P-type impurities are introduced into the outer major surface 52 through an ion implantation mask. The type impurities are introduced into the outer major surface 52 through the mask 115 in addition to the ion implantation mask. Good too.

[0204] Next, a plurality of FL regions 58 (FL structures 57) are formed on the surface layer portion of the first main surface 3 (outer main surface 52). The plurality of FL regions 58 (FL structures 57) are formed on the first main surface 3 by p-type impurity doping. The p-type impurity is introduced into the outer major surface 52 through an ion implantation mask. It will be entered.

[0205] Next, referring to FIG. 11F, the contact region 43 and the diode region 55 are The contact region 43 and the diode region 55 are formed on the surface of the first main surface 3. The p-type impurities are introduced into the GaN layer 3 through an ion implantation mask. and introduced into the first main surface 3 .

[0206] Next, referring to FIG. 11G, the gate insulating layer 22, the source insulating layer 32 and the outer insulating layer 6 An insulating base layer 119 serving as the base of the semiconductor device 1 is formed on the first main surface 3. 19 may contain silicon oxide.

[0207] The base insulating layer 119 may be formed by a CVD method or a thermal oxidation method. The portion of the source insulating layer 119 covering the sidewall of the gate trench 21 and the portion of the source trench 22 The portion covering the side wall of the insulating base layer 31 is formed thinner than the other portion. 9, the portion covering the opening edge of the gate trench 21 and the source trench 31 The portion covering the opening edge portion is formed thicker than the other portions.

[0208] The insulating base layer 119 having such a structure can be formed by adjusting the conditions of the CVD method or the thermal oxidation treatment method. For example, in the CVD method or thermal oxidation method, the gas flow rate, This can be achieved by adjusting predetermined conditions such as the type of gas, the gas ratio, the gas supply time, and the temperature.

[0209] Next, referring to FIG. 11H, the gate electrode 23, the gate wiring 28 and the source electrode 33 A first polysilicon layer 120 serving as a base is formed on the first main surface 3. The gate trench 21 and the source trench 31 are filled with the silicon layer 120, and the silicon layer 120 covers the first main surface 3. Overturn.

[0210] The first polysilicon layer 120 may be formed by a CVD method. The first polysilicon layer 120 may be formed by a p-type impurity CVD (Low Pressure CVD) method. It is made of conductive polysilicon that is given conductivity by impurities. P-type impurities are added by the CVD method. It may be added to the first polysilicon layer 120 at the same time as the CVD method, or may be added separately after the CVD method. That's fine.

[0211] Next, referring to FIG. 11I, unnecessary portions of the first polysilicon layer 120 are removed. 1. Unwanted portions of polysilicon layer 120 are removed until base insulating layer 119 is exposed. The unnecessary portions of the first polysilicon layer 120 may be removed by an etching method. The etching method may be a wet etching method and / or a dry etching method. As a result, the gate electrode 23, the gate wiring 28, and the source electrode 33 are formed.

[0212] In this step, a part of the first polysilicon layer 120 adheres to the active sidewall 54. As a result, a sidewall structure including a part of the first polysilicon layer 120 is formed. The sidewall structure 62 is formed in a self-aligned manner with respect to the active main surface 51. is formed.

[0213] Next, referring to FIG. 11J, a resist mask 121 having a predetermined pattern is applied to the first main surface. The resist mask 121 is formed on the source trench 31 and the source region 42. It has an opening 122 that exposes a part of the contact region 43 and covers the other regions. are.

[0214] Next, the unnecessary portion of the source insulating layer 32 and the unnecessary portion of the source electrode 33 are removed by a resist The SiC epitaxial layer is then removed by etching through the mask 121. A portion of the shear layer 112 is also removed. This removes the first trench portion 34 and the second trench portion 35. A source trench 31 having a trench portion 35 is formed in the source insulating layer 32. A sidewall window 36 is formed to expose the first trench portion 34 of the trench 31. The block 121 is then removed.

[0215] Next, referring to FIG. 11K, a second polysilicon layer 123 which will be the base of the source electrode 33 is formed. is formed on the first main surface 3. The second polysilicon layer 123 is formed on the first main surface 3. The first trench portion 34 is filled and the first main surface 3 is covered.

[0216] The second polysilicon layer 123 may be formed by a CVD method. The second polysilicon layer 123 may be formed by a p-type impurity CVD (Low Pressure CVD) method. It is made of conductive polysilicon that is given conductivity by impurities. P-type impurities are added by the CVD method. It may be added to the second polysilicon layer 123 at the same time as the CVD method, or may be added separately after the CVD method. That's fine.

[0217] Next, referring to FIG. 11L, unnecessary portions of the second polysilicon layer 123 are removed. The unnecessary portions of the second polysilicon layer 123 are removed until the first main surface 3 is exposed. Unwanted portions of the silicon layer 123 may be removed by etching. The etching method may be a wet etching method and / or a dry etching method. Thus, the source electrode 33 is formed again.

[0218] In this step, a part of the second polysilicon layer 123 is attached to the active sidewall 54. As a result, a sidewall structure including a part of the second polysilicon layer 123 is formed. The sidewall structure 62 is formed in a self-aligned manner with respect to the active main surface 51. is formed.

[0219] Next, referring to FIG. 11M, the gate electrode 23, the gate wiring 28 and the source electrode 33 are An overlying metal layer 124 is formed on the first major surface 3. The metal layer 124 is made of p-type polysilicon. The metal layer 124 includes a metal material that can be polycide-formed between the metal layer 124 and the conductive layer 126. ... material includes a metal material that can be polycide-formed between the metal layer 124 and the conductive layer 126. The metal material includes a metal material that can be polycide-formed between the metal layer The metal layer 124 may include at least one of O and Ti. It may be formed by sputtering and / or evaporation.

[0220] Next, the metal layer 124 is subjected to a heat treatment to remove the surface layer of the gate electrode 23 and the gate wiring A p-type polycide layer is formed on the surface layer of the source electrode 33 and the surface layer of the silicon nitride film 28. The method may be a rapid thermal annealing (RTA) method. At least one of iSi2, NiSi, CoSi, CoSi2, MoSi2 and WSi2 A p-type polycide layer including at least one of the first and second low-resistance electrodes is formed. A resistance layer 29 and a second low resistance layer 40 are formed.

[0221] Next, referring to Figure 11N, the unreacted portions of the metal layer 124 are removed. The unreacted portion may be removed by an etching method. The etching method may be a wet etch. The method may be a chipping method and / or a dry etching method.

[0222] When the first low resistance layer 29 and the second low resistance layer 40 contain TiSi or CoSi, After removing the unreacted portion of the layer 124, the first low resistance layer 29 and the second low resistance layer 40 are subjected to a heat treatment. The heat treatment for the first low resistance layer 29 and the second low resistance layer 40 may be carried out again. The method may be an RTA method, by which TiSi is converted to TiSi2 and CoSi is converted to Co It can be modified to Si2.

[0223] Next, referring to FIG. 11O, an interlayer insulating layer 63 is formed on the first main surface 3. The edge layer 63 collectively covers the active area 12 and the outer area 13. 3 includes a first insulating layer 64 and a second insulating layer 65. The first insulating layer 64 is made of a USG layer. The second insulating layer 65 is made of a BPSG layer. The first insulating layer 64 and the second insulating layer 65 are It may be formed by a CVD method.

[0224] Next, referring to FIG. 11P, a resist mask 125 having a predetermined pattern is applied to the interlayer insulating film. The resist mask 125 is formed on the layer 63. The resist mask 125 defines the gate hole 66, the source hole 67, and the die hole 68. A plurality of openings 126 are formed to expose the areas where the hole 68 and anchor holes 102 are to be formed. It has.

[0225] Next, unnecessary portions of the interlayer insulating layer 63 are removed by etching through a resist mask 125. The etching method is a wet etching method and / or a dry etching method. The etching method may be a dry etching method. As a result, a gate hole 66, a source hole 67, a diode hole 68, and an anchor hole 102 are formed. It is done.

[0226] After this, a heat treatment may be performed on the interlayer insulating layer 63. As a result, the gate hole the opening edge of the source hole 67; the opening edge of the diode hole 68; The opening edge of the anchor hole 102 is rounded.

[0227] Next, referring to FIG. 11Q, a layer that serves as a base for the first barrier layer 76 and the second barrier layer 87 is formed. A base barrier layer 127 is formed on the interlayer insulating layer 63. The base barrier layer 127 has: It has a laminated structure including a Ti layer and a TiN layer laminated in this order from the interlayer insulating layer 63 side. The Ti layer and the TiN layer may each be formed by a sputtering method.

[0228] Next, referring to FIG. 11R, a base layer 77 and a base layer 88 are formed. A base body layer 128 is formed on the base barrier layer 127. The base body layer 128 is a pure At least one of an Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer The base body layer 128 may be formed by a sputtering method.

[0229] Next, unnecessary portions of the laminated structure including the base barrier layer 127 and the base body layer 128 are removed. , which are then removed by etching through a resist mask (not shown). The etching may be a wet etching method and / or a dry etching method. The etching method is preferably a dry etching method. A source main surface electrode 81 is also formed.

[0230] Next, an insulating layer 91 is formed on the interlayer insulating layer 63. The insulating layer 91 is a passivation layer. The passivation layer 94 has a laminated structure including a passivation layer 94 and a resin layer 95. The resin layer 95 may be formed by a CVD method. 4. Next, the resin layer 95 is selectively exposed to light. This results in a second gate opening 98, a second source opening 99, and a die. The grooves DS are formed in the resin layer 95 .

[0231] Next, a second gate opening 98, a second source opening 99 and a second gate electrode 96 are formed in the passivation layer 94. The passivation layer 94 is then removed from the dicing street DS. The unnecessary portions may be removed by etching through the resin layer 95. The method may be a wet etching method and / or a dry etching method.

[0232] As a result, the first gate opening 96, the first source opening 97, and the dicing street D S is formed in the passivation layer 94. The first gate opening 96 is The first source opening 97 defines a gate pad opening 92 between the first source opening 97 and the second source opening 98. 9 defines a source pad opening 93.

[0233] Next, referring to FIG. 11S, a drain electrode 105 is formed on the second main surface 4. The conductive electrode 105 is made of at least one of a Ti layer, a Ni layer, a Pd layer, a Au layer, an Ag layer, and an Al layer. The Ti layer, Ni layer, Pd layer, Au layer, Ag layer and / or Al layer may be It may be formed by sputtering, vapor deposition, CVD and / or plating.

[0234] Prior to the step of forming the drain electrode 105, the second main surface 4 may be ground. In this way, the SiC semiconductor layer 2 may be thinned to a desired thickness. An annealing process using a laser irradiation method may be performed on the surface.

[0235] Thereafter, the SiC semiconductor layer 2 is cut along the dicing streets DS. In this way, a plurality of SiC semiconductor devices 1 are cut out from one SiC wafer 111. The SiC semiconductor device 1 is formed through the steps including the steps of:

[0236] FIG. 12 is an enlarged view of the area corresponding to FIG. 8, showing a SiC according to a second embodiment of the present invention. 1 is a diagram showing a part of a semiconductor device 131. The following description will be given for the SiC semiconductor device 1. The structures corresponding to those described above are denoted by the same reference numerals and the description thereof will be omitted.

[0237] Referring to FIG. 12, in this embodiment, the source insulating layer 32 is formed on the bottom wall of the source trench 31. The bottom wall window 132 exposes the source tray. The center of the bottom wall is exposed at a distance from the side wall of the chassis 31. The sidewalls and bottom wall of the source trench 31 are exposed on the bottom wall side of the source trench 31. That's fine.

[0238] In this embodiment, the bottom wall of the source trench 31 has a recess 1 recessed toward the second main surface 4. The recess 133 is spaced apart from the sidewall of the source trench 31 and is formed at the bottom wall thereof. The bottom wall window 132 communicates with a recess 133, leaving the central portion exposed.

[0239] The source electrode 33 is formed on the bottom wall (recess 1) of the source trench 31 exposed from the bottom wall window portion 132. Each contact region 43 has a bottom wall contact portion 134 that contacts the corresponding contact region 43. The portion covering the bottom wall of the source trench 31 is connected to the bottom wall contact portion 134 of the source electrode 33. are electrically connected.

[0240] Each deep well region 44 is connected to a contact region 43 at the bottom wall of the source trench 31. The part electrically connected to the bottom wall contact part 134 of the source electrode 33 via the The deep well region 44 is formed at the bottom wall of the source trench 31 so as to contact the bottom wall of the source electrode 33. It includes a portion electrically connected to the contact portion 134.

[0241] As described above, the SiC semiconductor device 131 has the same effects as those described for the SiC semiconductor device 1. Furthermore, according to the SiC semiconductor device 131, the source electrode 3 3 is exposed from the side wall window portion 36, and the side wall contact portion 39 is exposed from the bottom wall window portion 132. The contact region 43 includes a bottom wall contact portion 134 that contacts the opening of the source trench 31. The source trench is electrically connected to the sidewall contact portion 39 of the source electrode 33 on the side of the source trench. 31 is electrically connected to the bottom wall contact portion 134 of the source electrode 33. do.

[0242] A negative drain-source voltage VGS is applied between the source electrode 33 and the drain electrode 105. When a voltage is applied, the MISFET operates in the third quadrant. A forward current flows through the pn junction diode formed by the deep well region 44) This forward current flows from the source electrode 33 to the drain electrode 105, For MISFETs, this is reverse current.

[0243] The forward current of the pn junction diode flows from the sidewall contact portion 39 of the source electrode 33 to the sidewall The electrons flow into the drift region 8 through the window 36 and simultaneously contact the bottom wall of the source electrode 33. The electrons flow from the bottom wall window 134 into the drift region 8 through the bottom wall window 132. Since the current path of the forward current of the diode is increased, the on-resistance can be reduced. As a result, the forward characteristics of the pn junction diode can be improved.

[0244] In this embodiment, the recess 133 of the source trench 31 is covered by the contact region 43. However, the source trench 31 without the recess 133 may be formed. Also, a recess 133 may be formed that penetrates the contact region 43. In other words, the contacts cover the sidewalls of the recess 133 and expose the bottom wall of the recess 133. Region 43 may be formed.

[0245] 13A to 13F show an example of a method for manufacturing the SiC semiconductor device 131 shown in FIG. FIG.

[0246] Referring to FIG. 13A, a base insulating layer 119 is formed through the steps of FIGS. 11A to 11G. The SiC semiconductor layer 2 is prepared in a cooled state.

[0247] Next, referring to FIG. 13B, a base layer that serves as the base of gate electrode 23 and source electrode 33 is formed. A base polysilicon layer 135 is formed on the first main surface 3. The film is formed along the inner wall of the gate trench 21, the inner wall of the source trench 31, and the first main surface 3. It is formed in a shape.

[0248] The base polysilicon layer 135 may be formed by a CVD method. The base polysilicon layer 135 may be formed by a P-CVD (Low Pressure-CVD) method. It consists of conductive polysilicon that is made conductive by p-type impurities. It may be added to the base polysilicon layer 135 simultaneously with the D method, or may be added separately after the CVD method. may be added.

[0249] Next, referring to FIG. 13C, the unnecessary portions of the base polysilicon layer 135 are removed. The unnecessary portion of the base polysilicon layer 135 is the portion extending parallel to the first main surface 3. Unwanted portions of the base polysilicon layer 135 may be removed by etching. The etching method is preferably an anisotropic dry etching method. The etching method may be a reactive ion etching (RIE) method.

[0250] As a result, a part of the base polysilicon layer 135 covers the sidewall of the gate trench 21. However, the bottom wall of the gate trench 21 remains exposed. A portion of layer 135 covers the sidewalls of source trench 31 and exposes the bottom wall of source trench 31. It remains in the state it was released in.

[0251] Next, referring to FIG. 13D, a resist mask 136 having a predetermined pattern is applied to the first main surface. The resist mask 136 is formed on the source trench 31. 37 and covers the rest of the area.

[0252] Next, the insulating base layer 119 is etched using the resist mask 136. The exposed portion of the base polysilicon layer 135 in the source trench 31 is removed. The etching method is preferably an anisotropic dry etching method. The etching method may be an RIE method.

[0253] As a result, the portion of the base insulating layer 119 that covers the bottom wall of the source trench 31 is In this process, a bottom wall window 132 is formed to expose the bottom wall of the source trench 31. The portion of the SiC epitaxial layer 112 exposed through the bottom wall window 132 is also removed. As a result, a recess 133 communicating with the bottom wall window portion 132 is formed in the bottom wall of the source trench 31. The resist mask 136 is then removed.

[0254] Next, referring to FIG. 13E, the gate electrode 23, the gate wiring 28 and the source electrode 33 A first polysilicon layer 120 serving as a base is formed on the first main surface 3. The gate trench 21 and the source trench 31 are filled with the silicon layer 120, and the silicon layer 120 covers the first main surface 3. The first polysilicon layer 120 is formed in the gate trench 21 and the source trench 31. The polysilicon layer 135 is formed integrally with the base polysilicon layer 135 therein.

[0255] The first polysilicon layer 120 may be formed by a CVD method. The first polysilicon layer 120 may be formed by a p-type impurity CVD (Low Pressure CVD) method. It is made of conductive polysilicon that is given conductivity by impurities. P-type impurities are added by the CVD method. It may be added to the first polysilicon layer 120 at the same time as the CVD method, or may be added separately after the CVD method. That's fine.

[0256] Next, referring to FIG. 13F, unnecessary portions of the first polysilicon layer 120 are removed. 1. Unwanted portions of polysilicon layer 120 are removed until base insulating layer 119 is exposed. The unnecessary portions of the first polysilicon layer 120 may be removed by an etching method. The etching method may be a wet etching method and / or a dry etching method. As a result, the gate electrode 23, the gate wiring 28, and the source electrode 33 are formed.

[0257] In this step, a part of the first polysilicon layer 120 adheres to the active sidewall 54. As a result, a sidewall structure including a part of the first polysilicon layer 120 is formed. The sidewall structure 62 is formed in a self-aligned manner with respect to the active main surface 51. is formed.

[0258] Thereafter, the same steps as those shown in FIGS. 11J to 11S are carried out to form the SiC semiconductor device 131. It is done.

[0259] FIG. 14 is an enlarged view of the area corresponding to FIG. 8, showing a SiC according to a third embodiment of the present invention. 1 is a diagram showing a part of a semiconductor device 141. The following description will be given for the SiC semiconductor device 1. The structures corresponding to those described above are denoted by the same reference numerals and the description thereof will be omitted.

[0260] Referring to FIG. 14, the trench source structure 30 in this embodiment includes a source insulating layer 32. The source electrode 33 is formed in the source trench 31 by the first sidewall contact portion 1. 42, including a second sidewall contact portion 143 and a bottom wall contact portion 145.

[0261] The first sidewall contact portion 142 contacts the sidewall of the first trench portion 34. The contact portion 143 contacts the side wall of the second trench portion 35. Each contact region 43 is in contact with the bottom wall of the source trench 31. The first sidewall contact portion 142, the second sidewall contact portion 143 and the bottom wall contact portion 144 are 45 is electrically connected to the

[0262] Each deep well region 44 is connected to the first sidewall of the source electrode 33 via the contact region 43. The contact portion 142, the second side wall contact portion 143 and the bottom wall contact portion 145 are electrically connected. Each deep well region 44 includes a first sidewall contact of the source electrode 33. The contact portion 142, the second sidewall contact portion 143, and the bottom wall contact portion 145 are electrically connected to the Includes the part connected to

[0263] As described above, the SiC semiconductor device 141 has the same effects as those described for the SiC semiconductor device 1. In addition, according to the SiC semiconductor device 141, the source electrode 3 3 are the first sidewall contact portion 142, the second sidewall contact portion 143 and the bottom wall contact portion The contact region 43 includes a first sidewall contact portion 142 of the source electrode 33, It is electrically connected to the second sidewall contact portion 143 and the bottom wall contact portion 145 .

[0264] A negative drain-source voltage VGS is applied between the source electrode 33 and the drain electrode 105. When a voltage is applied, the MISFET operates in the third quadrant. A forward current flows through the pn junction diode formed by the deep well region 44) This forward current flows from the source electrode 33 to the drain electrode 105, For MISFETs, this is reverse current.

[0265] The forward current of the pn junction diode flows from the sidewall contact portion 39 of the source electrode 33 to the sidewall The electrons flow into the drift region 8 through the window 36 and simultaneously contact the bottom wall of the source electrode 33. The electrons flow from the bottom wall window 134 into the drift region 8 through the bottom wall window 132. Since the current path of the forward current of the diode is increased, the on-resistance can be reduced. As a result, the forward characteristics of the pn junction diode can be improved.

[0266] 15A and 15B show an example of a method for manufacturing the SiC semiconductor device 141 shown in FIG. FIG.

[0267] Referring to FIG. 15A, through the steps of FIGS. 11A to 11I, the first polysilicon layer 120 The SiC semiconductor layer 2 embedded in the gate trench 21 and the source trench 31 It will be prepared.

[0268] Next, referring to FIG. 15B, a resist mask 121 having a predetermined pattern is applied to the first main surface. The resist mask 121 is formed on the source trench 31 and the source region 42. It has an opening 122 that exposes a part of the contact region 43 and covers the other regions. are.

[0269] Next, the entire portion of the first polysilicon layer 120 embedded in the source trench 31 is The portion is removed by etching through the resist mask 121. The entire source insulating layer 32 is also removed. In this step, the SiC epitaxial layer 1 12 is also removed. This forms the first trench portion 34 and the second trench portion 35. A source trench 31 having a SiO 2 layer is formed.

[0270] Thereafter, the same steps as those shown in FIGS. 11K to 11S are carried out to form the SiC semiconductor device 141. It is done.

[0271] FIG. 16 is an enlarged view of the area corresponding to FIG. 8, showing a SiC according to a fourth embodiment of the present invention. 1 is a diagram showing a part of a semiconductor device 151. The following description will be given for the SiC semiconductor device 1. The structures corresponding to those described above are denoted by the same reference numerals and the description thereof will be omitted.

[0272] In the first embodiment, the source pad 82 is integrally formed from the same metal material. The source connection electrode 85 and the source covering electrode 86 are connected to each other. In this regard, the source pad 82 of the SiC semiconductor device 151 is made of different metal materials. The source connection electrode 85 and the source covering electrode 86 are formed separately.

[0273] Specifically, the source connection electrode 85 is made up of a plug electrode 152. The plug electrode 152 is Specifically, the barrier layer 153 and the tungsten layer 154 are stacked in this order from the source hole 67 side. The tungsten plug electrode includes a silicon layer 154.

[0274] The barrier layer 153 is formed in a film shape along the inner wall of the source hole 67 and the electrode surface of the source electrode 33. The barrier layer 153 defines a recess space within the source hole 67. The barrier layer 153 is made of a Ti layer and a TiN layer stacked in this order from the inner wall side of the source hole 67. The barrier layer 153 preferably has a laminated structure including a Ti layer or a TiN layer. The tungsten layer 154 may have a single layer structure consisting of a barrier layer 153 sandwiched therebetween. The source hole 67 is then buried therein.

[0275] The source covering electrode 86 has a laminated structure including a second barrier layer 87 and a second body layer 88. The source covering electrode 86 covers the interlayer insulating layer 63 and the source connecting electrode 85. The source covering electrode 86 is electrically connected to the source electrode 33 via the source connecting electrode 85. It has been done.

[0276] As described above, the SiC semiconductor device 151 has the same effects as those described for the SiC semiconductor device 1. Furthermore, according to the SiC semiconductor device 151, the plug electrode 1 A source connection electrode 85 made of 52 is buried in the source hole 67. The opening width of the hole 67 can be narrowed, and at the same time, the source connection electrode 8 can be inserted into the narrow source hole 67. Therefore, the source connection electrode 85 can be properly connected to the source electrode 33. The structure of the SiC semiconductor device 151 is the same as that of the SiC semiconductor device 131 according to the second embodiment. The present invention can also be applied to the SiC semiconductor device 141 according to the third embodiment.

[0277] The present invention may be embodied in other forms.

[0278] In the above-described embodiments, the first low-resistance layer 29 and the second low-resistance layer 40 are formed. However, either one of the first low resistance layer 29 and the second low resistance layer 40 or A structure in which neither of these is formed may also be employed.

[0279] In each of the above-described embodiments, the gate electrode 2 includes p-type polysilicon doped with p-type impurities. 3 and gate wiring 28 are formed. However, the gate threshold voltage Vt When the increase in h is not important, the gate electrode 23 and the gate wiring 28 are made of p-type polysilicon. Instead of the silicon, n-type polysilicon doped with n-type impurities may be included.

[0280] In this case, the first low resistance layer 29 is formed in the surface layer portion of the gate electrode 23 (n-type polysilicon). may be formed by silicidating the portion forming the That is, the first low resistance layer 29 may contain n-type polycide. In this case, the gate resistance can be reduced. Of course, the first low resistance layer 29 does not necessarily have to be formed.

[0281] In the above-described embodiments, the source electrode 3 includes p-type polysilicon doped with p-type impurities. However, instead of p-type polysilicon, n-type impurities are It may also include doped n-type polysilicon.

[0282] In this case, the second low resistance layer 40 is formed in the surface layer portion of the source electrode 33 (n-type polysilicon). may be formed by silicidating the portion forming the That is, the second low resistance layer 40 may include n-type polycide. The anti-layer 40 may not be formed.

[0283] In the above-described embodiments, the source electrode 3 includes p-type polysilicon doped with p-type impurities. However, the first polysilicon layer 120 made of p-type Then, by forming a second polysilicon layer 123 made of n-type, p-type polysilicon is formed. The source electrode 33 may be formed from a stacked structure of silicon and n-type polysilicon.

[0284] In this case, the second low resistance layer 40 is formed in the surface layer portion of the source electrode 33 (n-type polysilicon). may be formed by silicidating the portion forming the That is, the second low resistance layer 40 may include n-type polycide. The anti-layer 40 may not be formed.

[0285] In each of the above-described embodiments, the insulating layer 91 includes a passivation layer 94 and a resin layer 95. The example having a laminated structure has been described. However, the insulating layer 91 is a passivation layer. 94 or resin layer 95.

[0286] In each of the above-described embodiments, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal. and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. However, the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal. The second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. Good too.

[0287] In each of the above-described embodiments, a MISFET is formed as an example of an insulated gate transistor. However, n + Instead of the drain region 6 of type p + Type Collector According to this structure, an IGBT (insulator-type transistor) may be used instead of a MISFET. In this case, in each of the above-described embodiments, The "source" of the MISFET is replaced with the "emitter" of the IGBT, The "drain" can be read as the "collector" of the IGBT.

[0288] In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is inverted may be adopted. That is, a p-type portion may be made n-type, and an n-type portion may be made p-type.

[0289] In each of the above-described embodiments, an example was described in which the SiC semiconductor layer 2 made of SiC single crystal was included. However, in each of the above-described embodiments, instead of the SiC semiconductor layer 2, a Si single crystal Alternatively, a Si semiconductor layer may be employed.

[0290] Below are presented example features extracted from this specification and the accompanying drawings.

[0291] [A1] A first conductivity type SiC semiconductor layer having a main surface, and a sidewall and a a source trench having a bottom wall and a semiconductor layer buried in the source trench; a sidewall contact portion that contacts a region on the opening side of the source trench on the sidewall of the source trench; a source electrode formed in a surface layer portion of the main surface in a region along the source trench; a body region of a second conductivity type; and a side wall of the source electrode in a surface layer portion of the body region. a first conductivity type source region electrically connected to the contact portion. Place.

[0292] [A2] The body region is electrically connected to the sidewall contact portion of the source electrode. The SiC semiconductor device according to A1,

[0293] [A3] A1 or further including an insulating layer covering the source region on the main surface. or the SiC semiconductor device described in A2.

[0294] [A4] The insulating layer is formed on the main surface so as to cover the sidewall contact portion of the source electrode. The SiC semiconductor device according to A3, wherein the SiC semiconductor device is coated with

[0295] [A5] The insulating layer covers the entire area of ​​the source region in a cross-sectional view. or the SiC semiconductor device described in A4.

[0296] [A6] The insulating layer covers the entire source region in plan view, A5. The SiC semiconductor device according to any one of A5.

[0297] [A7] A source hole formed in the insulating layer to expose the source electrode; any one of A3 to A6 including a source connecting electrode embedded in the hole and connected to the source electrode; The SiC semiconductor device according to any one of the preceding claims.

[0298] [A8] The source-connecting electrode includes a conductive material different from that of the source electrode, SiC semiconductor device.

[0299] [A9] The source hole exposes only the source electrode, and the source connection electrode is connected only to the source electrode in the source hole, SiC semiconductor device.

[0300] [A10] The source electrode has a recess recessed toward the bottom wall of the source trench. an electrode surface having a source hole communicating with the recess of the source electrode; The SiC semiconductor device according to any one of A7 to A9.

[0301] [A11] The source electrode is made of a conductive material other than a metal material, The SiC semiconductor device according to any one of the preceding claims.

[0302] [A12] Any one of A1 to A11, wherein the source electrode is made of conductive polysilicon. The SiC semiconductor device described in one aspect.

[0303] [A13] The source electrode is made of p-type polysilicon, and is any one of A1 to A12. The SiC semiconductor device described in the above.

[0304] [A14] The source trench includes a first trench portion having a first width and formed on an opening side thereof, and and a second trench portion formed on the bottom wall side with a second width less than the first width, The sidewall contact portion of the base electrode is exposed from the first trench portion. 1. The SiC semiconductor device according to claim 1 ,

[0305] [A15] The surface layer of the body region is provided on the sidewall contact of the source electrode. The sidewall contact portion of the source region and the source electrode is electrically connected to the sidewall contact portion of the source region. and a second conductivity type impurity concentration that exceeds the second conductivity type impurity concentration of the body region. A contact region of a second conductivity type having a second conductivity type. SiC semiconductor device.

[0306] [A16] The plurality of contact regions are formed at intervals along the source trench. The SiC semiconductor device according to A15,

[0307] [A17] The contact region includes the sidewall contacts of the body region and the source electrode. The SiC semiconductor device according to A15 or A16, wherein the SiC semiconductor device is interposed between the contact portions.

[0308] [A18] The contact region covers the sidewall and the bottom wall of the source trench. The SiC semiconductor device according to any one of A15 to A17, wherein the SiC semiconductor device is covered.

[0309] [A19] The source stream is formed in a region below the body region in the surface layer portion of the main surface. a second conductivity type impurity concentration less than the second conductivity type impurity concentration of the contact region; Any of A15 to A18 further including a deep well region of the second conductivity type having a high concentration. The SiC semiconductor device according to any one of the preceding claims.

[0310] [A20] The deep well region includes the sidewalls and the bottom wall of the source trench. The SiC semiconductor device according to A19, wherein the SiC semiconductor device is coated with

[0311] [A21] A gate trench formed on the main surface and a gate electrode formed on the inner wall of the gate trench. a gate insulating layer formed on the gate insulating layer and a gate insulating layer embedded in the gate trench, the gate insulating layer being sandwiched between the gate insulating layer and the gate insulating layer; The SiC semiconductor device according to any one of A1 to A20, further comprising a back electrode.

[0312] [A22] The gate trench has a first depth, and the source trench has a The SiC semiconductor device according to A21, having a second depth greater than the first depth.

[0313] [A23] The sidewall of the source trench in the region on the opening side of the source trench a sidewall window portion exposing the source trench, the sidewall and the bottom wall of the source trench being covered with the sidewall window portion; The sidewall contact portion of the source electrode is formed through the sidewall window portion. Any one of A1 to A22 contacting the sidewall of the source trench exposed from The SiC semiconductor device described herein.

[0314] [A24] A region on the sidewall of the source trench on the opening side of the source trench a sidewall window portion exposing the bottom wall of the source trench; and a bottom wall window portion exposing the bottom wall of the source trench. and further including a source insulating layer covering at least the sidewalls of the source trench; The source electrode is embedded in the source trench with the source insulating layer interposed therebetween, and the sidewall contact portion in contact with the sidewall of the source trench exposed through the window portion; and a bottom wall contact portion in contact with the bottom wall of the source trench exposed from the bottom wall window portion; The SiC semiconductor device according to any one of A1 to A22,

[0315] [B1] A first conductivity type SiC semiconductor layer having a main surface, and a sidewall and a a source trench having a bottom wall and a semiconductor layer buried in the source trench; a sidewall contact portion that contacts a region on the opening side of the source trench on the sidewall of the source trench; a source electrode formed in a surface layer portion of the main surface in a region along the source trench; a body region of a second conductivity type; and a side wall of the source electrode in a surface layer portion of the body region. a first conductivity type source region electrically connected to the contact portion; and a surface layer portion of the body region. the source electrode is electrically connected to the sidewall contact portion of the source electrode. a first contact portion of the body region and the sidewall contact portion of the source electrode; A contact region of a second conductivity type having a second conductivity type impurity concentration exceeding the second conductivity type impurity concentration. and a SiC semiconductor device comprising:

[0316] [B2] The body region is electrically connected to the sidewall contact portion of the source electrode. The SiC semiconductor device according to B1,

[0317] [B3] B1 or B2 further includes an insulating layer covering the source region on the main surface. or the SiC semiconductor device according to B2.

[0318] [B4] The insulating layer is formed on the main surface so as to cover the sidewall contact portion of the source electrode. The SiC semiconductor device according to B3, wherein the SiC semiconductor device is coated with

[0319] [B5] The insulating layer covers the entire area of ​​the source region in a cross-sectional view. or the SiC semiconductor device according to B4.

[0320] [B6] The insulating layer covers the entire source region in plan view. The SiC semiconductor device according to any one of B5.

[0321] [B7] A source hole formed in the insulating layer to expose the source electrode; any one of B3 to B6, including a source connecting electrode embedded in the hole and connected to the source electrode; The SiC semiconductor device according to any one of the preceding claims.

[0322] [B8] The source-connecting electrode includes a conductive material different from that of the source electrode, SiC semiconductor device.

[0323] [B9] The source hole exposes only the source electrode, and the source connection electrode is connected only to the source electrode in the source hole, SiC semiconductor device.

[0324] [B10] The source electrode has a recess recessed toward the bottom wall of the source trench. the source hole communicates with the recess of the source electrode; B The SiC semiconductor device according to any one of B7 to B9.

[0325] [B11] The source electrode is made of a conductive material other than a metal material, The SiC semiconductor device according to any one of the preceding claims.

[0326] [B12] Any one of B1 to B11, wherein the source electrode is made of conductive polysilicon. The SiC semiconductor device described in one aspect.

[0327] [B13] The source electrode is made of p-type polysilicon, The SiC semiconductor device described in the above.

[0328] [B14] The source trench includes a first trench portion having a first width and formed on an opening side thereof; and a second trench portion formed on the bottom wall side with a second width less than the first width, The sidewall contact portion of the base electrode is exposed from the first trench portion. 1. The SiC semiconductor device according to claim 1 ,

[0329] [B15] The plurality of contact regions are formed at intervals along the source trench. The SiC semiconductor device according to any one of B1 to B14, wherein the SiC semiconductor device is configured as follows.

[0330] [B16] The contact region is formed by contacting the sidewall contacts of the body region and the source electrode. The SiC semiconductor device according to any one of B1 to B15, wherein the SiC semiconductor device is interposed between the contact portions. .

[0331] [B17] The contact region covers the sidewall and the bottom wall of the source trench. The SiC semiconductor device according to any one of B1 to B16, wherein the SiC semiconductor device is covered.

[0332] [B18] The source stream is formed in a region below the body region in the surface layer portion of the main surface. a second conductivity type impurity concentration less than the second conductivity type impurity concentration of the contact region; Any of B1 to B17 further including a deep well region of the second conductivity type having a high concentration. The SiC semiconductor device described in one aspect.

[0333] [B19] The deep well region includes the sidewalls and the bottom wall of the source trench. The SiC semiconductor device according to B18, wherein the SiC semiconductor device is coated with

[0334] [B20] A gate trench formed on the main surface and a gate electrode formed on the inner wall of the gate trench. a gate insulating layer formed on the gate insulating layer and a gate insulating layer embedded in the gate trench, the gate insulating layer being sandwiched between the gate insulating layer and the gate insulating layer; The SiC semiconductor device according to any one of B1 to B19, further comprising a back electrode.

[0335] [B21] The gate trench has a first depth, and the source trench has a The SiC semiconductor device according to B20, having a second depth greater than the first depth.

[0336] [B22] The sidewall of the source trench in the region on the opening side of the source trench a sidewall window portion exposing the source trench, the sidewall and the bottom wall of the source trench being covered with the sidewall window portion; The sidewall contact portion of the source electrode is formed through the sidewall window portion. any one of B1 to B21 in contact with the sidewall of the source trench exposed from the The SiC semiconductor device described herein.

[0337] [B23] A region on the sidewall of the source trench on the opening side of the source trench a sidewall window portion exposing the bottom wall of the source trench; and a bottom wall window portion exposing the bottom wall of the source trench. and further including a source insulating layer covering at least the sidewalls of the source trench; The source electrode is embedded in the source trench with the source insulating layer interposed therebetween, and the sidewall contact portion in contact with the sidewall of the source trench exposed through the window portion; and a bottom wall contact portion in contact with the bottom wall of the source trench exposed from the bottom wall window portion; The SiC semiconductor device according to any one of B1 to B21,

[0338] [C1] A first conductivity type SiC semiconductor layer having a main surface, and a sidewall and a a source trench having a bottom wall and a semiconductor layer buried in the source trench; a sidewall contact portion that contacts a region on the opening side of the source trench on the sidewall of the source trench; a source electrode provided on the surface of the main surface, the source electrode being electrically connected to the sidewall contact portion of the source electrode; a source region of a first conductivity type having a portion electrically connected to said source region and said source region; The sidewall contact portions of the source electrodes are spaced apart along the source trenches. a portion formed on the surface layer of the main surface at a distance and electrically connected to the sidewall contact portion; and a plurality of contact regions of the second conductivity type each having a respective component.

[0339] [C2] A second conductive layer formed in a region along the source trench in a surface layer portion of the main surface. a body region of the same conductivity type, the source region being formed in a front surface portion of the body region; The contact regions are electrically connected to the sidewall contact portions, and the contact regions are electrically connected to the body region. the surface layer of the SiC substrate is electrically connected to the sidewall contact portion. Semiconductor device.

[0340] [C3] C1 or C3 further includes an insulating layer covering the source region on the main surface. or the SiC semiconductor device according to C2.

[0341] [C4] The insulating layer is formed on the insulating layer so as to cover the sidewall contact portion of the source electrode. The solenoid is formed on the main surface across the boundary between the SiC semiconductor layer and the sidewall contact portion. The SiC semiconductor device according to C3, wherein the SiC substrate is extended onto a base electrode.

[0342] [C5] The insulating layer covers the entire area of ​​the source region in a cross-sectional view. or a SiC semiconductor device according to C4.

[0343] [C6] The insulating layer covers the entire source region in a plan view. The SiC semiconductor device according to any one of C5.

[0344] [C7] A source hole formed in the insulating layer to expose the source electrode; any one of C3 to C6 including a source connecting electrode embedded in the hole and connected to the source electrode; The SiC semiconductor device according to any one of the preceding claims.

[0345] [C8] The source connection electrode includes a conductive material different from that of the source electrode. SiC semiconductor device.

[0346] [C9] The source hole exposes only the source electrode, and the source connection electrode is connected only to the source electrode in the source hole, and is described in C7 or C8. SiC semiconductor device.

[0347] [C10] The source electrode has a recess recessed toward the bottom wall of the source trench. an electrode surface having a source hole communicating with the recess of the source electrode; The SiC semiconductor device according to any one of C7 to C9.

[0348] [C11] The source electrode is made of a conductive material other than a metal material, The SiC semiconductor device according to any one of the preceding claims.

[0349] [C12] The source electrode is made of conductive polysilicon. The SiC semiconductor device described in one aspect.

[0350] [C13] The plurality of contact regions sandwich a part of the source electrode in a plan view. The SiC semiconductor device according to any one of C1 to C12, wherein the first and second electrodes face each other.

[0351] [C14] The source trench includes a first trench portion having a first width and formed on an opening side thereof; and a second trench portion formed on the bottom wall side with a second width less than the first width, The sidewall contact portion of the source electrode is exposed from the first trench portion, and the source region is The contact regions have a portion along the first trench portion, and the contact regions are The SiC semiconductor device according to any one of C1 to C13, having a portion along the portion.

[0352] [C15] The plurality of contact regions have portions that extend along the second trench portion. , The SiC semiconductor device according to C14.

[0353] [C16] A front surface formed along a wall surface of the source trench in a surface layer portion of the main surface. a second conductive impurity having a second conductive impurity concentration lower than the second conductive impurity concentration of the contact region; The SiC semiconductor according to any one of C1 to C15, further comprising a deep well region. body equipment.

[0354] [C17] A gate trench formed on the main surface and a wall surface of the gate trench are coated. a gate insulating layer sandwiching the gate insulating layer and a gate buried in the gate trench; an electrode, and the source trench is spaced from the gate trench. The contact regions are formed on the main surface, and extend from the gate trench to the source trench. The wrench is formed on the main surface with a gap therebetween, as described in any one of C1 to C16. SiC semiconductor device.

[0355] [C18] The plurality of contact regions are arranged in a surface layer portion of the main surface. The SiC semiconductor device according to C17, having a layered portion extending toward the substrate.

[0356] [C19] The sidewall of the source trench in the region on the opening side of the source trench a sidewall window portion exposing the source trench, the sidewall and the bottom wall of the source trench being covered with the sidewall window portion; The sidewall contact portion of the source electrode is formed through the sidewall window portion. any one of C1 to C18 in contact with the sidewall of the source trench exposed from the The SiC semiconductor device described herein.

[0357] [C20] A region on the sidewall of the source trench on the opening side of the source trench. a sidewall window portion exposing the bottom wall of the source trench; and a bottom wall window portion exposing the bottom wall of the source trench. and further including a source insulating layer covering at least the sidewalls of the source trench; The source electrode is embedded in the source trench with the source insulating layer interposed therebetween, and the sidewall contact portion in contact with the sidewall of the source trench exposed through the window portion; and a bottom wall contact portion in contact with the bottom wall of the source trench exposed from the bottom wall window portion; The SiC semiconductor device according to any one of C1 to C18,

[0358] This application is a copy of patent application No. 2019-096 filed with the Japan Patent Office on May 22, 2019. 289, the entire disclosures of which are incorporated herein by reference.

[0359] Although the embodiments of the present invention have been described in detail, they do not clarify the technical contents of the present invention. These are merely examples used to illustrate the invention, and the present invention should not be construed as being limited to these examples. and the scope of the present invention is limited only by the appended claims. [Explanation of symbols]

[0360] 1. SiC semiconductor device 2 SiC semiconductor layer 3 First main surface 21 Gate Trench 22 Gate insulating layer 23 Gate electrode 31 Source Trench 32 Source insulating layer 33 Source electrode 34 First Trench Section 35 Second Trench Section 36 Side wall window 39 Sidewall contact 41 Body Region 42 Source Region 43 Contact Area 44 Deep well area 67 Source hole 69 Recess 85 Source connection electrode 91 Insulating layer 131 SiC semiconductor device 132 Bottom wall window 134 Bottom wall contact part 151 SiC semiconductor device D1 First depth of gate trench D2 Second depth of source trench W1 First width of the first trench W2 Second width of the second trench

Claims

1. a first conductivity type SiC semiconductor layer having a main surface; an active region having a plurality of trench gate structures formed on the main surface; a first impurity region of a second conductivity type formed in a surface layer portion of the main surface in a region between a periphery of the active region and a periphery of the SiC semiconductor layer, the first impurity region having a flat first bottom along the main surface; a second impurity region of a second conductivity type formed in a surface layer portion of the main surface in a region between an outer edge of the first impurity region and a periphery of the SiC semiconductor layer, the second impurity region being continuous with the first impurity region, the second impurity region having a flat second bottom along the main surface and located closer to the main surface than the first bottom; a source pad disposed on the main surface in the active region and electrically connected to a plurality of the trench gate structures; a gate finger disposed on the main surface on a peripheral side of the SiC semiconductor layer with respect to the source pad and electrically connected to the plurality of trench gate structures; The SiC semiconductor device, wherein the gate finger is disposed on the first impurity region.

2. A SiC semiconductor device as described in claim 1, wherein the first impurity region has an overlapping portion that overlaps with the source pad in a planar view.

3. The SiC semiconductor device according to claim 2 , wherein the overlapping portion includes a portion formed on an inner edge of the first impurity region.

4. 4. The SiC semiconductor device according to claim 1, wherein the first impurity region overlaps with both the source pad and the gate finger in a plan view.

5. 5. The SiC semiconductor device according to claim 1, wherein the plurality of trench gate structures are each formed in a band shape extending in a first direction and are formed in a stripe shape at intervals in a second direction intersecting the first direction.

6. The SiC semiconductor device according to claim 5 , wherein the second impurity region is disposed closer to the periphery of the SiC semiconductor layer than the first impurity region in the first direction.

7. 7. The SiC semiconductor device according to claim 5, wherein an outer edge of the first impurity region is located on a peripheral edge side of the SiC semiconductor layer relative to an end of the trench gate structure in the first direction.

8. 8. The SiC semiconductor device according to claim 1, wherein the second bottom is located closer to the main surface than the bottom of the trench gate structure.

9. The SiC semiconductor device according to any one of claims 1 to 8, wherein the trench gate structure includes: a gate trench formed in the main surface; a gate insulating layer formed on an inner wall of the gate trench; and a gate electrode embedded in the gate trench with the gate insulating layer sandwiched therebetween.

10. 10. The SiC semiconductor device according to claim 1, wherein the second impurity region has a peak value of the impurity concentration of the second conductivity type that is equal to or higher than that of the first impurity region.

11. 10. The SiC semiconductor device according to claim 1, wherein the second impurity region has a peak value of the concentration of the second conductivity type impurity that is lower than that of the first impurity region.

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