Design and manufacture of improved power devices

Abstract

This specification describes a device. The device includes a unit cell on a SiC substrate. The unit cell includes a gate insulating film, a trench in a well region, a first sinker region having a second conductivity type, and a second sinker region having the second conductivity type. The first sinker region has a depth equal to or greater than the depth of the well region. Each of the first sinker region and the second sinker region contacts a region having the first conductivity type to form a pn junction.

Description

[Technical Field]

[0001] This application is related to U.S. patent application Ser. No. 16 / 352,698, filed March 13, 2019, entitled "Design and Fabrication of Improved Power Devices," U.S. patent application Ser. No. 16 / 431,655, filed June 4, 2019, entitled "Design and Fabrication of Self-Aligned Power Devices," and U.S. patent application Ser. No. 17 / 342,761, filed June 9, 2021, entitled "Design and Fabrication of Self-Aligned Power Devices." U.S. patent application Ser. No. 16 / 374,025, filed April 3, 2019, entitled "Design and Fabrication of Power Devices Having an Inversion Channel." U.S. patent application Ser. No. 16 / 550,249, filed August 25, 2019, entitled "Design and Fabrication of Robust, High-Performance Devices." U.S. patent application Ser. No. 17 / 231,301, filed April 15, 2021, entitled "Design and Fabrication of Robust, High-Performance Devices." U.S. Patent Application No. 17 / 242,650, filed April 28, 2021, entitled "Design and Fabrication of Robust, High Performance Devices"; U.S. Patent Application No. 16 / 777,928, filed January 31, 2020, entitled "Improved Performance SIC Schottky Diodes"; U.S. Patent Application No. 17 / 099,305, filed November 16, 2020, entitled "Improved Performance SIC Schottky Diodes"; U.S. Patent Application No. 16 / 670,963, filed October 31, 2019, entitled "Silicon Carbide Power Devices"; U.S. Patent Application No. 16 / 741,800, filed January 14, 2020, entitled "Silicon Carbide Power Devices"; and U.S. Patent Application No. 16 / 945,781, filed July 31, 2020, entitled "Design and Fabrication of Power Devices With Increased Crossover Currents." U.S. Patent Application No. 17 / 227,897, filed April 12, 2021, entitled "Design and Fabrication of Power Devices With Increased Crossover Currents," U.S. Patent Application No. 17 / 227,921, filed April 12, 2021, entitled "Design and Fabrication of Power Devices With Increased Crossover Currents," U.S. Patent Application No. 17 / 227,936, filed April 12, 2021, entitled "Design and Fabrication of Power Devices With Increased Crossover Currents," U.S. Patent Application No. 17 / 227,951, filed April 12, 2021, entitled "Design and Fabrication of Power Devices With Increased Crossover Currents," and U.S. Patent Application No. 17 / 007,014, filed August 31, 2020, entitled "Inversion Channel Devices in Multiple Crystal Orientations."This application claims priority to U.S. Patent Application No. 63 / 072,473, filed August 31, 2020, entitled "Power Device," the disclosure of which and the entirety of which are incorporated herein by reference.

[0002] The present invention relates to power semiconductor devices using vertical silicon carbide (SiC) double-implanted metal-oxide-semiconductor field-effect transistors (DMOSFETs), which are a specific type of MOSFET designed to handle significant power levels.

[0003] Furthermore, the present invention relates to 4H—SiC devices including diodes and transistors with interdigitated N-type and P-type regions, such as JBS (Junction Barrier Schottky) diodes, MPS (Merged PiN / Schottky) diodes, MOSFETs (Metal oxide semiconductor field effect transistors) and JFETs (Junction field effect transistors). [Background technology]

[0004] Silicon-based power devices have long dominated power electronics and power system applications. However, SiC is a material with a wider bandgap (Eg = 3.3 eV) than silicon (Eg = 1.1 eV), and therefore has a higher blocking voltage than Si. SiC has a higher breakdown electric field (3×10 6 V / cm~5×10 6 V / cm) (The breakdown field of Si is 0.3×10 6SiC is a better thermal conductor (3.7 W / cm-K) compared to 1.6 W / cm-K for Si. SiC has become the material of choice for power MOSFETs. However, despite the successful introduction of SiC power MOSFETs into the commercial market, some major reliability issues have not been fully resolved. [Source: SiC Power MOSFET, A. Lelis, D. Habersat, R. Green, and E. Mooro of US Army Research Laboratory, Published in: ECS Transactions, 58(4)87-93(2013), DOI: 10.1149]

[0005] SiC exists in a variety of polymorphic crystalline structures known as polytypes, e.g., 3C-SiC, 4H-SiC, 6H-SiC, etc. Figure 1A shows a prior art SiC DMOSFET structure reported by BJ Baliga in Advanced High-Voltage Power Device Concepts (Springer Press, 2011). Figure IB shows the simulated electric field contour for the prior art SiC DMOSFET structure of Figure 1A. The electric field distribution near the surface of a 5 kV shielded 4H-SiC inversion-mode power MOSFET structure is shown in Figure IB, examining the electric fields in the junction-gate field-effect transistor (JFET) region and the gate region. A sharp peak of the electric field at the edge of the P+ shielded region can be observed in this prior art device, which leads to a high electric field in the gate oxide and thereby to poor performance of this MOSFET device. Figure 1C shows the electric field distribution for the shielded 4H-SiC inversion-mode MOSFET. The simulation results in the figure show an electric field as high as 4 MV / cm in the gate oxide of the prior art SiC DMOSFET structure of Figure 1A.

[0006] A typical SiC MOSFET device structure, as shown in Figure 1A, results in high electric field concentrations at the corners of the p-well region, leading to high electric fields within the gate oxide layer, especially during high drain bias (blocking mode) operation. The high critical electric field for breakdown in 4H-SiC (3 MV / cm) results in very high (>5 MV / cm) electric fields in the gate oxide. Fowler-Nordheim tunneling current is observed at such high electric fields in the gate oxide, which can result in trapped charges in the gate oxide, leading to poor device reliability.

[0007] While Si fabrication processes use techniques such as dopant diffusion, these conventional fabrication processes are not feasible for fabricating SiC devices because the diffusion coefficient in SiC is negligible at temperatures below 1800°C. SiC devices are fabricated by ion implantation of both the source and p-well regions, but ion implantation and deep ion implantation are difficult in SiC. Therefore, there is a long-felt need for improved power devices that address the reliability issues of SiC power MOSFETs.

[0008] Furthermore, due to the limited MOS channel mobility (10–25 cm / Vs) achievable on conventional SiC planar DMOSFETs, it is necessary to form the MOS channel with a submicron channel length to avoid significant degradation of the overall on-resistance of the power MOSFET. If the p-well region and the N+ source region are formed using different masks, misalignment of the two masks will result in different channel lengths on both sides of the cell. To avoid a reduction in threshold voltage (Vth) and reduce breakdown voltage (Vbr), the N+ mask is self-aligned with respect to the P-well. [Source: Design and Fabrication of 1.2 kV 4H-SiC DMOSFET by R. Huang et al. published in 2016 13th China International Forum on Solid State Lighting: International Forum on Wide Bandgap Semiconductors C] The MOSFET channel region is formed as a result of the offset between the p-well and N+ source regions in a DMOSFET structure. When the p-well and N+ source regions are formed by two separate masking steps, there is inevitably a certain amount of lithographic misalignment between these levels, resulting in different (or asymmetric) MOS channel lengths on the two sides of the unit cell. Using projection lithography techniques typically used in high-volume semiconductor manufacturing, the lithographic misalignment between the two masking levels can range from + / - 0.05 μm to + / - 0.2 μm or more, which sets a lower limit on the MOS channel length that can be practically achieved without significant asymmetry. For a target channel length of 0.5 μm, a misalignment (alignment error) of + / - 0.2 μm between the N+ source and p-well masking steps can result in a MOS channel length of 0.3 μm on one side of the unit cell and a MOS channel length of 0.7 μm on the other side of the unit cell. Although the on-resistance of a MOSFET increases with a higher MOS channel length, a MOS channel length shorter than the optimum can result in undesirable effects such as degradation of the gate threshold voltage (Vth) and other short-channel effects such as drain-induced barrier lowering (DIBL).

[0009] A self-aligned technique has been proposed in the literature to eliminate misalignment between the P-well and the N+ source regions. Self-aligned MOS channel formation with a channel length defined by sidewall spacer deposition and etching is one such technique. Figure 9 shows the prior art process flow for the self-aligned implantation technique with a channel length defined by sidewall spacer deposition and etching, as reported by R. Huang et al. in "Design and Fabrication of 1.2 kV 4H-SiC DMOSFET."

[0010] Also, "While SiC power MOSFETs share many similarities with silicon MOSFETs, many challenging differences remain. In particular, the wide bandgap nature of 4H-SiC (EG=3.26 eV) is both a blessing and a curse, resulting in low intrinsic carrier concentrations and high critical electric fields while presenting challenges regarding inversion layer mobility and reliability in the passivation dielectric layer." [Source: "Challenges in SiC Power MOSFET Design" by Kevin Matocha, GE Global Research Center, Niskayuna, NY USA, Semiconductor Technology Laboratory, December 12-14, 2007, College Park, MD, USA, 2007]

[0011] In a typical SiC planar MOSFET structure, shown in Figure 1A, a metal-oxide-semiconductor (MOS) channel is formed on the horizontal or 0001 crystal plane of SiC. The channel mobility, or field-effect mobility, on the 0001 crystal plane of SiC tends to be lower compared to vertical sidewalls or the so-called 11-20 or 10-10 crystal planes. The channel mobility, or field-effect mobility, on the 0001 crystal plane of SiC ranges from 15 to 25 cm² / V-sec, compared to silicon MOSFETs, which can exceed 350 cm² / V-sec. When fabricating planar SiC DMOSFETs, on-resistance tends to be high; the MOSFET is limited by the field-effect channel mobility. Therefore, there is a long-felt need for improved power devices that address the low channel mobility and high on-resistance in SiC MOSFETs.

[0012] Furthermore, the threshold voltage of a power MOSFET is an important design parameter from an application standpoint. In most system applications, the minimum threshold voltage must be kept above 1 volt to provide immunity to turn-on due to noise-induced voltage spikes. At the same time, the voltage available to generate charge in the channel inversion layer is determined by (VG-VT), where VG is the applied gate bias and VT is the threshold voltage. [Source: BJ Baliga, Silicon Carbide Power Devices, Springer Press(2005), Page 234]

[0013] Figure 22 [Source: BJ Baliga, Silicon Carbide Power Devices, Springer Press (2005), Page 235] shows the threshold voltages of 4H-SiC planar MOSFETs for a gate oxide thickness of 0.1 microns. Results obtained for silicon power MOSFETs with the same gate oxide thickness are also provided in the figure for comparison.

[0014] To achieve lower RDS, it is common practice to keep the channel length (LCH) as short as possible in planar-gate SiC MOSFETs with high voltage ratings to reduce most of the channel-related conduction losses. The trade-off is that as the channel length is shortened, the MOSFET device experiences a higher threshold voltage (VTH) roll-off at high drain bias and a higher drain leakage (I L The drawback of these devices is their susceptibility to undesirable phenomena such as the drain-induced barrier reduction effect (DIBL) that can lead to poor device performance, including, but not limited to, an increase in the doping concentration in the channel region. A conventional approach to alleviating this problem is to uniformly increase the doping concentration in the channel region, but this approach suffers from higher than optimal gate threshold voltages and on-resistances, which can offset the gains achieved from reducing the channel length.

[0015] Furthermore, there has been a continuing trend towards higher operating frequencies, especially in motor control and switch-mode power supplies. In power supplies, operation at high frequencies is attractive due to the reduction in passive component (inductor and capacitor) size and power losses, which leads to more efficient and compact system designs. To achieve higher frequency operation, improvements are needed. It is essential to use power transistors and rectifiers with improved switching performance, and the superior electronic parameters of SiC allow for dramatic improvements in this regard.

[0016] Figure 27 shows a prior-art structure of an MPS diode consisting of interdigitated pin and Schottky diodes connected in parallel. [T. Kimoto and J.A. Cooper, Fundamentals of Silicon Carbide Technology, IEEE Press (2014), page 296]. The MPS diode shown in prior art Figure 27 has a metal layer on top that forms an ohmic contact to the P+ region and a Schottky contact to the n region. Thus, the entire device consists of interdigitated Schottky and pin diodes connected in parallel. The P+ anode regions are spaced far enough apart so that their depletion regions do not touch under zero or forward bias. This leaves a conductive path through the drift region between each Schottky or non-Schottky contact and the N+ substrate. When a forward bias is applied, the Schottky or non-Schottky region conducts first because the current density of a Schottky barrier diode is orders of magnitude higher than that of a pin diode at the same forward voltage. Therefore, the Schottky or non-Schottky region effectively clamps the voltage drop across the pin region, and the pin region does not conduct. As a result, virtually all forward current is due to electrons injected from the n drift region via Schottky or non-Schottky contacts to the metal. Because the P+ region does not inject holes into the drift region, minority carrier charge does not accumulate, and the turn-off transient is fast, minimizing switching losses. In the absence of conductivity modulation, the series resistance of the drift region is determined by its thickness and doping. This relatively high resistance results in a voltage drop, VDR, that dominates the total voltage drop at high currents. This becomes problematic under high surge current events, as a pure Schottky diode can go into thermal runaway with potentially catastrophic results.

[0017] Further, "[A] silicon carbide (SiC) device can include a gate electrode disposed over a SiC semiconductor layer, the SiC semiconductor layer including a drift region having a first conductivity type, a well region disposed adjacent to the drift region, the well region having a second conductivity type, and a source region having the first conductivity type disposed adjacent to the well region, the source region including a source contact region and a pinch region, the pinch region being disposed only partially below the gate electrode, and a sheet doping density in the pinch region being 2.5×10 14 cm -2 and the pinch region is configured to deplete at current densities greater than the nominal current density of the SiC device to increase the resistance of the source region. [Source: Silicon Carbide Device and Method for Fabricating the Same. [Peter Almem Losee, Ljubisa Dragoljub Stevanovic, Gregory Thomas Dunne, Alexander Viktorovich Bolotnikov, published February 20, 2018 as US9899512B2] ,

[0018] US20190013312A1 discloses body regions numbered 3 and 5, respectively, containing N-type first and second source regions 4 and 6 extending from the top surface 2A into the body regions 3 and 5, and "a first metallization layer extends over the first surface and is in direct contact with the implanted structure and the JFET region to form a JBS diode." [Source: Silicon Carbide MOSFET Device with Integrated Diode and Fabrication Process Thereof, Mario Giuseppe Saggio, Simone Rascuna, published by the USPTO on January 10, 2019].

[0019] "The n-MOSFET device (11) has an n-type channel (2) between the substrate (1) and the gate structure (7, 8), the channel (2) being formed by a layer of n-doped germanium of a thickness such that the channel (2) is fully depleted without an applied gate voltage, whereby the device (11) operates in accumulation mode." [Source: Germanium n-mosfet Device and Fabrication Method, Daniele Caimi, Athanasios Dimoulas, Jean Fompeyrine, Chiara Marchiori, Christophe P. Rossel, Marilyne Sousa, Axelle M. Tapponnier, David J. Webb, published as WO2011013042A]

[0020] US9318597B2 discloses a semiconductor device including a vertical field effect transistor (FET) and a bypass diode. The vertical FET device further includes a substrate, a drift layer formed on the substrate, a gate contact, a plurality of source contacts disposed on a first surface of the drift layer opposite the substrate, a drain contact disposed on a surface of the substrate opposite the drift layer, and a plurality of junction implants, each of the plurality of junction implants being laterally separated on the surface of the drift layer opposite the substrate and extending downward toward the substrate. Each of the one or more bypass diodes is formed by disposing a Schottky metal contact on the first surface of the drift layer, each Schottky metal contact running between two of the plurality of junction implants. [Source: Layout configuration for integrating Schottky contacts in power transistor devices by Vipindas Paia, Edward Robert Van Brunt, Lin Cheng, and John Williams Palmour, published as US9318597B2 on April 19, 2016 in the USPTO.]

[0021] US9876104B2 discloses a multi-cell MOSFET device including MOSFET cells with integrated Schottky diodes, where the MOSFETs include n-type source regions formed in p-type well regions formed in an n-type drift layer, p-type body contact regions formed on the periphery of the MOSFETs, and source metallization of the device forming Schottky contacts with n-type semiconductor regions adjacent to the p-type body contact regions of the device. [Source: Kevin Matocha, Kiran Chatty, Sujit Ban, published as US9876104B2 on January 23, 2018]

[0022] US8436367B1 discloses a field-effect SiC power semiconductor device (MOSFET, IGBT, etc.) with "muted" channel conduction, a negative temperature coefficient of channel mobility, an in-situ "stabilized" source resistance, and optimized thermal management of the cell for an increased safe operating area. Control of the position of the zero temperature crossover point (ZTCP) relative to the drain current is achieved by the division between the "active" and "inactive" channels and by adjusting the carrier mobility in the channel for the temperature range of interest. [SiC Power Vertical DMOS with Increased Safe Operating Area, Dumitru Sdrulla, Marc Vandenberg, issued as US8436367B1 in the USPTO on May 7, 2013]

[0023] Given the knowledge of those skilled in the art, there is a long felt need for power devices with increased third quadrant crossover current to overcome performance and reliability issues.

[0024] Additionally, Figure 67A shows two implementations of power MOSFETs in the form of vertical planar DMOSFETs and vertical trench UMOSFETs. The term DMOSFET comes from the silicon device of the same name, where the n+ source and p-base regions are formed by diffusion of n-type and p-type impurities through the same mask opening (hence the "double-diffused" MOSFET). In SiC, the same structure is formed by double implantation. The term UMOSFET comes from the U-shaped geometry, although the term trench MOSFET is also used. Historically, the first SiC power MOSFETs were UMOSFETs, but were soon joined by ion-implanted DMOSFETs. [Source: T. Kimoto, J.A. Cooper in Fundamentals of Silicon Carbide Technology, IEEE Press (2014), pages 320-324.]

[0025] Due to their trench geometry, UMOSFETs present both opportunities and challenges compared to planar devices such as DMOSFETs. Because the MOS channel is oriented perpendicular to the surface, UMOSFETs can be fabricated using a smaller surface area than DMOSFETs. Because the channel length is determined by epi-growth, it is also easy to form short submicron channels. However, the MOS channel is formed on an etched nonpolar surface of the crystal, and the gate oxide characteristics differ from those on the (1000) surface. The channel mobility, or field-effect mobility, on the 0001 crystal plane tends to be lower compared to vertical sidewalls or the so-called 11-20 or 10-10 crystal planes. Channel mobility can range from 15 to 25 cm2 / Vs on the 1000 plane, but is much lower than that on the 11-20 or 101 planes of SiC. On the 0 crystal plane, the height can be 60-80 cm2 / Vs [SOURCE: T. Kimoto, JA Cooper in Fundamentals of Silicon Carbide Technology, IEEE Press(2014), pages 320-324]

[0026] Figures 67B and 67C show the dominant resistance in vertical DMOSFETs and UMOSFETs, respectively, and it is clear that the device geometry effectively eliminates the JFET resistance present in DMOSFETs. Figure 67(D) shows the electric field in a UMOSFET in the blocking state, with the trench corners being key locations for significant field concentrations. This is a serious problem inherent in UMOSFET device design, since the oxide field is approximately 2.5 times higher than the peak field in the semiconductor (due to Gauss's electrostatic law). [Source: T. Kimoto, J.A. Cooper in Fundamentals of Silicon Carbide Technology, IEEE Press (2014), pages 320-324]

[0027] Therefore, there is a long-felt need to combine the desirable features of planar DMOSFETs and trench UMOSFETs into a single device that can be advantageously and flexibly designed to exploit the specific advantages of each device structure for a given application. Additionally, there is a long-felt need to incorporate junction barrier Schottky (JBS) or coalesced PiN Schottky (MPS) rectifying elements into hybrid DMOSFET / UMOSFET device geometries. Summary of the Invention

[0028] One or more embodiments of the present invention are disclosed herein.

[0029] In one aspect, a device is described herein. The device includes a unit cell on a SiC substrate. The unit cell includes a gate dielectric, a trench in a well region, a first sinker region having a second conductivity type, and a second sinker region having the second conductivity type. The first sinker region has a depth equal to or greater than the depth of the well region. Each of the first sinker region and the second sinker region contacts a region having the first conductivity type to form a pn junction.

[0030] In one embodiment, the device comprises a semiconductor-metal-insulator-semiconductor transistor component.

[0031] In another embodiment, a well region is adjacent the insulator-semiconductor interface and a source region of the first conductivity type is formed in the well region.

[0032] In yet another embodiment, the depth of the trench is greater than or equal to the thickness of the source region.

[0033] In yet another embodiment, the first sinker region is located below the trench.

[0034] In yet another embodiment, the depth of the second sinker region is less than the depth of the first sinker region.

[0035] In yet another embodiment, the depth of the second sinker region is greater than the depth of the well region.

[0036] In yet another embodiment, the device has a gate dielectric with a resistance of 4 milliohm / cm 2 It has an on-resistance of less than 1.5 volts, a gate threshold voltage of greater than 1.5 volts, a breakdown voltage of greater than 500 volts, and an electric field of less than 3.5 megavolts / cm.

[0037] In another aspect, a device is described that includes a unit cell on a SiC substrate. The unit cell includes a gate dielectric, a trench in a well region, a first sinker region of a second conductivity type, a second sinker region of the second conductivity type, and a source region. The source region is connected to the second sinker region. - Direct contact with the area.

[0038] In one embodiment, the device comprises components of a semiconductor-metal-insulator transistor.

[0039] In another embodiment, the unit cell further comprises a semiconductor body of a first conductivity type comprising a drift zone, a well region of a second conductivity type adjacent the insulator-semiconductor interface, and a source region of the first conductivity type formed in the well region.

[0040] In yet another embodiment, the depth of the trench is equal to or greater than the thickness of the source region.

[0041] In yet another embodiment, the depth of the trench is greater than the depth of the source region.

[0042] In yet another embodiment, the device has an avalanche energy of 10 Joules / cm, calculated by dividing the avalanche energy in Joules by the total die area in centimeters squared. 2 It has an avalanche energy exceeding

[0043] In yet another embodiment, the avalanche defect is located within the unit cell.

[0044] In another aspect, a device is disclosed that includes a unit cell on a SiC substrate. The unit cell includes a gate dielectric, a trench in a well region, a first sinker region of a second conductivity type, a second sinker region of the second conductivity type, and a source region. The first sinker region has a depth greater than a depth of the second sinker region. The second sinker region has a width greater than a width of the first sinker.

[0045] In another embodiment, the first sinker region is located below the trench.

[0046] In yet another embodiment, the depth of the second sinker region is less than the depth of the first sinker region.

[0047] In yet another embodiment, the depth of the second sinker region is greater than the depth of the well region.

[0048] In yet another aspect, a device is disclosed that includes a unit cell on a silicon carbide (SiC) substrate. The unit cell includes a first source region of a first conductivity type, a second source region of the first conductivity type, a well region of a second conductivity type, and a silicide layer. The device includes a vertical silicon carbide (SiC) double-implantation metal-oxide-semiconductor field-effect transistor (DMOSFET) with a drain terminal on the backside of the SiC substrate and a source terminal on the top side of the SiC substrate. The second source region of the first conductivity type has a thickness that is less than the thickness of the first source region of the first conductivity type. The second source region of the first conductivity type is interspersed between the well region of the second conductivity type and the silicide layer. The second source region of the first conductivity type includes a sheet of source region located between a recessed SiC trench region and the well region of the second conductivity type.

[0049] In one embodiment, the sheet of source region comprises a thin sheet of source region.

[0050] In another embodiment, the second source region of the first conductivity type comprises at least one of (a) a target thickness, and (b) a target doping concentration.

[0051] In yet another embodiment, the target thickness of the second source region of the first conductivity type is in the range of 1 nm to 1 μm. and the target doping concentration is 10 15 cm -3 ~10 21 cm -3 The range is.

[0052] In yet another embodiment, the second source region of the first conductivity type includes a sheet of source region located between the silicide layer and the well region of the second conductivity type.

[0053] In yet another embodiment, the device is capable of carrying a drain current of less than negative 500 milliamps at a drain voltage of negative 3 volts.

[0054] In yet another aspect, a device is provided that includes a unit cell on a silicon carbide (SiC) substrate, the unit cell comprising a first conductivity type source region, a second conductivity type well region, and a second conductivity type shield region, the second conductivity type shield region being confined within the second conductivity type well region.

[0055] In one embodiment, a second conductivity type shield region is disposed within a metal oxide semiconductor field effect transistor (MOSFET) channel.

[0056] In another embodiment, the second conductivity type shield region is located closer to the edge of the second conductivity type well region.

[0057] In yet another embodiment, the doping concentration within the second conductivity type well region is laterally non-uniform.

[0058] In yet another embodiment, the doping concentration in the second conductivity type shield region is higher than the doping concentration in the second conductivity type well region.

[0059] In yet another embodiment, the second conductivity type shield region extends beyond the vertical extent of the second conductivity type well region.

[0060] In yet another embodiment, the device further comprises a trench region in the second conductivity type well region, the trench region having a depth equal to or greater than the thickness of the first conductivity type source region.

[0061] In yet another embodiment, the device comprises a gate oxide layer in contact with the second conductivity type well region and the first conductivity type source region. The device comprises a double-implantation metal-oxide-semiconductor field-effect transistor (DMOSFET).

[0062] In yet another embodiment, a device comprises a plurality of second conductivity type shield regions within a metal oxide semiconductor field effect transistor (MOSFET) channel.

[0063] In yet another embodiment, the plurality of second conductivity type shield regions are located closer to the edges of the second conductivity type well region.

[0064] In yet another embodiment, a plurality of second conductivity type shield regions extend beyond the vertical extent of the second conductivity type well region.

[0065] In yet another embodiment, a second conductivity type shield region is embedded within a second conductivity type well region.

[0066] In yet another aspect, a device is disclosed that includes a unit cell on a silicon carbide (SiC) substrate. The device includes a first conductivity type source region, a second conductivity type well region, and a second conductivity type shield region. The second conductivity type shield region is embedded within the second conductivity type well region. The second conductivity type shield region is configured to provide a M potential from a high potential applied to the drain terminal. Shielding the OSFET (metal oxide semiconductor field-effect transistor) channel.

[0067] In one embodiment, the device further comprises a trench region within the second conductivity type well region, the trench region having a depth equal to or greater than the thickness of the first conductivity type source region.

[0068] In another embodiment, the device has a gate threshold voltage greater than 2.5 volts, a breakdown voltage greater than 3300 volts at a gate-source voltage of 0 volts, and a resistivity of 15 milliohms / cm 2 It has an on-resistance of less than 100 Ω and a short-circuit withstand time of more than 4 microseconds at a drain voltage of 1500 volts.

[0069] In yet another embodiment, the device has a gate threshold voltage greater than 2 volts, a breakdown voltage greater than 1200 volts at a gate-source voltage bias of 0 volts, and a resistivity of 4.5 milliohms / cm 2It has an on-resistance of less than 100 Ω and a short-circuit withstand time of greater than 2.5 microseconds at a drain voltage of 800 volts.

[0070] In yet another embodiment, the device has a gate threshold voltage of 2.5 volts or greater, a breakdown voltage of greater than 6500 volts at a gate-source voltage of 0 volts, and a dielectric strength of 50 milliohms / cm 2 It has an on-resistance of less than 100 Ω and a short circuit withstand time of greater than 4 microseconds at a drain voltage of 3600 volts.

[0071] In yet another embodiment, the device has a gate threshold voltage of 2.5 volts or greater, a breakdown voltage of greater than 10,000 volts at a gate-source voltage of 0 volts, and a resistance of 100 milliohms / cm 2 and a short circuit withstand time of greater than 4 microseconds at a drain voltage of 5000 volts.

[0072] In yet another embodiment, the device has a gate threshold voltage of 2.5 volts or greater, a breakdown voltage of greater than 13,000 volts at a gate-source voltage of 0 volts, and a resistance of 400 milliohms / cm 2 It has an on-resistance of less than 10000 volts and a short circuit withstand time of more than 4 microseconds at a drain voltage of 10,000 volts.

[0073] In yet another embodiment, a second conductivity type shielding region shields a metal oxide semiconductor field effect transistor (MOSFET) channel from a high potential applied to the drain terminal during one of an off-state and a blocking operation.

[0074] In yet another aspect, a method is described herein that includes forming a silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET), forming a second conductivity type well region, forming a first conductivity type source region in the second conductivity type well region, and forming a second conductivity type shield region, wherein the second conductivity type shield region is located outside the first conductivity type source region.

[0075] In one embodiment, a second conductivity type shield region is disposed within the second conductivity type well region.

[0076] In another embodiment, the second conductivity type shield region extends beyond the second conductivity type well region.

[0077] In yet another embodiment, the SiC MOSFET is 14 ~10 18 cm -3 The silicon carbide (SiC) epitaxial wafers are fabricated on SiC epitaxial wafers with doping ranging from 0.1 to 1.0 μm and thickness ranging from 1 μm to 300 μm.

[0078] In yet another embodiment, forming the second conductivity type well region includes depositing a hard mask including at least one of a silicon dioxide layer, a silicon nitride layer, a polysilicon layer, a silicon oxynitride layer, and a metal layer having a total thickness ranging from 50 nanometers to 5 micrometers; patterning the hard mask; etching the hard mask; and performing ion implantation and epitaxial growth using second conductivity type ions. The step of performing ion implantation includes performing one of the following: 12 cm -2 ~10 15 cm -2 implanting ions of a second conductivity type at an implant dose in the range of 0.5 to 1.0 . The second conductivity type ions include one of aluminum and boron.

[0079] In one embodiment, forming the second conductivity type shield region includes forming the second conductivity type shield region closer to an edge of the second conductivity type well region.

[0080] In another embodiment, forming the second conductivity type shield region includes forming the second conductivity type shield region confined within a second conductivity type well region.

[0081] In yet another embodiment, the method further comprises forming a metal oxide semiconductor field effect transistor (MOSFET) channel.

[0082] In yet another embodiment, forming the second conductivity type shielding region includes forming the second conductivity type shielding region in contact with a metal oxide semiconductor field effect transistor (MOSFET) channel.

[0083] In yet another embodiment, forming the second conductivity type shielding region includes forming multiple second conductivity type shielding regions in contact with a metal oxide semiconductor field effect transistor (MOSFET) channel.

[0084] In yet another embodiment, forming the first conductivity type source region includes forming the first conductivity type source region using one of nitrogen ions and phosphorous ions.

[0085] In yet another embodiment, the method further includes forming a gate oxide layer, forming a polysilicon gate layer, forming an inter-layer dielectric (ILD) layer, forming a silicide region, and forming an interconnect metal layer.

[0086] In yet another embodiment, forming the gate oxide layer includes performing either one or a stacked combination of thermal oxidation and chemical vapor deposition (CVD) of a dielectric layer of one of a silicon dioxide layer, a silicon nitride layer, and a silicon oxynitride layer, and the gate oxide layer is formed to a thickness in the range of 10 nanometers to 100 nanometers.

[0087] In yet another embodiment, forming the polysilicon gate layer includes depositing the polysilicon layer using one of plasma enhanced chemical vapor deposition (PECVD) and low pressure chemical vapor deposition (LPCVD) via one of in situ doping and subsequent drive-in doping.

[0088] In yet another embodiment, forming the interlevel dielectric (ILD) layer includes depositing at least one of a silicon dioxide layer, a silicon nitride layer, and a silicon oxynitride layer, and one of a stacked combination of a silicon dioxide layer, a silicon nitride layer, and a silicon oxynitride layer, wherein the ILD layer has a thickness greater than or equal to 50 nanometers.

[0089] In yet another embodiment, forming the suicide regions includes forming nickel suicide regions on the exposed SiC surfaces.

[0090] In yet another embodiment, forming the second conductivity type shield region includes forming the second conductivity type shield region extending beyond the vertical extent of the second conductivity type well region.

[0091] In yet another aspect, the following method is described herein. The method includes forming a silicon carbide (SiC) metal oxide semiconductor field-effect transistor (MOSFET), forming a second conductivity type well region, forming a first conductivity type source region in the second conductivity type well region, and forming a second conductivity type shield region. The second conductivity type shield region is located outside the first conductivity type source region. The doping concentration of the second conductivity type well region in the channel of the transistor is non-uniform, and at least a portion of the second conductivity type shield region is located within the second conductivity type well region.

[0092] In one embodiment, the doping concentration profiles of the second conductivity type shielding regions at different locations are different.

[0093] In another embodiment, the doping concentration profiles of the second conductivity type shield regions at different locations are not different.

[0094] In yet another aspect, a semiconductor component is described herein. The semiconductor component includes a semiconductor body of a first conductivity type including a voltage blocking layer, islands of a second conductivity type on a contact surface, and a metal layer on the voltage blocking layer. The metal layer and the voltage blocking layer include Schottky contacts and layers of the first conductivity type not in contact with the Schottky contact interspersed between the islands of the second conductivity type.

[0095] In one embodiment, the vertical extent of the first conductivity type layer is smaller than the bottom of the second conductivity type island.

[0096] In another embodiment, the vertical extent of the first conductivity type layer is greater than the bottom of the second conductivity type island.

[0097] In yet another embodiment, the doping concentration in the first conductivity type layer is non-uniform in a direction perpendicular to the Schottky contact.

[0098] In yet another embodiment, the vertical extent of the first conductivity type layer is higher or lower than the bottom of the second conductivity type island.

[0099] In yet another embodiment, the first conductivity type layer has a doping concentration that does not vary in any direction along the interface.

[0100] In yet another embodiment, the first conductivity type layer has a first doping concentration that is greater than the second doping concentration of the drift region.

[0101] In yet another embodiment, the first conductivity type layer has a first doping concentration that is less than the second doping concentration of the drift region.

[0102] In yet another embodiment, the Schottky contact is composed of a metal including Al, Ag, Au, Mo, Ni, Ti, W, TiWy, TiNy, or a combination thereof.

[0103] In yet another embodiment, a diode includes P+ islands interspersed within an N+ region and an N region in contact with a Schottky layer.

[0104] In one embodiment, the vertical extent of the N+ region is smaller than the bottom of the P+ island.

[0105] In another embodiment, the vertical extent of the N+ region is greater than the bottom of the P+ island.

[0106] In yet another embodiment, the doping concentration in the N+ region is non-uniform in the direction perpendicular to the Schottky layer.

[0107] In yet another embodiment, the vertical extent of the N+ region is higher or lower than the bottom of the P+ island.

[0108] In yet another embodiment, a diode includes N+ islands interspersed within a P+ region and a pledione contact with a Schottky layer.

[0109] In one embodiment, the vertical extent of the P+ region is smaller than the bottom of the N+ island.

[0110] In another embodiment, the vertical extent of the P+ region is greater than the bottom of the N+ island.

[0111] In yet another embodiment, the doping concentration in the P+ region is non-uniform in the direction perpendicular to the Schottky layer.

[0112] In yet another embodiment, the vertical extent of the P+ region is higher or lower than the bottom of the N+ island.

[0113] In one aspect, a metal-insulator-semiconductor field-effect transistor is disclosed herein. The metal-insulator-semiconductor field-effect transistor includes a unit cell on a SiC substrate. The unit cell includes a trench in a well region having a second conductivity type, a source region of a first conductivity type, a first sinker region having the second conductivity type, and a second sinker region having the second conductivity type. The first sinker region has a depth equal to or greater than the depth of the well region. Each of the first sinker region and the second sinker region contacts a region having the first conductivity type to form a p-n junction.

[0114] In one embodiment, the first sinker region has a depth greater than the depth of the second sinker region, and the second sinker region has a width greater than the width of the first sinker.

[0115] In another aspect, a metal-insulator-semiconductor field-effect transistor is disclosed herein. The metal-insulator-semiconductor field-effect transistor includes a unit cell on a silicon carbide (SiC) substrate. The unit cell includes a first conductivity type source region, a second conductivity type well region, and a second conductivity type shield region. The second conductivity type shield region is located outside the first conductivity type source region.

[0116] In one embodiment, the second conductivity type shield region extends beyond the vertical extent of the second conductivity type well region.

[0117] In another embodiment, the device further comprises a trench region in the second conductivity type well region, the trench region having a depth equal to or greater than the thickness of the first conductivity type source region.

[0118] In yet another embodiment, the device further comprises a sinker region of the first conductivity type located directly below the trench region.

[0119] In yet another aspect, a semiconductor component is disclosed herein, comprising a semiconductor body of a first conductivity type including a voltage blocking layer, an island of a second conductivity type on a contact surface, and a metal layer on the voltage blocking layer. The layer and the voltage blocking layer include Schottky contacts and layers of the first conductivity type not in contact with the Schottky contacts interspersed between the islands of the second conductivity type.

[0120] In one embodiment, the vertical extent of the first conductivity type layer is smaller than the bottom of the second conductivity type island.

[0121] In another embodiment, the doping concentration in the first conductivity type layer is non-uniform in a direction perpendicular to the Schottky contact.

[0122] In yet another aspect, disclosed herein is a silicon carbide diode comprising islands of a first conductivity type interspersed within a second region of the first conductivity type, and a first region of the first conductivity type in contact with a metal layer. [Brief explanation of the drawings]

[0123] This patent or application contains at least one drawing executed in color. Copies of this patent or patent application publication with the color drawing(s) will be provided by the Patent and Trademark Office upon request and payment of the necessary fee.

[0124] FIG. 1A shows a prior art SiC DMOS reported by BJ Baliga in Advanced High-Voltage Power Device Concepts, Springer Press, 2011.

[0125] Figure IB shows the simulated electric field contours for the prior art SiC DMOSFET structure of Figure 1A.

[0126] Figure IC shows the electric field distribution for the prior art SiC DMOSFET structure of Figure 1A.

[0127] FIG. 2A shows an embodiment of a SiC DMOSFET with a p+ plug region for grounding a p-well region with an N+ source contact.

[0128] Figure 2B shows a breakdown simulation of the SiC DMOSFET structure of Figure 2A.

[0129] FIG. 3 shows an embodiment of a SiC DMOSFET in which the P+ plug region of FIG. 2A is replaced with a deep P-type Sinker #1 region.

[0130] 4A to 4R are cross-sectional views showing the manufacturing process of the SiC DMOSFET structure of FIG.

[0131] FIG. 5A shows an embodiment of a SiC DMOSFET in which a P-type Sinker #2 region is formed below the N+ source region in addition to a deep P-type Sinker #1 region.

[0132] FIG. 5B shows a breakdown simulation of a SiC DMOSFET structure designed according to the embodiment shown in FIGS. 3 and 5A.

[0133] 6A to 6J are cross-sectional views showing the manufacturing process of the SiC DMOSFET structure of FIG. 5A.

[0134] Figure 7A shows a SiC trench etched into the N+ source region before implanting the P-type Sinker#1 region. 1 illustrates an embodiment of a DMOSFET.

[0135] FIG. 7B shows a breakdown simulation of the SiC MOSFET structure of FIG. 7A.

[0136] 8A to 8BB are cross-sectional views showing the manufacturing process of the SiC DMOSFET structure in FIG. 7A.

[0137] FIG. 9 shows a prior art SiC DMOSFET process flow for self-aligned MOS channel formation.

[0138] FIG. 10 shows an embodiment of a SiC DMOSFET structure to eliminate the parasitic N+ source region formed in the periphery.

[0139] 11A to 11GG are cross-sectional views showing the manufacturing process of the SiC DMOSFET structure of FIG.

[0140] FIG. 12 shows an embodiment of a SiC DMOSFET with a dedicated process step utilized to mask the implant of the N+ source region at the periphery of the device.

[0141] 13(A) to 13(G) are cross-sectional views showing the manufacturing process of the SiC DMOSFET structure of FIG.

[0142] FIG. 14 shows an embodiment of a SiC DMOSFET with dedicated process steps to mask the implant of the N+ source region at the device periphery, as well as the N+ source region in the active area to allow for ohmic contact to the p-well region.

[0143] 15A to 15FF are cross-sectional views showing the manufacturing process of the SiC DMOSFET structure of FIG.

[0144] FIG. 16 shows an embodiment of a SiC DMOSFET in which the polysilicon gate metallization layer is segmented in the peripheral region.

[0145] 17A to 17FF are cross-sectional views illustrating the manufacturing process of the SiC DMOSFET structure of FIG.

[0146] FIG. 18 shows an embodiment of a SiC DMOSFET having a portion of the MOS channel on the (1000) and a second portion on the (11-20) or (11-00) crystal plane.

[0147] 19A to 19U are cross-sectional views illustrating the manufacturing process of the SiC DMOSFET structure of FIG.

[0148] FIG. 20 shows an embodiment of a SiC DMOSFET having a portion of the MOS channel on a (1000) crystal plane and a second portion on a (11-20) or (11-00) crystal plane, a deeper p-well trench, and the formation of a second p-well region below the N+ source region.

[0149] 21A to 21V are cross-sectional views illustrating the manufacturing process of the SiC DMOSFET structure of FIG.

[0150] FIG. 22 is prior art and shows a plot of threshold voltage versus p-base doping concentration for a 4H—SiC planar MOSFET.

[0151] 23A-23D show embodiments of SiC DMOSFET structures for electric field shielding in the p-well region.

[0152] 24A-24U are cross-sectional views illustrating process steps for fabricating the SiC DMOSFET structure of FIG. 23A.

[0153] 25A-25D show an embodiment of a SiC DMOSFET structure for field shielding formed embedded within a p-well structure.

[0154] 26A-26U are cross-sectional views illustrating process steps for fabricating the SiC DMOSFET structure of FIG. 25A.

[0155] FIG. 27 is a cross-sectional schematic diagram of a prior art SiC MPS diode.

[0156] FIG. 28A is an embodiment of an MPS diode structure with a buried N+ region.

[0157] FIG. 28B is the IV characteristics of the embodiment described in FIG. 28A.

[0158] FIG. 28C is a cross-sectional comparison of the device of FIG. 28A.

[0159] 29A to 29L are cross-sectional views showing the manufacturing process of the SiC MPS diode shown in FIG. 28A.

[0160] FIG. 30 is an embodiment of an MPS diode structure in which the bottom of the N+ region is higher than the bottom of the P+ region.

[0161] 31A to 31L are cross-sectional views showing the manufacturing process of the SiC MPS diode shown in FIG.

[0162] 32A-32F are embodiments of MPS diode structures having multiple N sub-regions, P sub-regions, or both.

[0163] 33AA to 33AL are cross-sectional views showing the manufacturing process of the SiC MPS diode shown in FIG. 32A.

[0164] 33BA to 33BL are cross-sectional views showing the manufacturing process of the SiC MPS diode shown in FIG. 32B.

[0165] 33EA to 33EL are cross-sectional views showing manufacturing steps of the SiC MPS diode shown in FIG. 32E.

[0166] 33FA to 33FL are cross-sectional views showing the manufacturing process of the SiC MPS diode shown in FIG. 32F.

[0167] FIG. 34 is an embodiment of an MPS diode structure having two different types of P+ wells depending on their depth compared to the depth of the N+ layer.

[0168] 35A to 35P are cross-sectional views showing the manufacturing process of the SiC MPS diode shown in FIG.

[0169] FIG. 36A shows the blocking performance of devices of the present invention with various Wl / Dl ratios.

[0170] FIG. 36B is a blocking IV curve of a device of the present invention with various ratios of Wl / Dl.

[0171] FIG. 36C is the forward IV curves of devices of the present invention with various ratios of Wl / Dl.

[0172] FIG. 36D is the differential specific on-resistance performance of the device of the present invention with various Wl / Dl ratios.

[0173] FIG. 37A illustrates a device structure of a DMOSFET according to one embodiment.

[0174] FIG. 37B illustrates a device structure for a junction field effect transistor (JFET) according to one embodiment.

[0175] FIG. 38 shows an example of an n-type layer formed using ion implantation, according to one embodiment.

[0176] 39A-39C illustrate the vertical extent of the N layer relative to the P+ gate layer in a JFET according to various embodiments.

[0177] 40A-40C illustrate vertical distribution diagrams of N-layers relative to p-well layers in DMOSFETs according to various embodiments. Indicates the area.

[0178] 41A-41E are cross-sectional schematic diagrams of a vertical JFET illustrating the process steps for the device shown in FIG. 37B.

[0179] 42A-42D are cross-sectional schematic diagrams of a power MOSFET structure illustrating the process steps for the device shown in FIG. 37A.

[0180] 43A and 43B show the output and breakdown IV characteristics of a 1200 V SiC DMOSFET fabricated using the teachings of the present invention.

[0181] 44A and 44B show the transfer (ID) curves of a 1200 V SiC MOSFET fabricated using the teachings of the present invention. V / s VGS) characteristics are shown.

[0182] FIG. 45 is the measured single pulse avalanche energy for a 1200 V SiC MOSFET fabricated using the teachings of the present invention.

[0183] FIG. 46 is a photograph showing a SiC DMOSFET fabricated using the teachings of these inventions and tested for single pulse avalanche energy testing.

[0184] Figures 47A and 47B are the output characteristics of two 3.3 kV SiC MOSFETs fabricated using the teachings of these inventions.

[0185] FIG. 47C is the transfer characteristics of two 3.3 kV SiC MOSFETs fabricated using the teachings of these inventions.

[0186] FIG. 47D is a short circuit test measured on two 3.3 kV SiC MOSFETs fabricated using the teachings of the present invention.

[0187] FIG. 48A illustrates an embodiment of a cross-sectional structure of a unit cell of a double-implanted metal-oxide-semiconductor field-effect transistor (DMOSFET) comprising a second source region of a first conductivity type within a first source region of a first conductivity type.

[0188] FIG. 48B illustrates an embodiment of a cross-sectional structure of one or more unit cells of a DMOSFET, including one or more unit cells of an integrated Schottky diode, each DMOSFET unit cell including a second source region of a first conductivity type within a first source region of a first conductivity type.

[0189] FIG. 48C illustrates an embodiment of a cross-sectional structure of one or more unit cells of a trench-gated MOSFET that includes one or more unit cells of an integrated Schottky diode, each MOSFET unit cell including a second source region of a first conductivity type within a first source region of a first conductivity type.

[0190] Figures 49A-49T illustrate one embodiment of a process for fabricating the DMOSFET structure shown in Figure 48A.

[0191] FIG. 50A shows one embodiment of the voltage-current characteristics of a SiC DMOSFET with a passivated pn junction (i.e., a second source region of a first conductivity type) versus a SiC DMOSFET with a conventional pn junction.

[0192] FIG. 50B is a perspective view illustrating an embodiment of a side view of a DMOSFET relative to a die.

[0193] 50C and 50D show the current flow paths through the MOSFETs and the intrinsic anti-parallel diode regions, respectively, in an H-bridge circuit.

[0194] FIG. 51A illustrates an embodiment of a cross-sectional structure of a unit cell of a double-implanted metal-oxide-semiconductor field-effect transistor (DMOSFET) comprising a second source region of a first conductivity type within a first source region of a first conductivity type.

[0195] FIG. 51B illustrates an embodiment of a cross-sectional structure of one or more unit cells of a DMOSFET, including one or more unit cells of an integrated Schottky diode, each DMOSFET unit cell including a second source region of a first conductivity type within a first source region of a first conductivity type.

[0196] 52A-52T illustrate one embodiment of a process for fabricating the DMOSFET structure shown in FIG. 51A.

[0197] FIG. 53A illustrates an embodiment of a cross-sectional structure of a unit cell of a double-implanted metal-oxide-semiconductor field-effect transistor (DMOSFET) including a first metal region in direct contact with a second conductivity type well contact region.

[0198] FIG. 53B illustrates an embodiment of a cross-sectional structure of one or more unit cells of a DMOSFET, including one or more unit cells of an integrated Schottky diode, each DMOSFET unit cell including a first metal region in direct contact with a respective second conductivity type well contact region.

[0199] FIG. 53C shows an embodiment of third quadrant current conduction through an intrinsic pn junction diode region versus a Schottky diode region connected in parallel with a DMOSFET.

[0200] FIG. 53D illustrates an embodiment of third quadrant current conduction through a DMOSFET after connecting one or more Schottky diode regions in series with one or more body diode regions of the DMOSFET.

[0201] 54A-54X illustrate one embodiment of a process for fabricating the DMOSFET structure shown in FIG. 53A.

[0202] 55A, 55B, and 55C each illustrate an embodiment of a cross-sectional structure of a unit cell of a double-implanted metal-oxide-semiconductor field-effect transistor (DMOSFET) with a second conductivity type well contact region serpentine at three different locations.

[0203] 55D, 55E, and 55F illustrate embodiments of cross-sectional structures of one or more unit cells of a diode-integrated DMOSFET, each DMOSFET unit cell comprising a second conductivity type well contact region that respectively serpentines at three different locations.

[0204] 56A-56T illustrate one embodiment of a process for fabricating the DMOSFET structure shown in FIG. 55A.

[0205] Figures 57A-57T illustrate one embodiment of a process for fabricating the DMOSFET structure shown in Figure 55B.

[0206] Figures 58A-58T illustrate one embodiment of a process for fabricating the DMOSFET structure shown in Figure 55C.

[0207] 59A, 59B, and 59C each illustrate an embodiment of a cross-sectional structure of a unit cell of a double-implanted metal-oxide-semiconductor field-effect transistor (DMOSFET) with a second conductivity type well contact region serpentine at three different locations, where the second conductivity type well region is It is possible to contact the source metal only through the contact region.

[0208] 59D, 59E, and 59F illustrate embodiments of cross-sectional structures of one or more unit cells of a diode-integrated DMOSFET, each DMOSFET unit cell comprising a second conductivity type well contact region that snakes at three different locations, respectively, allowing the second conductivity type well region to contact the source metal only through the second conductivity type well contact region.

[0209] FIG. 59G illustrates an embodiment of a cross-sectional structure of one or more unit cells of a diode-integrated trench-gate MOSFET comprising one or more unit cells of an integrated Schottky diode, each MOSFET unit cell comprising a second conductivity type well contact region at a first location allowing the second conductivity type well region to contact source metal only through the second conductivity type well contact region.

[0210] 60A-60T illustrate one embodiment of a process for fabricating the DMOSFET structure shown in FIG. 59A.

[0211] Figures 61A-61T illustrate one embodiment of a process for fabricating the DMOSFET structure shown in Figure 59B.

[0212] Figures 62A-62T illustrate one embodiment of a process for fabricating the DMOSFET structure shown in Figure 59C.

[0213] FIG. 63 illustrates an embodiment of a cross-sectional structure of one or more unit cells of a power MOSFET, where a first unit cell of the one or more unit cells comprises a first metal-oxide-semiconductor (MOS) interface on a horizontal surface of a semiconductor substrate and a trench sidewall, and a second unit cell of the one or more unit cells comprises a second metal-oxide-semiconductor (MOS) interface formed only on the trench sidewall.

[0214] 64A-64AB are cross-sectional views illustrating one embodiment of a manufacturing process for the MOSFET structure shown in FIG.

[0215] FIG. 65 illustrates an embodiment of a cross-sectional structure of one or more unit cells of a power MOSFET, where a first unit cell of the one or more unit cells comprises a first metal-oxide-semiconductor (MOS) interface on a horizontal surface of a semiconductor substrate and a trench sidewall, and a second unit cell of the one or more unit cells comprises a metal region formed adjacent to a first conductivity type drift layer of the MOSFET.

[0216] 66A-66AA are cross-sectional views illustrating one embodiment of a manufacturing process for the MOSFET structure shown in FIG.

[0217] FIG. 67A shows two implementations of a power MOSFET in the form of a vertical planar DMOSFET and a vertical trench UMOSFET.

[0218] Figures 67B and 67C show the dominant resistance in the vertical DMOSFET and UMOSFET, respectively, and it is clear that the device geometry effectively eliminates the JFET resistance present in the DMOSFET.

[0219] FIG. 67D shows the electric field in a blocking UMOSFET, with the trench corners being key locations of significant electric field concentrations.

[0220] Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows. DETAILED DESCRIPTION OF THE INVENTION

[0221] Definitions and Common Techniques Unless otherwise defined herein, scientific and technical terms used in connection with the present invention shall have the meanings commonly understood by those skilled in the art. Further, unless otherwise required by context, singular terms shall include the plural and plural terms shall include the singular. Generally, the nomenclature used in connection with the semiconductor processing described herein, and techniques thereof, are well known and commonly used in the art.

[0222] The methods and techniques of the present invention are generally carried out according to conventional methods well known in the art and as described in the various general and more specific references cited and discussed throughout the specification unless otherwise indicated. The nomenclature used in connection with, and procedures and techniques of, semiconductor device technology, semiconductor processing, and other related fields described herein are those well known and commonly used in the art.

[0223] For simplicity and clarity of explanation, the drawings show general constructional methods, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. In addition, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help understand embodiments of the present disclosure. The same reference numbers in different drawings refer to the same elements.

[0224] Terms such as "first," "second," "third," and "fourth" in this specification and claims, if any, are used to distinguish between similar elements and not necessarily to describe a particular sequential or chronological order. Terms so used are to be understood as interchangeable under appropriate circumstances, such that the embodiments described herein may, for example, operate in orders other than those illustrated or otherwise described herein. Furthermore, the terms "include" and "have," and any variations thereof, are intended to cover non-exclusive inclusions, and thus a process, method, system, article, device, or apparatus comprising a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, system, article, device, or apparatus.

[0225] Terms such as "left," "right," "front," "rear," "top," "bottom," "upper," "lower," and the like in this specification and claims are used for descriptive purposes and are not necessarily used to describe permanent relative positions. It is understood that terms so used are interchangeable under appropriate circumstances, such that embodiments of the apparatus, methods, and / or articles of manufacture described herein can, for example, operate in other orientations other than those illustrated or otherwise described herein.

[0226] No element, act, or instruction used herein should be construed as critical or required unless explicitly stated as such. Also, as used herein, the articles "a" and "an" are intended to include items and may be used interchangeably with "one or more." Furthermore, as used herein, the term "set" is intended to include items (e.g., related items, unrelated items, combinations of related items, and unrelated items, etc.) and may be used interchangeably with "one or more." Where only one item is intended, the term "one" or similar language is used. Also, as used herein, the terms "has," "have," "having," etc. are intended to be open-ended terms. Furthermore, the phrase "based on" is intended to mean "based at least in part on," unless otherwise specified.

[0227] The following terms and phrases, unless otherwise indicated, shall be understood to have the following meanings:

[0228] As used herein, the term "unit cell" refers to a portion of a pattern in a semiconductor that is repeated within the semiconductor.

[0229] As used herein, the term "SiC" refers to silicon carbide, a compound semiconductor and a mixture of silicon and carbon with the chemical formula SiC. The silicon is covalently bonded to the carbon. Here, 4H-SiC is written in the Ramsdell classification scheme, with 4H written as the layer, and the letters as the Bravais lattice. This means that in the 4HSiC structure, there are four hexagonal layers of SiC. SiC exists in a variety of polymorphic crystalline structures known as polytypes, for example, 3C-SiC, 4H-SiC, and 6H-SiC. Currently, 4H-SiC is used in power device fabrication. [Source: Complete Analytical Feasibility-Based Solutions for Nanoscale 4HSiC MOSFETs, MK Yadav, KP radhan and PK Sahu Published 24 May 2016 ·(c) 2016 Vietnam Academy of Science & Technology]

[0230] As used herein, the term "substrate" refers to a supporting material on which integrated circuit components are fabricated or attached.

[0231] As used herein, the term "JFET" refers to a junction-gate field-effect transistor, a three-terminal semiconductor device that can be used as an electronically controlled switch, amplifier, or voltage-controlled resistor. A FET (field-effect transistor) is a unipolar transistor in which current carriers are injected into the source terminal and pass to the drain terminal through a channel of semiconductor material whose conductivity is highly dependent on the electric field applied to the semiconductor from a control electrode. There are two main types of FETs: junction FETs and insulated-gate FETs. In a junction FET, the gate is insulated from the channel by a pn junction. In an insulated-gate FET, the gate is insulated from the channel by an insulating layer, so that the gate and channel form a capacitor with the insulating layer as the capacitor dielectric.

[0232] As used herein, the term "MOSFET" refers to a metal-oxide-semiconductor field-effect transistor, which is a four-terminal device having source (S), gate (G), drain (D), and body (B) terminals. The body of a MOSFET is often connected to the source terminal, making it a three-terminal device like a field-effect transistor.

[0233] As used herein, the term "DMOSFET" refers to a double-implantation metal-oxide-semiconductor field-effect transistor. The general physical structure of a SiC MOSFET is a planar in 4H-SiC (SiC-DMOSFET). It is a double injection MOSFET.

[0234] As used herein, the term "dopant" refers to an impurity added to a material from an external source by diffusion, coating, or implantation into a substrate, e.g., to change its properties. In semiconductor technology, impurities can be added to a semiconductor to change its electrical properties or can be added to a material to produce a semiconductor with desired electrical properties. N-type (negative) dopants (e.g., phosphorus for Group IV semiconductors) typically come from Group V of the periodic table. When added to a semiconductor, n-type dopants create a material that contains conduction electrons. P-type (positive) dopants (e.g., boron for Group IV semiconductors) typically come from Group III and provide conduction holes (i.e., vacancies in the electron shell).

[0235] As used herein, the term "drain" refers to the electrode of a field effect transistor that receives charge carriers that pass through the transistor channel from the source electrode.

[0236] As used herein, the term "source" refers to the active region / ectrod to which the source of charge carriers is connected in a field effect transistor

[0237] As used herein, the term "gate" refers to a control electrode or region that exerts an effect on a semiconductor region directly associated with it such that the conductive properties of the semiconductor region are temporarily altered, often resulting in an on-off switching action. The control electrode or region of a field effect transistor is located between and within the source and drain electrodes.

[0238] As used herein, the term "impurity" refers to a foreign substance present in a semiconductor crystal, such as boron or arsenic in silicon, that is added to the semiconductor to produce either a p-type or n-type semiconductor material, or to result in a material whose electrical properties would otherwise depend on the impurity dopant atom.

[0239] As used herein, the term "PN junction" refers to the interface and region of transition between p-type and n-type semiconductors.

[0240] As used herein, the term "polysilicon" refers to silicon in a polycrystalline form.

[0241] As used herein, the term "P-type" refers to an extrinsic semiconductor in which the hole density exceeds the conduction electron density.

[0242] As used herein, the term "band gap" refers to the difference between the energy level of electrons bound to nuclei (valence electrons) and the energy level that allows electrons to move freely (conduction electrons). The band gap depends on the particular semiconductor involved.

[0243] As used herein, the term "breakdown" refers to a sudden change in a reverse-biased semiconductor device (e.g., a reverse-biased junction between p-type and n-type semiconductor materials) from a high dynamic electrical resistance to a very low dynamic resistance, where the reverse current increases sharply for a small increase in applied reverse voltage and the device behaves as if it had a negative electrical resistance.

[0244] As used herein, the term "channel" refers to a path for conducting current between the source and drain of a field effect transistor.

[0245] As used herein, the term "chip" refers to a single crystal substrate of semiconductor material on which one or more active or passive solid-state electronic devices are formed. A chip may include integrated circuits. A chip is typically not ready for use until it is packaged and provided with external connectors.

[0246] As used herein, the term "contact" refers to a point or portion of an electrical conductor that contacts another electrical conductor or electrical component in order to carry electrical current between the electrical conductors or components.

[0247] As used herein, the term "die" refers to a minute piece of semiconductor material, also called a chip, on which one or more active electronic components are formed, separated from a semiconductor slice. N+ substrate.

[0248] The term "sinker," as used herein, refers to a deep implant region at a critical location within the DMOSFET structure.

[0249] As used herein, the term "plug" refers to a well and source contact that connects to ground. Refers to the structure used for

[0250] As used herein, the term "drift layer" refers to a lightly doped region for supporting high voltages in a power MOSFET.

[0251] The term "well" as used herein refers to a specific region within a Metal Oxide Semiconductor (MOS) transistor. MOS transistors are always formed in a "well" region. PMOS (positive channel MOS) transistors are fabricated in an N-doped region called an "N-well" region. Similarly, NMOS transistors (negative channel MOS) are formed in a "P-type" region called a "p-well." This ensures low leakage between the two transistors through the underside due to the reverse bias between the transistor region and the well region.

[0252] As used herein, the term "source interconnects metallization" refers to an interconnect metallization that uses fine-line metal patterns to interconnect thousands of MOSFETs.

[0253] The term "self-alignment," as used herein, refers to a processing step in the manufacture of semiconductor devices. It is often necessary to achieve precise alignment between structures fabricated at different lithographic stages in integrated circuit fabrication. Stringent requirements on lithographic alignment tolerances can be relaxed when the structures are "self-aligned," meaning that one is forced to a specific position relative to the other for a wide range of lithographically defined positions.

[0254] As used herein, the term "device" refers to the physical realization of individual electrical elements within a physically separate body, which cannot be further divided without destroying its described function.

[0255] As used herein, the term "surface" refers to the outside or outer boundary of an object.

[0256] As used herein, the term "trench" refers to the electrical isolation of electronic components within a monolithic integrated circuit through the use of grooves or other depressions in the surface of a substrate, which grooves or other depressions may or may not be filled with an electrically insulating (i.e., dielectric) material.

[0257] As used herein, the term "dielectric" refers to a material that is a non-conductor of electricity, otherwise known as an insulator.

[0258] As used herein, the term "mobility" refers to the facility with which carriers move through a semiconductor when subjected to an applied electric field. Electrons and holes typically have different mobilities in the same semiconductor.

[0259] As used herein, the term "RIE" refers to reactive ion etching, an etching technique used in microfabrication. RIE is a type of dry etching with different properties than wet etching. RIE uses a chemically reactive plasma to remove material deposited on the wafer. The plasma is generated under low pressure (vacuum) by an electromagnetic field. High-energy ions from the plasma attack and react with the wafer surface.

[0260] As used herein, the term "ILD" refers to interlayer dielectric, a dielectric material used to electrically isolate closely spaced interconnect lines located on several levels (multilayer metallization) within advanced integrated circuits.

[0261] As used herein, the term "CVD" refers to chemical vapor deposition, a method used to produce high-quality, high-performance solid materials, typically under vacuum. This process is often used in the semiconductor industry to produce thin films. In a typical CVD process, a wafer (substrate) is exposed to one or more volatile precursors that react and / or decompose on the substrate surface to produce the desired deposit. Often, volatile by-products are also produced, which are removed by gas flow through the reaction chamber.

[0262] As used herein, the term "PECVD" refers to a plasma-enhanced chemical vapor deposition process used to deposit thin films on a substrate from a gaseous (vapor) to a solid state. A chemical reaction is involved in the process, which occurs after the generation of a plasma of the reactant gases.

[0263] As used herein, the term "LPCVD" refers to a low-pressure chemical vapor deposition technique that uses heat to initiate the reaction of precursor gases on a solid substrate. This reaction at the surface is what forms a solid-phase material.

[0264] As used herein, the term "DIBL" refers to drain-induced barrier lowering, a short-channel effect in MOSFETs that originally referred to a reduction in the transistor's threshold voltage at higher drain voltages. In classical planar field-effect transistors with long channels, the bottleneck in channel formation occurs far enough from the drain contact that it is electrostatically shielded from the drain potential by the substrate-gate combination; therefore, classically, the threshold voltage was independent of the drain voltage. In short-channel devices, this is no longer true: the drain potential can gate the channel, and therefore, a high drain voltage can open the bottleneck and turn the transistor on prematurely.

[0265] As used herein, the term "ICP" refers to an inductively coupled plasma etching technique often used in the specialty semiconductor market for device fabrication. This technique combines both chemical reactions and ion-induced etching. Independent control of ion flux allows for high process flexibility. ICP etching is based on the use of an inductively coupled plasma source. An ICP source generates high-density plasma through inductive coupling between an RF antenna and the plasma. An antenna located in the plasma generation region generates an alternating RF magnetic field, which induces an RF electric field at low pressure that energizes electrons responsible for ionizing gas molecules and atoms. Because there is no electric field near the reactor walls, there is virtually no ion bombardment or erosion of the walls.

[0266] As used herein, the term "p-shield" refers to a carefully designed p-type doped region strategically placed near or within the MOSFET channel region, whose purpose is to shield the MOSFET channel from high potentials applied to the drain terminal during the off-state or blocking operation.

[0267] As used herein, the terms "first conductivity type region" and "second conductivity type region" are used to describe the n-type and p-type regions, respectively, for an N-type device. For a P-type device, "first conductivity type region" and "second conductivity type region" are used to describe the p-type and n-type regions, respectively.

[0268] As used herein, the term "IV characteristic curve" refers to the current-voltage characteristic curve, or simply IV curve, of an electrical device or component, and refers to a set of graphical curves used to define its behavior in an electrical circuit.

[0269] As used herein, the term "MV / cm" refers to megavolts per centimeter, a unit of electric field.

[0270] As used herein, the term "avalanche failure" refers to a phenomenon that can occur in both insulating and semiconducting materials. It is a form of current multiplication that can allow very large currents in materials that are otherwise good insulators. It is a type of electron avalanche. This avalanche process occurs when carriers in the transition region are accelerated by an electric field to sufficient energy to create mobile or free electron-hole pairs through collisions with bound electrons. The voltage at which breakdown occurs is called the breakdown voltage. Avalanche breakdown can cause structural damage to semiconductor devices.

[0271] As used herein, the term "avalanche energy" is defined as the amount of energy a MOSFET can withstand when placed in avalanche mode or when its breakdown voltage is exceeded.

[0272] As used herein, the term "top side" refers to the outer / top side of the DMOSFET. The top surface of a vertical SiC DMOSFET can include the source terminal.

[0273] As used herein, the term "bottom surface" refers to the lower / bottom surface of a DMOSFET. The bottom surface of a vertical SiC DMOSFET may comprise the drain terminal.

[0274] As used herein, the term "front surface" refers to the surface that is visible from the front side of the DMOSFET.

[0275] As used herein, the term "backside" refers to the backside of a DMOSFET. The backside of a vertical SiC DMOSFET may include the drain terminal.

[0276] As used herein, the term "positive" refers to a particular region in a metal-oxide-semiconductor (MOS) transistor that has an excess doping concentration.

[0277] As used herein, the term "active area" refers to the region of a DMOSFET where current conduction occurs.

[0278] As used herein, the term "depletion region" refers to a region where the flow of charge carriers is reduced over a given period of time.

[0279] As used herein, the term "thermal budget" refers to the total amount of thermal energy transferred to a wafer during a given high temperature operation.

[0280] As used herein, the term "work function" refers to the minimum amount of energy required to infinitely remove electrons from the surface of a given metal.

[0281] As defined herein, two or more elements are "unitary" if they are constructed from the same piece of material. As defined herein, two or more elements are "non-unitary" if they are each constructed from a different piece of material.

[0282] As used herein, the term "trench sidewall" refers to the wall that forms the side of a trench region.

[0283] As used herein, the term "bottom" refers to the bottom of the trench region.

[0284] As used herein, the term "crystal plane" refers to an imaginary plane within the crystal of a semiconductor substrate where a high atomic concentration exists.

[0285] As used herein, the term "MOS interface" refers to a region / path that electrically interconnects two regions.

[0286] As used herein, the term "horizontal surface" refers to an unetched surface on the top surface of a semiconductor substrate.

[0287] As used herein, the term "RF" refers to radio frequency, which is an alternating current or voltage, or the rate of oscillation of a magnetic, electric, or electromagnetic field or mechanical system.

[0288] Embodiments relate to SiC DMOSFET power devices, where the p-well region effectively shields the sensitive gate oxide from the high electric fields present in SiC, especially during high drain bias or blocking mode operation.

[0289] One embodiment involves using a p+ plug to ground the p-well region with an N+ source contact.

[0290] One embodiment relates to making the lateral spacing between p-well regions narrow enough to suppress the electric field in the gate oxide while ensuring that the on-resistance is not high.

[0291] One embodiment relates to replacing the P+ plug region of the DMOSFET with a deep P-type Sinker#1 region.

[0292] Embodiments relate to the formation of one or more deep implanted sinker regions at specific locations within a MOSFET device structure, such as a first P-type sinker region at the center of a MOSFET unit cell, whose depth may be equal to or greater than the depth of a p-well region.

[0293] An embodiment relates to forming a second P-type sinker region below the N+ source region, the depth of which may be equal to or greater than the p-well region, but may be equal to or less than the depth of the first P-type sinker region.

[0294] Embodiments relate to boron implants that can be advantageously used to form deep sinker regions because boron has a greater implant range than aluminum, which can result in a deeper implant profile.

[0295] Embodiments relate to the formation of a first trench having a desired shape that can be etched into the N+ source region prior to the formation of a first P-type sinker region, which can serve to increase the depth of the first P-type sinker region. The depth of the first trench can range from 0.01 μm to 2 μm. The resulting depth of the first sinker region can be 0% to 100% greater than the depth of the p-well region. The depth of the first P-type sinker region can be as large as the entire epitaxial layer.

[0296] Embodiments relating to forming a first trench in the N+ source region can reduce or eliminate the need for an expensive, very high energy implant step to form the first P-type sinker region.

[0297] The first trench embodiment can be advantageously used to remove the N+ source implant from the first P-type sinker region, which may be desirable to prevent compensation of the first P-type sinker region by the N+ source implant. This is because the N+ source region is in contact with the p-well region. This is particularly useful when the device is self-aligned.

[0298] An embodiment relates to gradually decreasing implant concentrations that can be used to form the first and second P-type sinker regions instead of a box-shaped implant profile, which can be advantageous for properly shaping the electric field under high drain bias. The doping in the P-type sinker regions can be linearly varied from a maximum value near the SiC surface to a value equal to or slightly higher than the doping concentration of the drift layer at the other end of the P-type sinker regions.

[0299] The design embodiments of the first and second sinker regions can simplify the design of the p-well region, which can be designed to support metal-oxide-semiconductor (MOS) channel formation and can be advantageously designed to achieve low on-resistance without compromising other performance metrics such as reverse leakage current and electric field in the gate oxide.

[0300] SiC devices in power electronics are characterized by fast switching times, high blocking voltage capability, and the ability to operate at high temperatures. These properties, along with recent advances in manufacturing processes, suggest that SiC has the potential to revolutionize power electronics as a successor to conventional silicon-based (Si) devices. SiC is a wide bandgap material (3.3 eV), offering a high breakdown field (3×10 V / cm) compared to Si (Si's bandgap is 1.1 eV and its breakdown field is 0.3×10 V / cm). 6 V / cm~5×10 6 SiC has a thermal conductivity of 3.7 W / cm-K compared to 1.6 W / cm-K for SiC, allowing SiC devices to operate at extremely high power levels and still dissipate the large amounts of excess heat generated. These material properties of SiC offer several advantages of using SiC instead of Si in power devices. In a comparison of SiC and Si semiconductor dies with identical structure and dimensions, the SiC die exhibits a lower specific on-resistance and higher breakdown voltage than the Si die.

[0301] The embodiments disclosed herein provide novel techniques for the design and fabrication of SiC DMOSFETs that shape the electric field over the device structure and reduce field concentrations at singular points. Embodiments herein reduce the electric field in the gate oxide region to less than 3.5 MV / cm, improving device reliability.

[0302] While fabrication processes in Si use techniques such as dopant diffusion, these conventional fabrication processes are not feasible for fabricating SiC devices because the diffusion coefficient in SiC is negligible at temperatures below 1800°C. SiC devices are fabricated by ion implantation of both the source and p-well regions, but ion implantation, and particularly deep ion implantation, is difficult in SiC. In embodiments herein, the ion implantation of the source and p-well regions is performed deep using a novel technique.

[0303] Compared to silicon devices, the high reliability, high operating temperature, high efficiency, and high voltage capability of SiC devices of embodiments herein make them highly desirable in the electric vehicle and renewable energy industries. Electric vehicle traction inverters are exposed to high heat (>150°C), and duty cycle and renewable energy converters are exposed to extreme environmental conditions. The embodiments described herein for SiC devices maximize power conversion efficiency, e.g., up to >98%, while providing high reliability, thus making them ideal candidates for electric vehicles, minimizing expensive maintenance and downtime for electric vehicle operators.

[0304] The disclosed embodiments modify how SiC power DMOSFET devices can effectively shield the sensitive gate oxide from the high electric fields present in 4H—SiC, especially during high drain bias (blocking mode operation).

[0305] In embodiments herein, SiC power DMOSFET devices overcome the trade-off between achieving low on-resistance and robust blocking performance, which implies a low electric field in the structure close to the gate oxide.

[0306] Embodiments herein include a SiC power DMOSFET unit cell comprising a vertical MOSFET. A particular region of a SiC power DMOSFET device is a p-well region formed by an implant, an N+ source region, an N drift layer, and an N+ substrate. In embodiments herein, during the on-state, current flows vertically from the drain through an inversion layer formed on top of the p-well layer, and a gate voltage is applied to the device when it is applied through the N+ source region and out through the source metallization. In the off-state or blocking state, embodiments herein support a voltage across the p-well and N drift layer junction. A PN junction is formed between the p-well and the N drift layer. A voltage applied to the structure is supported across this PN junction in reverse bias.

[0307] In embodiments herein, a power MOSFET has several physical dimensions, including the pitch of the unit cell, which is the repeating unit of the MOSFET; the channel length, which is the portion of the p-well where the inversion channel is formed; the distance between two consecutive p-wells, called the junction-gate field-effect transistor (JFET) region or JFET gap; the thickness of the gate oxide; and the inter-layer dielectric (ILD) layer used to insulate the source interconnect metallization from the polysilicon gate.

[0308] In embodiments herein, the advantage of using SiC over Si is that for a similar chip size, SiC can support a much higher power density. The amount of voltage that SiC can support is more than 10 times that of Si, and the current that a SiC chip can carry through a MOSFET is 10 to 50 times that of Si. The performance advantage relates to the tradeoff between voltage and current. The voltage blocking and current conducting capabilities are about 200 times better for SiC compared to Si.

[0309] In embodiments herein, the P+ plug at the center of a SiC DMOSFET unit cell is replaced by a PS#1 region. In embodiments, the PS#1 region extends below the p-well region. During blocking conditions, the electric field or primary region where breakdown can occur is essentially at the center of the SiC DMOSFET unit cell, between the PS#1 region and the Ndrift layer. SiC structures tend to break down between the p-well and Ndrift layer, especially at the curvature of the p-well region. In embodiments herein, the structure breaks down between the PS#1 region and the Ndrift layer. Here, the location of breakdown is moved toward the center of the unit cell, resulting in a lower electric field closer to the gate oxide region. Due to the PS#1 region, there is a reduced electric field closer to the gate oxide region in this embodiment, which should create a more robust device.

[0310] The embodiments herein have differences in structure, manufacturing method, device function, and device results compared to prior art SiC devices. Simulation data for the embodiments herein demonstrates the differences in structure performance and results. In addition to the PS#1 region, the devices of the embodiments herein also have a PS#2 region located below the N+ source region. This improves the electric field profile in the embodiments so that voltage is dropped across a larger area of ​​the unit cell during blocking mode of operation, resulting in even more robust operation. In the embodiments herein, the PS#2 region can be deeper than the p-well region and shallower than the PS#1 region. In the embodiments herein, of all p-type regions in the SiC DMOSFET structure, the deepest is the PS#1 region, the middle is the PS#2 region, and the shallower is the p-well region. The embodiments herein demonstrate better electric field shaping from these PS#1 and PS#2 structures.

[0311] In embodiments herein, another advantage of including a PS#2 region is that PS#2 functions as a secondary p-well region. The design of the p-well region must satisfy several different constraints: the electrical dose of the p-well region can be large enough to achieve the desired breakdown voltage, and at the same time, the doping of the p-well region near the gate oxide region where the MOS channel is formed can be low enough to achieve a reasonably low threshold voltage.

[0312] In this embodiment, the p-well region can satisfy the conflicting requirements. By placing PS#2 below the N+ source region, it relaxes the design of the p-well region, whose purpose is now simply for channel definition and channel formation. In the embodiments herein, the p-well does not need to be designed to support breakdown voltage. The embodiments herein give the designer more flexibility to design the p-well region appropriately only for MOS channel formation.

[0313] In embodiments herein, the PS#1 is formed after a trench is etched in the N+ source region at the center of the SiC DMOSFET unit cell. The advantage of this trench is that it moves the electric field location farther from the gate-oxide interface to the center of the SiC DMOSFET unit cell. In this embodiment, etching a recess trench in the N+ source region effectively creates a deeper PS#1 region. The electric field moves farther from the gate-oxide region, which results in more robust blocking capability. In embodiments herein, one reason for forming a trench is because ion implantation, especially deep ion implantation, into SiC is difficult. A deep PS#1 sinker region can be created for the source trench. In embodiments herein, etching a trench followed by ion implantation allows for the creation of a deeper PS#1 region, which is effective and achieves functionality.

[0314] In embodiments herein, reducing the oxide allows for a thinner oxide region to be formed because the trench helps form a deeper PS#1 due to the source trench. SiC DMOSFETs require a thicker oxide to prevent breakdown in the dielectric field. In embodiments herein, introducing a P-type sinker region allows for the use of a thinner oxide.

[0315] In embodiments herein, SiC DMOSFET devices are fabricated using a series of masking steps followed by either ion implantation or etching and deposition steps. In embodiments herein, a series of structures, or unit cells, are fabricated using photolithography, which is used to mask specific portions of a wafer or device, perform specific steps, then remove the mask and perform other steps. Minimizing the number of steps is crucial for cost-effectiveness. That is, if the number of steps can be reduced in some way, the cost structure will be lower. Additionally, certain steps in the fabrication of SiC are expensive, and embodiments herein minimize the number of these expensive steps. For example, ion implantation is a relatively expensive step in SiC. P-wells, P-plugs, and N+ source regions are fabricated using ion implantation. Ion implantation is an expensive step, and deeper ion implants, in particular, are even more expensive. Therefore, minimizing deep ion implants is important. Furthermore, P-type implants are 5 to 10 times more expensive than N-type implants because they must be performed at higher temperatures (400 to 1000°C), as opposed to N-type implants, which can be performed at room temperature. Therefore, minimizing the P-type implant is also important.

[0316] In the embodiments herein, the wafer first undergoes a series of ion implantation steps, which are typically referred to as the front end of the process, followed by a high temperature anneal, which is noteworthy. It is used to anneal the implant damage and electrically activate the implant. The back end of the process typically consists of forming the gate oxide, ILD, and other metallization steps.

[0317] In embodiments herein for fabricating SiC DMOSFET structures, photolithography is used to mask certain portions of the wafer to create p-well regions, after which a subsequent masking step can be used to realize N+ source regions, followed by another masking step to realize p+ plug regions. The wafer needs to be annealed to activate the implanted regions. After this, a gate oxide or gate dielectric can be grown by thermal oxide or using a deposited oxide. Gate metallization can be formed using polysilicon or other refractory metals. The gate metallization is then selectively patterned and etched to access the N+ source regions, after which an ILD is deposited and then patterned to realize windows to create these ohmic contacts for the N+ source regions. Ohmic contacts can be realized on the backside of the wafer for the drain region. At the end of the process, source interconnect metallization is used to connect the various unit cells.

[0318] SiC MOSFETs are typically fabricated with several masking steps. Some of these masking steps may be for forming implant regions, while others are for forming structures such as gate oxide, ILD, etc. All embodiments herein are performed with 11 masking steps without increasing masking steps for any additional features such as PS#1, PS#2, source trench formation, or other structures in the embodiments.

[0319] In SiC, ion implantation is the method for introducing dopants because diffusion does not work well. Therefore, a higher implant energy is required to make the PS#1 region deeper than the p-well region. In embodiments herein, either aluminum or boron is typically used to achieve P-type regions in SiC. Therefore, to achieve the PS#1 and deep PS#1 regions, embodiments herein use boron implantation instead of aluminum implantation because, for a given energy, boron implantation can result in a deeper region compared to aluminum implantation. Another way to achieve a deep PS#1 region is to use a much higher energy and still use aluminum as the P-type dopant.

[0320] In one embodiment herein, a p-well region is formed, followed by the formation of an N+ source region. While forming the N+ source region, ion implantation is performed to realize the PS#2 region. The same masking step is used to form the N+ source region and the PS#2 region. In an embodiment herein, this allows the PS#2 region to be realized exactly below the N+ source region.

[0321] In embodiments herein, the N+ source implant is self-aligned to the p-well implant to reduce or eliminate misalignment that can occur when the two regions are realized in different masking steps.

[0322] To achieve sub-0.5 micron or sub-1 micron channel lengths in the embodiments herein, the first p-well region is formed using conventional implant masking steps. A dielectric layer of sufficient thickness is deposited, then photolithography is used to selectively pattern this layer, and then an ion implant is performed to achieve the p-well region. Once this is done, a second dielectric layer is deposited over this patterned first dielectric layer and then subjected to a blanket etch. This allows for the N+ source implant to be performed. This provides a dielectric spacer region that defines the receiving area. Therefore, by selecting an appropriate thickness for the second dielectric layer, the MOS channel length can be defined.

[0323] In embodiments herein, to achieve a 0.5 micron wide channel, a p-well region may first be created using conventional photolithography techniques, for example by depositing and patterning a silicon dioxide layer, followed by depositing a second silicon dioxide layer of a thickness equal to 0.5 microns. This layer is then etched downward to achieve a 0.5 micron spacer. When an N+ source implant is performed, the MOS channel length is effectively 0.5 microns.

[0324] In this embodiment, the channel length is defined not by the limitations of lithography techniques, but by the ability to deposit a dielectric layer, e.g., silicon dioxide, where the dielectric layer has much better control: the dielectric layer or silicon dioxide layer can be deposited with much better resolution than lithography allows.

[0325] In one method, called a subtractive method, the process first fabricates the N+ source, then deposits a dielectric layer, and then forms the P+ layer through polysilicon variation. Embodiments herein perform an additive method, first forming the p-well, then depositing a dielectric of controlled thickness that defines the channel length, and then placing the N+ source. Thus, the order of the N+ and p-well is reversed in embodiments herein compared to how prior art SiC DMOSFETs are formed.

[0326] Embodiments herein avoid implanting an N+ source region into the gate region. In SiC MOSFET structures, a parasitic NPN transistor exists that can be triggered when switching the device from off to on or on to off very fast, but not during normal operation.

[0327] In the embodiments herein, the trench to the N+ source region is formed before the implantation of the PS#1 region, resulting in a deeper PS#1 region. However, another advantage of doing this is that it also allows the N+ source region to be removed from portions of the device where it is not desired to be implanted. Therefore, this is a second advantage of having the trench etched to the N+ source region. The same masking step is used to perform the SiC dry etch and then implant the PS#1 region. This is accomplished with only one masking step. In one embodiment, the PS#2 region is formed along with the N+ source region in the same masking step. The SiC trench and PS#1 region are again formed using the same masking step. In this embodiment, four features are created using two masking steps.

[0328] In embodiments herein, the cost of the PS#1 sinker is reduced because deep ion implantation does not need to be used. High-dose deep ion implantation is expensive. Also, having a deep P+ at the periphery is beneficial to prevent possible breakdown regions. In embodiments herein, a single step is used to create PS#1 and the trench, thus avoiding breakdown regions at the periphery. When forming a self-aligned MOS channel, an N+ source region is formed anywhere that has a p-well region that extends to the periphery of the device. In embodiments herein, breakdown at the periphery due to the formation of the trench and PS#1 is avoided.

[0329] The embodiment shown in Figure 2A is a unit cell of the cross-sectional structure of a SiC DMOSFET. The critical region of this device is the p-well region 203, formed by ion implantation or epitaxial regrowth of p-type species such as aluminum or boron. There are N+ source regions 204, an N drift layer 202, and an N+ substrate 201. In the on-state, when a gate voltage is applied to the polysilicon gate 206, current flows vertically from the drain 201, through an inversion layer formed on top of the p-well layer 203, through the N+ source region 204, and out through the source metallization 208. In the off-state, or blocking state, a voltage is supported across the p-well 203, N-drift layer 202 junction, resulting in a PN junction formed between the p-well and N-drift layer. A voltage applied to the structure is supported across this PN junction in reverse bias. A power MOSFET has several key features, including the unit cell pitch (the repeating unit of the MOSFET), the channel length (the portion of the p-well where the inversion channel is formed), the distance between two consecutive p-wells (called the JFET region or JFET gap), and the thickness of the gate oxide 205. Another feature is the ILD layer 207, which is used to insulate the source interconnect metallization 208 from the polysilicon gate 206. At the very center of the unit cell is a P+ plug layer 209, which is grounded by the N+ source metallization. The purpose of the p+ plug in a SiC DMOSFET is to ground the p-well region with the N+ source contact. Typically, the depth of the p+ plug implant is shallower than the p-well region, as shown in Figure 2A. The DMOSFET device structure can result in high electric field concentrations at the corners of the p-well region 203, resulting in high electric fields within the gate oxide layer 205, especially during high drain bias (blocking mode) operation. The high critical electric field for breakdown in 4H-SiC (∼3 MV / cm) results in very high (>5 MV / cm) electric fields within the gate oxide. Fowler-Nordheim tunneling currents are observed at such high electric fields in the gate oxide, which can result in trapped charges in the gate oxide, reducing device reliability. In embodiments herein, the lateral spacing between p-well regions (JFET regions) is narrow enough to suppress the electric field within the gate oxide while ensuring that the on-resistance of the MOSFET is sufficiently low.

[0330] Figure 2B is a breakdown simulation of the SiC MOSFET shown in Figure 2A. The simulation shows a peak electric field located at the corner of the p-well region, which results in a particularly high electric field in the gate oxide layer. The electric field is strongly concentrated at the corner of the p-well region because it is the region of greatest curvature (a limitation of this embodiment).

[0331] The embodiment shown in Figure 3 is a cross-sectional unit cell of a SiC DMOSFET. The critical region of this device is the p-well region 303, formed by ion implantation or epitaxial regrowth of p-type species such as aluminum or boron. There is an N+ source region 304, an N drift layer 302, and an N+ substrate 301. In the on-state, when a gate voltage is applied to the polysilicon gate 306, current flows vertically from the drain 301, through an inversion layer formed on top of the p-well layer 303, through the N+ source region 304, and out through the source metallization 308. A power MOSFET has several key features, including the unit cell pitch, which is the repeating unit of the MOSFET; the channel length, which is the portion of the p-well where the inversion channel is formed; the distance between two consecutive p-wells, called the JFET region or JFET gap; and the thickness of the gate oxide 305. Another feature is the ILD layer 307, used to insulate the source interconnect metallization 308 from the polysilicon gate 306. Here, the P+ plug region 209 of the SiC DMOSFET from FIG. 2A is replaced with a deep P-type sinker #1 (PS#1) region 309. The depth of the PS#1 region is greater than the depth of the p-well region. During the off-state or blocking state, the structure shown in FIG. 2A breaks down between the p-well 203 and the N-drift layer 202, especially at the curvature of the p-well region. However, with the PS#1 region 309 introduced in FIG. 3, the electric field or main region where breakdown would occur is now essentially in the middle of the figure, between the PS#1 region 309 and the N-drift layer 302. The presence of the deeper PS#1 region shifts the peak electric field location from the corner of the p-well region 303 to the PS#1 region 309. The location of the peak electric field in the 4H-SiC during high drain bias operation is shifted farther from the gate oxide 305. The electric field in the gate oxide 305 is lower than that of the device in FIG. 2A.

[0332] 4A-4R illustrate the process for fabricating the structure shown in FIG. 3. The fabrication process for the SiC DMOSFET is on a SiC substrate 401 with appropriate doping (10 ohms) for the epilayer 402 shown in FIG. 4A. 14 ~10 18 cm -3 It starts with the use of a 4H-SiC Si-face epitaxial wafer with a thickness (1 μm to 300 μm). A blanket hard mask 403 (silicon dioxide, silicon nitride, silicon oxynitride, or nickel) is applied. A CVD deposited layer of metal such as SiO2 (having a thickness ranging from 50 nm to 5 μm) is deposited in FIG. 4B and then patterned using photolithography, as shown in FIG. 4C, followed by dry etching (e.g., using reactive ion etching). In FIG. 4D, a P-type implant 404 (at an energy ranging from 10 keV to 800 keV, 10 12 cm -2 ~10 15 cm -2 ion (including boron or aluminum) at an implant dose in the range of 10 keV to 500 keV, into the p-well 405 in FIG. 4E. The mask 403 is removed, and another hard mask layer 406 is deposited (including CVD-deposited silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness in the range of 50 nm to 5 μm) and patterned in FIG. 4F to define the N+ source region. Note that for the source (SRC) implant, the center of the unit cell is masked. As shown in FIG. 4G, the SRC (n+ source region) 407 is implanted with n-type (n+) impurities 408 (including nitrogen or phosphorus) at an energy in the range of 10 keV to 500 keV, for a total of 10 μm. 13 cm -2 ~10 16 cm -2After removing hard mask 406, another hard mask layer 409 is deposited and patterned as shown in FIG. 4H. PS#1 region 411 is formed by implanting p-type impurities 410 in FIG. 4H. The deep PS#1 region can be formed using ion implantation of aluminum or boron, which are commonly used p-type dopants in 4H-SiC. Boron can be advantageously used to form this deep P-type sinker region because it has a significantly higher implant range compared to aluminum, and deep implants using boron can be formed at lower ion implantation energies. In one example, the PS#1 region can be formed with a boron implant that has a depth 20-50% higher than the p-well region. The boron implant can be performed at a dose of 10 12 cm -2 ~10 15 cm -2 The implantation dose may include an energy range of 10 keV to 800 keV, with a dose range of 10 keV to 800 keV. In related embodiments of the present invention, the doping profile of the PS#1 region may be formed with a gradually decreasing doping concentration with a peak value at the SiC surface. This graded doping profile for the PS#1 region can prevent the formation of sharp corners in the three-dimensional landscape and is beneficial for spreading the peak electric field over a larger area during high drain bias operation, resulting in a higher breakdown voltage. In one example, the PS#1 region is formed at a dose of 10 keV close to the SiC surface. 19 cm -3 ~I0 20 cm -3 can be formed with peak doping in the range of 10 14 ~10 16 cm -3The linearly graded doping profile of the PS#1 region ensures that a sufficient portion of the drain potential is supported in the PS#1 region and not just in the N drift region. This results in a pseudo-charge balance structure, which promotes breakdown across a larger SiC region, resulting in a lower critical electric field at breakdown and, consequently, a lower electric field in the gate insulator. Following this, in Figure 41, hard mask 409 is removed (using either dry or wet etching techniques commonly practiced by those skilled in the art). Next, in Figure 4J, oxide layer 412, the gate oxide, is thermally grown or deposited using chemical vapor deposition (CVD). The gate oxide thickness can range from 10 nm to 100 nm. Either dry or wet thermal oxidation can be used for oxide growth. Plasma-enhanced CVD (PECVD) or low-pressure CVD (LPCVD) can be used for gate oxide deposition. Next, in Figure 4K, a polysilicon gate layer is deposited on top 413. The polysilicon layer can be deposited using PECVD or LPCVD. The polysilicon layer can be degenerately doped in situ with boron or phosphorus, or in a subsequent step. In-situ doping can be achieved by adding a PH3 precursor to the polysilicon deposition chemistry. Post-deposition doping of the polysilicon can be performed by depositing a layer of POCh, followed by a drive-in step at a temperature in the range of 700-900°C. As shown in Figure 4L, a hard mask 414 is deposited on top and patterned. The polysilicon gate layer 413 is etched using the patterned mask layer 414 in Figure 4M. The mask layer 414 is then removed from the top in Figure 4N. An interlayer dielectric (ILD) layer 415 (comprising a 50 nm to 1000 nm thick silicon dioxide, silicon nitride, silicon oxynitride layer, or stacked combinations thereof) is deposited on the wafer, a hard mask 416 is deposited and patterned on top to define ILD openings, and the ILD layer is patterned using the hard mask 416, as shown in Figure 40. Furthermore, the gate oxide is etched using the same mask 416 in Figure 4P.Next, the mask 416 is removed, and in FIG. 4Q, the exposed SiC surface. On the surface, a nickel silicide region 417 is formed. The interconnect metal layer 418 (either Al or Ag or Au) is deposited and patterned on the top and bottom of the chip of FIG. 4R.

[0333] The main problem in the prior art device of FIG. 1A recognized by the inventors of the present invention is that the p-well region does not effectively shield the sensitive gate oxide from the high electric field present in 4H-SiC, especially during high drain bias (blocking mode operation). The presence of the deeper PS#1 region shifts the peak electric field position from the corner of the p-well region to the PS#1 region. In other words, the position of the peak electric field in 4H-SiC during high drain bias operation has moved further away from the gate oxide.

[0334] The advantage of this embodiment is that the breakdown position has moved from the corner of the p-well region to the base of the newly formed PS#1 region, which is further away from the gate oxide interface and deeper within the semiconductor. The electric field in the gate oxide of the device structure incorporating the PS#1 region is significantly lower than that of the prior art device shown using device simulation with SILVACO ATLAS in FIG. 5B.

[0335] The embodiment shown in Figure 5A is a cross-sectional unit cell of a vertical power DMOSFET. The critical region of this device is the p-well region 503, formed by ion implantation or epitaxial regrowth of p-type species such as aluminum or boron. There are N+ source regions 504, an N drift layer 502, and an N+ substrate 501. In the on-state, when a gate voltage is applied to the polysilicon gate 506, current flows vertically from the drain 501, through an inversion layer formed on top of the p-well layer 503, through the N+ source region 504, and out through the source metallization 508. A power MOSFET has several key features, including the unit cell pitch, which is the repeating unit of the MOSFET; the channel length, which is the portion of the p-well where the inversion channel is formed; the distance between two consecutive p-wells, called the JFET region or JFET gap; and the thickness of the gate oxide 505. Another feature is the ILD layer 507, used to insulate the source interconnect metallization 508 from the polysilicon gate 506. Here, a second P-type sinker #2 (PS#2) region 510 below the N+ source region 504 is formed in addition to the PS#1 region 509 already described in the embodiment shown in Figure 3. The PS#2 region is formed deeper than the p-well region 503 and shallower than the PS#1 region 509. For example, the PS#2 region 510 can be 20% deeper than the p-well region 503, and the PS#1 region 509 can be 20% deeper than the PS#2 region 510.

[0336] The presence of the PS#2 region results in the sharing of the peak electric field between the PS#1 and PS#2 regions under high drain bias operation. The presence of the PS#2 region mitigates the peak electric field maximum in the device structure under high drain bias conditions. In the prior art SiC MOSFET shown in Figure 1A, the design of the p-well region must satisfy conflicting requirements. The electrical dose in the p-well region below the N+ source region must be high enough to prevent reach-through breakdown under off-state (high drain bias) operation. At the same time, however, the surface doping of the p-well region must be low enough to maintain a reasonably low gate threshold voltage and device on-resistance. In this context, the PS#2 region introduced in this embodiment can be considered a secondary p-well region and can be designed primarily to prevent reach-through breakdown and properly shape the electric field profile under high drain bias operation. The presence of the PS#2 region frees up constraints on the design of the primary p-well region, which can be used for on-state related device metrics such as gate threshold voltage and on-resistance. The introduction of the PS#2 region gives the designer more flexibility to design a p-well region suitable only for MOS channel formation, since the p-well region does not need to be designed for the purpose of supporting breakdown voltage.

[0337] Breakdown simulation of a SiC DMOSFET designed according to the two embodiments described in FIGS. 3 and 5A. FIG. 5B shows that the peak electric field position has shifted from the corner of the p-well region to the center of the unit cell. This results in a lower electric field in the gate oxide layer.

[0338] 6A-6J illustrate the process for fabricating the structure shown in FIG. 5a. The fabrication process for the SiC DMOSFET is on a SiC substrate 601 with appropriate doping (10 ohms) for the epilayer 602 shown in FIG. 6A. 14 ~10 18 cm -3The process begins with the use of a 4H-SiC Si-face epitaxial wafer with a thickness (1 μm to 300 μm). A blanket hard mask 603 (comprising a CVD-deposited layer of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm) is deposited in Figure 6B and then patterned using photolithography, as shown in Figure 6C, followed by dry etching (e.g., using reactive ion etching). In Figure 6D, a P-type implant 604 (at an energy ranging from 10 keV to 800 keV, 10 12 cm -2 ~10 15 cm -2 ion implantation (including boron or aluminum at an implant dose in the range of 10 keV to 500 keV) to form the p-well 605 in FIG. 6E. The mask 603 is removed, and another hard mask layer 606 is deposited (including CVD-deposited silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness in the range of 50 nm to 5 μm) and patterned in FIG. 6F to define the N+ source region. Note that the center of the unit cell is masked for the source (SRC) implant. As shown in FIG. 6G, the SRC (n+ source region) 607 is implanted with n-type (n+) impurities 608 (including nitrogen or phosphorus) at an energy in the range of 10 keV to 500 keV, for a total of 10 μm. 13 cm -2 ~10 16 cm -2 The PS#2 region 609 is formed by implanting P-type impurities 610, as shown in FIG. 6(h). The deep PS#2 region can be formed using ion implantation of aluminum or boron, which are p-type dopants commonly used in 4H-SiC. Boron can be advantageously used to form this deep P-type sinker region because it has a significantly higher implant range compared to aluminum, and deep implants using boron can be formed at lower ion implant energies. When using aluminum, the PS#2 region can be formed using implant energies in the range of 100 keV to 1 MeV, and 10 13 cm -2 ~10 16 cm-2 When using boron, the PS#2 region can include implant energies ranging from 50 keV to 800 keV, and implant doses ranging from 10 13 cm -2 ~10 16 cm -2 The implantation dose can include implant doses in the range of 100 keV to 1 MeV. The same hard mask 606 used to form the N+ source region is used to define the ion-implanted PS#2 region. In this case, the PS#2 region is self-aligned below the N+ source region. In Figure 61, the hard mask 606 is removed, and another hard mask layer 612 is deposited and patterned. The PS#1 region 611 is formed by implantation of P-type impurities 613, which can include aluminum or boron. Boron has a significantly higher implant range compared to aluminum, so it can be advantageously used to form the PS#1 region, and deep implants using boron can be formed at lower ion implant energies. When using aluminum, the PS#1 region can be formed using implant energies in the range of 100 keV to 1 MeV, and 10 13 cm -2 ~10 16 cm -2 When using boron, the PS#1 region can include implant energies ranging from 50 keV to 800 keV, and implant doses ranging from 10 13 cm -2 ~10 16 cm -2The PS#2 region can be formed deeper than the p-well region, but deeper than the PS#1 region. As a second example of this embodiment, the PS#2 region can be 20% deeper than the p-well region, and the PS#1 region can be 20% deeper than the PS#2 region. In a related embodiment of the present invention, the doping profiles of the PS#1 and PS#2 regions can be formed with gradually decreasing doping concentrations that peak at the SiC surface. This graded doping profile for the PS#1 and PS#2 regions can prevent the formation of sharp corners in the three-dimensional landscape and is beneficial for spreading the peak electric field during high drain bias operation over a larger area, resulting in a higher breakdown voltage. As an example, the PS#1 and PS#2 regions can be formed with 10 Å or 20 Å near the SiC surface and near the N+ source region, respectively. 19 cm -3 ~10 20 cm -3 The doping concentration in the PS#1 and PS#2 regions is a function of depth into the silicon carbide, relative to the background N-drift layer doping (10 14 ~10 16 cm -3 The linearly graded doping profile of the PS#1 / PS#2 regions results in a significant portion of the drain potential being supported within the PS#1 / PS#2 regions, not just the N drift region. This results in a pseudo-charge balance structure, which This promotes breakdown over a larger SiC region, resulting in a lower critical electric field at breakdown and therefore a lower electric field in the gate insulator. Following formation of the PS#1 region, hard mask 612 in FIG. 6J is removed (dry or wet etch). The remaining steps in the process for creating the structure shown in FIG. 5A follow the exact same steps as shown in FIGS. 4J-4R.

[0339] This "staircase" arrangement of the PS#1 and PS#2 regions with specific depths can result in a lower electric field in the gate oxide under high drain bias operation. Another advantage of the PS#2 region is that the p-well region can be made shallower and with a lower implant dose, which can reduce the device's on-resistance and simultaneously increase the gate threshold voltage, both of which are desirable from an application perspective. Therefore, a better tradeoff between off-state and on-state performance is possible with the teachings of the present invention.

[0340] The embodiment shown in FIG. 7A is a cross-sectional unit cell of a SiC DMOSFET. The critical region of this device is the p-well region 703, formed by ion implantation or epitaxial regrowth of p-type species such as aluminum or boron. There is an N+ source region 704, an N drift layer 702, and an N+ substrate 701. In the on-state, when a gate voltage is applied to the polysilicon gate 706, current flows vertically from the drain 701, through an inversion layer formed on top of the p-well layer 703, through the N+ source region 704, and out through the source metallization 708. A power MOSFET has several key features, including the unit cell pitch, which is the repeating unit of the MOSFET; the channel length, which is the portion of the p-well in which the inversion channel is formed; the distance between two consecutive p-wells, called the JFET region or JFET gap; and the thickness of the gate oxide 705. Another feature is the interlayer dielectric (ILD) layer 707, used to insulate the source interconnect metallization 708 from the polysilicon gate 706. Here, trench 711 is etched into N+ source region 704 before implanting PS#1 region 709. Here, in addition to PS#1 region 709, PS#2 region 710 is formed below N+ source region 704. The PS#2 region is formed deeper than p-well region 703 but shallower than PS#1 region 709. It is desirable to move the electric field location away from the gate-oxide interface for robust blocking capability in device operation, improving device reliability. Moving the breakdown location to the center of the unit cell, farthest from gate oxide 705, is one embodiment; by etching recess trench 711 into N+ source region 704, one can effectively create a deeper PS#1 region than those shown in FIGS. 3 and 5A, further moving the electric field away from the gate oxide region.

[0341] The PS#1 region is designed to have the deepest depth of any P-type sinker region. While boron implantation is one technique for forming such deep P-type regions in SiC, given the full range of commercially available ion implanters, ion implantation into SiC is not an easy process, and deep ion implantation is particularly challenging. The function of the N+ source region, also called a source trench, is to allow the PS#1 region to be realized with lower ion implantation energy, reducing the cost and time of this implantation step without sacrificing implantation depth. In this embodiment, the trench can be dry-etched into the SiC after the N+ source region implantation but before the PS#1 region implantation. The same hard mask layer used for the PS#1 implantation can be used to etch the source trench into SiC. In this embodiment, the hard mask layer is patterned first, followed by dry-etching the trench into the SiC, followed immediately by the ion implantation of the PS#1 region. The source trench formation naturally extends to the depth of the PS#1 region. Therefore, the PS#1 region can be achieved with lower ion implantation energy, which reduces the cost / time of this implantation step without compromising implantation depth. The formation of the source trench also removes the N+ source region and allows for a direct connection between the P-well region and the N+ source ohmic contact, thereby grounding the p-well and shorting the P-well region to the N+ source region.

[0342] FIG. 7B is a breakdown simulation of a SiC MOSFET designed according to the embodiment shown in FIG. 7A, showing that the peak electric field location is moved from the corner of the p-well region to the center of the unit cell, resulting in a lower electric field in the gate oxide layer.

[0343] 8A-8BB illustrate the process of fabricating the SiC DMOSFET structure shown in FIG. 7A. The fabrication process of the SiC DMOSFET is on a SiC substrate 801 with appropriate doping (10 ohms) for the epilayer 802 shown in FIG. 8A. 14 ~10 18 cm -3The process begins with the use of a 4H-SiC Si-face epitaxial wafer with a thickness (1 μm to 300 μm). A blanket hard mask 803 (comprising a CVD-deposited layer of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm) is deposited in Figure 8B and then patterned using photolithography, as shown in Figure 8C, followed by dry etching (e.g., using reactive ion etching). In Figure 8D, a P-type implant 804 (at an energy ranging from 10 keV to 800 keV, 10 12 cm -2 ~10 15 cm -2 8E to form p-well 805. Mask 803 is removed and another hard mask layer 806 is deposited (including CVD-deposited silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm) and patterned in FIG. 8F to define N+ source regions. As shown in FIG. 8G, n+ source regions 807 are formed by implanting n-type (n+) impurities 808 (including nitrogen or phosphorus) at an energy ranging from 10 keV to 500 keV for 10 s. 13 cm -2 ~10 16 cm -2The PS#2 region 809 is formed by implanting a P-type impurity 810 in FIG. 8H. The deep PS#2 region can be formed using an ion implant of aluminum or boron, which are p-type dopants commonly used in 4H-SiC. Boron has a significantly higher implant range compared to aluminum, so it can be advantageously used to form this deep P-type sinker region, and deep implants using boron can be formed at lower ion implantation energies. The patterned hard mask 806 is removed from the top of FIG. 81. Another hard mask layer 811 is formed on top of FIG. 8J and patterned in FIG. 8K. The patterned mask 811 is used to etch 812 into the substrate in FIG. 8L to form a recessed region. A source trench, which is a recessed region 813, is formed in the substrate through the source region in FIG. 8M. A P-type implant 814 in FIG. 8N is performed to create the PS#1 region. When using aluminum, the PS#1 region is suitable for implant energies ranging from 100 keV to 1 MeV, and 13 cm -2 ~10 16 cm -2 When using boron, the PS#1 region can include implant energies ranging from 50 keV to 800 keV, and implant doses ranging from 10 13 cm -2 ~10 16 cm -2 The PS#1 815 can include an implant dose in the range of 0.5 to 1.5 . The PS#1 815 is formed by a self-aligned implant of p-type impurities in FIG. 80. As described more fully in the embodiment above, it is preferable to use a linearly graded doping profile for the PS#1 / PS#2 regions instead of a uniform (abrupt) doping profile, so that a sufficient portion of the drain potential is supported within the PS#1 / PS#2 regions and not just the Ndrift region. This results in a quasi-charge balance structure, which promotes breakdown over a larger SiC region, resulting in a lower critical electric field at breakdown and, consequently, a lower electric field within the gate insulator.

[0344] The PS#1 region is designed to be the deepest of the P-type sinker regions using boron implantation, and trench formation naturally extends the depth of the PS#1 region. The same hard mask used to etch the source trench 811 is used to define the PS#1 region. Those skilled in the art will appreciate that SiC trenches can be formed using dry etching techniques, including reactive ion etching, inductively coupled plasma (ICP)-RIE, and the like. While Figure 7A shows a 90° sidewall slope for this trench region, forming a trench region with sidewalls at a lower angle (60-90°) is advantageous because it reduces the curvature of the PS#1 region and therefore improves the blocking performance of the device.

[0345] The patterned hard mask 811 is removed from the top in Figure 8P. In Figure 8Q, an oxide layer 816 for the gate oxide is grown. A polysilicon gate layer is grown on top 817 in Figure 8R. The polysilicon layer can be deposited using PECVD or LPCVD. The polysilicon layer can be degenerately doped with boron or phosphorus in situ or in a subsequent step. In-situ doping can be achieved by adding a PH3 precursor to the polysilicon deposition chemistry. Post-deposition doping of the polysilicon can be achieved by depositing a layer of POCh followed by a drive-in step at a temperature ranging from 700 to 900 °C. As shown in Figure 8S, a hard mask 818 is deposited on top and patterned. The polysilicon gate layer 817 is etched using the patterned mask layer 818 in Figure 8T. The mask layer 818 is then removed from the top in Figure 8U. An interlayer dielectric (ILD) layer 819 (comprising a 50 nm to 1000 nm thick silicon dioxide, silicon nitride, silicon oxynitride layer, or stacked combinations thereof) is deposited on the wafer in Figure 8V. A hard mask 820 is deposited and patterned to define the ILD openings in Figure 8W. The ILD layer is patterned using the hard mask 820, as shown in Figure 8X. Furthermore, the gate oxide 816 is etched using the same mask 820 in Figure 8Y. The mask 820 is then removed in Figure 8Z. Nickel silicide regions 821 are formed on the exposed SiC surface in Figure 8AA. An interconnect metal layer 822 (either Al or Ag or Au) is deposited and patterned on the top and bottom of the chip in Figure 8BB.

[0346] An advantage of embodiments herein is that by etching the source trench region prior to implanting the PS#1 region, the breakdown location is moved further into the semiconductor and further away from the gate oxide layer. Due to the inherent hardness of silicon carbide, the observed range (depth) of implanted dopants is significantly lower than in silicon. For example, forming deep (>0.3 pm) implanted layers in silicon carbide requires extremely high implant energies (>300 keV), which require dual or triple implant species, dramatically reducing throughput and increasing the cost of these implantation steps. By forming the source trench as described in this embodiment, the dual / triple implantation step is eliminated, allowing for the low cost of using a high-throughput single implant to achieve the PS#1 region.

[0347] Embodiments relate to SiC DMOSFET power devices that can be used to fabricate self-aligned power MOSFETs.

[0348] One embodiment relates to increasing MOS channel density.

[0349] One embodiment relates to increasing the effective field effect mobility.

[0350] One embodiment relates to improved device reliability.

[0351] One embodiment relates to reducing the ON resistance for a given chip size.

[0352] One embodiment relates to the design and manufacture of self-aligned power devices.

[0353] One embodiment relates to the design and fabrication of MOS channels with submicron channel lengths.

[0354] One embodiment relates to the removal of parasitic N+ source regions inadvertently formed around the periphery of a device.

[0355] The embodiment relates to proper grounding of the p-well region with a source ohmic contact in the active area of ​​the device.

[0356] One embodiment relates to the elimination of parasitic NPN transistors formed in the active and peripheral areas of a self-aligned power device.

[0357] Embodiments relate to the combination of a properly placed source trench and an ion-implanted p+ plug region, allowing for proper grounding of the p-well region within the main active MOSFET area and elimination of the parasitic N+ source region formed around the MOSFET.

[0358] One embodiment involves forming a heavily doped P+ plug region around the periphery of the MOSFET, particularly beneath the gate pad and gate bus regions.

[0359] One embodiment relates to suppressing false turn-on of MOSFETs during fast switching transitions at vulnerable locations due to threshold voltage lowering caused by body bias effects.

[0360] One embodiment relates to improving the maximum dV / dt rating of a MOSFET.

[0361] One embodiment relates to improving the maximum avalanche energy rating of a MOSFET.

[0362] One embodiment relates to a dedicated process step utilized to mask the implantation of N+ source regions at the device periphery, where the P+ plug regions are formed first in this embodiment and the source trenches are formed later in the process during an ILD etch step.

[0363] One embodiment relates to a dedicated hard mask that is applied after the sidewall spacers are formed and before the N+ source implant. This layer prevents the formation of N+ source regions at the device periphery, thus avoiding parasitic NPN structures at the device periphery.

[0364] One embodiment relates to a p-well region (P-well #2) located below the N+ source region and electrically connected to the main p-well region. The P-well #2 provides an additional electrical dose below the N+ source implant, particularly to prevent reach-through breakdown after source trench formation.

[0365] One embodiment utilizes dedicated process steps to implant N+ source regions at the periphery of the device as well as mask the N+ source regions in the center of the unit cells in the active area to allow ohmic contact to the p-well regions.

[0366] One embodiment relates to forming a segmented polysilicon gate metallization around the periphery of the device instead of a continuous gate bus to reduce the gate-body capacitance of the MOSFET.

[0367] One embodiment relates to reducing the gate capacitance of a MOSFET.

[0368] One embodiment relates to increasing the switching speed of a MOSFET.

[0369] The embodiments described herein represent a novel technique for the design and fabrication of self-aligned SiC DMOSFET power devices. Due to the limited mobility achievable in SiC planar DMOSFETs, it is necessary to form sub-micron long n-well channels to avoid degrading the overall power and on-resistance of the MOSFET.

[0370] In a MOSFET, a channel region is formed due to an offset between the p-well and the N+ source region. When the p-well and N+ source region are formed by two separate masking steps, there may be lithographic misalignment, which results in asymmetric MOSFET channel lengths on the two sides of the unit cell. In the embodiments described herein, a MOS To minimize this asymmetry in the channel length, the p-well and N+ source implants are made in a self-aligned manner. To achieve a self-aligned MOSFET, several techniques have been proposed in the literature, including one that uses an oxide spacer approach to form self-aligned p-well and N+ source regions, where the N+ source implant is below the p-well implant.

[0371] Embodiments herein describe several innovative techniques during self-aligned channel formation that not only enable the elimination of misalignment errors during fabrication of SiC MOSFETs, but also the possibility of reducing the channel length, which can be made smaller using narrow spacers. While the self-aligned process offers the advantage of creating arbitrarily short channel lengths and eliminating misalignment, it creates several other problems with respect to the structure of the device outside of the unit cell, as the n+ region is co-incident with the p-well region.

[0372] In conventional MOSFETs where the p-well and N+ source regions are not self-aligned, there is a dedicated masking step used to form the N+ source implant. In the embodiments described herein, in a self-aligned process, there is no dedicated masking step to perform the N+ source implant. There are dedicated masking steps to perform the p-well implant, followed by depositing spacers, then etching the spacers, followed by an implant to achieve the N+ source region. Everywhere there is a p-well region, there is also an N+ source implant. It is undesirable to have an N+ source implant at the periphery of the device. It is important to terminate the device with only a p-type implant. Various embodiments described herein introduce techniques that can remove the N+ source implant at the periphery of the device and replace it with some other region.

[0373] The active area of ​​a MOSFET is where current conduction occurs, while the peripheral area of ​​the MOSFET is where edge termination of the device is provided to block any voltage. The gate pad and gate bus regions are also considered to be part of the peripheral area of ​​the MOSFET for purposes of describing the innovations in this document. In the embodiments described herein, the combination of a properly placed source trench and an ion-implanted p+ plug region allows for proper grounding of the p-well region in the main active MOSFET area and elimination of the parasitic N+ source region formed around the periphery of the MOSFET.

[0374] In a conventional MOSFET without self-alignment, the source implant can be done whenever needed and then a region can be created to ground the p-well. In a self-aligned DMOSFET, the source implant is self-aligned to the p-well, so not only does the p-well extend to the periphery, but the N+ source region also extends to the periphery.

[0375] The parasitic NPN transistor resides in the active region of a MOSFET unit cell, formed by the N+ source region acting as the N+ emitter, the p-well region forming the P base, and the N+ source ohmic contact. The N+ source ohmic contact is absent from the device's periphery and under the gate pad metallization, resulting in the parasitic NPN transistor's emitter and base regions not being shorted together in this region. While the parasitic NPN transistor is not activated under normal DC or switching operation of the MOSFET, operating the device under extreme conditions can cause the parasitic NPN transistor to trigger.

[0376] In the active region, the source trench shorts the emitter and base of this parasitic NPN transistor, ensuring that it does not turn on in the active region of the device. In the periphery of the device, where there is no source trench, the parasitic NPN transistor exists despite being shorted in the active region. The parasitic NPN transistor may turn on in the peripheral region, which is undesirable.

[0377] In embodiments herein, forming source trenches around the periphery of the device and providing p-type implanted plug regions ensures that the parasitic NPN transistor is completely eliminated. Because the emitter of this transistor is completely removed, there is no possibility of any kind of parasitic BJT structure. While a separate masking step is typically performed to mask the N+ source regions from being formed in these locations, in embodiments herein, the source trenches can be advantageously used to remove the parasitic N+ source regions and replace them with p+ plug regions that are self-aligned with the source trenches and electrically connected to the p-well region.

[0378] The doping concentration of the P+ plug region located at the device periphery can be advantageously made very high, thereby avoiding the other parasitic device effects described herein. In a typical power MOSFET device structure, a moderately doped P-well region exists at the device periphery, with or without a parasitic N+ source region, as described above. If the N+ source region is co-incident with the p-well region at the device periphery (i.e., if the n+ source region is not intentionally masked from the peripheral region), this results in partial compensation of the p-type electrical dose of the p-well region. In either case, the p-well region at the device periphery can be highly resistive from an electrical standpoint. During switching of a power MOSFET from its off state to its on state or vice versa, an extremely high rate of change of the drain voltage (or dV / dt) can result in capacitive current flow through this resistive peripheral p-well region, which is collected only by the source ohmic contact in the active region of the MOSFET. In other words, the capacitive current caused by the high dV / dt during device switching must traverse an extremely long distance from the device periphery to the source ohmic contact in the active region. The high resistivity of the p-well regions in prior art MOSFETs can result in significant body bias effects, which have the consequence of lowering the device threshold voltage in those regions. Therefore, these portions of the device may exhibit false turn-on, potentially resulting in device failure / destruction. The highly doped P+ plug region in this embodiment can mitigate these effects by reducing the amount of body bias that occurs in the surrounding regions of the MOSFET, which makes the MOSFET described in this embodiment more resilient to dV / dt-induced failures. In other words, the MOSFET structure described in this embodiment has a higher dV / dt rating than prior art MOSFETs. This reduces switching losses and improves circuit efficiency.

[0379] In one embodiment herein, a dedicated process step is utilized to mask the implantation of the N+ source regions at the device periphery: the P+ plug regions are formed first in this embodiment, and the source trenches are formed later in the process in an ILD etch step.

[0380] In the embodiments herein, source trenches are present in the active region of the device, but not at the periphery of the device. A dedicated masking step is distributed between the formation of sidewall spacers after the p-well implant and before the N+ source implant to mask the N+ source implant from the peripheral region of the MOSFET. The masking layer protects the periphery of the device from the source implant region. A second, deeper p-well region (P-Well #2) is formed using the same masking step used for the N+ source implant. P+ plug regions are formed in a later step in both the active region and the device periphery of the device. Trenches are later etched through the N+ source regions at discrete locations in the active region to contact the P+ plug regions, which are shorted to the N+ source regions by ohmic or silicide metallization.

[0381] In one embodiment herein, the source region implant is masked from the periphery of the device: a dedicated process step is used to mask the N+ source region implant at the device periphery, and the N+ source region in the center of the unit cell in the active area is used to allow ohmic contact to the p-well region.

[0382] In one embodiment herein, the polysilicon metallization is segmented at the periphery of the device, rather than being one continuous layer as is commonly found. After the p-well implant and before the N+ source implant is performed, there is a dedicated masking step interspersed among the formation of sidewall spacers to mask the N+ source regions from both the peripheral area of ​​the device and selected areas within the active area.

[0383] In one embodiment herein, segmenting the polysilicon metallization reduces the parasitic gate-to-body or gate-to-source capacitance. The polysilicon islands are not cut but connected at locations perpendicular to the plane of the drawing. Reducing the parasitic capacitance allows the device to switch faster, which increases circuit efficiency by reducing switching losses.

[0384] The embodiment shown in Figure 10 is a unit cell and device periphery of a cross-sectional structure of a SiC DMOSFET. The critical region of this device is the p-well region 203, formed by ion implantation or epitaxial regrowth of p-type species such as aluminum or boron. There are N+ source regions 204, N drift layer 202, and N+ substrate 201. In the on-state, when a gate voltage is applied to the polysilicon gate 208, current flows vertically from the drain 201, through an inversion layer formed on top of the p-well layer 203, through the N+ source region 204, and out through the source metallization 211. In the off-state or blocking state, a voltage is supported across the p-well 203, N drift layer 202 junction, and there is a PN junction formed between the p-well and N drift layer. A voltage applied to the structure is supported across this PN junction in reverse bias. A power MOSFET has several important features, including the unit cell pitch, which is the repeating unit of the MOSFET, the channel length, which is the portion of the p-well where the inversion channel is formed, the distance between two consecutive p-wells, called the junction-gate field-effect transistor (JFET) region or JFET gap, and the thickness of the gate oxide 207. Another feature is the ILD layer 209, which is used to insulate the source interconnect metallization 211 from the polysilicon gate 208.

[0385] The source trench region 205 is realized by dry etching through the N+ source layer at selected locations in the device, followed by a p-type ion implantation step to realize a p+ plug region 206 below the source trench. At the very center of the unit cell is a P+ plug layer 206 that is grounded with the N+ source metallization. The purpose of the p+ plug in a SiC DMOSFET is to ground the p-well region with the N+ source contact.

[0386] The formation of the source trench 205 device structure allows for proper grounding of the p-well region in the main active MOSFET area and elimination of the parasitic N+ source region 204 formed around the periphery of the MOSFET. When the N+ source region is formed self-aligned with the p-well region, the formation of the source trench after the N+ source region formation removes the parasitic N+ source region from the device periphery of the chip and from underneath the gate pad area.

[0387] In embodiments herein, the combination of the source trench and ion-implanted P+ plug region serves three important functions. First, it provides proper grounding of the p-well region with the source ohmic contact in the active area of ​​the device, and second, it helps eliminate parasitic N+ source regions inadvertently formed around the periphery of the device. Third, the highly doped P+ plug region increases the dV / dt rating of the MOSFET. In embodiments herein, both of the above ensure the elimination of parasitic NPN transistors that would otherwise form in these regions.

[0388] A parasitic NPN transistor is also present in the MOSFET unit cell (formed by the N+ source region). The N+ emitter (formed by the p-well region) and the P-base (formed by the p-well region) are shorted by the N+ source ohmic contact. However, even at the periphery of the device and under the gate pad metallization, no N+ source ohmic contact exists, and as a result, the emitter and base regions of the parasitic NPN transistor are not shorted in this region. While this parasitic NPN transistor is not activated under normal DC or switching operation of the MOSFET, operation of the device under extreme conditions, such as short circuit or avalanche mode, can result in the simultaneous presence of very high junction temperatures, high dV / dt, and high current densities, which can cause the parasitic NPN transistor to trigger. Typically, a separate masking step is performed to prevent the N+ source regions from forming in these locations. However, in embodiments herein, source trenches can be advantageously used to remove the parasitic N+ source regions and replace them with p+ plug regions that are self-aligned with the source trenches and electrically connected to the p-well region.

[0389] 11A-11FF illustrate the process for fabricating the structure shown in FIG. 10. The fabrication process for the SiC DMOSFET is on a SiC substrate 301, with appropriate doping (10 14 ~10 18 cm -3 The process begins with the use of a 4H-SiC Si-face epitaxial wafer with a surface roughness (SQUID) and thickness (1 μm to 300 μm). A blanket hard mask 303, comprising a chemical vapor deposition (CVD) layer of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness of 50 nm to 5 μm, is deposited in FIG. 1IB, then patterned using photolithography, and then dry-etched using reactive ion etching (RIE), for example, as shown in FIG. 11C. Next, a p-well region is first formed by ion implantation or epitaxial growth using aluminum or boron as p-type impurities. In FIG. 1I-D, 10 12 cm -2 ~10 15 cm-2 A p-type implant 304 containing boron or aluminum at an energy in the range of 10 keV to 800 keV with an implant dose in the range of 0.1 keV is performed to create a p-well 305 in the IE of FIG.

[0390] A second hard mask layer 306 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm in FIG. 1IF, on top of the patterned first hard mask layer 303. This is followed by an anisotropic etch 307 in FIG. 11G to form sidewall spacers 306, as shown in FIG. 11H.

[0391] An n-type implant 308 is performed in FIG. 11I to create n+ source region 309 in FIG. 11J. The n+ source region is formed by ion implantation or epitaxial regrowth with n-type impurities such as nitrogen or phosphorus. This forms source region 309 self-aligned with p-well region 304. First and second hard mask layers 303 and 306, respectively, are removed in FIG. 11K. While the above-described sequence of process steps constitutes one method for forming self-aligned p-well and N+ source regions, other methods may be used to achieve the same result. For example, N+ source region 309 may be first formed after deposition and patterning of a first hard mask layer, followed by further etch-back of the first hard mask layer, which then forms p-well region 304.

[0392] Another mask layer 310 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm at the top of FIG. 11L. The mask layer 310 is patterned in FIG. 11M. The patterned mask 310 is used to etch the substrate 311 of FIG. 1 using a dry etching method to form recessed regions in the SiC. The recessed regions are source trenches 312 formed in the substrate through the source regions of FIG. 11O. The entire N+ source regions are removed by dry etching at these selected locations of the device. Using the same hard mask 310, a p+ plug layer is formed in FIG. 11Q by implantation of a controlled dose of p-type impurities 313, such as aluminum or boron, in FIG. 11P. The depth of the p+ plug layer 314 may preferably exceed the depth of the N+ source implant and, in certain implementations, may exceed the depth of the p-well region. In FIG. 11D, 10 13 cm -2 ~10 17 cm -2 A p-type implant containing boron or aluminum is performed at an energy range of 10 keV to 800 keV with an implant dose in the range of 0.1 keV to 0.5 keV to form a P+ plug region 314. The p+ plug region 314 is formed below the source trench 312, electrically connected to the p-well region 304. The mask layer is removed as shown in Figure HR. The wafer is annealed to activate the implanted impurities.

[0393] The gate oxide, oxide layer 315, is formed in Figure 1IS using thermal oxidation or CVD of a dielectric layer such as silicon dioxide, silicon nitride, or silicon oxynitride. The gate oxide thickness can range from 5 nm to 100 nm. Either dry or wet thermal oxidation can be used for oxide growth. Plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) can be used for gate oxide deposition. Next, in Figure 11T, the polysilicon gate layer 316 is deposited. The polysilicon layer can be deposited using PECVD or LPCVD. The polysilicon layer can be degenerately doped in situ or in a subsequent step with boron or phosphorus. In-situ doping can be achieved by adding a PH3 precursor to the polysilicon deposition chemistry. Post-deposition doping of the polysilicon can be performed by depositing a layer of POCh followed by a drive-in step at temperatures ranging from 600 to 900 °C. A hard mask 317 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, having a thickness ranging from 50 nm to 5 μm, and is patterned on top, as shown in FIG. 11U. The polysilicon layer 316 is etched using the patterned mask layer 317 in FIG. 11V. Next, in FIG. 11W, the mask layer 317 is removed. An ILD layer 318, comprising a 50 nm to 1000 nm thick silicon dioxide, silicon nitride, silicon oxynitride layer, or a stacked combination thereof, is deposited on the wafer in FIG. 11X.

[0394] A hard mask 319 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm at the top, and is patterned on top to define an ILD opening (FIG. 11Y). The ILD layer 318 is etched using the hard mask 319 as shown in FIG. 11Z. Furthermore, the gate oxide 315 is etched using the same mask 319 as shown in FIG. 11AA. Next, the mask 319 is removed as shown in FIG. 11B. Nickel silicide regions 320 are formed on the exposed SiC surface (FIG. 11CC). A mask layer 321 is formed by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm at the top, and is patterned as shown in FIG. 11DD. The ILD layer 318 is etched using the mask 321 as shown in FIG. 11EE. The mask layer 321 is removed as shown in FIG. 11FF. An interconnect metal layer 322, either aluminum or silver or gold, is deposited and patterned on the top and bottom of the substrate. FIG. 11GG.

[0395] In embodiments herein, the same final structure for forming the source trench region and the P+ plug region may alternatively be realized using a slightly different approach. Similar to the method described above, the p-well region and the N+ source region are realized using a self-aligned process. However, in this embodiment, the P plug layer may first be formed using a deep boron or aluminum implant as a buried layer disposed below the N+ source region. Dry etching for realizing the N+ source trench may be performed after the process. The N+ source trench may preferably be realized after a high-temperature annealing process in one embodiment.

[0396] The embodiment shown in Figure 12 is a unit cell and device periphery of the cross-sectional structure of a SiC DMOSFET. The critical region of this device is the p-well region 403, which is formed by ion implantation or epitaxial regrowth of p-type species such as aluminum or boron. There is an N+ source region 404, an N drift layer 402, and an N+ substrate 401. In the on-state, when a gate voltage is applied to the polysilicon gate 407, current flows from the drain 401 to the top of the p-well layer 403. The current flows vertically through the inversion layer formed in the p-well, through the N+ source region 404, and out through the source metallization 412. In the off-state, or blocking, a voltage is supported across the p-well 403, N-drift layer 402 junction, and there is a PN junction formed between the p-well and N-drift layer. A voltage applied to the structure is supported across this PN junction in reverse bias. A power MOSFET has several important features, including the pitch of the unit cell, which is the repeating unit of the MOSFET; the channel length, which is the portion of the p-well where the inversion channel is formed; the distance between two consecutive p-wells, called the JFET region or JFET gap; and the thickness of the gate oxide 407. Another feature is the ILD layer 409, which is used to insulate the source interconnect metallization 412 from the polysilicon gate.

[0397] Dedicated masking steps are interspersed between the formation of sidewall spacers after the p-well implant and before the N+ source implant to mask the N+ source implant from the peripheral regions of the MOSFET. A second, deeper p-well region (P-well #2) 405 is formed using the same masking steps used for the N+ source implant. P+ plug regions 406 are formed in both the active region of the device and the device periphery in a later step. The P+ plug layer 406 is grounded by the N+ source metallization. The purpose of the p+ plug in a SiC DMOSFET is to ground the p-well region with the N+ source contact.

[0398] Trenches 410 are later etched through N+ source regions at discrete locations within the active area to contact the P+ plug regions, which are shorted to the N+ source regions by ohmic silicide 411 metallization. The source trenches 410 are etched into the SiC in selected areas using the same hard mask used to pattern the interlevel dielectric layer (ILD). In embodiments herein, the source trenches 410 serve two functions: first, they reveal the surface of the P+ plug layer previously buried beneath the N+ source regions for subsequent contact with ohmic silicide metal, and second, they reveal the sidewalls of the N+ source regions for subsequent contact with ohmic silicide metal.

[0399] In embodiments herein, a dedicated hard mask or photoresist layer is applied after the sidewall spacers are formed and before the N+ source implant, which prevents the formation of N+ source regions at the periphery of the device, thus avoiding parasitic NPN structures at the periphery of the device.

[0400] In embodiments herein, a second p-well region (P-well #2) 405 is disposed below the N+ source region 404 and is electrically connected to the primary p-well region to provide an additional electrical dose below the N+ source implant, particularly to prevent reach-through breakdown after source trench formation. The source trench etch may inadvertently etch a portion of the primary p-well region below the N+ source region, thereby locally reducing the p-well dose in this region and resulting in undesirable reach-through breakdown at these locations.

[0401] 13A-13GG show the fabrication steps of the structure shown in FIG. 12. The fabrication process of the SiC DMOSFET is on a SiC substrate 501, with appropriate doping (10 14 ~10 18 cm -3The process begins with the use of a 4H-SiC Si-face epitaxial wafer with a thickness (1 μm to 300 μm). A blanket hard mask 503, comprising a CVD-deposited layer of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm, is deposited in FIG. 13B, then patterned using photolithography, and then dry-etched using, for example, RIE, as shown in FIG. 13C. Next, a p-well region is first formed by ion implantation or epitaxial growth using aluminum or boron as p-type impurities. In FIG. 13D, 10 12 cm -2 ~10 15 cm -2 A p-type implant 504 containing boron or aluminum at an energy in the range of 10 keV to 800 keV with an implant dose in the range is performed to create a p-well 505 in FIG. 13E.

[0402] A second hard mask layer 506 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, and has a thickness ranging from 50 nm to 5 μm on top of the patterned first hard mask layer 503 in FIG. 13F. This is followed by an anisotropic etch 507 in FIG. 13G to form sidewall spacers 506 as shown in FIG. 13H. A patterned mask layer 508 is deposited by CVD deposition of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, and has a thickness ranging from 50 nm to 5 μm on top of the patterned mask layer with sidewall spacers in FIG. 13I. The hard mask layer 508 is patterned over the peripheral region of the device.

[0403] In FIG. 13J, an n-type implant 509 is performed to create n+ source regions 510. The n+ source regions are formed by ion implantation or epitaxial regrowth with n-type impurities such as nitrogen or phosphorus. The N+ source regions 510 are formed self-aligned with the p-well region 504. The source regions are formed self-aligned with the p-well region while being masked from the peripheral regions of the device. A deep second p-well region (PWell#2) 511 may be formed simultaneously with the N+ source regions of FIG. 13K. A buried P-well#2 region may be formed using aluminum or boron and may be located below the N+ source regions in the active region of the device. The P-well#2 region is preferably formed using the p-type species boron, which has a larger ion implantation range compared to aluminum in SiC. It is not necessary to mask the p-well region#2 from the peripheral regions of the device.

[0404] In Figure 13L, the first and second hard mask layers 503 and 506 are removed, respectively. Another mask layer 512 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm, at the top of Figure 13M. The mask layer 512 is patterned in Figure 13N. In Figure 13O, a controlled dose of p-type impurities 513, such as aluminum or boron, is implanted to create a p+ plug region 514 buried beneath the N+ source region 510 in Figure 13P. The p+ plug region 514 is electrically connected to the P-well region 504 and the p-well #2 region 511. The p+ plug region may be formed deeper than the P-well region and the p-well #2 region. Next, the mask layer 512 is removed in Figure 13Q, and the implant is activated by a high-temperature anneal.

[0405] The gate oxide, oxide layer 515, is formed in Figure 13R by thermal oxidation or using CVD of a dielectric layer such as silicon dioxide, silicon nitride, or silicon oxynitride. The gate oxide thickness can range from 10 nm to 100 nm. Either dry or wet thermal oxidation can be used for oxide growth. PECVD or LPCVD can be used for gate oxide deposition. Next, in Figure 13S, a polysilicon gate layer 516 is deposited. The polysilicon layer can be deposited using PECVD or LPCVD. The polysilicon layer can be degenerately doped with boron or phosphorus in situ or in a subsequent step. In-situ doping can be performed by adding a PH3 precursor to the polysilicon deposition chemistry. Post-deposition doping of the polysilicon can be performed by depositing a layer of POCh followed by a drive-in step at a temperature ranging from 700 to 900 °C. A hard mask 517 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, having a thickness ranging from 50 nm to 5 μm, and is patterned as shown in FIG. 13T. The polysilicon layer 516 is etched using the patterned mask layer 517 in FIG. 13U. The mask layer 517 is then removed in FIG. 13V. An ILD layer 518, including a 50 nm to 1000 nm thick silicon dioxide, silicon nitride, silicon oxynitride layer, or a stacked combination thereof, is deposited on the wafer in FIG. 13W. A hard mask 519 is deposited by CVD deposition of a metal layer such as silicon dioxide, silicon nitride, silicon oxynitride, or nickel, having a thickness ranging from 50 nm to 5 μm, and is patterned to define an ILD opening in FIG. 13X. The ILD layer 518 is then etched using the hard mask as shown in FIG. 13Y. Additionally, gate oxide 515 is deposited using the same mask 519 of FIG. The ILD layer 518 is then etched away. The hard mask used to pattern the ILD layer 519 is then used to achieve source trench regions 520 by etching completely through the N+ source layer to the P+ plug layer in FIG. 13AA. The mask 519 is then removed in FIG. 13BB. Nickel silicide regions 521 are formed on the exposed SiC surface in FIG. 13CC. A mask layer 522 is formed by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 pm, which is then patterned in FIG. 13DD. The ILD layer 518 is then etched away in FIG. 13EE. The mask layer 522 is removed in FIG. 13FF. An interconnect metal layer 523, either aluminum, silver, or gold, is deposited on the top and bottom of the substrate and patterned in FIG. 13GG. Ohmic contact to the N+ source region is made through the etched sidewalls of the source trench region in this embodiment, as opposed to the horizontal surface of the N+ source region in a conventional MOSFET.

[0406] The embodiment shown in Figure 14 is a unit cell and device periphery of the cross-sectional structure of a SiC DMOSFET. The critical region of this device is the p-well region 603, formed by ion implantation or epitaxial regrowth of p-type species such as aluminum or boron. There is an N+ source region 604, an N drift layer 602, and an N+ substrate 601. In the on-state, when a gate voltage is applied to the polysilicon gate 607, current flows vertically from the drain 601, through an inversion layer formed on top of the p-well layer 603, through the N+ source region 604, and out through the source metallization 610. In the off-state or blocking state, a voltage is supported across the p-well 603, N drift layer 602 junction, and there is a PN junction formed between the p-well and N drift layer. A voltage applied to the structure is supported across this PN junction in reverse bias. A power MOSFET has several important features, including the pitch of the unit cell, which is the repeating unit of the MOSFET; the channel length, which is the portion of the p-well where the inversion channel is formed; the distance between two consecutive p-wells, called the JFET region or JFET gap; and the thickness of the gate oxide 606. Another feature is the ILD layer 608, which is used to insulate the source interconnect metallization 610 from the polysilicon gate 607. At the very center of the unit cell is a P+ plug layer 605, which is grounded with the N+ source metallization. The purpose of the p+ plug in a SiC DMOSFET is to ground the p-well region with the N+ source contact.

[0407] In one embodiment herein, a dedicated masking step is interspersed between the formation of sidewall spacers after the p-well implant and before the N+ source implant to mask the N+ source implant from the peripheral regions of the MOSFET. This also masks the N+ source implant from selected regions within the active area of ​​the device, which allows for ohmic contact to the p-well or p+ plug region. This embodiment eliminates the need for a source trench present in the previous embodiment.

[0408] In embodiments herein, a dedicated hard mask or photoresist layer is applied after sidewall spacers are formed and before N+ source implantation, which avoids the formation of N+ source regions at the device periphery and parasitic NPN structures at the device periphery. The N+ source region implantation is avoided in selected areas within the active area, which allows for ohmic contact to p-well or p+ plug regions without an intervening N+ source region.

[0409] 15A-15F show the fabrication steps of the structure shown in FIG. 14. The fabrication process of the SiC DMOSFET is on a SiC substrate 701, with appropriate doping (10 14 ~10 18 cm -3 The process begins with the use of a 4H-SiC Si-face epitaxial wafer with a thickness (1 μm to 300 μm). A blanket hard mask 703, comprising a CVD-deposited layer of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm, is deposited in FIG. 15B, then patterned using photolithography, and then dry-etched using, for example, RIE, as shown in FIG. 15C. Next, a p-well region is first formed by ion implantation or epitaxial growth using aluminum or boron as p-type impurities. In FIG. 15D, 10 12 cm -2 ~10 15 cm -2 Injection dose ranges from 10 keV to 800 keV. A p-type implant 704 containing boron or aluminum at an energy of 0.1 .mu.m is performed to form a p-well 705 in FIG. 15E.

[0410] A second hard mask layer 706 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 pm, on top of the patterned first hard mask layer 703 in FIG. 15F. This is followed by an anisotropic etch 707 in FIG. 15G to form sidewall spacers 706, as shown in FIG. 15H. A hard mask layer 708 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 pm, and is patterned in FIG. 15I. A patterned mask layer is formed alongside the patterned mask layer with sidewall spacers 706 on top. An n-type implant 709 is performed in FIG. 15J to create n+ source regions 710 in FIG. 15K. The n+ source regions are formed by ion implantation or epitaxial regrowth with n-type impurities such as nitrogen or phosphorus. Thus, source region 710 is formed self-aligned with p-well region 705 while being masked from the peripheral region of the device, as well as selected areas of the active region of the device, allowing contact with the source ohmic metallization. In Figure 15L, first and second hard mask layers 703 and 708, respectively, are removed. Another mask layer 711 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm, at the top of Figure 15M. Mask layer 711 is then patterned in Figure 15N.

[0411] Using a hard mask 711, a p+ plug region is realized in FIG. 15P by implanting a controlled dose of p-type impurities 712, such as aluminum or boron, in FIG. 150. The depth of the p+ plug layer 713 preferably exceeds the depth of the N+ source implant, and in certain implementations may exceed the depth of the p-well region. The mask layer 711 is removed in FIG. 15Q. The wafer is annealed to activate the implanted impurities.

[0412] The gate oxide, oxide layer 714, is formed in Figure 15R by thermal oxidation or using CVD of a dielectric layer such as silicon dioxide, silicon nitride, or silicon oxynitride. The gate oxide thickness can range from 10 nm to 100 nm. Either dry or wet thermal oxidation can be used for oxide growth. PECVD or LPCVD can be used for gate oxide deposition. Next, in Figure 15S, a polysilicon gate layer 715 is deposited. The polysilicon layer can be deposited using PECVD or LPCVD. The polysilicon layer can be degenerately doped in situ or in a subsequent step with boron or phosphorus. In-situ doping can be achieved by adding a PH3 precursor to the polysilicon deposition chemistry. Post-deposition doping of the polysilicon can be achieved by depositing a layer of POOL followed by a drive-in step at temperatures ranging from 700 to 900 °C. A hard mask 716 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, having a thickness ranging from 50 nm to 5 μm, and patterned on top, as shown in FIG. 15T. The polysilicon layer 715 is etched using the patterned mask layer 716 in FIG. 15U. Then, in FIG. 15V, the mask layer 716 is removed. An ILD layer 717, comprising a 50 nm to 1000 nm thick silicon dioxide, silicon nitride, silicon oxynitride layer, or a stacked combination thereof, is deposited on the wafer in FIG. 15W.

[0413] A hard mask 718 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm, and patterned on top to define an ILD opening, FIG. 15X. The ILD layer 717 is then etched using the hard mask, as shown in FIG. 15Y. Furthermore, the gate oxide 714 is etched using the same mask 718, FIG. 15Z. Next, in FIG. 15A, the mask 718 is removed. In FIG. 15B, nickel silicide regions 719 are formed on the exposed SiC surface. A mask layer 720 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel. The ILD layer 717 is then etched away in Figure 15D. The mask layer 720 is removed in Figure 15E. An interconnect metal layer 721, either aluminum, silver, or gold, is deposited and patterned on the top and bottom of the substrate in Figure 15F.

[0414] The embodiment shown in Figure 8 is a unit cell and device periphery of a cross-sectional structure of a SiC DMOSFET. The critical region of this device is the p-well region 803, formed by ion implantation or epitaxial regrowth of p-type species such as aluminum or boron. There are N+ source regions 804, N drift layer 802, and N+ substrate 801. In the on-state, when a gate voltage is applied to the polysilicon gate 807, current flows vertically from the drain 801, through an inversion layer formed on top of the p-well layer 803, through the N+ source region 804, and out through the source metallization 810. In the off-state or blocking state, a voltage is supported across the p-well 803, N drift layer 802 junction, and there is a PN junction formed between the p-well and N drift layer. A voltage applied to the structure is supported across this PN junction in reverse bias. A power MOSFET has several important features, including the pitch of the unit cell, which is the repeating unit of the MOSFET; the channel length, which is the portion of the p-well where the inversion channel is formed; the distance between two consecutive p-wells, called the JFET region or JFET gap; and the thickness of the gate oxide 806. Another feature is the ILD layer 808, which is used to insulate the source interconnect metallization 810 from the polysilicon gate 807. At the very center of the unit cell is a P+ plug layer 805, which is grounded with the N+ source metallization. The purpose of the p+ plug in a SiC DMOSFET is to ground the p-well region with the N+ source contact.

[0415] In one embodiment herein, a dedicated masking step is interspersed between the formation of sidewall spacers after the p-well implant and before the N+ source implant to mask the N+ source implant from the peripheral regions of the MOSFET. This also masks the N+ source implant from selected regions within the active area of ​​the device, which allows for ohmic contact to the p-well or p+ plug region. This embodiment eliminates the need for a source trench present in some previous embodiments.

[0416] In embodiments herein, a dedicated hard mask or photoresist layer is applied after sidewall spacers are formed and before N+ source implantation, which avoids the formation of N+ source regions at the device periphery and parasitic NPN structures at the device periphery. The N+ source region implantation is avoided in selected areas within the active area, which allows for ohmic contact to p-well or p+ plug regions without an intervening N+ source region.

[0417] In embodiments herein, the polysilicon metallization in the peripheral region of device 807 is segmented and not a continuous layer. By forming segmented gate metallization at the periphery of the device instead of an adjacent gate bus, embodiments herein can significantly reduce the gate body capacitance of the MOSFET, which can result in a significant increase in the switching speed of the MOSFET.

[0418] 17A-17F illustrate the fabrication steps for the structure shown in FIG. 8. The fabrication process for a SiC DMOSFET begins with the use of a 4H-SiC Si-face epi-wafer on a SiC substrate 901 with the appropriate doping (1014-1018 cm'3) and thickness (1 pm-300 pm) for the epi-layer 902 shown in FIG. 17A. A blanket hard mask 903, comprising a CVD-deposited layer of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm, is deposited in FIG. 17B, then patterned using photolithography and then dry-etched using, for example, RIE, as shown in FIG. 17C. Next, a p-well region is first formed by ion implantation or epitaxial growth using aluminum or boron as a p-type impurity. In FIG. 17D, 10 12 cm -2 ~10 15 cm -2 with implant doses ranging from 10 keV to 800 keV. A p-type implant 904 containing boron or aluminum at an energy level is performed to create a p-well 905 in FIG. 17E.

[0419] A second hard mask layer 906 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm in FIG. 17F, on top of the patterned first hard mask layer 903. This is followed by an anisotropic etch 907 in FIG. 17G to form sidewall spacers 906, as shown in FIG. 17H. A hard mask layer 908 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm, and is patterned in FIG. 17I. The patterned mask layer 908 is then formed alongside the patterned mask layer with sidewall spacers on top. An n-type implant 909 is performed in FIG. 17J to create n+ source regions 910 in FIG. 17K. The n+ source regions are formed by ion implantation or epitaxial regrowth with n-type impurities such as nitrogen or phosphorus. Thus, source region 910 is formed self-aligned with p-well region 905 while being masked from the peripheral region of the device, as well as selected areas of the active region of the device, allowing contact with the source ohmic metallization. In Figure 17L, first and second hard mask layers 903 and 908, respectively, are removed. Another mask layer 911 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm, at the top of Figure 17M. Mask layer 911 is then patterned in Figure 17N.

[0420] Using the hard mask 911, a p+ plug region 913 is realized in Fig. 17P by implanting a controlled dose of p-type impurities 912, such as aluminum or boron, in Fig. 170. The mask layer 911 is removed in Fig. 17Q. The wafer is annealed to activate the implanted impurities.

[0421] The gate oxide, oxide layer 914, is formed in Figure 17R by thermal oxidation or using CVD of a dielectric layer such as silicon dioxide, silicon nitride, or silicon oxynitride. The gate oxide thickness can range from 10 nm to 100 nm. Either dry or wet thermal oxidation can be used for oxide growth. PECVD or LPCVD can be used for gate oxide deposition. Next, in Figure 17S, a polysilicon gate layer 915 is deposited. The polysilicon layer can be deposited using PECVD or LPCVD. The polysilicon layer can be degenerately doped with boron or phosphorus in situ or in a subsequent step. In-situ doping can be performed by adding a PH3 precursor to the polysilicon deposition chemistry. Post-deposition doping of the polysilicon can be performed by depositing a layer of POCh followed by a drive-in step at a temperature ranging from 700 to 900 °C. A hard mask 916 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm, and then patterned, as shown in FIG. 17T. The polysilicon layer 915 is etched using the patterned mask layer 916 in FIG. 17U. In the embodiment described herein, the masking step used to pattern the polysilicon gate metal results in a partially segmented polysilicon pattern. Although not apparent in the cross-sectional schematic, the isolated gate fingers are connected at locations perpendicular to the plane of the drawing. In FIG. 17V, the patterned mask 916 is used to etch the gate insulator 914. Next, in FIG. 17W, the mask layer 916 is removed. An ILD layer 917, comprising a 50 nm to 1000 nm thick silicon dioxide, silicon nitride, silicon oxynitride layer, or a stacked combination thereof, is deposited on the wafer in FIG. 17X.

[0422] The hard mask 918 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm at the top, and is patterned at the top to define the ILD openings in FIG. 17Y. The ILD layer 917 is then patterned at the top to define the ILD openings in FIG. 17Z. The SiC layer is then etched using a hard mask. Next, in FIG. 17AA, the mask 918 is removed. In FIG. 17BB, nickel silicide regions 919 are formed on the exposed SiC surface. A mask layer 920 is formed by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm, as patterned in FIG. 17CC. The ILD layer 917 is then etched in FIG. 17DD. The mask layer 920 is removed in FIG. 17EE. An interconnect metal layer 921, either aluminum, silver, or gold, is deposited and patterned on the top and bottom of the substrate.

[0423] Embodiments relate to SiC DMOSFET power devices, where the p-well region effectively shields the sensitive gate oxide from the high electric fields present in SiC, especially during high drain bias or blocking mode operation.

[0424] One embodiment involves using a p+ plug to ground the p-well region with an N+ source contact.

[0425] One embodiment involves a p-well trench formed by dry etching in the p-well implant region just prior to source region formation, resulting in a portion of the MOS channel formed on the (0001) or horizontal plane and another portion of the MOS channel formed on the (11-20 / 10-10) or vertical crystallographic plane of the SiC, which has the advantage of increasing MOS channel mobility.

[0426] One embodiment involves a much deeper vertical MOS channel formed by completely etching the p-well region, followed by ion implantation of a second p-well region (PW#2) under and around the N+ source region to suppress reach-through breakdown after the formation of the N+ source region.

[0427] Embodiments relate to the formation of p-well trenches, which provides device designers the flexibility to either increase the effective channel length for a given on-resistance target or decrease the on-resistance for a given chip size.

[0428] SiC devices in power electronics are characterized by fast switching times, high blocking voltage capability, and the ability to operate at high temperatures. These properties, along with recent advances in manufacturing processes, suggest that SiC has the potential to revolutionize power electronics as a successor to conventional silicon-based (Si) devices. SiC is a wide bandgap material (3.3 eV), offering a high breakdown field (3×10 V / cm) compared to Si (Si's bandgap is 1.1 eV and its breakdown field is 0.3×10 V / cm). 6 V / cm~5×10 6 SiC has a thermal conductivity of 3.7 W / cm-K compared to 1.6 W / cm-K for SiC, allowing SiC devices to operate at extremely high power levels and still dissipate the large amounts of excess heat generated. These material properties of SiC offer several advantages of using SiC instead of Si in power devices. In a comparison of SiC and Si semiconductor dies with identical structure and dimensions, the SiC die exhibits a lower specific on-resistance and higher breakdown voltage than the Si die.

[0429] The embodiments disclosed herein provide novel techniques for the design and fabrication of SiC DMOSFETs, which may be advantageous for having higher channel densities and reduced device on-resistance.

[0430] In a typical SiC planar MOSFET structure, also known as a DMOSFET, the MOS channel is formed on the horizontal or 0001 crystal plane of the SiC. The channel mobility, or field-effect mobility, on the 0001 crystal plane of SiC tends to be lower compared to the vertical sidewalls or so-called 11-20 or 10-10 crystal planes. When fabricating planar SiC DMOSFETs, the on-resistance tends to be higher, and the DMOSFET is limited by the field-effect channel mobility.

[0431] The channel mobility or field effect mobility on the 0001 crystal plane of SiC is 350 cm 2 15-25cm / V-sec compared to silicon MOSFETs, which can exceed 2 / V-sec range. One way to design SiC MOSFETs with lower resistance is to find a way to create a very small channel length, so that the inversion layer mobility is active only in a smaller region of the device's current conduction path, but this can lead to short-channel effects. Therefore, simply reducing the channel length does not solve the low channel mobility in the 0001 crystal plane; it introduces short-channel effects, resulting in poor device reliability and poor robustness. In one embodiment herein, one way to address this problem is by introducing trench MOSFETs in SiC. In trench MOSFETs, instead of forming the MOS channel on a horizontal plane or the 0001 crystal plane, the channel is formed on a vertical sidewall, or on the so-called A-plane or M-plane, also known as the 10-10 or 11-20 plane. Both of these planes have significantly higher channel mobility, nearly five times higher than horizontal planes, with a vertical channel mobility of 110-120 cm. 2 / V-sec.

[0432] Trench MOSFETs offer higher channel density compared to planar MOSFETs, thus increasing packing density. High channel mobility allows for devices with lower on-resistance. While conventional trench MOSFETs have advantages over DMOSFETs, a problem with conventional trench MOSFET structures in SiC is the presence of a high electric field at the base of the trench, and the portion of the gate oxide within the trench experiences a high electric field during blocking mode of operation. This presents a failure point for typical trench MOSFET structures, and to overcome this issue, it is necessary to shield the gate oxide at the base of the trench. P-type implants are used to shield the gate oxide, and approaches such as W-trench MOSFETs are used to shield the gate oxide.

[0433] However, creating these shielding regions increases the on-resistance. Compared to DMOSFETs, trench MOSFETs allow for higher channel mobility, thus reducing the on-resistance, but they also create higher electric fields at the trench corners. To counter this, shielding regions are introduced, which increases the on-resistance. Some of the benefits of reduced on-resistance from trench MOSFETs are currently lost due to the shielding, a trade-off when designing conventional trench MOSFETs.

[0434] In the embodiments herein, the device is neither a pure DMOSFET nor a pure trench MOSFET: in this device, the MOS channel is formed on both the 0001 plane and the vertical sidewall or 11-20 (or 10-10) plane, and therefore it is a hybrid between a DMOSFET and a trench MOSFET.

[0435] In embodiments herein, the device has a shorter overall channel length compared to a pure DMOSFET, but maintains the same effective channel mobility. This increased channel length overcomes some of the robustness and reliability issues associated with fabricating short-channel DMOSFETs. In embodiments herein, the device has a trench that is completely surrounded or surrounded by a p-type implanted region. This provides natural shielding from high electric fields. Because the trench is formed entirely within the p-well, no area of ​​the trench is exposed to the n-type epilayer, mitigating the high-electric field issues in trench combers.

[0436] In the embodiments herein, this device structure is distinguished by a trench etched into the p-well region, and this trench is referred to as a p-well trench. In the first embodiment, the p-well region is formed, and then a trench is etched into the p-well region, so that all sides of the trench are contained within the p-well region. This trench is also present just prior to the formation of the N+ source region. As described in this embodiment, this process The device has part of the MOS channel formed on the 0001 plane, and another part of the channel formed on the 11-20 or 10-10 plane.

[0437] The primary step in forming the device described in this embodiment is the formation of a p-well region by either ion implantation or epitaxial growth using aluminum or boron as p-type impurities, followed by a controlled etch into the p-well region to form a p-well trench using either reactive ion etching (RIE) or a higher power inductively coupled plasma (ICP) source with an appropriate hard mask layer to form this trench.

[0438] In embodiments herein, the trench may be formed with a sidewall angle between 70° and 90°, i.e., the approximate angle at which the trench is formed. By way of example, the depth of the trench may range from 0.1 μm to 0.5 μm. The depth of the p-well trench may be tailored to be less than the depth of the p-well region such that the bottom of the p-well trench is completely enclosed within the p-well region.

[0439] In this embodiment, after forming the p-well trench, the N+ source region is formed by ion implantation or epitaxial regrowth using impurities such as nitrogen or phosphorus. The N+ source is contained entirely within the p-well region; the N+ source does not extend beyond the p-well region. One option for the embodiments herein is that the p-well trench region is not required, but can be formed using the same masking steps that may be used to form the N+ source region. Next, a p+ plug layer for grounding the p-well is formed by implanting either aluminum or boron. The depth of the p+ plug layer may exceed the depth of the source implant layer, thereby shorting the source implant layer with an overlying ohmic layer and providing ground for the p-well region. The remainder of the process consists of electrical activation, electrical formation, gate metal formation, interlayer dielectric (ILD), patterning ILD, ohmic metallization, and thermal processing of the wafer for thick pad metallization.

[0440] In embodiments herein, either thermal oxidation or chemical vapor deposition (CVD) of a dielectric layer, such as silicon dioxide, silicon nitride, or oxynitride, is used to form the gate insulator. SiC has a different oxidation rate on the 0001 plane compared to the 11-20 or 10-10 plane, meaning that the oxidation rate is different on the horizontal and vertical sidewalls. This can result in a thicker gate oxide on the vertical sidewall compared to the horizontal sidewall. In embodiments herein, CVD silicon dioxide can be deposited, ensuring that the thickness is the same on the horizontal and vertical sides.

[0441] In one embodiment using the SiC DMOSFET described herein, a p-well trench is formed before source region formation and after p-well region formation. Here, a portion of the MOS channel in the device is formed parallel to the 0001 plane, and another portion is formed parallel to the 11-20 plane. MOSFETs fabricated according to this embodiment have higher channel density compared to planar devices for the same lateral footprint, thus allowing for tighter packing. In addition to geometrically increasing channel density, embodiments herein can also take advantage of the higher channel mobility of vertical sidewalls.

[0442] In embodiments herein, the device has a higher channel density, a higher channel mobility, and a lower on-resistance. For a given on-resistance target, the effective channel length can be increased. While comparing the device described in an embodiment with a typical planar DMOSFET, for the same on-resistance target, the channel length of the device can be increased in this embodiment. Short channel effects can degrade reliability and robustness characteristics, and a longer channel length can mitigate short channel effects. This Another way to use the device in this embodiment is to realize a smaller chip for the same channel length as a planar DMOSFET, which means a lower cost device.

[0443] This embodiment of the device can have the same channel length as a planar DMOSFET, but due to the higher channel mobility in the 11-20 and 10-10 directions, a longer channel can be achieved in the vertical sidewalls, while still having a shorter horizontal channel. Because of the higher channel mobility, this embodiment of the device has a lower on-resistance. This allows for a smaller chip size for the same on-resistance, and allows for the design of a device with a longer vertical channel and a shorter horizontal channel, resulting in a MOSFET with a lower on-resistance.

[0444] The embodiments described herein are distinguishable from the prior art disclosed by Tega et al. in U.S. Patent Application US 2018 / 0331174 A1 from Hitachi, Ltd. (Hitachi), published in November 2018. The prior art structure described by Tega et al. in Hitachi's U.S. Patent describes a SiC MOSFET structure in which the MOS channel is formed in both the horizontal and vertical p-well surfaces, and the p-well trench forming this MOS channel is not continuously formed on the vertical and horizontal sidewalls. The p-well trench is formed only at orthogonal locations in the 3D landscape. If it were continuously formed, a cross section at any location within the device would show the same structure. However, in the prior art, cross sections through these types of trenches show different cross sections at each location because there are many regions within the device where no p-well trench exists. However, the p-well trench in the device described in the embodiments herein is essentially continuous, and therefore differs from the prior art structure described by Tega et al. from Hitachi, Ltd.

[0445] The second difference is that the structure of the MOS channel in the prior art structure described by Tega et al. from Hitachi, Ltd. is completely different when compared to that described in the embodiments herein. The prior art MOS channel is formed between an N+ source region and a separate N+ accumulation region. In the device in the embodiments described herein, the p-well region is formed first, then a trench is formed in the p-well region, and then a source implant is formed. However, in the prior art structure described by Tega et al. from Hitachi, Ltd., the p-well region is formed, followed by a source implant, an accumulation region, a thermal treatment, and then a p-well trench. The difference lies in how and when the MOS channel is formed during the process.

[0446] The third difference is that the trench formation process for realizing a MOS channel on the vertical SiC crystal plane is performed after all implantation steps are completed in the prior art described by Tega et al. of Hitachi, Ltd. As a result, the N+ source region is elevated compared to a MOS channel formed on the vertical sidewall. In the device described in the embodiments herein, the p-well trench is etched immediately after the p-well implant and before the N+ source implant formed on the recessed region created by etching the p-well trench.

[0447] The structure proposed by Tega et al. has p+ plug, N+ source, and p-well regions, as well as N+ accumulation and p+ shield regions.

[0448] The embodiments described herein allow for the formation of extremely long channels on vertical sidewalls. The p-well trench can be formed significantly deeper, allowing the bottom of the p-well trench to extend beyond the p-well region.

[0449] In one embodiment herein, a p-well region is formed, followed by a deep p-well trench and a source implant. After the source implant, a second p-well region is formed. The second p-well region The region extends under the source region and has a cover around the corners to prevent any reliability issues with having sharp edges.

[0450] In embodiments herein, angled implants are used to extend the p-well region beyond the lateral extent of the p-well region, shielding the gate oxide from any drain-induced electric field. The structure in embodiments provides a natural way to shield the drain potential from the channel region by extending a second p-well region beyond the source region.

[0451] The method for forming the device described herein includes forming a p-well region by ion implantation or epitaxial growth using aluminum or boron. This is followed by forming a p-well trench by controlled etching into the p-well region using RIE or ICP-based etching. The p-well trench may be formed with a sidewall angle between 75° and 90°. The depth of the p-well trench region may range from 0.1 μm to 2 μm. An n+ source region is then formed by ion implantation or epitaxial regrowth with n-type impurities such as nitrogen or phosphorus. In embodiments herein, a second p-well region is formed because the bottom of the p-well trench may not be completely enclosed within the p-well region. The second p-well is formed to a sufficient depth below the N+ source region, ensuring that the lateral extent of the p-well region is greater than the original p-well region.

[0452] Two methods for forming the second p-well are described in the embodiments herein. In one case, a dedicated hard mask layer may be deposited and patterned slightly larger than the original p-well region, followed by ion implantation for PW#2. In the second case, angled ion implantation may be advantageously used to achieve PW#2. In the embodiment described here, the same hard mask may be used to create the p-well trench, N+ source region, and then PW#2 region, whose lateral extent is larger than that of the original PW region, using angled ion implantation of p-type impurities. The remainder of the process consists of wafer heat treatment for electrical activation of the implanted impurities, gate insulator formation, gate electrode formation, interlevel dielectric formation, source / drain ohmic metallization, and finally, formation of pads or interconnect metal compatible with die probing and packaging. The gate insulator is formed by thermal oxidation of silicon carbide or by CVD of a dielectric layer such as silicon dioxide, silicon nitride, or silicon oxynitride.

[0453] The devices described in this embodiment allow for greater latitude in on-resistance versus robustness trade-offs often encountered with SiC power MOSFETs: the longer channel allows for better short-circuit performance, while the on-resistance is higher due to the inherently lower channel mobility of SiC.

[0454] The embodiment shown in Figure 18 is a unit cell of the cross-sectional structure of a SiC DMOSFET. The critical region of this device is the p-well region 203, formed by ion implantation or epitaxial regrowth of p-type species such as aluminum or boron. There are N+ source regions 204, N drift layer 202, and N+ substrate 201. In the on-state, when a gate voltage is applied to the polysilicon gate 206, current flows vertically from the drain 201, through an inversion layer formed on top of the p-well layer 203, through the N+ source region 204, and out through the source metallization 208. In the off-state or blocking state, a voltage is supported across the p-well 203, N drift layer 202 junction, and there is a PN junction formed between the p-well and N drift layer. A voltage applied to the structure is supported across this PN junction in reverse bias. A power MOSFET has several important characteristics, including the unit cell pitch, which is the repeating unit of the MOSFET; the channel length, which is the portion of the p-well where the inversion channel is formed; the distance between two consecutive p-wells, called the JFET region or JFET gap; and the thickness of the gate oxide 205. Another characteristic is the thickness of the gate oxide 205, which is used to insulate the source interconnect metallization 208 from the polysilicon gate 206. The ILD layer 207 is used for grounding the N+ source metallization. At the very center of the unit cell is a P+ plug layer 209, which is grounded with the N+ source metallization. The purpose of the p+ plug in a SiC DMOSFET is to ground the p-well region with the N+ source contact.

[0455] First, p-well region 203 is formed by ion implantation or epitaxial growth using aluminum or boron as p-type impurities. Next, p-well trench 210 is formed by controlled etching into p-well region 203 using either RIE or ICP etching with an appropriately patterned hard mask layer. The p-well trench may be formed with a sidewall angle between 70° and 90°. The depth of p-well trench region 210 may range from 0.1 μm to 0.5 μm. The depth of the p-well trench can be tailored to be shallower than the depth of the p-well region. The bottom of the p-well trench may be enclosed within the p-well region. N+ source regions are then formed by ion implantation or epitaxial regrowth with n-type impurities such as nitrogen or phosphorus. The p-well trench region is preferably formed using the same masking steps used to perform the ion implantation required to form N+ source region 204. P+ plug layer 209 can be formed by implanting a controlled dose of p-type impurities such as aluminum or boron. The depth of the p+ plug layer may exceed the depth of the N+ source implant and, in certain implementations, may exceed the depth of the p-well region. The remainder of the process consists of electrical activation of the implanted impurities, gate insulator formation, gate electrode formation, interlevel dielectric formation, source / drain ohmic metallization, and finally, thermal processing of the wafer for the formation of pads or interconnect metal compatible with die probing and packaging. The gate dielectric 205 is formed using thermal oxidation or CVD of a dielectric layer such as silicon dioxide, silicon nitride, or silicon oxynitride.

[0456] In the present embodiment, a trench is formed in the p-well region immediately prior to the formation of the N+ source region A portion of the MOS channel, and the other portion of the MOS channel is formed parallel to the (0001) crystal plane of SiC, while the other portion of the MOS channel is formed parallel to the (1120) or (1100) crystal plane of SiC. DMOSFETs fabricated according to this embodiment have higher channel density, which may be advantageous for reducing the on-resistance of the device. It is well known to those skilled in the art that MOS channels formed on vertical sidewalls parallel to the (1120) or (1010) crystal plane of 4H-SiC can achieve much higher field-effect mobility compared to MOS channels formed on a flat (0001) crystal plane. In addition to increasing channel density, one embodiment described herein is expected to increase the effective channel mobility of DMOSFETs fabricated according to this embodiment compared to DMOSFETs fabricated using MOS channels that are always parallel to the (0001) crystal plane of 4H-SiC. This desirable feature can be exploited to increase the effective channel length for a given on-resistance target, or to decrease the on-resistance for a given chip size, either of which may be of interest to a device designer.

[0457] The embodiments described in this application are distinguishable from the device disclosed by Tega et al. in U.S. Patent Application No. 2018 / 0331174 [hereinafter referred to as Reference 1], which describes a SiC MOSFET structure in which the MOS channel is formed on vertical and horizontal p-well surfaces:

[0458] (1) In Reference 1, the MOS channel on the vertical SiC crystal plane is not formed continuously, but only at discrete orthogonal positions within the active region. Therefore, there is a cross section of the MOSFET in Reference 1 that does not include MOS channel formation on the vertical SiC sidewall.

[0459] (2) The MOS channel configuration in Reference 1 is completely different from that described in the embodiments herein. In Reference 1, the MOS channel is formed between an N+ source region and a separate N+ accumulation region that connects the MOS channel to the JFET region.

[0460] (3) In Reference 1, the trench creation process for realizing the MOS channel on the vertical SiC crystal plane is performed after all implantation steps are completed. As a result, the N+ source region is elevated compared to the MOS channel formed on the vertical sidewall. In the embodiment described herein, the p-well trench is etched immediately after the p-well implant and before the N+ source implant formed on the recessed region created by the etching of the p-well trench.

[0461] 19A-19U illustrate the process for fabricating the structure shown in FIG. 18. The fabrication process for the SiC DMOSFET is on a SiC substrate 301, with appropriate doping (10 14 ~10 18 cm -3 The process begins with the use of a 4H-SiC Si-face epitaxial wafer with a thickness (1 μm to 300 μm). A blanket hard mask 303, comprising a CVD-deposited layer of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm, is deposited in FIG. 19B, then patterned using photolithography, and then dry-etched using, for example, RIE, as shown in FIG. 19C. Next, a p-well region is first formed by ion implantation or epitaxial growth using aluminum or boron as p-type impurities. In FIG. 19D, 10 12 cm -2 ~10 15 cm -2A p-type implant 304 containing boron or aluminum at an energy range of 10 keV to 800 keV with an implant dose range of 100 keV to 800 keV is performed to create a p-well 305 in FIG. 19E. The mask 303 is removed, and another hard mask layer 306 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 pm, and then patterned as shown in FIG. 19F. A p-well trench 308 is formed in the p-well region by a controlled etching process 307 using RIE or ICP etching using the appropriately patterned hard mask layer 306 in FIG. 19G. The p-well trench 308 is formed with a sidewall angle of 70° to 90°. The depth of the p-well trench region is in the range of 0.1 μm to 0.5 μm. The depth of the p-well trench may be adjusted to be shallower than the depth of the p-well region 305. The bottom of the p-well trench 308 may be enclosed within a p-well region 305. An n-type implant 309 is performed to create n+ source regions 310 in FIG. 19H. The N+ source regions are formed by ion implantation or epitaxial regrowth with n-type impurities such as nitrogen or phosphorus. The same hard mask layer 306 used to etch the p-well trench may be advantageously used to pattern the N+ source implant so that the source implant is perfectly aligned beneath the p-well trench. The masking layer 306 is removed in FIG. 19I. Another hard mask layer 311 is deposited in FIG. 19J. In FIG. 19K, the hard mask layer 311 is patterned. A p+ plug layer may be formed by implanting a controlled dose of p-type impurities 312, such as aluminum or boron, in FIG. 19L. The depth of the p+ plug layer 313 may preferably exceed the depth of the N+ source implant and, in the particular embodiment of FIG. 19M, may exceed the depth of the p-well region. This is followed by removal of the hard mask 311 using either dry or wet etching techniques commonly practiced by those skilled in the art in Fig. 19N. Next, in Fig. 190, an oxide layer 314, which is the gate oxide, is formed by thermal oxidation or using CVD of a dielectric layer such as silicon dioxide, silicon nitride, silicon oxynitride, etc.The gate oxide thickness can range from 10 nm to 100 nm. Either dry or wet thermal oxidation can be used for oxide growth. Plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) can be used for gate oxide deposition. Next, in Figure 19P, a polysilicon gate layer 315 is deposited. The polysilicon layer can be deposited using PECVD or LPCVD. The polysilicon layer can be degenerately doped with boron or phosphorus, either in situ or in a subsequent step. In-situ doping can be performed by adding a PH3 precursor to the polysilicon deposition chemistry. Post-deposition doping of the polysilicon can be performed by depositing a layer of POCh followed by a drive-in step at a temperature in the range of 700 to 900°C. As shown in Figure 19Q, a hard mask 316 is deposited on top and patterned. The polysilicon gate layer 315 is then etched using the patterned mask layer 316. Next, in Figure 19R, mask layer 316 is removed. An ILD layer 317, comprising a 50 nm to 1000 nm thick silicon dioxide, silicon nitride, silicon oxynitride layer, or stacked combinations thereof, is deposited on the wafer. A hard mask is deposited and patterned on top to define ILD openings, and the ILD layer 317 is patterned using the hard mask, as shown in Figure 19S. Additionally, the gate oxide 314 is etched using the same mask. The mask is then removed, forming nickel silicide regions 318 on the exposed SiC surface, as shown in Figure 19T. An interconnect metal layer 319, either aluminum, silver, or gold, is deposited and patterned on the top and bottom of the chip, as shown in Figure 19U.

[0462] The embodiment shown in Figure 20 is a unit cell of the cross-sectional structure of a SiC DMOSFET. The critical region of this device is the p-well region 403, formed by ion implantation or epitaxial regrowth of p-type species such as aluminum or boron. There are N+ source regions 404, N drift layer 402, and N+ substrate 401. In the on-state, when a gate voltage is applied to the polysilicon gate 406, current flows vertically from the drain 401, through an inversion layer formed on top of the p-well layer 403, through the N+ source region 404, and out through the source metallization 408. In the off-state or blocking state, a voltage is supported across the p-well 403, N drift layer 402 junction, and there is a PN junction formed between the p-well and N drift layer. A voltage applied to the structure is supported across this PN junction in reverse bias. A power MOSFET has several important features, including the pitch of the unit cell, which is the repeating unit of the MOSFET; the channel length, which is the portion of the p-well where the inversion channel is formed; the distance between two consecutive p-wells, called the JFET region or JFET gap; and the thickness of the gate oxide 405. Another feature is the ILD layer 407, which is used to insulate the source interconnect metallization 408 from the polysilicon gate 406. At the very center of the unit cell is a P+ plug layer 409, which is grounded with the N+ source metallization. The purpose of the p+ plug in a SiC DMOSFET is to ground the p-well region with the N+ source contact.

[0463] A p-well trench 410 is dry-etched into the p-well implant region immediately prior to the formation of the source region 404, resulting in one portion of the MOS channel formed on the (0001) or horizontal surface and another portion of the MOS channel formed on the (11-20 / 10-10) or vertical crystal plane of the SiC. However, in the embodiment shown in FIG. 20, a much deeper vertical MOS channel is formed by completely etching the p-well region. Subsequently, after the formation of the N+ source region, a second p-well region, designated PW#2411, is ion-implanted under and around the N+ source region to suppress reach-through breakdown.

[0464] First, a p-well region 403 is formed by ion implantation or epitaxial growth using aluminum or boron as p-type impurities. Next, a p-well trench 410 is formed by controlled etching into the p-well region using RIE or ICP etching with an appropriately patterned hard mask layer. The p-well trench 410 may be formed with a sidewall angle of 75° to 90°. The depth of the p-well trench region may range from 0.1 μm to 2 μm. Compared to the device shown in FIG. 18, the device in FIG. 20 has a p-well trench depth that can be adjusted to be the same depth as the p-well region or slightly deeper than the p-well region. The bottom of the p-well trench in the embodiment shown in FIG. 20 may not be completely enclosed within the p-well region. An n+ source region is then formed by ion implantation or epitaxial regrowth with n-type impurities such as nitrogen or phosphorus. A second p-well region (PW#2) 411 is then formed to a sufficient depth below the N+ source region such that the lateral extent of the PW#2 region is greater than the lateral extent of the original p-well region. Two methods are identified for forming the PW#2 411 region: (1) a dedicated hard mask layer can be deposited and patterned to be slightly larger than the original p-well region, followed by ion implantation of PW#2; (2) angled ion implantation can be advantageously used to realize PW#2. In the present embodiment, the same hard mask may be used to form the trench, the N+ source region, and then the PW#2 region, the lateral extent of which is determined using angled ion implantation of p-type impurities. The gate insulator 405 is then formed by thermal oxidation of silicon carbide or by CVD of a dielectric layer such as silicon dioxide, silicon nitride, or silicon oxynitride.

[0465] The device described in this embodiment of FIG. 20 is an improvement over the device described in the embodiment of FIG. 18 and has several additional features and advantages. The vertical portion of the MOS channel in the embodiment of FIG. 20 can be much larger than that of the device shown in FIG. 18 due to the deeper p-well trench 410 for the MOSFET of FIG. 20. A greater percentage of the MOS channel can be realized on the vertical sidewalls, which allows for higher channel mobility, compared to horizontal surfaces. For example, for a total channel length of 1 μm, 0.25 μm of the MOS channel can be realized on the horizontal surfaces and 0.75 μm of the MOS channel can be realized on the vertical sidewalls. Therefore, the effective channel mobility of the device described in the embodiment shown in FIG. 20 can be greater than that of the device described in the embodiment shown in FIG. 18 for the same MOS channel length. Therefore, for the same effective channel mobility, a longer channel MOSFET can be fabricated using the embodiment of FIG. 20 compared to a MOSFET fabricated using the embodiment of FIG. 18. Longer channel MOSFETs offer higher device robustness, including lower drain saturation current, higher short-circuit robustness, lower Vth roll-off with drain voltage, and immunity from drain-induced barrier lowering (DIBL) effects.

[0466] In the embodiment of FIG. 20, a larger extent for PW#2 411 compared to the original p-well 403 is necessary and beneficial for reducing the channel length of the horizontal portion of the MOS channel. By forming PW#2 with a larger lateral extent than the original p-well, the drain potential during high-voltage blocking conditions is effectively shielded from the original p-well region by the PW#2 region. This allows for a significant reduction in the lateral extent (electrical dose) of the original p-well region extending beyond the p-well trench without the risk of reach-through breakdown. Reducing the lateral extent of the p-well region beyond the p-well trench results in a smaller portion of the MOSFET channel being formed on the horizontal surface.

[0467] 21A-21V illustrate the process for fabricating the structure shown in FIG. 20. The fabrication process for the SiC DMOSFET is on a SiC substrate 501 with appropriate doping (10 ohms) for the epilayer 502 shown in FIG. 21A. 14 ~10 18 cm -3 The process begins with the use of a 4H-SiC Si-face epitaxial wafer with a thickness (1 μm to 300 μm). A blanket hard mask 503, comprising a CVD-deposited layer of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm, is deposited in FIG. 21B, then patterned using photolithography, and then dry-etched using, for example, RIE, as shown in FIG. 21C. Next, a p-well region is first formed by ion implantation or epitaxial growth using aluminum or boron as p-type impurities. In FIG. 21D, 10 12 cm -2 ~10 15 cm -2A p-type implant 504 containing boron or aluminum at an energy range of 10 keV to 800 keV, with an implant dose in the range of 100 keV to 800 keV, is performed to create a p-well 505 in Figure 2IE. The mask 503 is removed, and another hard mask layer 506 is deposited by CVD deposition of a 50 nm to 5 μm thick layer of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, which is then patterned as shown in Figure 21F. A deep p-well trench 508 is formed by a controlled etching process 507 into the p-well region by RLE or ICP etching using the appropriately patterned hard mask layer 506 in Figure 21G. The p-well trench 508 may be formed with a sidewall angle of 75° to 90°. The depth of the p-well trench region may be in the range of 0.5 μm to 2 μm, for example. The depth of the p-well trench 508 can be adjusted to be the same depth as the p-well region or slightly deeper than the p-well region. The bottom of the p-well trench is sealed within the p-well region. It does not have to be included.

[0468] An N-type implantation 509 is performed to create the N+ source region 510 of FIG. 21H. The n+ source region is formed by ion implantation or epitaxial regrowth with n-type impurities such as nitrogen or phosphorus. A second p-well region (PW#2) 511 is then formed to a sufficient depth below the N+ source region, resulting in a lateral extent of the PW#2 region greater than that of the original p-well region of FIG. 21H. Two methods for forming the PW#2 region 511 are identified: (1) a dedicated hard mask layer can be deposited and patterned to be slightly larger than the original p-well region, followed by the ion implantation of PW#2; or (2) angled ion implantation can be advantageously used to realize PW#2. In this implementation, the same hard mask 506 can be used to create the p-well trench 508, the N+ source region 510, and then the PW#2 region 511, whose lateral extent is greater than that of the original p-well region, using angled ion implantation of p-type impurities.

[0469] The masking layer 506 is removed in Figure 21J. Another hard mask layer 512 is deposited in Figure 21K. The hard mask layer 512 is patterned in Figure 21L. A p+ plug layer can be formed in Figure 21M by implanting a controlled dose of p-type impurities 513, such as aluminum or boron. The depth of the p+ plug layer 514 preferably exceeds the depth of the N+ source implant, and in the specific embodiment of Figure 21N, may exceed the depth of the p-well region. This is followed by removal of the hard mask 512 using either dry or wet etching techniques commonly practiced by those skilled in the art in Figure 21O. Next, in Figure 21P, an oxide layer 515, which is the gate oxide, is formed by thermal oxidation or using CVD of a dielectric layer such as silicon dioxide, silicon nitride, or silicon oxynitride. The thickness of the gate oxide can range from 10 nm to 100 nm. Either dry or wet thermal oxidation can be used for oxide growth. PECVD or LPCVD can be used for gate oxide deposition. Next, in Figure 21Q, a polysilicon gate layer 516 is deposited. The polysilicon layer can be deposited using PECVD or LPCVD. The polysilicon layer can be degenerately doped with boron or phosphorus, either in situ or in a subsequent step. In situ doping can be performed by adding a PH3 precursor to the polysilicon deposition chemistry. Post-deposition doping of the polysilicon can be performed by depositing a layer of POCL, followed by a drive-in step at a temperature in the range of 700-900°C. As shown in Figure 21R, a hard mask 517 is deposited and patterned. The polysilicon gate layer 516 is etched using the patterned mask layer 517. Next, in Figure 21S, the mask layer 517 is removed. An ILD layer 518 comprising a 50 nm to 1000 nm thick silicon dioxide, silicon nitride, silicon oxynitride layer, or stacked combination thereof is deposited on the wafer, a hard mask is deposited and patterned on top to define ILD openings, and the ILD layer 518 is patterned using the hard mask as shown in Figure 2 IT.Further, gate oxide 515 is etched using the same mask. The mask is then removed, forming nickel silicide regions 519 on the exposed SiC surface in Figure 21U. An interconnect metal layer 520 of either aluminum, silver, or gold is deposited and patterned on the top and bottom of the chip in Figure 21V.

[0470] The present invention relates to the design and fabrication of short-channel SiC MOSFETs.

[0471] The embodiments described herein relate to minimizing the DIBL effect in high voltage short channel SiC MOSFETs.

[0472] The embodiments described herein relate to the design and fabrication of MOS channels with submicron channel lengths.

[0473] The embodiments described herein achieve devices that have both sufficiently low on-resistance and sufficiently high short circuit withstand times.

[0474] Embodiments described herein relate to locally increasing the channel doping concentration in specific regions of the channel. A non-uniformly doped channel for a SiC MOSFET provides a better tradeoff between on-resistance, threshold voltage, and short-circuit withstand time.

[0475] The embodiments described herein relate to locally increasing the doping concentration in the channel to achieve a better trade-off, with less increase in threshold voltage, but at the same time reducing the DIBL effect.

[0476] In one embodiment described herein, a p-type shield layer, referred to as a p-shield, is formed within the p-well region. The p-shield always originates within the p-well region, but can extend beyond the vertical extent of the p-well region.

[0477] In the embodiments described herein, the bottom of the p-type shield region can extend below the p-type well.

[0478] In one embodiment described herein, there can be multiple p-shield regions, and the doping concentrations in the different p-shield regions can differ from each other.

[0479] The present invention relates to devices with p-shield regions embedded within a p-well structure. The p-shield region always occurs within the p-well region, but can extend beyond the vertical extent of the p-well region.

[0480] In one embodiment herein, the device structure may have multiple p-shield regions, in which case the doping concentration profiles of different p-shield regions do not necessarily have to be the same, but may be different from each other.

[0481] In the race to achieve lower on-stage resistance in planar-gate SiC MOSFETs, especially those with high voltage ratings, it is common to shorten the channel length as much as possible to reduce most of the conduction losses associated with the SiC channel. MOS mobility in SiC MOS structures is significantly lower than that found in silicon MOSFETs, and as a result, channel lengths need to be extremely short, sometimes in the submicron range, to achieve sufficiently low on-state resistance.

[0482] As the channel length becomes shorter, short channel effects become a problem in SiC power MOSFETs, causing the drain-induced barrier lowering effect (also known as the DIBL effect), which is the cause of many reliability issues in SiC MOSFETs.

[0483] One related problem is the threshold voltage roll-off at high drain bias, where a designed device achieves a specific desired threshold voltage only at very low drain bias. However, as the drain bias approaches its blocking value, the threshold voltage drops substantially, which is undesirable because it can inadvertently turn on the channel.

[0484] Additionally, devices that suffer from the DIBL effect have extremely large saturation currents under high drain bias, resulting in excessive power dissipation under short-circuit load conditions, which in turn reduces short-circuit endurance time. The limited MOS channel mobility of SiC MOSFETs can be overcome by using short channel lengths, but this is still associated with problems due to the DIBL effect.

[0485] One approach to alleviating this problem is to increase the doping concentration in the channel region, which uniformly increases the device's threshold voltage. This approach can reduce the saturation drain current, but it also increases the device's on-resistance.

[0486] The embodiments described herein can help achieve devices with both sufficiently low on-resistance and sufficiently high short-circuit withstand time. While the conventional approach is to simply uniformly increase the doping concentration in the channel region, the embodiments described herein increase the doping concentration locally in specific regions of the channel rather than uniformly increasing the doping concentration in the rest of the channel. A non-uniformly doped channel for a SiC MOSFET provides a better tradeoff between on-resistance, threshold voltage, and short-circuit withstand time.

[0487] In the embodiments herein, the doping concentration is increased to not significantly increase the threshold voltage, but at the same time reduce the DIBL effect, thus achieving a better trade-off.

[0488] In one embodiment herein, a p-type shield layer, referred to as a p-shield, is formed within the p-well region. The p-shield always originates within the p-well region, but in certain instances of this embodiment, it can extend beyond the vertical extent of the p-well region.

[0489] In one embodiment of the present disclosure, the bottom of the p-shield region can extend further downward and reach below the p-well. In one embodiment of the present disclosure, there can be multiple p-shield regions. The doping concentrations in different p-shield regions can be different from each other.

[0490] In one embodiment herein, a p-type shield layer, referred to as a p-shield, is formed embedded within the p-well region. The p-shield always originates within the p-well region, but in certain instances of this embodiment, it can extend beyond the vertical extent of the p-well region.

[0491] In one embodiment of the present disclosure, the bottom of the p-shield region can extend further downward and reach below the p-well. In one embodiment of the present disclosure, there can be multiple p-shield regions embedded in the p-well region. The doping concentrations in different p-shield regions can be different from each other.

[0492] The p-shield region is formed recessed within the p-well structure to locally re-enhance the doping of the p-well region, providing better shielding of the MOSFET channel at the surface while minimizing the DIBL effect. In the embodiments described herein, the p-shield does not change the VTH because it is not directly connected to the channel.

[0493] The embodiment shown in FIG. 23A is a half-unit cell of the cross-sectional structure of a SiC DMOSFET. The critical region of this device is the p-well region 203, formed by ion implantation or epitaxial regrowth of p-type species such as aluminum or boron. There are N+ source regions 205, N drift layer 202, and N+ substrate 201. In the on-state, when a gate voltage is applied to polysilicon gate 207, current flows vertically from drain 201, through an inversion layer formed on top of p-well layer 203, through N+ source region 205, and out through source metallization 210. In the off-state or blocking state, a voltage is supported across the p-well 203, N drift layer 202 junction, and there is a PN junction formed between the p-well and N drift layer. A voltage applied to the structure is supported across this PN junction in reverse bias. A power MOSFET has several characteristics: the pitch of the unit cell, which is the repeating unit of the MOSFET; the channel length, which is the portion of the p-well where the inversion channel is formed; the Junction Gate Field Effect Transistor (JFET) region or There are several important features of the P-well, including the distance between two consecutive p-wells, called the JFET gap, and the thickness of the gate oxide 206. Another feature is the ILD layer 208, which is used to insulate the source interconnect metallization 210 from the polysilicon gate 207.

[0494] In embodiments herein, a p-type shield layer, referred to as p-shield 204a, is formed within the p-well region. The p-shield can be located inside the p-well such that the lateral location of the point with the highest doping concentration compared to the average background doping concentration of the p-well is located within the boundary of the p-well. The p-shield region always occurs within the p-well region. Points A and B are provided as reference points to illustrate what the doping profile of an implanted p-shield region looks like.

[0495] The embodiment shown in Figure 23B is similar to the embodiment of Figure 23A, except that the bottom of the p-shield region extends further down into the p-well and can reach outside the p-well region.

[0496] In the embodiment shown in Figures 23C and 23D, the device is similar to Figure 23A. The devices of Figures 23C and 23D illustrate the case where there are multiple p-shield regions. In these cases, the doping concentration profiles of the different p-shield regions do not necessarily have to be the same, but can be different from each other.

[0497] When biasing the drain at a high voltage, the p-shield formed in the center of the channel can help mitigate the drain bias-induced depletion region expansion, eliminating the DIBL effect. In addition to mitigating the DIBL effect, the p-shield region also provides a simple method for controlling the VTH of the MOSFET, allowing for improved short-circuit time (tsc). The p-shield allows for a local increase in the p-well doping concentration at critical locations within the device structure, as opposed to a uniform increase in the p-well doping concentration. A better tradeoff in terms of lower Vth, on-resistance, and better immunity to short-channel effects can be achieved by the method described in the embodiments. If the depth of the p-shield region is greater than the p-well region, i.e., if the p-shield extends vertically beyond the p-well region, the p-shield can also provide better shielding of the electric field to the channel region, which further mitigates the DIBL effect in the channel. Device structures with multiple p-shield regions can be designed with different doping concentrations in different p-shield regions. In the embodiments described herein, a higher doping concentration can be applied to the p-shield region closer to the edge of the p-well (POINT A), while the p-shield region closer to POINT B can be made with a lower doping concentration. This structure has the advantages of a lower gate threshold voltage for a given channel length as well as better resistance to short channel effects.

[0498] 24A-24U illustrate the process of fabricating the structure shown in FIG. 23A. The fabrication process of the SiC DMOSFET is on a SiC substrate 301, with appropriate doping (10 14 ~10 18 cm -3 The process begins with the use of a 4H-SiC Si-face epitaxial wafer with a thickness (1 μm to 300 μm). A blanket hard mask 303, comprising a chemical vapor deposition (CVD) layer of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness of 50 nm to 5 μm, is deposited in FIG. 24B, then patterned using photolithography, and then dry-etched using, for example, reactive ion etching (RIE), as shown in FIG. 24C. First, a p-well region is formed by ion implantation or epitaxial growth using aluminum or boron as p-type impurities. In FIG. 24D, 10 12 cm -2 ~10 15 cm -2 A p-type implant 304 containing boron or aluminum at an implant dose in the range of 0.1 keV to 1000 keV and an energy in the range of 10 keV to 1000 keV is performed to create a p-well 305. The patterned mask layer 303 is removed in Figure 24E.

[0499] Hard mask layer 306 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm in FIG. 24F. Mask layer 306 is patterned using photolithography and then dry etched using, for example, RTE in FIG. 24G.

[0500] A p-type implant 307 is performed to form a p-type region in the p-well called p-shield 308, as shown in FIG. 24H. Aluminum or boron can be used as the p-type impurity to form p-shield region 308. The doping concentration in the p-shield region may be in the range of 1E16 cm-3 to 1E21 cm-3. In FIG. 241, the patterned mask layer 306 is removed.

[0501] A blanket hard mask 309 comprising a chemical vapor deposition (CVD) deposited layer of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, having a thickness of 50 nm to 5 μm, is deposited as shown in FIG. 24J, then patterned using photolithography, and then dry etched using, for example, RIE, as shown in FIG. 24K.

[0502] N+ source regions 311 are formed in Figure 24L by ion implantation or epitaxial regrowth with n-type impurities such as nitrogen or phosphorus 310. The patterned mask layer 309 is removed as shown in Figure 24M.

[0503] The gate oxide, oxide layer 312, is formed by thermal oxidation or using CVD of a dielectric layer such as silicon dioxide, silicon nitride, or silicon oxynitride, as shown in Figure 24N. The gate oxide thickness can range from 10 nm to 100 nm. Either dry or wet thermal oxidation can be used for oxide growth. Plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) can be used for gate oxide deposition. Next, in Figure 240, a polysilicon gate layer 313 is deposited. The polysilicon layer can be deposited using PECVD or LPCVD. The polysilicon layer can be degenerately doped in situ or in a subsequent step with boron or phosphorus. In-situ doping can be performed by adding a PH3 precursor to the polysilicon deposition chemistry. Post-deposition doping of the polysilicon can be performed by depositing a layer of POCh followed by a drive-in step at a temperature ranging from 700 to 900°C. In Figure 24P, the polysilicon layer 313 is patterned. An ILD layer 314, comprising a 50 nm to 1000 nm thick silicon dioxide, silicon nitride, silicon oxynitride layer, or stacked combination thereof, is deposited on the wafer in Figure 24Q. The ILD layer 314 is patterned as shown in Figure 24R. In Figure 24S, the gate oxide 312 is patterned.

[0504] In Figure 24T, nickel silicide regions 315 are formed on the exposed SiC surface. Interconnect metal layers 316, either aluminum or silver or gold, are deposited and patterned on the top and bottom of the substrate as shown in Figure 24U.

[0505] The embodiment shown in Figure 25A is a half-unit cell of the cross-sectional structure of a SiC DMOSFET. The critical region of this device is the p-well region 403, formed by ion implantation or epitaxial regrowth of p-type species such as aluminum or boron. There is an N+ source region 405, an N drift layer 402, and an N+ substrate 401. In the on-state, when a gate voltage is applied to the polysilicon gate 407, current flows vertically from the drain 401, through an inversion layer formed on top of the p-well layer 403, through the N+ source region 405, and out through the source metallization 410. In the off-state or blocking state, a voltage is supported across the p-well 403, N drift layer 402 junction, and a PN junction is formed between the p-well and N drift layer. A voltage applied to the structure is supported across this PN junction in reverse bias. A power MOSFET has a pitch of unit cells, which are the repeating units of the MOSFET, and an inversion channel is formed. There are several important features including the channel length, which is the portion of the p-well that is connected to the source interconnect metallization 410, the distance between two consecutive p-wells, called the junction gate field effect transistor region (JFET region) or JFET gap, and the thickness of the gate oxide 406. Another feature is the ILD layer 408, which is used to insulate the source interconnect metallization 410 from the polysilicon gate 407.

[0506] A buried p-shield region 404a is formed within the p-well structure. In other words, the p-shield is formed below the SiC surface where the MOSFET channel is located. The p-shield region always occurs within the p-well region, as seen in FIG. 25A, but in the specific example of this embodiment, it may extend beyond the vertical extent of the p-well region, as shown in FIG. 25B.

[0507] The embodiment shown in Figure 25B is similar to the embodiment of Figure 25A, except that the bottom of the p-shield region extends further down into the p-well and can reach outside the p-well region.

[0508] The device structures shown in Figures 25C and 25D are similar to those of Figure 25A, but illustrate the presence of multiple p-shield regions. In these cases, the doping concentration profiles of the different p-shield regions do not necessarily have to be the same and may differ from one another. Points A and B in each of these figures are provided as reference points to illustrate what the doping profile of the implanted p-shield regions might look like.

[0509] The p-shield in Figures 25A-25D locally "re-enhances" the doping in the p-well region, providing better shielding of the MOSFET channel at the surface while minimizing the DIBL effect. Because the p-shield is not directly connected to the channel, the p-shield does not change the threshold voltage in this case. The device shown in Figure 25A provides the same type of field shielding to mitigate DIBL, but without the necessary threshold voltage change required for the device in Figure 23A.

[0510] 26A-26U illustrate the process for fabricating the structure shown in FIG. 25A. The fabrication process for the SiC DMOSFET is on a SiC substrate 501 with appropriate doping (10 14 ~10 18 cm -3 The process begins with the use of a 4H-SiC Si-face epitaxial wafer with a thickness (1 μm to 300 μm). A blanket hard mask 503, including a chemical vapor deposition (CVD) layer of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness of 50 nm to 5 μm, is deposited as shown in FIG. 26B, then patterned using photolithography, and then dry-etched using, for example, reactive ion etching (RIE), as shown in FIG. 26C. Next, a p-well region is first formed by ion implantation or epitaxial growth using aluminum or boron as p-type impurities. In FIG. 26D, 10 12 cm -2 ~10 15 cm -2A p-type implant 504 containing boron or aluminum at an implant dose in the range of 0.1 keV to 1000 keV and an energy in the range of 10 keV to 1000 keV is performed to create a p-well 505. The patterned mask layer 503 is removed in Figure 26E.

[0511] Hard mask layer 506 is deposited by CVD deposition of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, with a thickness ranging from 50 nm to 5 μm in FIG. 26F. Mask layer 506 is patterned using photolithography and then dry etched using, for example, RIE in FIG. 26G.

[0512] In Figure 26H, a p-type implant 507 is performed to form a p-type region within the p-well called p-shield 508. Aluminum or boron can be used as the p-type impurity to form the p-shield region 508. A buried p-shield region is formed within the p-well structure. In other words, the p-shield is formed below the SiC surface where the MOSFET channel is located. The p-shield region always occurs within the p-well region. The location of the p-shield region is controlled by careful adjustment of the implant energy used to achieve the p-shield region.

[0513] The p-type shield region is 1012cm -2 ~10 15 cm -2 The dopant concentration may be produced by a p-type ion implantation step comprising boron or aluminum at an energy in the range of 25 keV to 800 keV, with an implant dose in the range of 0.015 keV to 0.15 keV. In Fig. 261, the patterned mask layer 506 is removed.

[0514] A blanket hard mask 509 comprising a chemical vapor deposition (CVD) deposited layer of silicon dioxide, silicon nitride, silicon oxynitride, or a metal layer such as nickel, having a thickness of 50 nm to 5 μm, is deposited as shown in Fig. 261, then patterned using photolithography, and then dry etched using, for example, RIE, as shown in Fig. 26K.

[0515] N+ source regions 511 are formed in Figure 26L by ion implantation or epitaxial regrowth with n-type impurities such as nitrogen or phosphorus 510. The patterned mask layer 509 is removed in Figure 26M.

[0516] The gate oxide, oxide layer 512, is formed in Figure 26N by thermal oxidation or using CVD of a dielectric layer such as silicon dioxide, silicon nitride, or silicon oxynitride. The gate oxide thickness can range from 10 nm to 100 nm. Either dry or wet thermal oxidation can be used for oxide growth. Plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) can be used for gate oxide deposition. Next, in Figure 260, a polysilicon gate layer 513 is deposited. The polysilicon layer can be deposited using PECVD or LPCVD. The polysilicon layer can be degenerately doped in situ or in a subsequent step with boron or phosphorus. In-situ doping can be achieved by adding a PH3 precursor to the polysilicon deposition chemistry. Post-deposition doping of the polysilicon can be achieved by depositing a layer of POOL followed by a drive-in step at temperatures ranging from 700 to 900°C. In Figure 26P, polysilicon layer 513 is patterned. An ILD layer 514, comprising a 50 nm to 1000 nm thick silicon dioxide, silicon nitride, silicon oxynitride layer, or stacked combination thereof, is deposited on the wafer in Figure 26Q. ILD layer 514 is patterned in Figure 26R. Gate oxide 512 is patterned in Figure 26S.

[0517] In Figure 26T, nickel silicide regions 515 are formed on the exposed SiC surface. Interconnect metal layers 516, either aluminum or silver or gold, are deposited and patterned on the top and bottom of the substrate as shown in Figure 26U.

[0518] The embodiments described herein relate to SiC transistors.

[0519] The device described in one embodiment herein has a buried N+ region located between its P+ islands. The buried N+ region is formed so that it does not contact the Schottky layer and is therefore physically isolated from the wafer surface. A portion of the N drift layer is in contact with the Schottky surface. The physical isolation of the N+ region from the wafer surface is an important feature of this embodiment, since SiC devices have an N doping concentration rather than an N+ doping concentration in the Schottky metal. The silicon carbide surface in contact with the Schottky metal has an N doping concentration that is important for reducing the strength of the electric field at the Schottky metal interface with SiC. In one embodiment described herein, the buried N+ region extends vertically lower than and covers the bottom of the P+ region. Compared to prior art MPS diodes, the spacing between the P+ islands is narrower and the depth of the P+ islands is deeper. The presence of the N+ region allows for closer spacing between the P+ islands. The P+ islands shield the electric field generated during high-voltage operation from the Schottky interface. In the embodiments herein, the P+ regions interspersed with N+ regions are designed to achieve a level of charge balance between the P+ islands and the N+ regions, which further reduces the ON resistance of the device and also provides the advantage of maintaining a low electric field.

[0520] In one embodiment herein, the bottom of the N+ region is higher than the bottom of the P+ region. The bottom of the P+ region is in contact with the N drift layer, which allows for lower leakage current, but is a trade-off because it allows for higher on-resistance. Better on-resistance can be achieved in device embodiments where the N+ region located between the P+ islands is buried, and lower leakage current can be achieved in device embodiments where the N+ region does not completely surround the bottom of the P+ islands. In embodiments described herein, both buried N+ regions located between the P+ islands and N+ regions that do not completely surround the bottom of the P+ islands can be present on the same device.

[0521] In one embodiment described herein, the N+ region is formed from several sub-N regions, and the P+ region is formed from many sub-P regions, and the doping concentration in each of these different layers or slices can be different. In one embodiment herein, the final slice of N+ region is below the P+ island and completely surrounds the P+ island, or the bottom of the N+ slice is higher than the bottom of the P+ region. The doping concentration of the N+ type subregions farther from the silicon carbide surface can be progressively higher, which can have the advantage of lower conduction losses. In another embodiment, the doping concentration of the p-type subregions farther from the SiC surface can be progressively lower, which can enable better blocking characteristics. The doping concentration variations described in the embodiments herein allow flexibility to appropriately tune device designs for lower leakage current, better conduction losses, lower resistance, etc. A better tradeoff can be achieved with layered and differently doped N+ and P+ regions, as opposed to having only one P+ layer and one N+ layer, which can be achieved by using multiple ion implantation steps or multiple epi growths.

[0522] In one embodiment herein, N+ regions interspersed among a set of multiple P+ wells are formed to be physically isolated from the wafer surface and extend completely into the N drift region. The physical isolation of the N+ regions from the SiC wafer surface in this embodiment herein distinguishes it from other similar inventions.

[0523] In one embodiment herein, the portion of the SiC wafer that is in contact with the Schottky metal (METAL 1) and is an n-type semiconductor has the same doping concentration of N drift because the doping concentration of the n-type SiC semiconductor that is in direct contact with the Schottky metal (METAL 1) is important for reducing the strength of the electric field at the wafer surface during the high-voltage blocking mode of operation of the SiC MPS diode.

[0524] The embodiment device shown in Figure 28A is a cross-sectional schematic of a SiC MPS diode. The critical region of this device is the bottom N+ substrate 201, which provides mechanical support for the wafer and is ~350 μm thick. There is an N drift region 202, typically an epilayer, that overlies the N+ substrate. There are multiple P+ wells 204, formed as linear stripes or more complex circular or hexagonal patterns. The device has a first metal layer 205, designated METAL 1, which is a Schottky metal to the n-type SiC semiconductor region and forms a Schottky contact to the underlying n-type region. On the front side of the wafer in contact with METAL 1, the device has a second metal layer 206, designated METAL 2. Metal 2 is often referred to as the "power metal" and is typically aluminum. Beneath the bottom of the N+ substrate is a silicide layer 207. Beneath the back side of the wafer in contact with the silicide layer is a third metal layer 208, designated METAL 3.

[0525] The device shown in FIG. 28A has N+ regions 203 interspersed among a set of multiple P+ wells 204. The N+ regions 203 are formed to be physically isolated from the wafer surface and extend completely into the N drift region 202. The physical isolation of the N+ regions from the SiC wafer surface is an important feature of the embodiments described herein and distinguishes them from other similar inventions. The portion of the SiC wafer that is in contact with the Schottky metal 205, referred to as METAL 1, and is an n-type semiconductor, is the N drift region 202. The doping concentrations are the same. In the embodiment described herein, the doping concentration of the n-type SiC semiconductor in direct contact with the Schottky metal 205, labeled METAL 1, is important for reducing the strength of the electric field at the wafer surface during the high-voltage blocking mode of operation of the SiC MPS diode. The vertical extent of the N+ region 203 is smaller than the bottom of the P+ region 204. The buried N+ region completely surrounds the P+ region, which provides a conductive migration path for Schottky-injected majority carriers and reduces the overall forward conduction loss.

[0526] The embodiments described herein use a different type of Schottky metal for the Metal 1 layer compared to Metal 1 in the prior art. The selection of Metal 1 205 in the device described in FIG. 28A is made so that the barrier height of its Schottky contact is lower than that of the prior art. The smaller Schottky barrier height results in more efficient injection of majority carriers onto the Schottky barrier, which is reflected as a lower Knee voltage (VKnee) in the forward IV characteristics, as shown in FIG. 28B. The new devices with lower VKnee (labeled #2 and #3) have lower forward conduction losses than their counterparts (labeled #1). The lower the Schottky barrier height, the higher the reverse leakage current, as shown in the reverse IV curves (labeled #2 and #3). The amount of leakage current can be kept under control in the embodiments described herein by fine-tuning the barrier height, which depends on various design factors, including, but not limited to, the annealing temperature of the Schottky contact, the pitch of the device, the depth and doping of the P+ region, the doping and depth of the N+ region, and the doping of the Ndrift region.

[0527] Another distinguishing feature of the embodiments described herein is that the N+ substrate of the new device is thinner (typically 100-200 μm) than its counterpart (typically -350 μm). The thinner N+ substrate directly affects the forward IV characteristics, which are the linear region of the forward IV curve. Here, the steeper VF > VKnee slope is due to the thinner substrate's reduced series resistance contributing to the total forward conduction loss. As shown in Figure 28B, a diode with a lower VKnee and a thinned substrate (marked #3) should have lower conduction losses than another diode with a precisely lower VKnee and a thicker substrate (marked #2). In the embodiments described herein, the differential on-resistance (RON, Diff), which is the inverse of the slope of the linear segment of the forward IV curve, is significantly reduced by thinning the N+ substrate. The lower VKnee and RON, Diff of the diodes in the embodiments described herein allow for a significant reduction in forward conduction losses while maintaining reverse leakage low enough for appropriate market needs.

[0528] 29A-29L illustrate the process for fabricating the structure shown in FIG. 28A. The device fabrication process includes preparing a SiC wafer consisting of a highly conductive N+ substrate 301 and an N drift region 302, where the N drift region is typically epitaxially grown, in FIG. 29A. The N drift region 302 is designed such that the doping concentration and thickness of the N drift region are selected primarily based on the desired blocking performance. Once the SiC wafer is prepared, an ion implantation step with n-type species 303, such as nitrogen and / or phosphorus, is performed on the active region of the device in FIG. 29B to form an n+ region within the n drift region. The edge termination, not shown, must be masked during the n-type ion implantation step. Note that in FIG. 29C, the n-type ion implantation step 303 must be performed so that the n+ region 304 is completely embedded within the n drift region. The ion implantation step should form an N+ region 304 whose top is physically separated from the wafer surface.

[0529] A patterned mask 305, preferably a hard mask made of oxide, nitride, polysilicon layer, or a combination thereof, is formed on the wafer surface in Figure 29D. The patterned mask must be thick enough to completely block high energy impurities during the subsequent ion implantation step. A p-type ion implantation step using p-type impurities 306, such as aluminum and / or boron, is performed in Figure 29E, resulting in a p-type ion implantation step in Figure 29F. A set of p+ wells 307 is formed. The bottoms of the set of P+ wells 307 are formed so that they are above the bottom of the N+ region 304. In the embodiment herein, the depth of the set of P+ wells is less than the depth of the N+ region. In FIG. 29F, the collection of P+ wells 305 collectively forms a P+ region. Note that an end termination region (not shown) may be formed by a p-type ion implantation process. The patterned mask 305 is removed by a dry or wet etching process in FIG. 29G. This is followed by a process step in which the wafer is coated with an appropriate coating material, such as a carbon cap, and annealed at a high temperature, such as 1700°C, to electrically activate all of the implanted impurity species. Next, a field oxide layer is formed over the entire wafer surface, and an active region is defined by removing the portion of the field oxide through which conduction current must flow for the device's on-state operation.

[0530] The Schottky contact is formed on the wafer surface by depositing a Schottky metal 308, marked METAL 1, directly onto the wafer surface in Figure 29H. The deposited Schottky metal layer is then patterned using dry etching, wet etching, or lift-off processes and annealed at a specific temperature for a specific time using a furnace or rapid thermal anneal (RTA). The thermal budget of the annealing step after Schottky metal deposition directly affects the barrier height of the Schottky contact and must be carefully designed and controlled. Next, in Figure 29I, a first pad metal 309, marked METAL 2, is deposited on top of the wafer and patterned by dry etching, wet etching, or lift-off. The first pad metal may be an aluminum / aluminum-based alloy. Next, in Figure 29J, the wafer is thinned from its backside until the wafer thickness reaches a target thickness of 100–200 μm. If wafer thinning technology improves to provide a target thickness less than the aforementioned 100–200 μm, the thickness may be further reduced in the future. Wafer thinning can be achieved by chemical mechanical polishing (CMP), wet etching, dry etching, or a combination of the aforementioned grinding techniques with an appropriate protective coating on the front side of the wafer.

[0531] Next, in Figure 29K, a silicide region 310 is formed on the backside of the wafer. The silicide region is required to form a good ohmic contact to the backside of the wafer. The silicide region is formed, for example, by depositing an ohmic metal stack and annealing the wafer using a laser annealing technique. In Figure 29L, a second pad metal 311, marked Metal 3, is formed on the backside of the wafer. The second pad metal may be aluminum or an aluminum-based alloy. After the second pad metal step is completed, a protective coating process step may follow on the wafer to form a moisture barrier.

[0532] Another way to fabricate this embodiment is to start with a SiC wafer with multiple n-type epitaxial layers. In this case, the SiC wafer consists of three n-type epitaxial layers with different doping concentrations and thicknesses, and an n+ substrate at the bottom of the SiC wafer, as shown in Figure 29C. The three n-type epitaxial layers should be formed so that n-layer 302 meets the device side of the wafer, and n+ layer 304 is located directly below the n-layer, which is on top of a second n-layer, also labeled 302, which functions as the drift region, and which is on top of n+ substrate 301.

[0533] To fabricate a SiC wafer with the above epi structure, a patterned mask 305, preferably a hard mask such as an oxide, nitride, polysilicon layer, or a combination thereof, is formed on the wafer surface in FIG. 29D. The patterned mask must be thick enough to completely block high-energy impurities during the subsequent ion implantation step. A p-type ion implantation step using p-type impurities 306, such as aluminum and / or boron, is performed in FIG. 29E to form a set of multiple p+ wells 307 in FIG. 29F. The bottoms of the set of multiple P+ wells 307 are formed such that they are above the bottoms of the N+ regions 304. In an embodiment, the depth of the set of multiple P+ wells is less than the depth of the N+ region. In FIG. 29F, the set of multiple P+ wells collectively forms a P+ region. Note that an end termination region (not shown) may be formed by a p-type ion implantation process. The patterned mask 305 is then removed by a dry or wet etching process in FIG. 29G. This is followed by a process step in which all of the implanted impurity species are electrically activated by coating the wafer with an appropriate coating material, such as a carbon cap, and annealing at a high temperature, such as 1700°C. Active regions are then defined by forming a field oxide layer over the entire wafer surface and removing the portion of the field oxide through which conduction current must flow for the device's on-state operation.

[0534] The Schottky contact is formed on the wafer surface by depositing a Schottky metal layer 308, marked METAL 1, directly onto the wafer surface in Figure 29H. The deposited Schottky metal layer is then patterned using dry etching, wet etching, or lift-off processes and annealed at a specific temperature for a specific time using a furnace or RTA. The thermal budget of the annealing step after Schottky metal deposition directly affects the barrier height of the Schottky contact and must be carefully designed and controlled. Next, in Figure 29I, a first pad metal 309, marked METAL 2, is deposited on top of the wafer and patterned by dry etching, wet etching, or lift-off. The first pad metal may be an aluminum / aluminum-based alloy. Next, in Figure 29J, the wafer is thinned from its backside until the wafer thickness reaches a target thickness of 100–200 μm. If wafer thinning technology improves to provide a target thickness below the aforementioned 100–200 μm, the thickness may be further reduced in the future. Wafer thinning can be achieved by CMP, wet etching, dry etching, or a combination of the aforementioned grinding techniques with an appropriate protective coating on the front side of the wafer.

[0535] Next, in Figure 29K, a silicide region 310 is formed on the backside of the wafer. The silicide region is required to form a good ohmic contact to the backside of the wafer. The silicide region is formed, for example, by depositing an ohmic metal stack and annealing the wafer using a laser annealing technique. In Figure 29L, a second pad metal 311, marked Metal 3, is formed on the backside of the wafer. The second pad metal may be aluminum or an aluminum-based alloy. After the second pad metal step is completed, a protective coating process step may follow on the wafer to form a moisture barrier.

[0536] As seen in the embodiment shown in FIG. 28A , the P+ region 204 of the SiC MPS diode of the present invention is formed as a set of multiple P+ wells that are laterally spaced closer together and extend vertically deeper into the N drift region 202 compared to the prior art. The P+ region of the present invention, in conjunction with the aforementioned N+ region, is designed to provide robust shielding to the Schottky barrier formed on the wafer surface. In contrast, prior art devices are vulnerable to high electric field stresses at the Schottky contact, which easily result in temporary or permanent degradation of the Schottky contact, leading to high leakage currents and / or irreversible breakdown of the device. It is clear that prior art devices have the N drift region as the only conduction path, and majority carriers flowing through the JFET-like region between the P+ wells near the wafer surface are affected by carrier transport, increasing the total forward conduction loss.

[0537] Figure 28C compares the key dimensions of the device structures of the present invention. Regardless of the device type, the lateral spacing between two adjacent P+ wells is defined as Wl, and the vertical depth of the P+ well measured from the surface of the SiC wafer is defined as DI. Note that the ratio of Wl to DI (or Wl / Dl) for the devices of the present invention is less than 3.0 (or Wl / Dl < 3.0).

[0538] The embodiment device shown in Figure 30 is a cross-sectional schematic of a SiC MPS diode. The critical area of ​​this device is the bottom N+ substrate 401, which provides mechanical support for the wafer and is ~350 μm thick. There is an N drift region 402, typically an epilayer, that overlies the N+ substrate. There are multiple P+ wells 404, formed as linear stripes or more complex circular or hexagonal patterns. The device has a first metal layer 405, designated METAL 1, which is a Schottky metal to the n-type SiC semiconductor region and forms a Schottky contact to the underlying n-type region. On the front side of the wafer in contact with METAL 1, the device has a second metal layer 406, designated METAL 2. Metal 2 is often referred to as the "power metal" and is typically aluminum. Beneath the bottom of the N+ substrate is a silicide layer 407. Beneath the back side of the wafer in contact with the silicide layer is a third metal layer 408, designated METAL 3.

[0539] The device shown in FIG. 30 has N+ regions 403 interspersed among a set of multiple P+ wells 404. The N+ regions 403 extend adjacent to the P+ regions 404 but do not completely cover the bottom of the P+ regions. The physical separation of the N+ regions from the SiC wafer surface is an important feature of the embodiments described herein and distinguishes them from other similar inventions. The portion of the SiC wafer that is in contact with the Schottky metal 405, labeled METAL 1, and is an n-type semiconductor has the same doping concentration as Ndrift 402. In the embodiments described herein, the doping concentration of the n-type SiC semiconductor in direct contact with the Schottky metal 405, labeled METAL 1, is important for reducing the strength of the electric field at the wafer surface during the high-voltage blocking mode of operation of the SiC MPS diode. The vertical extent of the N+ regions 403 is above the bottom of the P+ regions 404. The buried N+ regions do not completely cover the bottom of the P+ regions.

[0540] 31A-31L illustrate the process for fabricating the structure shown in FIG. 30. The device fabrication process involves preparing a SiC wafer consisting of a highly conductive N+ substrate 501 and an N drift region 502, where the N drift region is typically epitaxially grown, in FIG. 31A. The N drift region 502 is designed such that the doping concentration and thickness of the N drift region are selected primarily based on the desired blocking performance. Once the SiC wafer is prepared, an ion implantation step with n-type species 503, such as nitrogen and / or phosphorus, is performed on the active region of the device in FIG. 31B to form an n+ region within the n drift region. The edge termination, not shown, must be masked during the n-type ion implantation step. Note that in FIG. 31C, the n-type ion implantation step 503 must be performed so that the n+ region 504 is completely embedded within the n drift region. The ion implantation step should form an N+ region 504 whose top is physically separated from the wafer surface.

[0541] A patterned mask 505, preferably a hard mask made of oxide, nitride, polysilicon layer, or a combination thereof, is formed on the wafer surface in FIG. 31D. The patterned mask must be thick enough to completely block high-energy impurities during a subsequent ion implantation step. A p-type ion implantation step using p-type impurities 506, such as aluminum and / or boron, is performed in FIG. 31E, forming a set of p+ wells 507 in FIG. 31F. The bottoms of the set of P+ wells 507 are formed such that they are below the bottom of the N+ region 504. In embodiments herein, the depth of the set of P+ wells is greater than the depth of the N+ region. In FIG. 31F, the set of P+ wells collectively forms a P+ region. Note that an end termination region (not shown) may also be formed by the p-type ion implantation step. The patterned mask 505 is removed by a dry or wet etching process in FIG. 31G. This is followed by a process step in which all of the implanted impurity species are electrically activated by coating the wafer with a suitable coating material, such as a carbon cap, and annealing at a high temperature, such as 1700° C. The activation is then completed by forming a field oxide layer over the entire wafer surface and removing the portion of the field oxide through which conduction current must flow for the device's on-state operation. A region is defined.

[0542] The Schottky contact is formed on the wafer surface by depositing a Schottky metal layer 508, marked METAL 1, directly onto the wafer surface (Figure 31H). The deposited Schottky metal layer is then patterned using dry etching, wet etching, or lift-off processes and annealed at a specific temperature for a specific time using a furnace or RTA. The thermal budget of the annealing step after Schottky metal deposition directly affects the barrier height of the Schottky contact and must be carefully designed and controlled. Next, in Figure 311, a first pad metal 509, marked METAL 2, is deposited on top of the wafer and patterned by dry etching, wet etching, or lift-off. The first pad metal may be an aluminum / aluminum-based alloy. Next, in Figure 31J, the wafer is thinned from its backside until the wafer thickness reaches a target thickness of 100–200 μm. If wafer thinning technology improves to provide a target thickness below the aforementioned 100–200 μm, the thickness may be further reduced in the future. Wafer thinning can be achieved by CMP, wet etching, dry etching, or a combination of the aforementioned grinding techniques with an appropriate protective coating on the front side of the wafer.

[0543] Next, in FIG. 31K, a silicide region 510 is formed on the backside of the wafer. The silicide region is required to form a good ohmic contact to the backside of the wafer. The silicide region is formed, for example, by depositing an ohmic metal stack and annealing the wafer using a laser annealing technique. In FIG. 31L, a second pad metal 511, marked METAL 3, is formed on the backside of the wafer. The second pad metal may be aluminum or an aluminum-based alloy. After the second pad metal step is completed, a protective coating process step may follow on the wafer to form a moisture barrier.

[0544] Another way to fabricate this embodiment is to start with a SiC wafer with multiple n-type epitaxial layers. In this case, the SiC wafer consists of three n-type epitaxial layers with different doping concentrations and thicknesses, as shown in Figure 31C, and an n+ substrate at the bottom of the SiC wafer. The three n-type epitaxial layers should be formed so that n layer 502 meets the device side of the wafer, and n+ layer 504 is located directly below the n layer, which is on top of a second n layer, also labeled 502, which acts as the drift region, and which is on top of n+ substrate 501.

[0545] In preparing a SiC wafer having the above-described epi structure, a patterned mask 505, preferably a hard mask made of oxide, nitride, polysilicon, or a combination thereof, is formed on the wafer surface in FIG. 31D. The patterned mask must be thick enough to completely block high-energy impurities during a subsequent ion implantation step. A p-type ion implantation step using p-type impurities 506, such as aluminum and / or boron, is performed in FIG. 31E, forming a set of p+ wells 507 in FIG. 31F. The bottoms of the set of P+ wells 507 are formed below the bottom of the N+ region 504. In embodiments herein, the depth of the set of P+ wells is greater than the depth of the N+ region. In FIG. 31F, the set of P+ wells collectively forms a P+ region. Note that an edge termination region (not shown) may also be formed by the p-type ion implantation step. The patterned mask 505 is then removed by a dry or wet etching process in FIG. 31G. This is followed by a process step in which all of the implanted impurity species are electrically activated by coating the wafer with a suitable coating material, such as a carbon cap, and annealing at a high temperature, such as 1700° C. The active area is then defined by forming a field oxide layer over the entire wafer surface and removing the portion of the field oxide through which conduction current must flow for on-state operation of the device. do.

[0546] The Schottky contact is formed on the wafer surface by depositing a Schottky metal layer 508, marked METAL 1, directly onto the wafer surface (Figure 31H). The deposited Schottky metal layer is then patterned using dry etching, wet etching, or lift-off processes and annealed at a specific temperature for a specific time using a furnace or RTA. The thermal budget of the annealing step after Schottky metal deposition directly affects the barrier height of the Schottky contact and must be carefully designed and controlled. Next, in Figure 311, a first pad metal 509, marked METAL 2, is deposited on top of the wafer and patterned by dry etching, wet etching, or lift-off. The first pad metal may be an aluminum / aluminum-based alloy. Next, in Figure 31J, the wafer is thinned from its backside until the wafer thickness reaches a target thickness of 100–200 μm. If wafer thinning technology improves to provide a target thickness below the aforementioned 100–200 μm, the thickness may be further reduced in the future. Wafer thinning can be achieved by CMP, wet etching, dry etching, or a combination of the aforementioned grinding techniques with an appropriate protective coating on the front side of the wafer.

[0547] Next, in FIG. 31K, a silicide region 510 is formed on the backside of the wafer. The silicide region is required to form a good ohmic contact to the backside of the wafer. The silicide region is formed, for example, by depositing an ohmic metal stack and annealing the wafer using a laser annealing technique. In FIG. 31L, a second pad metal 511, marked METAL 3, is formed on the backside of the wafer. The second pad metal may be aluminum or an aluminum-based alloy. After the second pad metal step is completed, a protective coating process step may follow on the wafer to form a moisture barrier.

[0548] The embodiment shown in FIG. 30 further reduces the electric field at the Schottky metal interface, thereby providing lower leakage current and better blocking performance than the embodiment shown in FIG. 28A, but at the cost of a higher on-state voltage drop compared to the embodiment shown in FIG. 28A.

[0549] The embodiment devices shown in Figures 32A-32F are cross-sectional schematic diagrams of SiC MPS diodes. The critical area of ​​these devices is the bottom N+ substrate 601, which provides mechanical support for the wafer and is -350 μm thick. An N drift region 602, typically an epilayer, sits atop the N+ substrate. The device has a first metal layer 605, designated METAL 1, which is a Schottky metal to the n-type SiC semiconductor region and forms a Schottky contact to the underlying n-type region. The device has a second metal layer 606, designated METAL 2, on the front side of the wafer in contact with METAL 1. Metal 2 is often referred to as the "power metal" and is typically aluminum. Beneath the bottom of the N+ substrate is a silicide layer 607. Beneath the back side of the wafer in contact with the silicide layer is a third metal layer 608, designated METAL 3. The device of the embodiment of Figures 32A-32F differs from the device shown in the embodiment of Figures 28A and 30 because the N+ region in the previous embodiment is replaced by a set of multiple N sub-regions 603 arranged in layers. The thickness and doping concentration in each of these sub-regions may be different. Similarly, the P+ region of the device in the embodiment of Figures 28A and 30 is replaced by a set of multiple layered P sub-regions. The doping concentration in each slice can be preferably designed.

[0550] The device in the embodiment shown in Figures 32A-32F has N+ regions 603 interspersed among a set of P+ wells 604. Some potential examples of the embodiment shown in Figures 32A-32F 32A and 32B , devices with multiple sets of n-type sublayers with different thicknesses and doping concentrations, but with multiple sets of p-type wells of the same type as in FIGS. 32A and 32B ; devices with multiple sets of p-type sublayers with different thicknesses and doping concentrations, but with a single n-type layer that serves as an n+ region, as in FIGS. 32C and 32D ; devices with multiple sets of n-type sublayers with different thicknesses and doping concentrations, as in FIGS. 32E and 32F ; and devices with multiple sets of p-type sublayers with different thicknesses and doping concentrations. The devices in FIGS. 32A , 32C , and 32E have N+ regions 603 around and below P+ wells 604, while the devices in FIGS. 32B , 32D , and 32F have N+ regions 603 located between the P+ wells, but not around them. The physical separation of the N+ regions from the SiC wafer surface is a key feature of the embodiments described herein and distinguishes them from other similar inventions. The portion of the SiC wafer that is in contact with the Schottky metal 605, labeled METAL 1, and that is an n-type semiconductor, has the same doping concentration of Ndrift 602. In the embodiments described herein, the doping concentration of the n-type SiC semiconductor that is in direct contact with the Schottky metal 605, labeled METAL 1, is important for reducing the strength of the electric field at the wafer surface during the high-voltage blocking mode of operation of the SiC MPS diode.

[0551] FIGS. 33AA-33AL illustrate the process for fabricating the structure shown in FIG. 32A. The device fabrication process includes preparing a SiC wafer consisting of a highly conductive N+ substrate 701a and an N drift region 702a, where the N drift region is typically epitaxially grown, in FIG. 33AA. The N drift region 702a is designed such that the doping concentration and thickness of the N drift region are selected primarily based on the desired blocking performance. Once the SiC wafer is prepared, a set of ion implantation steps with n-type species 703a, such as nitrogen and / or phosphorus, is performed on the active region of the device in FIG. 33AB. The set of ion implantation steps with n-type species forms a set of sub-n-type regions 704a in FIG. 33AC, each defined by a dotted line in the schematic diagram to indicate the top and bottom of the sub-region, and all sub-regions are interconnected. The interconnected sub-regions collectively comprise an N+ region. Edge terminations, not shown, need to be masked during the set of n-type ion implantation steps. Note that in Figure 33C, n-type ion implantation step 703a must be performed so that n+ region 704a is completely embedded within the n-drift region. The ion implantation step should form N+ region 704a such that the top of the N+ region is physically separated from the wafer surface.

[0552] A patterned mask 705a, preferably a hard mask made of oxide, nitride, polysilicon, or a combination thereof, is formed on the wafer surface in FIG. 33AD. The patterned mask must be thick enough to completely block high-energy impurities during a subsequent ion implantation step. A p-type ion implantation step using p-type impurities 706a, such as aluminum and / or boron, is performed in FIG. 33AE, resulting in the formation of a set of p+ wells 707a in FIG. 33AF. The bottoms of the set of P+ wells 707a are formed such that they are above the bottoms of N+ regions 704a. In embodiments herein, the depth of the set of P+ wells is less than the depth of the N+ regions. The set of P+ wells collectively forms a P+ region in FIG. 33AF. An end termination region, not shown, may be formed by the p-type ion implantation step. The patterned mask 705a is removed by a dry or wet etching process in FIG. 33AG. This is followed by a process step in which all of the implanted impurity species are electrically activated by coating the wafer with a suitable coating material, such as a carbon cap, and annealing at a high temperature, such as 1700° C. The active area is then defined by forming a field oxide layer over the entire wafer surface and removing the portion of the field oxide through which conduction current must flow for the device's on-state operation.

[0553] Schottky contacts are formed on the wafer surface by depositing Schottky metal 708a, marked as Metal 1 in Figure 33AH, directly on the wafer surface. The deposited Schottky metal layer is then patterned using dry etching, wet etching, or lift-off processes and annealed at a specific temperature for a specific time using a furnace or RTA. The thermal budget of the annealing step after Schottky metal deposition directly affects the barrier height of the Schottky contact and must be carefully designed and controlled. Next, in Figure 33AI, a first pad metal 709a, marked METAL 2, is deposited on top of the wafer and patterned by dry etching, wet etching, or lift-off. The first pad metal may be an aluminum / aluminum-based alloy. Next, in Figure 33AJ, the wafer is thinned from its backside until it reaches a target thickness of 100–200 μm. If wafer thinning technology improves to provide a target thickness below the aforementioned 100–200 μm, the thickness may be further reduced in the future. Wafer thinning can be achieved by CMP, wet etching, dry etching, or the aforementioned grinding techniques in combination with an appropriate protective coating on the front side of the wafer.

[0554] Next, in FIG. 33AK, a silicide region 710a is formed on the backside of the wafer. The silicide region is required to form a good ohmic contact to the backside of the wafer. The silicide region is formed, for example, by depositing an ohmic metal stack and annealing the wafer using a laser annealing technique. In FIG. 33(A), a second pad metal 711a, labeled Metal 3, is formed on the backside of the wafer. The second pad metal may be aluminum or an aluminum-based alloy. After the second pad metal step is completed, a protective coating process step may follow on the wafer to form a moisture barrier.

[0555] Another method for fabricating this embodiment is to start with a SiC wafer with multiple n-type epitaxial layers. In this case, the SiC wafer consists of multiple n-type epitaxial layers with different doping concentrations and thicknesses, and an n+ substrate at the bottom of the SiC wafer, as shown in Figure 33C. An N drift layer 702a can be epitaxially grown on top of the N+ substrate 701a to function as a drift / blocking layer. On top of the n drift layer, several n-type epitaxial layers can be grown to form an n+ region 704a as a whole, which consists of a set of sub-n-type regions, each defined by a different doping concentration and thickness, and all sub-regions interconnected. On top of the buried N+ region, an N layer can be formed that reaches the surface of the SiC wafer 702a.

[0556] To prepare a SiC wafer having the epitaxial structure described above, a patterned mask 705a, preferably a hard mask made of oxide, nitride, polysilicon, or a combination thereof, is formed on the wafer surface in FIG. 33D. The patterned mask must be thick enough to completely block high-energy impurities during a subsequent ion implantation step. In FIG. 33AE, a p-type ion implantation step using p-type impurities 706a, such as aluminum and / or boron, is performed, resulting in the formation of a set of p+ wells 707a in FIG. 33AF. The bottoms of the set of P+ wells 707a are formed so that they are above the bottoms of the N+ regions 704a. In embodiments herein, the depth of the set of P+ wells is less than the depth of the N+ regions. The set of P+ wells collectively forms a P+ region in FIG. 33AF. Note that an edge termination region (not shown) may also be formed by the p-type ion implantation step. The patterned mask 705a is then removed by a dry or wet etching process in FIG. 33A-G. This is followed by a process step in which all of the implanted impurity species are electrically activated by coating the wafer with a suitable coating material, such as a carbon cap, and annealing at a high temperature, such as 1700° C. The active area is then defined by forming a field oxide layer over the entire wafer surface and removing the portion of the field oxide through which conduction current must flow for the device's on-state operation.

[0557] The Schottky contact is formed on the wafer surface by depositing a Schottky metal 708a, marked METAL 1, directly on the wafer surface in Figure 33AH. The deposited Schottky metal layer is then patterned using dry etching, wet etching, or lift-off processes and annealed at a specific temperature for a specific time using a furnace or RTA. The thermal budget of the annealing step after Schottky metal deposition directly affects the barrier height of the Schottky contact and must be carefully designed and controlled. Next, in Figure 33AI, a first pad metal 709a, marked METAL 2, is deposited on top of the wafer and patterned by dry etching, wet etching, or lift-off. The first pad metal may be an aluminum / aluminum-based alloy. Next, in Figure 33AJ, the wafer is thinned from its backside until it reaches a target thickness of 100 to 200 μm. If wafer thinning technology improves to provide a target thickness less than the aforementioned 100 to 200 μm, the thickness may be further reduced in the future. Wafer thinning can be achieved by CMP, wet etching, dry etching, or a combination of the aforementioned grinding techniques with an appropriate protective coating on the front side of the wafer.

[0558] Next, in Figure 33AK, silicide regions 710a are formed on the backside of the wafer. The silicide regions are required to form good ohmic contacts to the backside of the wafer. By way of example, the silicide regions are formed by depositing an ohmic metal stack and annealing the wafer using a laser annealing technique. In Figure 33AL, a second pad metal 711, labeled Metal 3, is formed on the backside of the wafer. The second pad metal may be aluminum or an aluminum-based alloy. After the second pad metal step is completed, a protective coating process step may follow on the wafer to form a moisture barrier.

[0559] Figures 33BA-33BL illustrate the process for fabricating the structure shown in Figure 32B. The device fabrication process includes preparing a SiC wafer consisting of a highly conductive N+ substrate 701b and an N drift region 702b, where the N drift region is typically epi-grown, in Figure 33BA. The N drift region 702b is designed such that the doping concentration and thickness of the N drift region are selected primarily based on the desired blocking performance. Once the SiC wafer is prepared, a set of ion implantation steps with n-type species 703b, such as nitrogen and / or phosphorus, is performed on the active region of the device in Figure 33BB. The set of ion implantation steps with n-type species forms a set of subregions 704b in Figure 33BC, where each subregion is defined by a dotted line in the schematic diagram to indicate the top and bottom of the subregion, and all subregions are interconnected. The interconnected subregions collectively comprise the N+ region. Edge terminations, not shown, need to be masked during the set of n-type ion implantation steps. Note that in Figure 33(BC), n-type ion implantation step 703b must be performed so that n+ region 704b is completely embedded within the n-drift region. The ion implantation step should form N+ region 704b such that the top of the N+ region is physically separated from the wafer surface.

[0560] A patterned mask 705b, preferably a hard mask made of oxide, nitride, polysilicon layer, or a combination thereof, is formed on the wafer surface in Figure 33BD. The patterned mask must be thick enough to completely block high-energy impurities during a subsequent ion implantation step. A p-type ion implantation step using p-type impurities 706b, such as aluminum and / or boron, is performed in Figure 33BE to form a set of p+ wells 707b in Figure 33BF. The bottoms of the set of P+ wells 707b are formed such that they are below the bottom of N+ region 704b. In embodiments herein, the depth of the set of P+ wells is greater than the depth of the N+ region. In Figure 33BF, the set of P+ wells collectively results in a P+ region. Note that an end termination region, not shown, is formed by the p-type ion implantation step. The patterned mask 705b is then removed in Figure 33BG by a dry or wet etching process. This is followed by a process step in which all of the implanted impurity species are electrically activated by coating the wafer with a suitable coating material, such as a carbon cap, and annealing at a high temperature, such as 1700°C. The active area is then defined by forming a field oxide layer over the entire wafer surface and removing the portion of the field oxide through which conduction current must flow for on-state operation of the device.

[0561] The Schottky contact is formed on the wafer surface by depositing Schottky metal 708b, marked as Metal 1, directly on the wafer surface in Figure 33BH. The deposited Schottky metal layer is then patterned using dry etching, wet etching, or lift-off processes and annealed at a specific temperature for a specific time using a furnace or RTA. The thermal budget of the annealing step after Schottky metal deposition directly affects the barrier height of the Schottky contact and must be carefully designed and controlled. Next, in Figure 33BI, a first pad metal 709b, marked as Metal 2, is deposited on top of the wafer and patterned by dry etching, wet etching, or lift-off. The first pad metal may be an aluminum / aluminum-based alloy. Next, in Figure 33BJ, the wafer is thinned from the backside until the wafer reaches a target thickness of 100 to 200 μm. If wafer thinning technology improves to provide a target thickness less than the aforementioned 100 to 200 μm, the thickness may be further reduced in the future. Wafer thinning can be achieved by CMP, wet etching, dry etching, or a combination of the aforementioned grinding techniques with an appropriate protective coating on the front side of the wafer.

[0562] Next, in FIG. 33BK, a silicide region 710b is formed on the backside of the wafer. The silicide region is required to form a good ohmic contact to the backside of the wafer. The silicide region is formed, for example, by depositing an ohmic metal stack and annealing the wafer using a laser annealing technique. In FIG. 33BL, a second pad metal 711b, labeled Metal 3, is formed on the backside of the wafer. The second pad metal may be aluminum or an aluminum-based alloy. After the second pad metal step is completed, a protective coating process step may follow on the wafer to form a moisture barrier.

[0563] Another method for fabricating this embodiment is to start with a SiC wafer with multiple n-type epitaxial layers. In this case, the SiC wafer consists of multiple n-type epitaxial layers with different doping concentrations and thicknesses, and an n+ substrate at the bottom of the SiC wafer, as shown in Figure 33BC. An N drift layer 702b can be epitaxially grown on top of the N+ substrate 701b to function as a drift / blocking layer. On top of the n drift layer, several n-type epitaxial layers can be grown to form an n+ region 704b as a whole, which consists of a set of n-type subregions, each defined by a different doping concentration and thickness, and all subregions interconnected. On top of the buried N+ region, an N layer can be formed that reaches the surface of the SiC wafer 702b.

[0564] In preparing the epitaxial SiC wafer, a patterning mask 705b, preferably a hard mask made of oxide, nitride, polysilicon, or a combination thereof, is formed on the wafer surface as shown in FIG. 33(b). The patterned mask must be thick enough to completely block high-energy impurities during the subsequent ion implantation step. A p-type ion implantation step using p-type impurities 706b, such as aluminum and / or boron, is performed in FIG. 33BE to form a set of p+ wells 707b in FIG. 33BF. The bottoms of the set of p+ wells 707b are formed such that they are below the bottoms of the N+ regions 704b. In the embodiments herein, the depth of the set of multiple P+ wells is greater than the depth of the N+ region. In FIG. 33BF, the set of multiple P+ wells collectively forms a P+ region. Note that an end termination region (not shown) may be formed by a p-type ion implantation step. The patterned mask 705b is then removed by a dry or wet etching process in FIG. 33BG. This is followed by a process step in which the wafer is coated with an appropriate coating material, such as a carbon cap, and annealed at a high temperature, such as 1700°C, to electrically activate all of the implanted impurity species. Next, an active region is defined by forming a field oxide layer over the entire wafer surface and removing the portion of the field oxide through which conduction current must flow for the device's on-state operation.

[0565] The Schottky contact is formed on the wafer surface by depositing a Schottky metal layer 708b, marked Metal 1, directly onto the wafer surface in Figure 33BH. The deposited Schottky metal layer is then patterned using dry etching, wet etching, or lift-off processes and annealed at a specific temperature for a specific time using a furnace or RTA. The thermal budget of the annealing step after Schottky metal deposition directly affects the barrier height of the Schottky contact and must be carefully designed and controlled. Next, in Figure 33BI, a first pad metal layer 709b, marked Metal 2, is deposited on top of the wafer and patterned by dry etching, wet etching, or lift-off. The first pad metal may be an aluminum / aluminum-based alloy. Next, in Figure 33BJ, the wafer is thinned from the backside until the wafer reaches a target thickness of 100–200 μm. If wafer thinning technology improves to provide a target thickness less than the aforementioned 100–200 μm, the thickness may be further reduced in the future. Wafer thinning can be achieved by CMP, wet etching, dry etching, or a combination of the aforementioned grinding techniques with an appropriate protective coating on the front side of the wafer.

[0566] Next, in FIG. 33BK, a silicide region 710b is formed on the backside of the wafer. The silicide region is required to form a good ohmic contact to the backside of the wafer. The silicide region is formed, for example, by depositing an ohmic metal stack and annealing the wafer using a laser annealing technique. In FIG. 33BL, a second pad metal 711b, labeled Metal 3, is formed on the backside of the wafer. The second pad metal may be aluminum or an aluminum-based alloy. After the second pad metal step is completed, a protective coating process step may follow on the wafer to form a moisture barrier.

[0567] Figures 33EA-33EL illustrate the process for fabricating the structure shown in Figure 32E. The device fabrication process involves preparing a SiC wafer of Figure 33EA consisting of a highly conductive N+ substrate 701e and an N drift region 702e, which is typically epitaxially grown. The N drift region 702e is designed so that the doping concentration and thickness of the N drift region are selected primarily based on the desired blocking performance. When preparing the SiC wafer, a set of ion implantation steps with n-type species 703e, such as nitrogen and / or phosphorus, is performed on the active region of the device of Figure 33EB. The set of ion implantation steps using n-type species forms a set of sub-type regions 704e of Figure 33EC, where each sub-region is defined by dotted lines in the schematic diagram to indicate the top and bottom of the sub-region, and all sub-regions are interconnected. The interconnected sub-regions collectively comprise an N+ region. Edge terminations, not shown, need to be masked during the set of n-type ion implantation steps. Note that in Figure 33C, n-type ion implantation step 703e must be performed so that n+ region 704e is completely embedded within the n-drift region. The ion implantation step should form N+ region 704e such that the top of the N+ region is physically separated from the wafer surface.

[0568] A patterned mask 705e, preferably a hard mask made of oxide, nitride, polysilicon layer, or a combination thereof, is formed on the wafer surface in FIG. 33ED. The patterned mask must be thick enough to completely block high-energy impurities during subsequent ion implantation steps. A set of ion implantation steps using p-type impurities 706e, such as aluminum and / or boron, is performed in FIG. 33EE to form a set of p+ wells 707e in FIG. 33EF. The set of ion implantation steps with p-type species forms a set of sub-p-type regions 707e in FIG. 33EF, where each sub-region is defined by dotted lines in the schematic diagram to indicate the top and bottom of the sub-region, and all sub-regions are interconnected. P+ region 707e is formed by a plurality of P sub-regions. The bottoms of the set of P+ wells 707e are formed such that they are above the bottoms of N+ regions 704e. In embodiments herein, the depth of the set of P+ wells is less than the depth of the N+ regions. The set of multiple P+ wells collectively results in a P+ region in Figure 33EF. Note that an end termination region (not shown) may be formed by a p-type ion implantation process. The patterned mask 705e is then removed by a dry or wet etching process in Figure 33EG. This is followed by a process step in which all of the implanted impurity species are electrically activated by coating the wafer with a suitable coating material, such as a carbon cap, and annealing at a high temperature, such as 1700°C. The active region is then defined by forming a field oxide layer over the entire wafer surface and removing the portion of the field oxide through which conduction current must flow for the device's on-state operation.

[0569] The Schottky contact is formed on the wafer surface by depositing a Schottky metal layer 708e, marked METAL 1, directly onto the wafer surface in Figure 5FEH. The deposited Schottky metal layer is then patterned using dry etching, wet etching, or lift-off processes and annealed at a specific temperature for a specific time using a furnace or RTA. The thermal budget of the annealing step after Schottky metal deposition directly affects the barrier height of the Schottky contact and must be carefully designed and controlled. Next, in Figure 33EI, a first pad metal layer 709e, marked METAL 2, is deposited on top of the wafer and patterned by dry etching, wet etching, or lift-off. The first pad metal may be an aluminum / aluminum-based alloy. Next, in Figure 33EJ, the wafer is thinned from the backside until the wafer thickness reaches a target thickness of 100–200 μm. If wafer thinning technology improves to provide a target thickness below the aforementioned 100–200 μm, the thickness may be further reduced in the future. Wafer thinning can be achieved by CMP, wet etching, dry etching, or a combination of the aforementioned grinding techniques with an appropriate protective coating on the front side of the wafer.

[0570] Next, in Figure 33EK, a silicide region 710e is formed on the backside of the wafer. The silicide region is required to form a good ohmic contact to the backside of the wafer. The silicide region is formed, for example, by depositing an ohmic metal stack and annealing the wafer using a laser annealing technique. In Figure 33EL, a second pad metal 711e, labeled Metal 3, is formed on the backside of the wafer. The second pad metal may be aluminum or an aluminum-based alloy. After the second pad metal step is completed, a protective coating process step may follow on the wafer to form a moisture barrier.

[0571] Another way to fabricate this embodiment is to start with a SiC wafer with multiple n-type epitaxial layers. In this case, the SiC wafer consists of multiple n-type epitaxial layers with different doping concentrations and thicknesses, and an n+ substrate at the bottom of the SiC wafer, as shown in Figure 33EC. On top of the N+ substrate 701e, an N drift layer 702e can be epitaxially grown to act as ...

Claims

1. A device comprising a unit cell on a silicon carbide (SiC) substrate, the unit cell comprising: a gate insulating film, a trench in a well region, and a second conductive type semiconductor layer in the well region; and a second sinker region having the second conductivity type, wherein the first sinker region and the second sinker region each contact a region having the first conductivity type to form a pn junction, the first sinker region beneath the trench, and a lateral extent of the first sinker region aligned with the lateral extent of the trench, and the device has an on-resistance of less than 4 milliohm centimeters squared, a gate threshold voltage of greater than 1.5 volts, a breakdown voltage of greater than 500 volts, and an electric field in the gate dielectric of less than 3.5 megavolts / cm.

2. The device comprises a metal-insulator-semiconductor transistor component. The device of claim 1.

3. The well region is adjacent to the insulator-semiconductor interface, and the source region of the first conductivity type is The device of claim 1 formed in a well region.

4. 4. The method of claim 3, wherein the depth of the trench is equal to or exceeds the thickness of the source region. device.

5. The device of claim 1 , wherein the depth of the second sinker region is less than the depth of the first sinker region.

6. 10. The method of claim 1, wherein a depth of the second sinker region exceeds a depth of the well region. device.

7. A device comprising a unit cell on a silicon carbide (SiC) substrate, the unit cell comprising:

1. A device comprising: a gate insulating film; a trench in a well region; a first sinker region of a second conductivity type; a second sinker region of the second conductivity type; and a source region, the source region being in direct contact with the second sinker region, the device having an avalanche energy, calculated by dividing the avalanche energy in Joules by the total die area in cm, of greater than 10 Joules / cm.

8. The device comprises a metal-insulator-semiconductor transistor component.

7. The device according to claim 7.

9. The unit cell comprises a semiconductor body of a first conductivity type including a drift zone, an insulator-semiconductor body, and 8. The device of claim 7, further comprising a well region of the second conductivity type adjacent the conductor interface, and a source region of the first conductivity type formed within the well region.

10. The depth of the trench is equal to or greater than the thickness of the source region.

8. The device of claim 7.

11. The device of claim 7 , wherein the depth of the trench exceeds the depth of the source region.

12. The device of claim 7 , wherein the avalanche fault is located within the unit cell.

13. A device comprising a unit cell on a silicon carbide (SiC) substrate, the unit cell a gate dielectric, a trench in a well region, a first sinker region of a second conductivity type, a second sinker region of a second conductivity type, and a source region, wherein the first sinker region has a depth greater than a depth of the second sinker region and the second sinker region has a width greater than that of the first sinker region, and the device has an avalanche energy greater than 10 Joules / cm2, calculated by dividing the avalanche energy in Joules by a total die area in cm2.

14. The device of claim 13 , wherein the avalanche fault is located within the unit cell.

15. the depth of the second sinker region is less than the depth of the first sinker region; 14. The device of claim 13.

16. 14. The device of claim 13, wherein a depth of the second sinker region exceeds a depth of the well region. Vice.

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