Semiconductor component and method for manufacturing semiconductor component

Abstract

To provide a silicon carbide semiconductor component having a deep p-doped layer.SOLUTION: There is provided a semiconductor component 200 including a semiconductor substrate 201. The semiconductor substrate has a first side, and an epitaxial layer 202 is situated on the first side. On the epitaxial layer, body regions 203 are sectionally situated, and on the body regions, source regions 204 are situated. A plurality of first trenches 205 and a plurality of second trenches 206 extend starting from the source regions into the epitaxial layer. The first trenches have a greater depth than the second trenches. A second trench sectionally extends into a first trench in each case. On a trench surface of the first trenches, a layer having a first doping concentration is situated in each case. The first trenches are filled with a first material 207 having a second doping concentration, the first doping concentration having a higher value than the second doping concentration.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to semiconductor components and methods for manufacturing semiconductor components. [Background technology]

[0002] Silicon carbide-based semiconductor components have a breakdown strength approximately seven times higher than silicon-based semiconductor components. Therefore, the gate oxide must be shielded from the high electric field strength during a high positive voltage between the drain and source during a blocking operation. The short-circuit current is high in silicon carbide substrates due to the high doping and thin epitaxial layer, and therefore must be limited. A deep p-doped region specially designed for this purpose, which creates a pronounced JFET effect, i.e., the current path is narrowed as the voltage increases, both shielding the electric field during the blocking operation and limiting the current during a short circuit.

[0003] This deep, structured p-doped region is created by high-energy implantation, which extends through the body region and into the epitaxial layer, shielding the gate oxide from high electric field strengths. Creating a deep p-doped region requires energies greater than 1 MeV. This not only increases manufacturing costs, but can also cause severe damage to the semiconductor crystal and lateral ion scattering over the pitch dimension.

[0004] The object of the present invention is to overcome these drawbacks. Summary of the Invention [Means for solving the problem]

[0005] The semiconductor component includes a semiconductor substrate having a first surface on which an epitaxial layer is disposed. A body region is disposed on a portion of the epitaxial layer. A source region is disposed on the body region. multiple The first groove and multiple The second trenches extend into the epitaxial layer. The first trenches have a greater depth than the second trenches. Each second trench partially extends into one first trench. According to the present invention, a layer having a first doping concentration is disposed on the trench surface of each first trench. The first trenches are filled with a first material, and the first material has a second doping concentration. The first doping concentration is higher than the second doping concentration.

[0006] The advantage in this case is that the semiconductor component has a low gate-drain capacitance, a high blocking strength, and a high short-circuit strength.

[0007] In one variation, metal areas are placed in some areas just above the epitaxial layer.

[0008] In this case, it is advantageous that the Schottky diode is monolithically integrated in the semiconductor component and connected in parallel with the body diode, which allows stable reverse operation at low forward voltages and low blocking currents.

[0009] In a further embodiment, a first insulating layer having a dielectric constant higher than silicon dioxide is disposed on the surface of the second trench, and the second trench is filled with a second material, i.e., a dielectric constant greater than 3.9. The advantage of this is that the gate-drain capacitance is reduced. The problem is that the quantity is small.

[0010] In one variant, the first insulating layer has a constant thickness. The advantage here is that it is easy to manufacture.

[0011] In a further aspect, the first insulating layer on the sidewalls of the trench surface of the second trench has different thicknesses. The advantage in this case is that the gate terminal is more shielded in case of interruption.

[0012] In one variation, the semiconductor substrate comprises silicon carbide. In a further embodiment, the semiconductor component is a MISFET.

[0013] In one variation, the semiconductor substrate comprises gallium nitride. A method for manufacturing a semiconductor component according to the present invention includes applying an epitaxial layer on a semiconductor substrate, forming a body region on the epitaxial layer in a region, and forming a source region on the body region. The method further includes forming a first trench extending from a surface of the source region into the epitaxial layer, forming a layer having a first doping concentration at a surface of the first trench, and filling the first trench with highly p-doped polysilicon. The method further includes forming a second trench extending from a surface of the source region into the epitaxial layer and partially extending into the first trench, forming a first insulating layer at a surface of the second trench, filling the second trench with highly n-doped polysilicon, forming a second insulating layer over the source region, forming an ohmic contact, and forming a backside metallization.

[0014] Further advantages are apparent from the following description of exemplary embodiments or from the dependent claims. The present invention will be described below based on preferred embodiments and the accompanying drawings. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram showing a transistor cell of a MISFET according to the prior art. [Figure 2] 1 shows a cell of a first exemplary embodiment of a semiconductor component; [Figure 3]FIG. 2 shows a cell of a second exemplary embodiment of a semiconductor component. [Figure 4] FIG. 10 shows a cell of a third exemplary embodiment of a semiconductor component. [Figure 5] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor component. DETAILED DESCRIPTION OF THE INVENTION

[0016] FIG. 1 shows a prior art metal-insulator-semiconductor field-effect transistor (MISFET) cell 100. The MISFET 100 comprises a highly n-doped semiconductor substrate 101, for example made of SiC. A weakly n-doped epitaxial layer 102 is arranged on the semiconductor substrate 101. A moderately p-doped body region 103 is arranged on the epitaxial layer 102. A planar, very highly n-doped source region 104 is arranged on the body region 103. From the top surface of the source region 104, an implanted, trough-shaped p-doped region 115 and a multipleThe second trenches 106 extend into the epitaxial layer 102. The second trenches 106 partially extend into the implanted trough regions 115. In other words, the second trenches 106 overlap the implanted trough regions 115. The implanted trough regions 115 have a greater depth than the second trenches 106, i.e., the implanted trough regions 115 extend deeper into the epitaxial layer 102. The implanted trough regions 115 contain highly p-doped polysilicon, which is produced by high-energy implantation using, for example, aluminum. One trench wall of each second trench 106 contacts the body region 103 and the source region 104. The trench surfaces of the second trenches 106 are covered with a thin oxide layer 108 made of silicon dioxide. The second trenches 106 are filled with highly n-doped polysilicon, known as gate poly. An insulating layer 110 is disposed in some areas on the wafer surface, i.e., above the source regions 104 and implanted trough-shaped regions 115. A first metal layer 111 is disposed on the insulating layer 110 and on the wafer surface. The first metal layer 111 forms an ohmic contact with the source regions 104 and implanted trough-shaped regions 115, which is the source contact. A second metal layer 112 is disposed below the semiconductor substrate 101. The second metal layer 112 functions as the drain contact. The gate poly is electrically connected to a metal terminal, the so-called gate pad, which is not shown in FIG. 1. This is usually done via one or more highly doped polysilicon conductor paths, the so-called gate runners.

[0017] 2 shows a cell 200 of a first exemplary embodiment of a semiconductor component, the semiconductor component 200 having a semiconductor substrate 201. The semiconductor substrate 201 has a first surface and a second surface, where the first surface faces the second surface. An epitaxial layer 202 is disposed on the first surface of the semiconductor substrate 201. A body region 203 is disposed on a portion of the epitaxial layer 202. A source region 204 is disposed on the body region 203. From the top surface of the source region 204, multipleThe first groove 205 and multiple The second trench 206 extends into the epitaxial layer 202. This second trench 206 extends into the first trench 205 in some areas. In other words, the second trench 206 partially overlaps the first trench 205. The first trench 205 has a greater depth than the second trench 206, i.e., it extends deeper into the epitaxial layer 202. One trench wall of each second trench 206 contacts the body region 203 and the source region 204. The trench surface of the second trench 206 has a first insulating layer 208, the so-called gate dielectric, which is typically an oxide layer. The first insulating layer 208 may have a thickness of, for example, 50 nm. This means that the thickness of the first insulating layer 208 is constant, and therefore the filling of the second trench 206 is symmetrical. Preferably, the gate dielectric has a higher dielectric constant than silicon dioxide. This is due to the relative dielectric constant ε r This means that the dielectric constant (D) is greater than 3.9. The first insulating layer 208 may be made of, for example, Al2O3, HfO3, or TiO2. While the breakdown field strength of HfO3 and TiO2 is lower than that of SiO2, the electric field strength in the gate dielectric is lower than that of SiO2 due to their higher dielectric constants. Therefore, the insulating layer 208 may be thinner than that of SiO2. Alternatively, the first insulating layer 208 may be made of a combination of SiO2 and a material with a higher dielectric constant, resulting in a stack consisting of, for example, a thin SiO2 layer and a thicker Al2O3 layer. A second insulating layer 210 is disposed in some areas on the wafer surface, i.e., above the source region 204 and first trench 205. A first metal layer 211 is disposed on the second insulating layer 210 and on the wafer surface. The first metal layer 211 forms an ohmic contact with the source region 204 and first trench 205, which is the source contact. A second metal layer 212 is disposed on a second surface of the semiconductor substrate 201, i.e., underneath the semiconductor substrate 201. The second metal layer 212 functions as a drain contact.

[0018] The semiconductor substrate 201 comprises, for example, SiC. The epitaxial layer 202 is weakly n-doped SiC. The trench walls 213 of the first trench 205 comprise very highly doped 4H-SiC. The first trench 205 is filled with highly p-doped polysilicon. A heterojunction is thus formed between the 4H-SiC and the p-doped polysilicon, with the first trench 205 having a depth of 0.5 μm to 10 μm. The first trenches 205 are spaced apart from each other by 0.2 μm to 10 μm, which improves the shielding effect against electric fields and increases short-circuit strength. The second trench 206 is filled with highly n-doped polysilicon, so-called gate poly. The body region 203 comprises p-doped SiC, and the source region 204 comprises It has highly n-type doped SiC.

[0019] FIG. 3 shows a cell 300 of a second semiconductor component. The structure of the second semiconductor component 300 substantially corresponds to the structure of the first semiconductor component 200 according to FIG. 2, except that the internal structure of the filling of the second groove 306 of the second semiconductor component 300 differs from the internal structure of the filling of the second groove 206 of the first semiconductor component 200. The same digits after the reference numerals in FIG. 3 indicate the same elements as in FIG. 2. The groove surface of the second groove 306 of the second semiconductor component 300 has a first insulating layer 308, where the first insulating layer 308 on the sidewalls and at the groove bottom of the second groove 306 have different thicknesses. In this regard, the area of ​​the first insulating layer 308 directly adjacent to the first groove 305 is thicker than the side facing this area. Additionally or alternatively, the first insulating layer 308 in the area of ​​the groove bottom is thicker than that on the sidewalls of the second groove 306. The second trench 306 is filled with highly n-doped polysilicon. In other words, the second trench 306 is filled asymmetrically with respect to the perpendicular bisector of the second trench 306. This reduces the gate-drain capacitance. In addition, the electric field strength in the thicker areas of the first insulating layer 308 is smaller than in the case of a uniform layer thickness.

[0020] FIG. 4 shows a cell 400 of a third exemplary embodiment of a semiconductor component having a Schottky contact 414. The third semiconductor component 400 includes a semiconductor substrate 401 made of, for example, SiC. The third semiconductor component 400 is, for example, a MOSFET. Compared to silicon-based MOSFETs, silicon carbide-based MOSFETs are disadvantageous in the forward operation of the inverse or body diode. For one thing, the forward voltage is approximately three times larger due to the larger bandgap. For another thing, SiC can experience a drop in current during bipolar structure operation. This can be attributed to the recombination of electrons and holes, which can stimulate the formation of stacking faults from dislocations. Therefore, the third semiconductor component 400 monolithically incorporates a Schottky diode with a low and stable forward voltage. The Schottky diode occurs at the junction between the Schottky contact 414 and the epitaxial layer 402. The Schottky diode is connected in parallel with a body diode, which is formed at the junction of the body region 403 and the epitaxial layer 402. The structure of the third semiconductor component 400 is similar to that of the first semiconductor component 200 according to FIG. 2. The same digits after the reference numerals according to FIG. 4 indicate the same elements as in FIG. 2. The third semiconductor component 400 includes an epitaxial layer 402, on which a body region 403 is arranged in a certain region. A source region 404 is arranged on the body region 403. A metal region 414 is arranged directly above the epitaxial layer 402. This means that the metal region 414 is arranged in a portion of the epitaxial layer 402 where the body region 403 is not present. 2, in some areas, the body region, source region, second trench, first insulating layer, gate poly, and second insulating layer are replaced with metal areas 414. Metal areas 414 include, for example, nickel, titanium, or molybdenum. Due to the location of the Schottky contact between the first trenches 405, the electric field during blocking operation is directed away from the Schottky contact.This is because the space charge zones extending from the first trench 405 into the epitaxial layer 402 touch each other, thus shielding the electric field from the Schottky contact. This avoids the barrier lowering effect at the Schottky contact, resulting in low leakage current. In other words, the shielding structure of the trench region, i.e., the first trench 405, reduces leakage current.

[0021] The semiconductor components 200, 300, and 400 are preferably MOSFETs or MISFETs. The semiconductor components 200, 300, and 400 can be used in inverters for electric or hybrid vehicles. The semiconductor components 200, 300, and 400 can also be used in renewable energy generation, for example in inverters for photovoltaic or wind power plants. Furthermore, applications in traction drives and high voltage rectifiers are possible.

[0022] FIG. 5 illustrates a method 500 for manufacturing a semiconductor component. The method 500 begins in step 501 with the application of an epitaxial layer on a semiconductor substrate. The epitaxial layer has the same material as the semiconductor substrate, but with a different dopant concentration. The epitaxial layer is weakly n-doped. In subsequent step 502, a body region is created in a region on the epitaxial layer. This is achieved by lithography and ion implantation. The body region is p-doped. In subsequent step 503, a source region is created on the body region. The source region is heavily n-doped. In subsequent step 504, the dopants are activated by a thermal treatment. In subsequent step 505, a first trench is created, extending from the surface of the source region into the epitaxial layer. In this regard, the first trench is created by a hard mask and reactive etching. Optionally, in subsequent step 506, the trench bottom can be rounded. In a subsequent step 507, aluminum or boron is implanted into the trench surface of the first trench. In a subsequent step 508, the first trench is filled with highly doped polysilicon (p-type or n-type doping). Alternatively, the first trench can be filled with p-type or n-type doped 3C-SiC. In a subsequent step 509, an annealing step is performed. In a subsequent step 510, a second trench is created, extending from the surface of the source region into the epitaxial layer and extending into the first trench in some areas. In an optional step 511, the trench bottom of the second trench is rounded. In a subsequent step 512, a first insulating layer is created on the trench surface of the second trench. In a subsequent step 513, the first insulating layer is structured. In this regard, the first insulating layer can have a constant thickness, or the sidewalls and the trench bottom can have different thicknesses. In a subsequent step 514, the second trench is filled with doped polysilicon. In a subsequent step 515, a second insulating layer is applied over the source region. In a subsequent step 516, ohmic contacts are created, and in a subsequent step 517, backside metallization is created.

Claims

1. A semiconductor component (200, 300, 400) including a semiconductor substrate (201, 301, 401), the semiconductor substrate (201, 301, 401) having a first surface, an epitaxial layer (202, 302, 402) disposed on the first surface, and a body region (203, 303, 403) disposed on a portion of the epitaxial layer (202, 302, 402). and a source region (204, 304, 404) is disposed on the body region (203, 303, 403), and a plurality of first trenches (205, 305, 405) and a plurality of second trenches (206, 306, 406) extend from the source region (204, 304, 404) into the epitaxial layer (202, 302, 402), and the first trenches (205, a semiconductor component (200, 300, 400) in which each of the first grooves (205, 305, 405) has a depth greater than that of the second grooves (206, 306, 406), and each of the second grooves (206, 306, 406) extends into one of the first grooves (205, 305, 405) in a partial area, wherein a layer having a first doping is disposed on the groove surface of each of the first grooves (205, 305, 405), the first grooves (205, 305, 405) are filled with a first material (207, 307, 407), and the first material (207, 307, 407) has a second doping, the first doping having a value higher than the second doping, and a heterojunction is formed between the layer having the first doping and the first material having the second doping; a first insulating layer (208, 308, 408) having a dielectric constant higher than that of silicon dioxide is disposed on a groove surface of the second groove (206, 306, 406), and the second groove (206, 306, 406) is filled with a second material (209, 309, 409); The first insulating layer (208, 308, 408) has a constant thickness. A semiconductor component (200, 300, 400) characterized by:

2. 2. The semiconductor component (200, 300, 400) of claim 1, further comprising a metal (414) disposed in a portion of the epitaxial layer (202, 302, 402).

3. 2. The semiconductor component (200, 300, 400) of claim 1, wherein the first insulating layer (208, 308, 408) on the sidewalls of the groove surface of the second groove (206, 307, 407) has different thicknesses.

4. 4. The semiconductor component (200, 300, 400) according to any one of claims 1 to 3, characterized in that the semiconductor substrate (201, 301, 401) comprises silicon carbide.

5. 5. The semiconductor component (200, 300, 400) according to any one of claims 1 to 4, characterized in that the semiconductor component (200, 300, 400) is a MISFET.

6. 6. The semiconductor component (200, 300, 400) according to any one of claims 1 to 5, characterized in that the semiconductor substrate (201, 301, 401) comprises gallium nitride.

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