Semiconductor device manufacturing method

Abstract

To provide a semiconductor device capable of preventing occurrence of a crack in a silicon oxide film between sections of pieces of adjoining top wiring.SOLUTION: A semiconductor device includes: a semiconductor substrate having a first principal surface and a second principal surface being opposite to the first principal surface; a plurality of interlayer insulation films which is laminated and arranged on the first principal surface in a direction from the second principal surface to the first principal surface; top wiring arranged on an inter-top-layer insulation film, among the a plurality of interlayer insulation films, being an interlayer insulation film most apart from the first principal surface in a thickness direction; and a passivation film which is arranged on the inter-top-layer insulation film so as to cover the top wiring. The top wiring extends in a first direction in a plan view, and includes a first wiring section and a second wiring section being adjacent to each other in a second direction orthogonal to the first direction. A first distance being a distance in a thickness direction from an upper surface of the top wiring and the inter-top-layer insulation film is 2.7 μm or more.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] For example, Japanese Patent Laid-Open Publication No. 2018-186285 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 includes a semiconductor substrate, multiple interlayer insulating films, top wiring, and a passivation film.

[0003] The semiconductor substrate has a first main surface and a second main surface. The second main surface is the surface opposite to the first main surface. The direction from the second main surface toward the first main surface is defined as the thickness direction. A plurality of interlayer insulating films are stacked on the first main surface in the thickness direction. The interlayer insulating film farthest from the first main surface in the thickness direction among the plurality of interlayer insulating films is defined as the top interlayer insulating film. The top wiring is disposed on the top interlayer insulating film. The top wiring is formed of aluminum or an aluminum alloy. The passivation film includes a silicon oxide film and a silicon nitride film. The silicon oxide film is disposed on the top interlayer insulating film so as to cover the top wiring. The silicon nitride film is disposed on the silicon oxide film. The silicon oxide film is a TEOS (TetraEthOxySilane) film formed using a plasma CVD (Chemical Vapor Deposition) method. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-186285 Summary of the Invention [Problem to be solved by the invention]

[0005] When the gap between adjacent top wiring portions is small compared to the thickness of the top wiring, attempting to fill the gap between the adjacent top wiring portions with a silicon oxide film using the HDP-CVD (High Density Plasma Chemical Vapor Deposition) method increases the wafer temperature due to the longer bias application time during film formation. As the wafer temperature increases, cracks may occur in the silicon oxide film between the adjacent top wiring portions due to the difference in thermal expansion coefficient between the top wiring and the silicon oxide film.

[0006] The present disclosure provides a semiconductor device and a method for manufacturing the semiconductor device that can suppress the occurrence of cracks in a silicon oxide film between portions of adjacent top wirings. [Means for solving the problem]

[0007] The semiconductor device according to the embodiment includes a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; a plurality of interlayer insulating films stacked on the first main surface in a thickness direction from the second main surface toward the first main surface; a top interconnect disposed on a top interlayer insulating film, which is the interlayer insulating film among the plurality of interlayer insulating films that is farthest from the first main surface in the thickness direction; and a passivation film disposed on the top interlayer insulating film so as to cover the top interconnect. The top interconnect extends along a first direction in a plan view and has a first interconnect portion and a second interconnect portion adjacent to each other in a second direction perpendicular to the first direction. A first distance, which is the distance between an upper surface of the top interconnect and the top interlayer insulating film in the thickness direction, is 2.7 μm or more. The top interconnect has a portion where the value obtained by dividing the first distance by a second distance, which is the distance between the first interconnect portion and the second interconnect portion in the second direction, is 1.35 or more. The passivation film includes a silicon oxide film and a silicon nitride film or a silicon oxynitride film disposed on the silicon oxide film. The silicon oxide film has a first layer and a second layer disposed on the first layer. The distance between the top surface of a portion of the first layer between the first wiring portion and the second wiring portion in the thickness direction and the top interlayer insulating film is 0.42 times or less the first distance. The distance between the top surface of a portion of the second layer between the first wiring portion and the second wiring portion in the thickness direction and the top interlayer insulating film is 0.65 times or more the first distance. The first layer and the second layer are HDP-CVD films.

[0008] A method for manufacturing a semiconductor device according to an embodiment includes the steps of: preparing a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; forming a plurality of interlayer insulating films stacked on the first main surface in a thickness direction from the second main surface toward the first main surface; forming a top wiring disposed on a top interlayer insulating film, which is an interlayer insulating film among the plurality of interlayer insulating films that is farthest from the first main surface in the thickness direction; and forming a passivation film disposed on the top interlayer insulating film so as to cover the top wiring. The top wiring extends along a first direction in a plan view and has a first wiring portion and a second wiring portion adjacent to each other in a second direction perpendicular to the first direction. A first distance, which is the distance between an upper surface of the top wiring and the top interlayer insulating film in the thickness direction, is 2.7 μm or more. The top wiring has a portion where a value obtained by dividing the first distance by a second distance, which is the distance between the first wiring portion and the second wiring portion in the second direction, is 1.35 or more. The passivation film forming step includes a step of forming a silicon oxide film and a step of forming a silicon nitride film or a silicon oxynitride film disposed on the silicon oxide film. The silicon oxide film forming step includes a first step of forming a first layer by HDP-CVD and a second step of forming a second layer disposed on the first layer by HDP-CVD. The first step is completed before the distance between the top surface of a portion of the first layer located between the first wiring portion and the second wiring portion in the thickness direction and the top interlayer insulating film exceeds 0.42 times the first distance. The second step is completed after the distance between the top surface of a portion of the second layer located between the first wiring portion and the second wiring portion in the thickness direction and the top interlayer insulating film becomes 0.65 times the first distance or more. [Effects of the Invention]

[0009] According to the semiconductor device and the method for manufacturing the semiconductor device according to the embodiment, it is possible to prevent cracks from occurring in the silicon oxide film between adjacent portions of the top wiring. [Brief explanation of the drawings]

[0010] [Figure 1]FIG. 2 is a plan view of the semiconductor device DEV1. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 3 is an enlarged view of III in FIG. [Figure 4] 10A to 10C are process diagrams showing a manufacturing method of the semiconductor device DEV1. [Figure 5] FIG. 2 is a cross-sectional view illustrating a first ion implantation step S1. [Figure 6] FIG. 10 is a cross-sectional view illustrating an element isolation film forming step S2. [Figure 7] FIG. 10 is a cross-sectional view illustrating a gate insulating film forming step S3. [Figure 8] In the gate formation step S4, the gate G is formed. [Figure 9] FIG. 10 is a cross-sectional view illustrating a second ion implantation step S5. [Figure 10] FIG. 10 is a cross-sectional view illustrating a sidewall spacer forming step S6. [Figure 11] FIG. 10 is a cross-sectional view illustrating a third ion implantation step S7. [Figure 12] FIG. 10 is a cross-sectional view illustrating a first interlayer insulating film forming step S8. [Figure 13] FIG. 10 is a cross-sectional view illustrating a contact plug forming step S9. [Figure 14] FIG. 10 is a cross-sectional view illustrating a first wiring forming step S10. [Figure 15] FIG. 10 is a cross-sectional view illustrating a second interlayer insulating film forming step S11. [Figure 16] FIG. 10 is a cross-sectional view illustrating a first via plug forming step S12. [Figure 17] FIG. 10 is a cross-sectional view illustrating a second wiring formation step S13. [Figure 18] FIG. 10 is a cross-sectional view illustrating a third interlayer insulating film forming step S14. [Figure 19] FIG. 10 is a cross-sectional view illustrating a second via plug forming step S15. [Figure 20] FIG. 10 is a cross-sectional view illustrating a third wiring formation step S16. [Figure 21A]FIG. 10 is a cross-sectional view illustrating a fourth layer forming step S171a. [Figure 21B] FIG. 10 is a cross-sectional view illustrating a first layer forming step S171b. [Figure 21C] FIG. 10 is a cross-sectional view illustrating a second layer forming step S171c. [Figure 21D] FIG. 10 is a cross-sectional view illustrating a third layer forming step S171d. [Figure 21E] FIG. 10 is a cross-sectional view illustrating a fifth layer forming step S171e. [Figure 22] FIG. 10 is a cross-sectional view illustrating a silicon nitride film forming step S172. [Figure 23] 10 is a simulation result showing the relationship between the stress applied to the silicon oxide film PV1 when the temperature is returned from the film formation temperature to room temperature and the thickness of the silicon oxide film PV1. [Figure 24] FIG. 2 is an enlarged cross-sectional view of the semiconductor device DEV2. [Figure 25] 10A to 10C are process diagrams showing a method for manufacturing the semiconductor device DEV2. [Figure 26] FIG. 2 is an enlarged cross-sectional view of the semiconductor device DEV3. DETAILED DESCRIPTION OF THE INVENTION

[0011] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0012] (First embodiment) A semiconductor device according to a first embodiment will be described below. The semiconductor device according to the embodiment is designated as semiconductor device DEV1.

[0013] <Configuration of semiconductor device DEV1> The configuration of the semiconductor device DEV1 will be described below.

[0014] Fig. 1 is a plan view of the semiconductor device DEV1. Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1. Fig. 3 is an enlarged view taken along line III in Fig. 2. As shown in Figs. 1 to 3, the semiconductor device DEV1 includes a semiconductor substrate SUB, an isolation film ISL, a gate insulating film GI, a gate G, a sidewall spacer SWS, an interlayer insulating film ILD1, a contact plug CP, a wiring WL1, an interlayer insulating film ILD2, a via plug VP1, a wiring WL2, an interlayer insulating film ILD3, a via plug VP2, a wiring WL3, and a passivation film PV.

[0015] The semiconductor substrate SUB has a first main surface MS1 and a second main surface MS2. The first main surface MS1 and the second main surface MS2 form end surfaces in the thickness direction of the semiconductor substrate SUB. The second main surface MS2 is the surface opposite to the first main surface MS1. The direction from the second main surface MS2 toward the first main surface MS1 is defined as the thickness direction. The semiconductor substrate SUB is formed of, for example, single-crystal silicon (Si).

[0016] A well region WR, a source region SR, and a drain region DR are formed in the semiconductor substrate SUB. Dopants are implanted into the source region SR and the drain region DR so that they have a first conductivity type. Dopants are implanted into the well region WR so that they have a second conductivity type. The first conductivity type is, for example, n-type. The second conductivity type is the opposite conductivity type to the first conductivity type. In other words, if the first conductivity type is, for example, n-type, the second conductivity type is p-type.

[0017] The well region WR is formed in the first main surface MS1. The source region SR and the drain region DR are formed in the first main surface MS1 so as to be surrounded by the well region WR. The source region SR and the drain region DR are spaced apart from each other.

[0018] The source region SR has a first portion SR1 and a second portion SR2. The first portion SR1 is closer to the drain region DR than the second portion SR2. The impurity concentration in the second portion SR2 is higher than the impurity concentration in the first portion SR1. That is, the source region SR has an LDD (Lightly Doped Diffusion) structure.

[0019] The drain region DR has a first portion DR1 and a second portion DR2. The first portion DR1 is closer to the source region SR than the second portion DR2. The impurity concentration in the second portion DR2 is higher than the impurity concentration in the first portion DR1. That is, the drain region DR has an LDD structure.

[0020] A trench TR is formed in the first main surface MS1. The trench TR extends from the first main surface MS1 toward the second main surface MS2. Although not shown, the trench TR is formed to surround the well region WR in plan view. An element isolation film ISL is buried in the trench TR. The element isolation film ISL is made of, for example, silicon oxide (SiO2). This forms STI (Shallow Trench Isolation). Note that in this example, element isolation is performed by STI, but element isolation may also be performed by LOCOS (Local Oxidation Of Silicon).

[0021] The gate insulating film GI is disposed on the first main surface MS1. The gate insulating film GI is formed of, for example, silicon oxide. The gate G is disposed on the gate insulating film GI. More specifically, the gate G faces a portion of the first main surface MS1 between the source region SR and the drain region DR, with the gate insulating film GI interposed therebetween. The gate G is formed of, for example, polycrystalline silicon containing a dopant. The well region WR, the source region SR, the drain region DR, the gate insulating film GI, and the gate G constitute a transistor.

[0022] The sidewall spacers SWS are disposed on the gate insulating film GI. More specifically, the sidewall spacers SWS are disposed on the portion of the gate insulating film GI covering the first portion SR1 and on the portion of the gate insulating film GI covering the first portion DR1. The sidewall spacers SWS are formed in contact with the side surfaces of the gate G. The sidewall spacers SWS are formed of, for example, silicon nitride (SiN).

[0023] The interlayer insulating film ILD1 is disposed on the first main surface MS1 so as to cover the gate insulating film GI, the gate G, and the sidewall spacers SWS. The interlayer insulating film ILD1 is made of, for example, silicon oxide.

[0024] A contact hole CH is formed in the interlayer insulating film ILD1. The contact hole CH penetrates the interlayer insulating film ILD1 in the thickness direction. The contact hole CH also penetrates the gate insulating film GI. The source region SR, the drain region DR, and the gate G are exposed from the contact hole CH. Although not shown, the portions of the source region SR, the drain region DR, and the gate G exposed from the contact hole CH may be silicided.

[0025] A contact plug CP is buried in the contact hole CH. The contact plug CP is made of, for example, tungsten (W). The contact plug CP is electrically connected to the source region SR, the drain region DR, and the gate G. Although not shown, a barrier metal made of, for example, titanium (Ti) and titanium nitride (TiN) may be disposed between the inner wall surface of the contact hole CH and the contact plug CP.

[0026] The wiring WL1 is disposed on the interlayer insulating film ILD1. The wiring WL1 is electrically connected to the contact plug CP. The wiring WL1 is formed of, for example, aluminum (Al) or an aluminum alloy. Although not shown, a barrier metal formed of titanium and titanium nitride may be disposed between the interlayer insulating film ILD1 and the wiring WL1. Furthermore, although not shown, an anti-reflection film formed of titanium nitride may be formed on the wiring WL1.

[0027] The interlayer insulating film ILD2 is disposed on the interlayer insulating film ILD1 so as to cover the wiring WL1. The interlayer insulating film ILD2 is formed of, for example, silicon oxide. A via hole VH1 is formed in the interlayer insulating film ILD2. The via hole VH1 penetrates the interlayer insulating film ILD2 in the thickness direction. The wiring WL1 is exposed from the via hole VH1. A via plug VP1 is buried in the via hole VH1.

[0028] The via plug VP1 is electrically connected to the wiring WL1. The via plug VP1 is made of, for example, tungsten. Although not shown, a barrier metal made of titanium and titanium nitride may be disposed between the inner wall surface of the via hole VH1 and the via plug VP1.

[0029] The wiring WL2 is disposed on the interlayer insulating film ILD2. The wiring WL2 is electrically connected to the via plug VP1. The wiring WL2 is formed of, for example, aluminum or an aluminum alloy. Although not shown, a barrier metal formed of titanium and titanium nitride may be disposed between the interlayer insulating film ILD2 and the wiring WL2. Furthermore, although not shown, an anti-reflection film formed of titanium nitride may be formed on the wiring WL2.

[0030] The interlayer insulating film ILD3 is disposed on the interlayer insulating film ILD2 so as to cover the wiring WL2. The interlayer insulating film ILD3 is formed of, for example, silicon oxide. A via hole VH2 is formed in the interlayer insulating film ILD3. The via hole VH2 penetrates the interlayer insulating film ILD3 in the thickness direction. The wiring WL2 is exposed from the via hole VH2. A via plug VP2 is buried in the via hole VH2.

[0031] As described above, a plurality of interlayer insulating films (interlayer insulating film ILD1, interlayer insulating film ILD2, and interlayer insulating film ILD3) are stacked in the thickness direction on the first main surface MS1, and the interlayer insulating film ILD3 is the interlayer insulating film farthest from the first main surface MS1. That is, the interlayer insulating film ILD3 is the top interlayer insulating film. In the above, the number of interlayer insulating films stacked on the first main surface MS1 is three, but the number of interlayer insulating films stacked on the first main surface MS1 may be two, four, or more.

[0032] The via plug VP2 is electrically connected to the wiring WL2. The via plug VP2 is made of, for example, tungsten. Although not shown, a barrier metal made of titanium and titanium nitride is disposed between the inner wall surface of the via hole VH2 and the via plug VP2.

[0033] The wiring WL3 is disposed on the interlayer insulating film ILD3. That is, the wiring WL3 is a top wiring. The wiring WL3 is electrically connected to the via plug VP2. The wiring WL3 is made of, for example, aluminum or an aluminum alloy. A barrier metal BM made of titanium and titanium nitride is disposed between the interlayer insulating film ILD3 and the wiring WL3.

[0034] The wiring WL3 has a first wiring portion WL3a, a second wiring portion WL3b, and a bonding pad portion WL3c. The first wiring portion WL3a and the second wiring portion WL3b extend along a first direction D1 in a plan view. The first wiring portion WL3a and the second wiring portion WL3b are adjacent to each other in a second direction D2. The second direction D2 is a direction perpendicular to the first direction D1.

[0035] The distance between the top surface of the wiring WL3 and the top surface of the interlayer insulating film ILD3 in the thickness direction is defined as a first distance DIS1. The distance between the first wiring portion WL3a and the second wiring portion WL3b in the second direction D2 is defined as a second distance DIS2. The first distance DIS1 is 2.7 μm or more. The wiring WL3 has a portion where the value obtained by dividing the first distance DIS1 by the second distance DIS2 is 1.35 or more.

[0036] The passivation film PV is disposed on the interlayer insulating film ILD3 so as to cover the wiring WL3. The passivation film PV has a silicon oxide film PV1 and a silicon nitride film PV2.

[0037] The silicon oxide film PV1 is made of silicon oxide. The silicon oxide film PV1 has a first layer PV1a, a second layer PV1b, and a third layer PV1c. The silicon oxide film PV1 may further have a fourth layer PV1d and a fifth layer PV1e.

[0038] The first layer PV1a, the second layer PV1b, and the third layer PV1c are HDP-CVD films. That is, the first layer PV1a, the second layer PV1b, and the third layer PV1c are silicon oxide films formed by the HDP-CVD method. The fourth layer PV1d and the fifth layer PV1e are not HDP-CVD films. Because the first layer PV1a, the second layer PV1b, and the third layer PV1c are HDP-CVD films, the top surfaces of the first layer PV1a, the second layer PV1b, and the third layer PV1c on the wiring WL3 are trapezoidal or triangular.

[0039] The fourth layer PV1d is disposed on the interlayer insulating film ILD3 so as to cover the wiring WL3. The first layer PV1a is disposed on the fourth layer PV1d. The second layer PV1b is disposed on the first layer PV1a. The third layer PV1c is disposed on the second layer PV1b. The fifth layer PV1e is disposed on the third layer PV1c.

[0040] The distance between the upper surface of the interlayer insulating film ILD3 and the upper surface of the portion of the first layer PV1a between the first wiring portion WL3a and the second wiring portion WL3b in the thickness direction is defined as a third distance DIS3. Note that the third distance DIS3 is measured at a position where the distance between the upper surface of the portion of the first layer PV1a between the first wiring portion WL3a and the second wiring portion WL3b in the thickness direction and the upper surface of the interlayer insulating film ILD3 is minimum.

[0041] The distance between the upper surface of the interlayer insulating film ILD3 and the upper surface of the portion of the second layer PV1b between the first wiring portion WL3a and the second wiring portion WL3b in the thickness direction is defined as a fourth distance DIS4. Note that the fourth distance DIS4 is measured at a position where the distance between the upper surface of the portion of the second layer PV1b between the first wiring portion WL3a and the second wiring portion WL3b in the thickness direction and the upper surface of the interlayer insulating film ILD3 is minimum.

[0042] The distance between the upper surface of the interlayer insulating film ILD3 and the upper surface of the portion of the third layer PV1c between the first wiring portion WL3a and the second wiring portion WL3b in the thickness direction is defined as a fifth distance DIS5. Note that the fifth distance DIS5 is measured at a position where the distance between the upper surface of the portion of the third layer PV1c between the first wiring portion WL3a and the second wiring portion WL3b in the thickness direction and the upper surface of the interlayer insulating film ILD3 is minimum.

[0043] The third distance DIS3 is 0.42 times or less the first distance DIS1. The fourth distance DIS4 is 0.65 times or more the first distance DIS1. The fifth distance DIS5 is 1.00 times or more the first distance DIS1. From another perspective, the space between the first wiring portion WL3a and the second wiring portion WL3b is completely buried with the HDP-CVD film. The fourth distance DIS4 may be 1.00 times or more the first distance DIS1. In this case, the silicon oxide film PV1 does not need to have the third layer PV1c.

[0044] The interface between the fourth layer PV1d and the first layer PV1a, the interface between the first layer PV1a and the second layer PV1b, the interface between the second layer PV1b and the third layer PV1c, and the interface between the third layer PV1c and the fifth layer PV1e can be identified by relief etching the cross section of the semiconductor device DEV1 with mixed acid OJ (a mixture of HF, NH4F, and CH3COOH) for 5 to 10 seconds.

[0045] The silicon nitride film PV2 is made of silicon nitride. The silicon nitride film PV2 is disposed on the silicon oxide film PV1. More specifically, it is disposed on the fifth layer PV1e. A silicon oxynitride film PV3 may be used instead of the silicon nitride film PV2. The silicon oxynitride film PV3 is made of silicon oxynitride (SiON). The silicon oxynitride film PV3 is disposed on the silicon oxide film PV1.

[0046] An opening OP is formed in the passivation film PV. The opening OP penetrates the passivation film PV in the thickness direction. The bonding pad portion WL3c is exposed from the opening OP.

[0047] <Method of Manufacturing Semiconductor Device DEV1> A method for manufacturing the semiconductor device DEV1 will be described below.

[0048] Fig. 4 is a process diagram showing a method for manufacturing the semiconductor device DEV1. As shown in Fig. 4, the method for manufacturing the semiconductor device DEV1 includes a first ion implantation step S1, an element isolation film formation step S2, a gate insulating film formation step S3, a gate formation step S4, a second ion implantation step S5, a sidewall spacer formation step S6, and a third ion implantation step S7.

[0049] The manufacturing method of the semiconductor device DEV1 further includes a first interlayer insulating film forming step S8, a contact plug forming step S9, a first wiring forming step S10, a second interlayer insulating film forming step S11, a first via plug forming step S12, a second wiring forming step S13, a third interlayer insulating film forming step S14, a second via plug forming step S15, a third wiring forming step S16, a passivation film forming step S17, and an opening forming step S18.

[0050] 5 is a cross-sectional view illustrating the first ion implantation step S1. As shown in FIG. 5, in the first ion implantation step S1, ions are implanted to form a well region WR.

[0051] FIG. 6 is a cross-sectional view illustrating the element isolation film forming step S2. As shown in FIG. 6, in the element isolation film forming step S2, first, a trench TR is formed. The trench TR is formed by dry etching. Second, the trench TR is filled with a constituent material of the element isolation film ISL. The filling of the constituent material of the element isolation film ISL is performed by, for example, CVD (Chemical Vapor Deposition). Third, the constituent material of the element isolation film ISL that protrudes from the trench TR is removed. The constituent material of the element isolation film ISL that protrudes from the trench TR is removed by, for example, CMP (Chemical Mechanical Polishing).

[0052] 7 is a cross-sectional view illustrating the gate insulating film forming step S3. As shown in Fig. 7, in the gate insulating film forming step S3, the gate insulating film GI is formed. The gate insulating film GI is formed by thermally oxidizing the first main surface MS1.

[0053] In FIG. 8, in the gate formation step S4, a gate G is formed. In the gate formation step S4, first, a constituent material of the gate G is formed on the gate insulating film GI. This film formation is performed by, for example, CVD. Second, the formed constituent material of the gate G is patterned. This patterning is performed by photolithography and dry etching.

[0054] 9 is a cross-sectional view illustrating the second ion implantation step S5. As shown in FIG. 9, in the second ion implantation step S5, ion implantation is performed using the element isolation film ISL and the gate G as a mask, thereby forming the first portion SR1 and the first portion DR1.

[0055] 10 is a cross-sectional view illustrating the sidewall spacer formation step S6. As shown in FIG. 10, in the sidewall spacer formation step S6, the sidewall spacers SWS are formed. In the sidewall spacer formation step S6, first, a material for the sidewall spacers SWS is deposited on the gate insulating film GI so as to cover the gate G. Second, the deposited material for the sidewall spacers SWS is etched back.

[0056] 11 is a cross-sectional view illustrating the third ion implantation step S7. In the third ion implantation step S7, as shown in FIG. 11, ion implantation is performed to form the second portion SR2 and the second portion DR2.

[0057] 12 is a cross-sectional view illustrating the first interlayer insulating film forming step S8. As shown in FIG. 12, in the first interlayer insulating film forming step S8, an interlayer insulating film ILD1 is formed. In the first interlayer insulating film forming step S8, first, a constituent material of the interlayer insulating film ILD1 is deposited so as to cover the gate insulating film GI, the sidewall spacers SWS, and the gate G. This deposition is performed by, for example, CVD. Second, the deposited constituent material of ILD1 is planarized by, for example, CMP. As a result, the interlayer insulating film ILD1 is formed. Third, the interlayer insulating film ILD1 and the gate insulating film GI are dry-etched to form contact holes CH in the interlayer insulating film ILD1 and the gate insulating film GI.

[0058] 13 is a cross-sectional view illustrating the contact plug forming step S9. As shown in FIG. 13, in the contact plug forming step S9, a contact plug CP is formed. In the contact plug forming step S9, first, a constituent material of the contact plug CP is filled into the contact hole CH by CVD or the like. Second, the constituent material of the contact plug CP that protrudes from the contact hole CH is removed by, for example, CMP.

[0059] 14 is a cross-sectional view illustrating the first wiring formation step S10. In the first wiring formation step S10, wiring WL1 is formed as shown in FIG. 14. In the first wiring formation step S10, first, a film of the constituent material of the wiring WL1 is formed by sputtering or the like. Second, the formed film of the constituent material of the wiring WL1 is patterned by, for example, photolithography and etching.

[0060] 15 is a cross-sectional view illustrating the second interlayer insulating film forming step S11. As shown in FIG. 15, in the second interlayer insulating film forming step S11, an interlayer insulating film ILD2 is formed. In the first interlayer insulating film forming step S8, first, a constituent material of the interlayer insulating film ILD2 is deposited on the interlayer insulating film ILD1 so as to cover the wiring WL1. This deposition is performed by, for example, CVD. Second, the deposited constituent material of the interlayer insulating film ILD2 is planarized by, for example, CMP. As a result, the interlayer insulating film ILD2 is formed. Third, the interlayer insulating film ILD2 is dry-etched to form a via hole VH1 in the interlayer insulating film ILD2.

[0061] 16 is a cross-sectional view illustrating the first via plug forming step S12. As shown in FIG. 16, in the first via plug forming step S12, a via plug VP1 is formed. In the first via plug forming step S12, first, the constituent material of the via plug VP1 is embedded in the via hole VH1 by, for example, CVD. Second, the constituent material of the via plug VP1 that protrudes from the via hole VH1 is removed by, for example, CMP.

[0062] FIG. 17 is a cross-sectional view illustrating the second wiring forming step S13. In the second wiring forming step S13, a wiring WL2 is formed as shown in FIG. 17. FIG. 18 is a cross-sectional view illustrating the third interlayer insulating film forming step S14. In the third interlayer insulating film forming step S14, an interlayer insulating film ILD3 is formed as shown in FIG. 18. FIG. 19 is a cross-sectional view illustrating the second via plug forming step S15. In the second via plug forming step S15, a via plug VP2 is formed as shown in FIG. 20. FIG. 20 is a cross-sectional view illustrating the third wiring forming step S16. In the third wiring forming step S16, a wiring WL3 is formed as shown in FIG. 20.

[0063] The method for forming the wiring WL2 and the wiring WL3 is the same as the method for forming the wiring WL1. The method for forming the interlayer insulating film ILD3 is the same as the method for forming the interlayer insulating film ILD2. The method for forming the via plug VP2 is the same as the method for forming the via plug VP1.

[0064] The passivation film forming step S17 includes a silicon oxide film forming step S171 and a silicon nitride film forming step S172. The silicon oxide film forming step S171 includes a fourth layer forming step S171a, a first layer forming step S171b, a second layer forming step S171c, a third layer forming step S171d, and a fifth layer forming step S171e.

[0065] 21A is a cross-sectional view illustrating the fourth layer forming step S171a. As shown in FIG. 21A, in the fourth layer forming step S171a, a fourth layer PV1d is formed. The fourth layer PV1d is formed by, for example, a parallel plate PE-CVD (Plasma Enhanced Chemical Vapor Deposition) method.

[0066] 21B is a cross-sectional view illustrating the first layer forming step S171b. As shown in FIG. 21B, in the first layer forming step S171b, a first layer PV1a is formed. The first layer PV1a is formed by the HDP-CVD method. The first layer forming step S171b is terminated before the third distance DIS3 exceeds 0.42 times the first distance DIS1.

[0067] 21C is a cross-sectional view illustrating the second layer forming step S171c. As shown in FIG. 21C, in the second layer forming step S171c, a second layer PV1b is formed. The second layer PV1b is formed by the HDP-CVD method. The second layer forming step S171c is terminated after the fourth distance DIS4 becomes equal to or greater than 0.65 times the first distance DIS1.

[0068] 21D is a cross-sectional view illustrating the third layer forming step S171d. As shown in FIG. 21D, in the third layer forming step S171d, a third layer PV1c is formed. The third layer PV1c is formed by the HDP-CVD method. The third layer forming step S171d is terminated after the fifth distance DIS5 becomes 1.00 times or more the first distance DIS1. Note that if the second layer forming step S171c is performed until the fourth distance DIS4 becomes 1.00 times or more the first distance DIS1, the third layer forming step S171d may be omitted.

[0069] 21E is a cross-sectional view illustrating the fifth layer forming step S171e. As shown in FIG. 21E, in the fifth layer forming step S171e, a fifth layer PV1e is formed. The fifth layer PV1e is formed by, for example, a parallel plate PE-CVD method.

[0070] 22 is a cross-sectional view illustrating the silicon nitride film forming step S172. As shown in FIG. 22, in the silicon nitride film forming step S172, a silicon nitride film PV2 is formed. The silicon nitride film PV2 is formed, for example, by a parallel plate PE-CVD method. Note that when the passivation film PV has a silicon oxynitride film PV3 instead of the silicon nitride film PV2, a silicon oxynitride film forming step S173 is performed instead of the silicon nitride film forming step S172. The silicon oxynitride film PV3 in the silicon oxynitride film forming step S173 is formed, for example, by a parallel plate PE-CVD method.

[0071] In the opening forming step S18, the openings OP are formed. The openings OP are formed by, for example, dry etching. In this way, the semiconductor device DEV1 having the structure shown in FIGS.

[0072] <Effects of semiconductor device DEV1> The effects of the semiconductor device DEV1 will be described below.

[0073] FIG. 23 shows simulation results showing the relationship between the stress applied to the silicon oxide film PV1 when the temperature is returned to room temperature from the film formation temperature and the thickness of the silicon oxide film PV1. The vertical axis in FIG. 23 represents the stress applied to the portion of the silicon oxide film PV1 between the first wiring portion WL3a and the second wiring portion WL3b. The horizontal axis in FIG. 23 represents the value obtained by dividing the first distance DIS1 by the thickness of the portion of the silicon oxide film PV1 between the first wiring portion WL3a and the second wiring portion WL3b. In the simulation shown in FIG. 23, the first distance DIS1 was set to 3 μm and the second distance DIS2 was set to 2 μm. In addition, in the simulation results shown in FIG. 23, the film formation temperature was set to 400°C.

[0074] 23, when the value obtained by dividing the first distance DIS1 by the thickness of the portion of the silicon oxide film PV1 between the first wiring portion WL3a and the second wiring portion WL3b approaches 0.5, the stress applied to the portion of the silicon oxide film PV1 between the first wiring portion WL3a and the second wiring portion WL3b reaches a maximum. When the value obtained by dividing the first distance DIS1 by the thickness of the portion of the silicon oxide film PV1 between the first wiring portion WL3a and the second wiring portion WL3b is further increased, the stress applied to the portion of the silicon oxide film PV1 between the first wiring portion WL3a and the second wiring portion WL3b begins to decrease.

[0075] Table 1 shows the value obtained by dividing the first distance DIS1 by the thickness of the portion of the silicon oxide film PV1 between the first wiring portion WL3a and the second wiring portion WL3b at the end of film formation, and the results of observing whether or not there are cracks in the portion of the silicon oxide film PV1 between the first wiring portion WL3a and the second wiring portion WL3b.

[0076] [Table 1]

[0077] In Samples 1 to 3, the silicon oxide film PV1 was formed through the steps up to the first layer forming step S171b, and no subsequent steps were performed. In Samples 4 and 5, the silicon oxide film PV1 was formed through the steps up to the second layer forming step S171c, and no subsequent steps were performed. Note that in Samples 4 and 5, the first layer forming step S171b was completed before the value obtained by dividing the first distance DIS1 by the third distance DIS3 exceeded 0.42.

[0078] As shown in Table 1, in Sample 1 and Sample 2, no cracks were observed in the portion of the silicon oxide film PV1 between the first wiring portion WL3a and the second wiring portion WL3b. On the other hand, in Sample 3, cracks were observed in the portion of the silicon oxide film PV1 between the first wiring portion WL3a and the second wiring portion WL3b. In Sample 4 and Sample 5, no cracks were observed in the portion of the silicon oxide film PV1 between the first wiring portion WL3a and the second wiring portion WL3b.

[0079] 23 and Table 1, in the manufacturing method of the semiconductor device DEV1, the first layer forming step S171b is completed before the value obtained by dividing the first distance DIS1 by the third distance DIS3 exceeds 0.42, and the second layer forming step S171c is completed after the value obtained by dividing the first distance by the fourth distance DIS4 becomes 0.65 or greater, thereby avoiding the timing at which the first layer forming step S171b and the second layer forming step S171c are completed, which would increase the stress applied to the portion of the silicon oxide film PV1 between the first wiring portion WL3a and the second wiring portion WL3b. As a result, in the semiconductor device DEV1, the occurrence of cracks in the portion of the silicon oxide film PV1 between the first wiring portion WL3a and the second wiring portion WL3b is suppressed.

[0080] In addition, from the viewpoint of suppressing the occurrence of cracks in the portion of the silicon oxide film PV1 between the first wiring portion WL3a and the second wiring portion WL3b, it is considered to perform the first layer formation process S171b until the value obtained by dividing the first distance DIS1 by the third distance DIS3 exceeds 1.00, and not to perform the second layer formation process S171c and the third layer formation process S171d.

[0081] However, in this case, the bias application time in the HDP-CVD method becomes longer, causing the temperature of the wiring WL3 to become excessively high, which may result in hillocks and whiskers on the wiring WL3.In addition, in this case, the bias application time becomes longer in the HDP-CVD method, causing charges to accumulate between the wafer and the electrostatic chuck that holds the wafer, which may result in the wafer sticking to the electrostatic chuck or an increase in particles on the wafer.

[0082] <Modification> In the above example, the first layer forming step S171b is performed in one go, but the first layer forming step S171b may be performed in multiple steps. That is, the first layer PV1a may be formed of multiple layers. However, at the time when the final step of the first layer forming step S171b performed in multiple steps is completed, the value obtained by dividing the first distance DIS1 by the third distance DIS3 does not exceed 0.42.

[0083] (Second embodiment) A semiconductor device according to a second embodiment will be described. The semiconductor device according to the second embodiment will be referred to as semiconductor device DEV2. Here, differences from semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0084] <Configuration of semiconductor device DEV2> The configuration of the semiconductor device DEV2 will be described below.

[0085] The semiconductor device DEV2 includes a semiconductor substrate SUB, an isolation film ISL, a gate insulating film GI, a gate G, a sidewall spacer SWS, an interlayer insulating film ILD1, a contact plug CP, a wiring WL1, an interlayer insulating film ILD2, a via plug VP1, a wiring WL2, an interlayer insulating film ILD3, a via plug VP2, a wiring WL3, and a passivation film PV. In this respect, the configuration of the semiconductor device DEV2 is common to the configuration of the semiconductor device DEV1.

[0086] Fig. 24 is an enlarged cross-sectional view of the semiconductor device DEV2. Fig. 24 shows an enlarged cross-section of the semiconductor device DEV2 at a position corresponding to III in Fig. 3. As shown in Fig. 24, in the semiconductor device DEV2, the silicon oxide film PV1 does not have a fourth layer PV1d and a fifth layer PV1e. In this respect, the configuration of the semiconductor device DEV2 differs from the configuration of the semiconductor device DEV1.

[0087] <Method of manufacturing semiconductor device DEV2> A method for manufacturing the semiconductor device DEV2 will be described below.

[0088] Fig. 25 is a process diagram showing a method for manufacturing the semiconductor device DEV2. As shown in Fig. 25, the method for manufacturing the semiconductor device DEV2 includes a first ion implantation step S1, an element isolation film formation step S2, a gate insulating film formation step S3, a gate formation step S4, a second ion implantation step S5, a sidewall spacer formation step S6, and a third ion implantation step S7.

[0089] The method for manufacturing the semiconductor device DEV2 further includes a first interlayer insulating film forming step S8, a contact plug forming step S9, a first wiring forming step S10, a second interlayer insulating film forming step S11, a first via plug forming step S12, a second wiring forming step S13, a third interlayer insulating film forming step S14, a second via plug forming step S15, a third wiring forming step S16, a passivation film forming step S17, and an opening forming step S 18. In these respects, the method for manufacturing the semiconductor device DEV2 is common to the method for manufacturing the semiconductor device DEV1.

[0090] The method for manufacturing the semiconductor device DEV2 differs from the method for manufacturing the semiconductor device DEV1 in that the silicon oxide film forming step S171 does not include the fourth layer forming step S171a and the fifth layer forming step S171e. The method for manufacturing the semiconductor device DEV2 also differs from the method for manufacturing the semiconductor device DEV1 in terms of the details of the first layer forming step S171b and the third layer forming step S171d.

[0091] In the manufacturing method of the semiconductor device DEV2, the first layer forming step S171b is divided into a first stage and a second stage. The bias applied in the first stage of the first layer forming step S171b for the HDP-CVD method is weaker than the bias applied in the second stage of the first layer forming step S171b for the HDP-CVD method. The fact that the bias applied in the first stage of the first layer forming step S171b for the HDP-CVD method is weaker than the bias applied in the second stage of the first layer forming step S171b also includes the case where no bias is applied in the HDP-CVD method for the first stage of the first layer forming step S171b.

[0092] In the manufacturing method of the semiconductor device DEV2, the third layer forming step S171d is divided into a first stage and a second stage. The bias applied in the second stage of the third layer forming step S171d is weaker than the bias applied in the HDP-CVD method in the first stage of the third layer forming step S171d. While the bias applied in the first stage of the third layer forming step S171d is weaker than the bias applied in the HDP-CVD method in the second stage of the third layer forming step S171d, the bias applied in the HDP-CVD method may be omitted.

[0093] <Effects of semiconductor device DEV2> The effects of the semiconductor device DEV2 will be described below.

[0094] In the manufacturing method of the semiconductor device DEV1, in order to prevent the corners of the wiring WL3 from being sputtered in the first layer forming step S171b, a fourth layer forming step S171a is performed using a parallel plate PE-CVD method before the first layer forming step S171b. In the manufacturing method of the semiconductor device DEV2, the bias applied in the HDP-CVD method in the first stage of the first layer forming step S171b is weakened, so that the corners of the wiring WL3 are less likely to be sputtered in the first layer forming step S171b, and the fourth layer forming step S171a can be omitted.

[0095] In the manufacturing method of the semiconductor device DEV1, a fifth layer forming step S171e is performed using a parallel plate PE-CVD method after the third layer forming step S171d in order to reduce the shape of the upper surface of the third layer PV1c after the third layer forming step S171d. In the manufacturing method of the semiconductor device DEV2, the bias application in the HDP-CVD method in the second stage of the third layer forming step S171d is weakened, thereby reducing the shape of the upper surface of the third layer PV1c after the third layer forming step S171d, so it is possible to omit the fifth layer forming step S171e.

[0096] In this way, the semiconductor device DEV2 can omit some steps in the manufacturing process, thereby reducing manufacturing costs.

[0097] (Third embodiment) A semiconductor device according to a third embodiment will be described. The semiconductor device according to the third embodiment will be referred to as semiconductor device DEV3. Here, differences from the semiconductor device DEV2 will be mainly described, and overlapping descriptions will not be repeated.

[0098] <Configuration of semiconductor device DEV3> The configuration of the semiconductor device DEV3 will be described below.

[0099] The semiconductor device DEV3 includes a semiconductor substrate SUB, an isolation film ISL, a gate insulating film GI, a gate G, a sidewall spacer SWS, an interlayer insulating film ILD1, a contact plug CP, a wiring WL1, an interlayer insulating film ILD2, a via plug VP1, a wiring WL2, an interlayer insulating film ILD3, a via plug VP2, a wiring WL3, and a passivation film PV. In this respect, the configuration of the semiconductor device DEV3 is common to the configuration of the semiconductor device DEV2.

[0100] Fig. 26 is an enlarged cross-sectional view of the semiconductor device DEV3. Fig. 26 shows an enlarged cross-section at a position corresponding to III in Fig. 3. As shown in Fig. 26, in the semiconductor device DEV3, the first layer PV1a has layers PV1aa and PV1ab, the second layer PV1b has layers PV1ba and PV1bb, and the third layer PV1c has layers PV1ca and PV1cb.

[0101] The layer PV1aa is formed of silicon oxide that is richer in silicon than the layer PV1ab. The layer PV1ab is disposed on the layer PV1aa. That is, the first layer PV1a is partially formed of silicon oxide that is richer in silicon. The entire first layer PV1a may be formed of silicon oxide that is richer in silicon. The layer PV1ba is formed of silicon oxide that is richer in silicon than the layer PV1bb. The layer PV1bb is disposed on the layer PV1ba. That is, the second layer PV1b is partially formed of silicon oxide that is richer in silicon. The entire second layer PV1b may be formed of silicon oxide that is richer in silicon.

[0102] The layer PV1ca is formed of silicon oxide that is richer in silicon than the layer PV1cb. The layer PV1cb is disposed on the layer PV1ca. That is, the third layer PV1c is partially formed of silicon-rich silicon oxide. The entire third layer PV1c may be formed of silicon-rich silicon oxide. In these respects, the configuration of the semiconductor device DEV3 differs from the configuration of the semiconductor device DEV2.

[0103] In the above, an example has been shown in which the first layer PV1a, the second layer PV1b, and the third layer PV1c are all constructed by stacking a layer formed from silicon-rich silicon oxide and a layer formed from silicon oxide that is not silicon-rich, but it is sufficient if any of the first layer PV1a, the second layer PV1b, and the third layer PV1c are constructed by stacking a layer formed from silicon-rich silicon oxide and a layer formed from silicon oxide that is not silicon-rich.

[0104] While the refractive index of non-silicon-rich silicon oxide for light with a wavelength of 633 nm is approximately 1.45 to 1.46, the refractive index of silicon-rich silicon oxide for light with a wavelength of 633 nm is 1.5 or higher. Therefore, whether or not a silicon-rich silicon oxide layer is included in the first layer PV1a (second layer PV1b, third layer PV1c) can be determined, for example, by measuring the refractive index. In addition, whether or not a silicon-rich silicon oxide layer is included in the first layer PV1a (second layer PV1b, third layer PV1c) can also be determined by Fourier transform infrared spectroscopy (FTIR).

[0105] <Method of manufacturing semiconductor device DEV3> A method for manufacturing the semiconductor device DEV3 will be described below.

[0106] The manufacturing method of the semiconductor device DEV3, like the manufacturing method of the semiconductor device DEV2, includes a first ion implantation step S1, an element isolation film formation step S2, a gate insulating film formation step S3, a gate formation step S4, a second ion implantation step S5, a sidewall spacer formation step S6, and a third ion implantation step S7.

[0107] Furthermore, the manufacturing method for the semiconductor device DEV3, like the manufacturing method for the semiconductor device DEV2, further includes a first interlayer insulating film forming step S8, a contact plug forming step S9, a first wiring forming step S10, a second interlayer insulating film forming step S11, a first via plug forming step S12, a second wiring forming step S13, a third interlayer insulating film forming step S14, a second via plug forming step S15, a third wiring forming step S16, a passivation film forming step S17, and an opening forming step S18.

[0108] Furthermore, in the method for manufacturing the semiconductor device DEV3, the silicon oxide film forming step S171 includes a first layer forming step S171b, a second layer forming step S171c, and a third layer forming step S171d.

[0109] In the manufacturing method of the semiconductor device DEV3, the first layer forming step S171b, the second layer forming step S171c, and the third layer forming step S171d are divided into a first stage and a second stage.

[0110] The bias applied for the HDP-CVD method in the first stage of the first layer formation step S171b is weaker than the bias applied for the HDP-CVD method in the second stage of the first layer formation step S171b. The bias applied for the HDP-CVD method in the first stage of the first layer formation step S171b is weaker than the bias applied for the HDP-CVD method in the second stage of the first layer formation step S171b. This also includes the case where no bias is applied for the HDP-CVD method in the first stage of the first layer formation step S171b. As a result, a layer PV1aa is formed in the first stage of the first layer formation step S171b, and a layer PV1ab is formed in the second stage of the first layer formation step S171b.

[0111] By changing the gas ratio of the HDP-CVD method in the first stage of the first layer formation process S171b (more specifically, the flow rate ratio of oxygen (O2) gas and monosilane (SiH4) gas) from the gas ratio of the HDP-CVD method in the second stage of the first layer formation process S171b, a layer PV1aa is formed in the first stage of the first layer formation process S171b, and a layer PV1ab is formed in the second stage of the first layer formation process S171b.

[0112] Regarding the second layer formation process S171c (third layer formation process S171d), a stacked structure of layers PV1ba and PV1bb (layers PV1ca and PV1cb) can be similarly formed by applying a bias or changing the gas ratio of the HDP-CVD method in the first and second stages.

[0113] <Effects of semiconductor device DEV3> The effects of the semiconductor device DEV3 will be described below.

[0114] The thermal expansion coefficients of non-silicon-rich silicon oxide, silicon, and aluminum are 0.55 ppm / °C, 2.6 ppm / °C, and 24 ppm / °C, respectively. Therefore, the thermal expansion coefficient of silicon-rich silicon oxide is closer to that of aluminum than that of non-silicon-rich silicon oxide. As a result, in the semiconductor device DEV3, stress applied to the portion of the silicon oxide film PV1 between the first wiring portion WL3a and the second wiring portion WL3b due to the difference between the thermal expansion coefficient of the silicon oxide film PV1 and the thermal expansion coefficient of the wiring WL3 is alleviated, making cracks less likely to occur in that portion.

[0115] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0116] BM barrier metal, CH contact hole, CP contact plug, D1 first direction, D2 second direction, DEV1 semiconductor device, DEV2, DEV3 semiconductor device, DIS1 first distance, DIS2 second distance, DIS3 third distance, DIS4 fourth distance, DIS5 fifth distance, DR drain region, DR1 first portion, DR2 second portion, G gate, GI gate insulating film, ILD1, ILD2, ILD3 interlayer insulating film, ISL element isolation film, MS1 first main surface, MS2 second main surface, OP opening, PV passivation film, PV1 silicon oxide film, PV1a first layer, PV1aa, PV1ab layers, PV1b second layer, PV1ba, PV1bb layers, PV1c third layer, PV1ca layer, PV1cb layer, PV1d fourth layer, PV1e fifth layer, PV2 silicon nitride film, PV3 Silicon oxynitride film, S1 first ion implantation step, S2 element isolation film formation step, S3 gate insulating film formation step, S4 gate formation step, S5 second ion implantation step, S6 sidewall spacer formation step, S7 third ion implantation step, S8 first interlayer insulating film formation step, S9 contact plug formation step, S10 first wiring formation step, S11 second interlayer insulating film formation step, S12 first via plug formation step, S13 second wiring formation step, S14 third interlayer insulating film formation step, S15 second via plug formation step, S16 third wiring formation step, S17 passivation film formation step, S18 opening formation step, S171 silicon oxide film formation step, S171a fourth layer formation step, S171b first layer formation step, S171c second layer formation step, S171d third layer formation step, S171e fifth layer formation step, S172 Silicon nitride film formation process, S173 silicon oxynitride film formation process, SR source region, SR1 first portion, SR2 second portion, SUB semiconductor substrate, SWS sidewall spacer, TR trench, VH1 via hole, VH2 via hole, VP1, VP2 via plug, WL1, WL2, WL3 wiring, WL3a first wiring portion, WL3b second wiring portion, WL3c bonding pad portion, WR well region.

Claims

1. providing a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; forming a plurality of interlayer insulating films on the first main surface in a thickness direction from the second main surface toward the first main surface; forming a top wiring on a top interlayer insulating film that is an interlayer insulating film farthest from the first main surface in the thickness direction among the plurality of interlayer insulating films; forming a passivation film on the top interlayer insulating film so as to cover the top wiring; the top wiring extends along a first direction in a plan view and includes a first wiring portion and a second wiring portion adjacent to each other in a second direction perpendicular to the first direction; a first distance between an upper surface of the top wiring and the top interlayer insulating film in the thickness direction is 2.7 μm or more; the top wiring has a portion in which a value obtained by dividing the first distance by a second distance, which is a distance between the first wiring portion and the second wiring portion in the second direction, is 1.35 or more; the step of forming the passivation film includes a step of forming a silicon oxide film, and a step of forming a silicon nitride film or a silicon oxynitride film on the silicon oxide film, the step of forming the silicon oxide film includes a first step of forming a first layer by a PE-CVD method, a second step of forming a second layer on the first layer by an HDP-CVD method, and a third step of forming a third layer directly on the second layer by an HDP-CVD method; the second step is terminated before a distance between an upper surface of a portion of the second layer between the first wiring portion and the second wiring portion in the thickness direction and the top interlayer insulating film exceeds 0.42 times the first distance; the third step is terminated after a distance between an upper surface of the portion of the third layer between the first wiring portion and the second wiring portion in the thickness direction and the top interlayer insulating film becomes 0.65 times or more of the first distance.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the silicon oxide film further comprises a fourth step of forming a fourth layer disposed on the third layer by HDP-CVD.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a bias voltage or a gas ratio is changed at least during the second step and during the third step.

4. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the top wiring is made of aluminum or an aluminum alloy.

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