Porous FLI Bumps for Reducing Bump Thickness Variation Sensitivity to Enable Bump Pitch Scaling

Abstract

To reduce the sensitivity of first level interconnect (FLI) with respect to bump thickness fluctuations.SOLUTION: Embodiment disclosed in the present application include electronic packages with fine pitch first level interconnects. In one embodiment, the electronic package includes a die and a package substrate attached to the die by a plurality of first level interconnects (FLIs). In one embodiment, each of the plurality of FLIs includes a first pad on the package substrate, a solder on the first pad, a second pad on the die, and a bump on the second pad. In one embodiment, the bump includes a porous nanostructure, and the solder at least partially fills the porous nanostructure.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to semiconductor devices, and more particularly to electronic packages having porous first level interconnect (FLI) bumps. [Background technology]

[0002] New architectures for electronic systems increasingly require die splitting and bump pitch scaling to achieve increased inter-die communication bandwidth and die area savings. This requirement for reduced bump pitch necessitates precise control of bump thickness variation (rBTV). To achieve good process yield, an rBTV of 10 μm or less is highly desirable, which is not trivial considering that thickness variation in a typical multilayer organic substrate can exceed 40 μm even before reaching the final first-level interconnect (FLI) layer.

[0003] Current approaches to meeting the stringent rBTV requirements for next-generation architectures have focused primarily on reducing the thickness variation of the package substrate. For example, processes such as mechanical planarization, advanced stacking techniques, new tools for improving FLI plating uniformity, and specialized lithography steps have been proposed. However, such processing operations are costly and complex. [Brief explanation of the drawings]

[0004] [Figure 1A] FIG. 1A is a cross-sectional view of a die with nanoporous bumps on a package substrate with solder on the pads, according to one embodiment. [Figure 1B] FIG. 1B is a cross-sectional view of a die after it has been attached to a pad with solder penetrating the nanoporous bump, according to one embodiment. [Figure 2A] FIG. 2A is a cross-sectional view of a die with nanoporous bumps on a package substrate with multiple solder bumps having non-uniform bump thickness, according to one embodiment. [Figure 2B] FIG. 2B is a cross-sectional view of a die after it has been attached to a package substrate with solder penetrating the nanoporous bumps, according to one embodiment. [Figure 3A] FIG. 3A is a photomicrograph of solder between a standard bump and a standard pad, according to one embodiment. [Figure 3B] FIG. 3B is a photomicrograph of the solder between a bump and a nanoporous pad showing the penetration of the solder into the nanoporous pad, according to one embodiment. [Figure 4A] FIG. 4A is a cross-sectional view of a bump including an alloying composition according to one embodiment. [Figure 4B] FIG. 4B is a cross-sectional view of the bump of FIG. 4A after removing one of the alloy components to form a nanoporous bump, according to one embodiment. [Figure 5A] FIG. 5A is a planar scanning electron microscope (SEM) image of the surface of a nanoporous bump, according to one embodiment. [Figure 5B] FIG. 5B is a cross-sectional SEM image of a nanoporous bump according to one embodiment. [Figure 6A] FIG. 6A is a cross-sectional view of a die with bumps on a package substrate with nanoporous bumps on the pads, according to one embodiment. [Figure 6B] FIG. 6B is a cross-sectional view of a die attached to a package substrate with solder penetrating the nanoporous bumps, according to one embodiment. [Figure 7A] FIG. 7A is a cross-sectional view of a die with nanoporous bumps on a package substrate with solder on the pads, according to one embodiment. [Figure 7B] FIG. 7B is a cross-sectional view of a die attached to a package substrate with solder penetrating the nanoporous bumps, according to one embodiment. [Figure 8] FIG. 8 is a cross-sectional view of an electronic system including a first level interconnect (FLI) with nanoporous bumps according to one embodiment. [Figure 9] FIG. 9 is a schematic diagram of a computing device constructed in accordance with one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0005] This specification describes electronic packages having porous first-level interconnect (FLI) bumps, according to various embodiments. The following describes various aspects of example implementations using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are set forth to provide a thorough understanding of example implementations. However, it will be apparent to those skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features have been omitted or simplified in order not to obscure the example implementations.

[0006] Although various operations are described sequentially as multiple discrete operations in a manner that is most useful in understanding the invention, the order of description should not be construed as implying that these operations are necessarily order dependent, and in particular, these operations need not be performed in the order presented.

[0007] As mentioned above, minimizing bump thickness variation (rBTV) is necessary to enable high-yield first-level interconnect (FLI) in advanced system architectures. Specifically, it is predicted that rBTV of approximately 10 μm will be required for some applications. Current approaches to reaching such stringent rBTV values ​​currently rely on advances in the fabrication of organic packaging substrates. However, such approaches are very costly.

[0008] Therefore, embodiments disclosed herein offer an alternative route to enabling advanced system architectures. Instead of reducing rBTV, embodiments disclosed herein reduce or eliminate FLI's sensitivity to rBTV. By reducing sensitivity to rBTV, modifications to the fabrication of organic packaging substrates may not be necessary in some embodiments. Notably, embodiments reduce reliance on rBTV by utilizing nanoporous bumps in FLI. In one embodiment, the internal porous structure of the nanoporous bump is infiltrated with solder. Additionally, the large surface area converts most of the solder to intermetallic compounds (IMCs). Solder penetration and conversion to IMCs reduces solder spreading. For example, solder spreading can be one-third of the spreading that occurs with existing FLI architectures. Therefore, excess solder does not spread laterally from the interconnect, reducing rBTV sensitivity. This enables tight-pitch FLI, which is necessary for advanced system architectures.

[0009] Referring now to FIG. 1A , a cross-sectional view of an electronic package 100 is shown before first-level interconnect (FLI) is attached, according to one embodiment. As shown, a die 105 is located on a package substrate 101. In one embodiment, the package substrate 101 includes stacked layers of organic material. The package substrate 101 includes embedded conductive features, such as vias 131, traces, and pads. In the illustrated embodiment, pads 132 are located on the top surface of the package substrate 101 and overlie vias 131 that provide electrical connection to additional conductive features (not shown) within the package substrate. In some embodiments, the pads 132 may be covered by a barrier layer 133. For example, the barrier layer 133 may include nickel or any other suitable barrier material common in electronic packaging applications. In one embodiment, solder bumps 134 are located on the barrier layer 133. The solder bumps 134 may be any suitable solder material for electronic packaging applications, such as a tin-based solder.

[0010] In one embodiment, die 105 may include a semiconductor substrate, such as, but not limited to, a silicon substrate. Die 105 may include transistor devices (not shown) and back-end (BEOL) routing (not shown) from the transistor devices to pads 122 on the surface of die 105. In one embodiment, die 105 may be a processor, a graphics processor, a system-on-chip (SoC), a memory, or any other similar component.

[0011] In one embodiment, a nanoporous bump 124 is provided on the pad 122. The nanoporous bump 124 extends away from the die 105. The nanoporous bump 124 may include a plurality of nano-sized pores passing through the nanoporous bump 124. In FIG. 1A, the nanoporous bump 124 is shown as having a grid-like pattern for simplicity. However, it should be understood that the structure of the nanoporous bump 124 may have an irregular structure. Exemplary micrographs of nanoporous structures are provided in more detail below with respect to FIGS. 5A and 5B. In one embodiment, the individual pores of the nanoporous structure may have an average diameter (or other cross-sectional dimension) of 1 nm to 1000 nm. In one embodiment, the nanoporous structure may include copper, gold, silver, cobalt, or other conductive materials capable of being formed as nanoporous structures.

[0012] 1B, a cross-sectional view of the electronic package 100 after the die 105 has been attached to the package substrate 101 is shown, according to one embodiment. As shown, the solder 134 has penetrated the nanoporous bump 124 to form the solder-filled bump 125. In the illustrated embodiment, all pores in the bump 125 are completely filled. However, in some embodiments, the bump 125 may only be partially filled. Due to the large surface area at the interface between the bump 125 and the solder 134, a significant portion of the solder 134 and the bump 125 are converted to an intermetallic compound (IMC). That is, in some embodiments, the porous structure of the nanoporous bump 124 is converted to an IMC, and the pores in the nanoporous bump 124 are not discernible within the bump 125.

[0013] The penetration of solder 134 and the formation of IMC are particularly beneficial in that the solder 134 is consumed or retained within the bump 125. This reduces the amount of residual solder 134 and limits solder spreading, resulting in an interconnect that is less sensitive to rBTV. With standard bumps, a large rBTV can result in an excessive amount of solder that must spread laterally. In embodiments disclosed herein, the excess solder from the large rBTV is consumed or otherwise stored within the bump 125. Thus, the solder spreading in embodiments disclosed herein can be approximately one-third of the solder spreading when standard copper bumps are used.

[0014] In one embodiment, the remaining portion of the solder 134 remains between the bump 125 and the barrier layer 133. In one embodiment, the profile 136 of the remaining solder 134 may have a fillet shape from the edge of the barrier layer to the edge of the filled bump 125.

[0015] 2A, a cross-sectional view of an electronic package 200 according to one embodiment is shown. In one embodiment, a set of interconnects 230 A , 230 B and 230 C Each interconnect includes a via 231, a pad 232, a barrier layer 233, and a solder bump 234. In one embodiment, the diameter of the pad 232 is equal to the diameter of a set of interconnects 230. A , 230 B and 230 C For example, pad 232 A is the largest pad, and pad 232 B Pad 232 A Smaller than pad 232 C Pad 232 A Variations in pad diameter can result in uneven solder bump 234 heights. For example, A and interconnection 230 B A first height difference D1 is provided between the interconnect 230 B and interconnection 230C 2A, a second height difference D2 is provided between the organic package substrate 201 and the organic package substrate 201. As such, the electronic package may be considered to have a relatively high rBTV. Although not shown in FIG. 2A, non-uniformities across the organic package substrate 201 may also add to the rBTV.

[0016] In one embodiment, a die 205 is located on a package substrate 201. The die 205 may include a plurality of pads 222 and a plurality of nanoporous bumps 224 on the pads 222. Each of the nanoporous bumps 224 is connected to an interconnect 230. A , 230 B or 230 c The nanoporous bumps 224 may be substantially similar to the nanoporous bumps 124 described above. For example, the nanoporous bumps 224 may comprise copper, gold, silver, cobalt, etc. Additionally, each of the nanoporous bumps 224 may comprise a plurality of pores having an average cross-sectional dimension of about 1 nm to about 1,000 nm.

[0017] Referring now to FIG. 2B, a cross-sectional view of electronic package 200 is shown after contacting the die with solder 234, according to one embodiment. In one embodiment, solder 234 may penetrate nanoporous bump 224 to form bump 225 at least partially filled with solder 234. Bump 225 may further include IMCs resulting from the interaction of solder 234 with the material of nanoporous bump 224. Due to the penetration of solder 234 and its conversion to IMCs, excess solder 234 caused by a high rBTV is confined within bump 225 instead of spreading laterally to adjacent interconnects 230. This allows interconnects 230 to be built at the fine pitch required for advanced system architectures. In some embodiments, interconnects 230 may have a pitch of about 5 μm to about 1500 μm.

[0018] In one embodiment, the residual solder 234 between the bump 225 and the barrier layer 233 may have a fillet profile 237. Depending on the amount of solder 234, the location of the fillet may vary. ANow, fillet profile 237 A is outside the perimeter of the bump 225 and the interconnect 230 B and 230 C Now, fillet profile 237 B and 237 C is within the perimeter of bump 225.

[0019] 3A and 3B, which show micrographs of a standard FLI interconnect (FIG. 3A) and a nanoporous interconnect (FIG. 3B), according to one embodiment. FIGS. 3A and 3B are shown at approximately the same magnification and contain substantially similar amounts of solder. As such, the two figures can be compared.

[0020] 3A, copper bump 340 extends away from die 305. Pad 332 is opposite bump 340, with solder 334 disposed between pad 332 and bump 340. Pad 332 is solid copper; that is, neither bump 340 nor pad 332 includes a nanoporous structure. As shown, solder 334 does not penetrate either bump 340 or pad 332. Additionally, only a small amount of IMC 342 forms at the interfaces between pad 332 and solder 334 and between bump 340 and solder 334.

[0021] Referring to FIG. 3B , copper bump 340 extends away from die 305. However, instead of a solid copper pad, a nanoporous pad 332 is provided opposite bump 340. The dashed line indicates the original boundary where nanoporous pad 332 ended. As shown, a fill region 325 is provided on the top half of pad 332. This light gray region indicates that solder 334 has penetrated nanoporous pad 332 and been converted into IMC 342. Furthermore, it indicates that a significant portion of solder 334 has been converted into IMC 342. The bottom 324 of nanoporous pad 332 may be free of solder 334; that is, in some embodiments, solder 334 may not penetrate the entire nanoporous pad 332.

[0022] In addition to permeation and conversion to IMC, the solder 334 in FIG. 3B does not spread laterally as much as the solder 334 in FIG. 3A. In some embodiments, the solder 334 may spread three times laterally in an interconnect similar to that of FIG. 3A compared to an interconnect similar to that of FIG. 3B. Additionally, the embodiment shown in FIG. 3B exhibits a fillet-like profile. While not as sharp as the idealized version in the previous figure, it should be understood that there is a distinct profile that differs from the nearly linear taper in the solder 334 of the interconnect shown in FIG. 3A.

[0023] 4A and 4B, a pair of cross-sectional views illustrating a process for forming a nanoporous structure, according to one embodiment, are shown. The process illustrated in FIGS. 4A and 4B may be referred to as a dealloying process. While a dealloying process is described as one method for forming a nanoporous structure, it is not the only method for forming such a structure. For example, a plating process with controlled additives and conditions may also result in the formation of a nanoporous structure. Similarly, a high-pressure sputtering process may be used to form a nanoporous structure.

[0024] 4A, an idealized diagram of a bump 421 including an alloy having a first constituent 428 and a second constituent 429 is shown, according to one embodiment. The bump 421 may be on a pad 432 on a package substrate 401. However, it should be understood that the dealloying process may also be performed on the die-side bump 421 using a similar process. For clarity, FIG. 4A shows the first constituent 428 and second constituent 429 in a grid-like pattern. However, it should be understood that the microstructure of the die-side bump 421 has a more natural distribution of the first constituent 428 mixed with the second constituent 429.

[0025] In one embodiment, the first component 428 and the second component 429 are materials that can be selectively etched relative to one another. For example, a wet etching chemistry can be provided that selectively removes the second component 429 while leaving the first component 428. In a particular embodiment, the first component 428 can be copper and the second component 429 can be zinc. Other alloys are also possible, such as an alloy in which the first component 428 is gold and the second component 429 is silver. Additionally, while an embodiment having a pair of components 428 and 429 has been illustrated and described, it should be understood that alloys having three or more components can be selectively dealloyed in a similar manner to provide a nanoporous structure.

[0026] 4B, a cross-sectional view of an interconnect after a dealloying process is shown, according to one embodiment. In one embodiment, the dealloying process results in the removal of second constituent material 429 to leave nanoporous bump 424 having substantially only first constituent material 428. It should be understood that in some implementations, the etching process may not completely remove all of second constituent material 429, and thus residual portions of second constituent material 429 may remain.

[0027] 5A and 5B, scanning electron microscope (SEM) images of a nanoporous structure are shown, according to one embodiment. FIG. 5A is an image of the top surface of a nanoporous bump, and FIG. 5B is a cross-sectional view of the nanoporous bump. As shown in the images, the nanoporous structure results in a textured surface. The lighter portions of the images are the solid structure of the nanoporous bump, while the darker areas are the pores of the nanoporous bump. As shown, the pores are substantially evenly distributed throughout the nanoporous bump.

[0028] 6A and 6B, a process for assembling an electronic package 600 with nanoporous bumps 651 on the package side is shown, according to one embodiment.

[0029] Referring now to FIG. 6A , a package substrate 601 is provided beneath the die 605. In one embodiment, the package substrate 601 may include an organic layer with embedded conductive routing (not shown). The conductive routing may be electrically connected to pads 632. The pads 632 may be any conductive material, such as copper. In one embodiment, a nanoporous bump 651 is provided on each of the pads 632. The nanoporous bumps 651 may be substantially similar to any of the nanoporous bumps described in detail above. For example, the nanoporous bumps 651 include a conductive material and have a plurality of holes extending therethrough. In one embodiment, the conductive material may include copper, gold, silver, cobalt, or the like. In one embodiment, the holes may have a cross-sectional dimension of approximately 1 nm to 1000 nm. The nanoporous bumps 651 may be fabricated on the pads 632 by a process such as, but not limited to, a dealloying process, a controlled plating process, or a high-pressure sputtering process.

[0030] In one embodiment, die 605 is disposed opposite package substrate 601. Die 605 may include a transistor (not shown) electrically coupled to pad 622 via a conductive feature (not shown) in the BEOL stack. In one embodiment, bump 640 is disposed on pad 622. Bump 640 may be a copper bump or the like. In one embodiment, solder 634 may be disposed on bump 640.

[0031] 6B, a cross-sectional view of electronic package 600 after die 605 is attached to package substrate 601 is shown, according to one embodiment. In one embodiment, solder 634 may penetrate nanoporous bump 651 to form solder-filled bump 652. Due to the high surface area between solder 634 and nanoporous bump 651, solder-filled bump 652 may contain a substantially large amount of IMC. In one embodiment, solder-filled bump 652 may be substantially filled with solder 634; that is, substantially all of the pores of nanoporous bump 651 may be filled with solder 634 (which may later be converted to IMC). In other embodiments, solder 634 may not completely penetrate nanoporous bump 651, and solder-filled bump 652 may maintain some open pores.

[0032] 7A and 7B, a process for assembling an electronic package 700 with die-side nanoporous bumps 761 is shown, according to one embodiment.

[0033] 7A, a cross-sectional view of an electronic package 700 is shown having a die 705 located on a package substrate 701, according to one embodiment. In one embodiment, package substrate 701 may include an organic layer with embedded conductive routing (not shown). The conductive routing may be electrically connected to pads 732. Pads 732 may be any conductive material, such as copper. In one embodiment, solder 734 is disposed on each of pads 732.

[0034] In one embodiment, a die 705 is disposed opposite the package substrate 701. The die 705 may include a transistor (not shown) electrically coupled to the pads 722 via conductive features (not shown) in the BEOL stack. In one embodiment, a nanoporous bump 761 is disposed on each of the pads 722. The nanoporous bump 761 may be substantially similar to any of the nanoporous bumps described in more detail above. For example, the nanoporous bump 761 may include a conductive material having a plurality of holes extending therethrough. In one embodiment, the conductive material may include copper, gold, silver, cobalt, or the like. In one embodiment, the holes may have a cross-sectional dimension of approximately 1 nm to 1000 nm. The nanoporous bump 761 may be fabricated on the pads 722 by a process such as, but not limited to, a dealloying process, a controlled plating process, or a high-pressure sputtering process.

[0035] 7B, a cross-sectional view of electronic package 700 after die 705 is attached to package substrate 701 is shown, according to one embodiment. In one embodiment, solder 734 may penetrate nanoporous bump 761 to form solder-filled bump 762. Due to the high surface area between solder 734 and nanoporous bump 761, solder-filled bump 762 may contain a substantially large amount of IMC. In one embodiment, solder-filled bump 762 may be substantially filled with solder 734; that is, substantially all of the pores of nanoporous bump 761 may be filled with solder 734 (which may later be converted to IMC). In other embodiments, solder 734 may not completely penetrate nanoporous bump 761, and solder-filled bump 762 may maintain some open pores.

[0036] 8, a cross-sectional view of an electronic system 890 is shown, according to one embodiment. In one embodiment, electronic system 890 may include a board 891. Package substrate 801 is attached to board 891 by interconnects 892. Interconnects 892 are shown as solder balls. However, it should be understood that interconnects 892 may include any suitable interconnect architecture, such as a socket. In one embodiment, package substrate 801 includes multiple stacked organic layers. Conductive routing (not shown) may be electrically coupled to pads 832 on the top surface of package substrate 801.

[0037] In one embodiment, the die 805 is electrically coupled to the package substrate by a plurality of FLIs 830. The FLIs 830 connect pads 822 on the die 805 to pads 832 on the package substrate. In one embodiment, the FLIs 830 include nanoporous bumps 862 and solder 834. The nanoporous bumps 862 may be substantially similar to any of the nanoporous bumps described in more detail above. For example, the nanoporous bumps 862 may include a conductive material having a plurality of pores extending therethrough. In one embodiment, the conductive material may include copper, gold, silver, cobalt, or the like. In one embodiment, the pores may have cross-sectional dimensions of approximately 1 nm to 1000 nm. The nanoporous bumps 862 may be fabricated on the pads 822 by a process such as, but not limited to, a dealloying process, a controlled plating process, or a high-pressure sputtering process.

[0038] In one embodiment, solder 834 may penetrate nanoporous bump 862 to form solder-filled bump 862. Due to the high surface area between solder 834 and nanoporous bump 862, solder-filled bump 862 may contain a substantially large amount of IMC. In one embodiment, solder-filled bump 862 may be substantially filled with solder 834; that is, substantially all of the pores of nanoporous bump 862 may be filled with solder 834 (which may later be converted to IMC). In other embodiments, solder 834 may not completely penetrate nanoporous bump 862, and solder-filled bump 862 may maintain some open pores.

[0039] In the illustrated embodiment, solder filled bump 862 is on the die side of electronic system 890. However, it should be understood that solder filled bump 862 may alternatively be provided on the package substrate 801 side of electronic system 890. That is, solder filled bump 862 may be formed on pad 832 instead of pad 822.

[0040] In one embodiment, the presence of nanoporous bump 862 prevents lateral spreading of solder 834. Notably, if excess solder 834 is present (e.g., due to a high rBTV), the excess solder 834 will penetrate nanoporous bump 862 and convert to an IMC. Therefore, successful formation of FLI 830 is not dependent on having a low rBTV.

[0041] 9 illustrates a computing device 900 according to one implementation of the present invention. The computing device 900 houses a substrate 902. The substrate 902 may include a number of components, including, but not limited to, a processor 904 and at least one communications chip 906. The processor 904 is physically and electrically coupled to the substrate 902. In some implementations, the at least one communications chip 906 is also physically and electrically coupled to the substrate 902. In further implementations, the communications chip 906 is part of the processor 904.

[0042] These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, Global Positioning System (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0043] The communications chip 906 enables wireless communications for the transfer of data to and from the computing device 900. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data through the use of modulated electromagnetic radiation over a non-solid medium. Such terms do not imply that the associated devices do not include wires (which may be the case in some embodiments). The communications chip 906 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G, and beyond. The computing device 900 may include multiple communications chips 906. For example, the first communications chip 906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and the second communications chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0044] The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. In some implementations of the invention, the processor's integrated circuit die may be electrically coupled to a package substrate by an FLI including nanoporous bumps penetrated by solder according to embodiments described herein. The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that may be stored in registers and / or memory.

[0045] The communications chip 906 also includes an integrated circuit die packaged within the communications chip 906. According to another implementation of the present invention, the integrated circuit die of the communications chip may be coupled to the package substrate by FLI including nanoporous bumps penetrated by solder according to embodiments described herein.

[0046] The above description of exemplary implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise form disclosed. While specific implementations and examples of the invention have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as will be recognized by those skilled in the art.

[0047] These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

[0048] Example 1: An electronic package comprising: a die; and a package substrate attached to the die by a plurality of first level interconnects (FLIs), each of the plurality of FLIs comprising: a first pad on the package substrate; solder on the first pad; a second pad on the die; and a bump on the second pad, the bump comprising a porous nanostructure, the porous nanostructure at least partially filled with the solder.

[0049] Example 2: The electronic package of example 1, wherein the bumps and the solder react to form an intermetallic compound.

[0050] Example 3: The electronic package of example 1 or example 2, wherein a portion of the solder remains between the bump and the first pad.

[0051] Example 4: The electronic package of Example 3, wherein the profile of the portion of the solder has a fillet shape between the first pad and the bump.

[0052] Example 5: The electronic package of example 4, wherein the fillet shape is outside the footprint of the bump.

[0053] Example 6: The electronic package of example 4, wherein the fillet shape is within the footprint of the bump.

[0054] Example 7: The electronic package of any one of Examples 1 to 6, further comprising a barrier layer between the first pad and the solder.

[0055] Example 8: The electronic package of example 7, wherein the barrier layer comprises nickel.

[0056] Example 9: The electronic package of any one of Examples 1 to 8, wherein the bumps comprise copper, gold, silver, or cobalt.

[0057] Example 10: An electronic package as described in Examples 1 to 9, wherein the plurality of FLIs include a first FLI, wherein the first pad of the first FLI has a first dimension, and a second FLI, wherein the first pad of the second FLI has a second dimension that is smaller than the first dimension.

[0058] Example 11: An electronic package comprising: a die; and a package substrate attached to the die by a plurality of first level interconnects (FLIs), each of the plurality of FLIs comprising: a first pad on the package substrate; a bump on the first pad, the bump comprising a porous nanostructure; solder on the bump, the porous nanostructure being at least partially filled with the solder; and a second pad on the die, the second pad overlying the solder.

[0059] Example 12: The electronic package of example 11, wherein the bumps and the solder react to form an intermetallic compound.

[0060] Example 13: The electronic package of example 11 or example 12, wherein a portion of the solder remains between the bump and the first pad.

[0061] Example 14: The electronic package of Example 13, wherein the profile of the portion of the solder has a fillet shape between the first pad and the bump.

[0062] Example 15: The electronic package of Example 14, wherein the fillet shape is outside the footprint of the bump.

[0063] Example 16: The electronic package of Example 14, wherein the fillet shape is within the footprint of the bump.

[0064] Example 17: The electronic package of Example 11, further comprising a barrier layer between the first pad and the solder.

[0065] Example 18: The electronic package of Example 17, wherein the barrier layer comprises nickel.

[0066] Example 19: The electronic package of any one of Examples 11 to 18, wherein the bump comprises copper, gold, silver, or cobalt.

[0067] Example 20: A die comprising a substrate and a plurality of first level interconnects (FLIs) on the substrate, each of the FLIs comprising a pad on the substrate and a bump on the pad extending away from the substrate, the bump comprising a porous nanostructure.

[0068] Example 21: The die of example 20, wherein the bump comprises copper, gold, silver, or cobalt.

[0069] Example 22: The die of Example 20, wherein the pores of the porous nanostructure have an average diameter of less than or equal to about 1000 nm.

[0070] Example 23: An electronic system comprising: a board; a package substrate coupled to the board; and a die coupled to the package substrate by a plurality of first level interconnects (FLIs), each of the FLIs comprising a bump having a porous nanostructure, the porous nanostructure being at least partially filled with solder.

[0071] Example 24: The electronic system of Example 23, wherein the bump is on the package substrate side of the FLI.

[0072] Example 25: The electronic system of Example 23, wherein the bump is on the die side of the FLI.

Claims

1. Dai and a package substrate attached to the die by a plurality of first level interconnects (FLIs), each of the plurality of FLIs comprising: a first pad on the package substrate; solder on the first pad; a second pad on the die; a bump on the second pad, the bump including a porous nanostructure, the porous nanostructure being at least partially filled with the solder; a package substrate including:

1. An electronic package comprising: the solder at least partially filling the porous nanostructure has penetrated the porous nanostructure and been transformed into an intermetallic compound with the porous nanostructure, and the portion of the solder that has not penetrated the porous nanostructure remains between the bump and the first pad to form residual solder; The electronic package, wherein the solder penetrates the porous nanostructure and is transformed into an intermetallic compound along with the porous nanostructure, thereby limiting the lateral spread of the residual solder and resulting in reduced sensitivity of the plurality of FLIs to bump thickness variations.

2. The electronic package of claim 1 , wherein the profile of the residual solder has a fillet shape between the first pad and the bump.

3. The electronic package of claim 2 , wherein the fillet shape is outside the footprint of the bump.

4. The electronic package of claim 2 , wherein the fillet shape is within the footprint of the bump.

5. The electronic package of claim 1 , further comprising a barrier layer between the first pad and the solder.

6. The electronic package of claim 5 , wherein the barrier layer comprises nickel.

7. The electronic package of claim 1 , wherein the bumps comprise copper, gold, silver, or cobalt.

8. The plurality of FLIs include: a first FLI, wherein the first pad of the first FLI has a first dimension; a second FLI, the first pad of the second FLI having a second dimension smaller than the first dimension; 8. The electronic package of claim 1, comprising:

9. Dai and a package substrate attached to the die by a plurality of first level interconnects (FLIs), each of the plurality of FLIs comprising: a first pad on the package substrate; a bump on the first pad, the bump comprising a porous nanostructure; solder on the bump, the porous nanostructures being at least partially filled with the solder; a second pad on the die, the second pad overlying the solder; and a package substrate including:

1. An electronic package comprising: the solder at least partially filling the porous nanostructure has penetrated the porous nanostructure and been transformed into an intermetallic compound with the porous nanostructure, and the portion of the solder that has not penetrated the porous nanostructure remains between the bump and the first pad to form residual solder; The electronic package, wherein the solder penetrates the porous nanostructure and is transformed into an intermetallic compound along with the porous nanostructure, thereby limiting the lateral spread of the residual solder and resulting in reduced sensitivity of the plurality of FLIs to bump thickness variations.

10. 10. The electronic package of claim 9, wherein the residual solder has a fillet shape between the first pad and the bump.

11. The electronic package of claim 10 , wherein the fillet shape is outside the footprint of the bump.

12. The electronic package of claim 10 , wherein the fillet shape is within the footprint of the bump.

13. The electronic package of claim 10 further comprising a barrier layer between the first pad and the solder.

14. The electronic package of claim 13 , wherein the barrier layer comprises nickel.

15. 15. The electronic package of claim 9, wherein the bumps comprise copper, gold, silver, or cobalt.

16. Board and a package substrate connected to the board; a die coupled to the package substrate by a plurality of first level interconnects (FLIs), each of the FLIs comprising: a bump having a porous nanostructure, the porous nanostructure being at least partially filled with solder; Dai and pads on the package substrate or on the die; An electronic system comprising: the solder at least partially filling the porous nanostructure has penetrated the porous nanostructure and been transformed into an intermetallic compound with the porous nanostructure, and the portion of the solder that has not penetrated the porous nanostructure remains between the bump and the pad to form residual solder; The electronic system, wherein the solder penetrates the porous nanostructure and is transformed into an intermetallic compound along with the porous nanostructure, thereby limiting the lateral spread of the residual solder and resulting in reduced sensitivity of the multiple FLIs to bump thickness variations.

17. The electronic system of claim 16 , wherein the bumps are on the package substrate side of the FLI.

18. The electronic system of claim 16 , wherein the bump is on the die side of the FLI.

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