Semiconductor Devices

Abstract

To provide a semiconductor device that can suppress the peeling of an upper substrate.SOLUTION: A semiconductor device 10 has a lower substrate 20, a semiconductor element 30 mounted on the upper surface of the lower substrate 20, an upper substrate 40 provided on the upper surface of the semiconductor element 30, a through hole 44 passing through the upper substrate 40 in the thickness direction, a sealing resin 50 provided between the lower substrate 20 and the upper substrate 40 to seal the semiconductor element 30, and a wiring layer 60 provided on the upper surface of the upper substrate 40. The sealing resin 50 is formed to cover the upper surface of the upper substrate 40 and to fill the through hole 44.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] A power semiconductor device (power module) that controls and supplies electric power has been known as a conventional semiconductor device. This type of semiconductor device includes a semiconductor element mounted between a lower substrate and an upper substrate, a sealing resin that is provided between the lower substrate and the upper substrate and seals the semiconductor element, and a wiring layer that is electrically connected to the semiconductor element and formed on the upper surface of the upper substrate.

[0003] Incidentally, Patent Document 1 is disclosed as a prior art related to the above conventional technology. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-120902 Summary of the Invention [Problem to be solved by the invention]

[0005] In conventional semiconductor devices, the difference in coefficient of thermal expansion (CTE) between the semiconductor element and the upper substrate can be large. In such cases, when heat is applied to the semiconductor device during a temperature cycle test or the like, the difference in coefficient of thermal expansion between the semiconductor element and the upper substrate can easily cause the upper substrate to peel off from the semiconductor device. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a semiconductor device comprising: a lower substrate; a semiconductor element mounted on an upper surface of the lower substrate; an upper substrate provided on an upper surface of the semiconductor element; a through hole penetrating the upper substrate in a thickness direction; a sealing resin provided between the lower substrate and the upper substrate and sealing the semiconductor element; a wiring layer provided on the upper surface of the upper substrate; and a coating resin provided to cover the upper surface of the upper substrate and fill the through hole. The upper substrate has a substrate body and an adhesive layer provided on the lower surface of the substrate body, and the through-hole is formed so as to penetrate the substrate body and the adhesive layer in the thickness direction. . [Effects of the Invention]

[0007] According to one aspect of the present invention, it is possible to suppress peeling of the upper substrate. [Brief explanation of the drawings]

[0008] [Figure 1] 1(a) is a schematic cross-sectional view (cross-sectional view taken along line 1-1 in FIGS. 2 and 3) showing a semiconductor device according to one embodiment, and FIG. 1(b) is an enlarged cross-sectional view of a portion of the semiconductor device shown in FIG. 1(a). [Figure 2] 1 is a schematic plan view illustrating a semiconductor device according to an embodiment; [Figure 3] 1 is a schematic plan view illustrating a semiconductor device according to an embodiment; [Figure 4] 4 is a schematic cross-sectional view (cross-sectional view taken along line 4-4 in FIGS. 2 and 3) illustrating a semiconductor device according to an embodiment. FIG. [Figure 5] 5 is a schematic cross-sectional view (cross-sectional view taken along line 5-5 in FIGS. 2 and 3) illustrating a semiconductor device according to an embodiment. FIG. [Figure 6] 1A and 1B are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 1A and 1B are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a modified example. [Figure 9] 11 is a schematic cross-sectional view (cross-sectional view taken along line 9-9 in FIG. 10) showing a semiconductor device according to a modified example. [Figure 10] FIG. 10 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 11] FIG. 10 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 12] FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a modified example. [Figure 13] FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a modified example. [Figure 14] 14 is a schematic cross-sectional view (cross-sectional view taken along line 14-14 in FIG. 15) showing a semiconductor device according to a modified example. [Figure 15] FIG. 10 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 16] FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a modified example. [Figure 17] FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a modified example. [Figure 18] 20 is a schematic cross-sectional view (cross-sectional view taken along line 18-18 in FIG. 19) showing a semiconductor device according to a modified example. [Figure 19] FIG. 10 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 20] FIG. 10 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 21] FIG. 10 is a schematic plan view showing a semiconductor device according to a modified example. [Figure 22] FIG. 10 is a schematic plan view showing a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0009] An embodiment will be described below with reference to the accompanying drawings. For convenience, the accompanying drawings may show characteristic portions enlarged to facilitate understanding of the features, and the dimensional proportions of each component may not be the same in each drawing. In cross-sectional views, to facilitate understanding of the cross-sectional structure of each component, some components are shown with matte finish instead of hatching, and some components are not hatched at all. In this specification, "planar view" refers to viewing an object from a vertical direction (the up-down direction in FIG. 1(a)), such as in FIG. 1(a) , and "planar shape" refers to the shape of an object viewed from a vertical direction (the up-down direction in FIG. 1(a)) in this specification. The terms "vertical direction" and "horizontal direction" in this specification refer to directions in which the symbols indicating each component in each drawing can be correctly read, assuming the correct position. In this specification, "parallel" and "orthogonal" do not only refer to strictly parallel or orthogonal, but also include roughly parallel or orthogonal within the scope of the effects of this embodiment.

[0010] (Overall configuration of semiconductor device 10) First, the overall configuration of a semiconductor device 10 will be described with reference to FIG. The semiconductor device 10 is, for example, a power semiconductor device (power module) that controls and supplies power. For example, the semiconductor device 10 is a DC-DC converter. The semiconductor device 10 includes a lower substrate 20, one or more (two in this embodiment) semiconductor elements 30 mounted on the upper surface of the lower substrate 20, and an upper substrate 40 provided on the upper surface of the semiconductor elements 30. The semiconductor device 10 includes a sealing resin 50 provided between the lower substrate 20 and the upper substrate 40 to seal the semiconductor elements 30, and a wiring layer 60 electrically connected to the semiconductor elements 30 and provided on the upper surface of the upper substrate 40. Each semiconductor element 30 is provided between the upper surface of the lower substrate 20 and the lower surface of the upper substrate 40. In the semiconductor device 10, the semiconductor elements 30 are embedded between the lower substrate 20 and the upper substrate 40.

[0011] (Configuration of semiconductor element 30) Each semiconductor element 30 is made of, for example, silicon (Si) or silicon carbide (SiC). Each semiconductor element 30 is, for example, a power semiconductor element. For example, an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a diode, or the like can be used as the semiconductor element 30. The semiconductor element 30 of this embodiment is a MOSFET. The planar shape of the semiconductor element 30 can be any shape and any size. The planar shape of the semiconductor element 30 is, for example, rectangular. The thickness of the semiconductor element 30 can be, for example, in the range of 50 μm to 600 μm. The thermal expansion coefficient of the semiconductor element 30 can be, for example, in the range of 3 ppm / °C to 6 ppm / °C.

[0012] The semiconductor element 30 has, for example, an electrode pad 31, an electrode pad 32, and an electrode pad 33. The electrode pad 31 is formed, for example, on the lower surface of the semiconductor element 30. For example, the electrode pad 31 is formed so as to cover the entire lower surface of the semiconductor element 30. The electrode pads 32 and 33 are formed, for example, on the upper surface of the semiconductor element 30. The electrode pads 32 and 33 are provided spaced apart from each other on the upper surface of the semiconductor element 30. The electrode pad 31 is, for example, a drain electrode of a MOSFET. The electrode pad 32 is, for example, a source electrode of the MOSFET. The electrode pad 33 is, for example, a gate electrode of the MOSFET.

[0013] The electrode pads 31, 32, and 33 may be made of a metal such as aluminum (Al) or copper (Cu), or an alloy containing at least one metal selected from these metals. If necessary, a surface treatment layer may be formed on the surfaces of the electrode pads 31, 32, and 33. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer formed by laminating a Ni layer and an Au layer in this order), and a Ni layer / palladium (Pd) layer / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and an Au layer in this order). The Au layer, Ni layer, and Pd layer may be, for example, a metal layer formed by electroless plating (electroless plated metal layer). The Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy.

[0014] (Configuration of lower substrate 20) The lower substrate 20 is formed in a flat plate shape. The lower substrate 20 is a ceramic substrate made of ceramics such as oxide ceramics or non-oxide ceramics. Examples of oxide ceramics include aluminum oxide (Al2O3) and zirconia (ZrO2). Examples of non-oxide ceramics include aluminum nitride (AlN) and silicon nitride (Si3N4). The thermal expansion coefficient of the lower substrate 20 can be set in the range of 2 ppm / °C to 7 ppm / °C.

[0015] The planar shape of the lower substrate 20 can be any shape and any size. For example, the planar shape of the lower substrate 20 is formed into a rectangular shape. The thickness of the lower substrate 20 can be, for example, in the range of 200 μm to 400 μm.

[0016] (Configuration of wiring layer 21) 2 and 3, for example, a wiring layer 21 is formed on the upper surface of the lower substrate 20. The wiring layer 21 has, for example, one or more (here, one) wiring patterns 22, one or more (here, two) wiring patterns 23, and one or more (here, two) wiring patterns 24. Note that FIGS. 2 and 3 are plan views of the semiconductor device 10 shown in FIG. 1(a) as viewed from above. Also, in FIG. 3, the sealing resin 50 is drawn in a perspective manner.

[0017] The wiring patterns 22, 23, and 24 may be made of, for example, copper or a copper alloy. If necessary, a surface treatment layer may be formed on the surfaces (top and side surfaces, or only the top surfaces) of the wiring patterns 22, 23, and 24. Examples of the surface treatment layer include a metal layer such as an Au layer, a Ni layer / Au layer, or a Ni layer / Pd layer / Au layer. The thermal expansion coefficient of the wiring layer 21 may be, for example, in the range of 15 ppm / °C to 18 ppm / °C. The thickness of the wiring patterns 22, 23, and 24 may be, for example, in the range of 100 μm to 800 μm.

[0018] 3, the wiring patterns 22, 23, 24 are provided apart from one another on the upper surface of the lower substrate 20. The planar shapes of the wiring patterns 22, 23, 24 can be any shape and any size.

[0019] The planar shape of the wiring pattern 22 is formed, for example, in a rectangular shape. The wiring pattern 22 is formed, for example, larger than the planar shapes of the wiring patterns 23 and 24. The wiring pattern 22 is formed, for example, in a solid shape. For example, the wiring pattern 22 is formed on the upper surface of the lower substrate 20 so as to extend entirely over the left half region in the figure. The wiring pattern 22 is provided, for example, so that a portion thereof overlaps with the upper substrate 40 in a planar view. The wiring pattern 22 is electrically connected, for example, to the electrode pads 31 (see FIG. 1(a)) of the semiconductor element 30.

[0020] The planar shape of each wiring pattern 23 is formed, for example, in a rectangular shape. Each wiring pattern 23 is formed, for example, in a strip shape having a predetermined width in the vertical direction in the figure and extending in the horizontal direction in the figure. For example, the two wiring patterns 23 are provided outside the wiring pattern 24 in the vertical direction in the figure. For example, the two wiring patterns 23 are provided so as to sandwich the two wiring patterns 24 in the vertical direction in the figure. For example, each wiring pattern 23 is provided so as to partially overlap the upper substrate 40 in a planar view. Each wiring pattern 23 is electrically connected, for example, to an electrode pad 32 of the semiconductor element 30 (see FIG. 1(a)).

[0021] The planar shape of each wiring pattern 24 is formed, for example, in a rectangular shape. Each wiring pattern 24 is formed, for example, in a strip shape having a predetermined width in the vertical direction in the figure and extending in the horizontal direction in the figure. Each wiring pattern 24 is formed, for example, so as to extend parallel to each wiring pattern 23. For example, the two wiring patterns 24 are provided more inward than the wiring pattern 23 in the vertical direction in the figure. For example, each wiring pattern 24 is provided so that a portion thereof overlaps with the upper substrate 40 in a planar view. Each wiring pattern 24 is electrically connected, for example, to an electrode pad 33 of the semiconductor element 30 (see FIG. 1(a)).

[0022] (Configuration of metal layer 26) As shown in FIG. 1(a), for example, a metal layer 26 is formed on the lower surface of the lower substrate 20. The planar shape of the metal layer 26 can be any shape and any size. The planar shape of the metal layer 26 is formed, for example, in a rectangular shape. The metal layer 26 is formed, for example, in a solid shape. For example, the metal layer 26 is formed so as to extend over the entire lower surface of the lower substrate 20 except for the outer peripheral edge portion. The metal layer 26 functions, for example, as a reinforcing layer that suppresses warping of the lower substrate 20. The metal layer 26 can also function, for example, as a heat dissipation member.

[0023] The metal layer 26 may be made of, for example, copper or a copper alloy. If necessary, a surface treatment layer may be formed on the surface (bottom and side surfaces, or bottom surface only) of the metal layer 26. Examples of the surface treatment layer include an Au layer, a Ni layer / Au layer, or a Ni layer / Pd layer / Au layer. The thickness of the metal layer 26 may be, for example, in the range of 100 μm to 800 μm. The thickness of the metal layer 26 is formed to be thinner than the wiring layer 21, for example.

[0024] (Configuration of joint 71) The semiconductor element 30 is bonded to the upper surface of the wiring pattern 22 via a conductive bonding portion 71. The bonding portion 71 is bonded to the wiring pattern 22 and also to the electrode pad 31. The bonding portion 71 electrically connects the wiring pattern 22 and the electrode pad 31 of the semiconductor element 30.

[0025] 4, the bonding portions 71 are provided individually for, for example, the plurality of semiconductor elements 30. In this embodiment, each bonding portion 71 is bonded to the electrode pad 31 of each semiconductor element 30 and also bonded to the wiring pattern 22. As a result, each electrode pad 31 and the wiring pattern 22 are electrically connected via each bonding portion 71.

[0026] Each semiconductor element 30 is bonded to the upper surface of the wiring pattern 22 via a bonding portion 71. The two semiconductor elements 30 are provided spaced apart from each other in a planar direction (here, the left-right direction in the figure) perpendicular to the stacking direction of the semiconductor device 10 (the up-down direction in the figure). The two semiconductor elements 30 are provided side by side along the left-right direction in the figure. The two semiconductor elements 30 are formed to have, for example, the same thickness. The two semiconductor elements 30 are formed to have, for example, the same planar shape and the same size. As shown in FIG. 3 , each semiconductor element 30 is provided so that, for example, its entirety overlaps with the wiring pattern 22 in a planar view. Each semiconductor element 30 is provided so that, for example, its entirety overlaps with the upper substrate 40 in a planar view.

[0027] (Configuration of joint 72) 5, a conductive joint 72 is formed on the upper surface of each of the wiring patterns 23, 24. A connection member 75 is formed on the upper surface of each of the joints 72. The joint 72 is joined to the wiring pattern 23 or the wiring pattern 24, and is also joined to the connection member 75. The joint 72 electrically connects the wiring pattern 23 and the connection member 75. The joint 72 electrically connects the wiring pattern 24 and the connection member 75.

[0028] The bonding portions 71, 72 may be made of, for example, a metal sintered material. Examples of the sintered material include a sintered material (silver sintered material) primarily composed of silver (Ag) particles and a sintered material (copper sintered material) primarily composed of copper particles. The bonding portions 71, 72 may also be made of, for example, solder, conductive paste such as silver paste, or a metal brazing material. The thickness of the bonding portions 71, 72 may be, for example, in the range of 10 μm to 60 μm.

[0029] (Configuration of connecting member 75) The connection member 75 is electrically connected to the wiring layer 60 formed on the upper surface of the upper substrate 40. As a result, the wiring patterns 23, 24 are electrically connected to the wiring layer 60 via the joints 72 and the connection member 75. The connection member 75 is formed, for example, in a columnar shape extending along the stacking direction of the semiconductor device 10 (the up-down direction in the figure). The connection member 75 is, for example, a metal post. As shown in FIG. 1(a), the connection member 75 is formed, for example, to the same thickness as the semiconductor element 30. The thickness of the connection member 75 can be, for example, in the range of 50 μm to 775 μm. For example, the upper surface of the connection member 75 is formed on the same plane as the upper surface of the semiconductor element 30. The connection member 75 can be made of, for example, copper or a copper alloy.

[0030] (Configuration of upper substrate 40) The upper substrate 40 is provided on the upper surface of the semiconductor element 30 and the upper surface of the connecting member 75. The upper substrate 40 is formed in a flat plate shape. The planar shape of the upper substrate 40 can be any shape and any size. As shown in FIG. 3, the planar shape of the upper substrate 40 is formed, for example, in a rectangular shape. The planar shape of the upper substrate 40 is formed, for example, to be smaller than the planar shape of the lower substrate 20. For example, the horizontal dimension of the upper substrate 40 in the figure is formed to be smaller than the horizontal dimension of the lower substrate 20 in the figure. For example, the vertical dimension of the upper substrate 40 in the figure is formed to be smaller than the vertical dimension of the lower substrate 20 in the figure. The upper substrate 40 is provided, for example, so that its entirety overlaps with the lower substrate 20 in a planar view.

[0031] As shown in FIG. 1(b), the upper substrate 40 includes, for example, a substrate main body 41 and an adhesive layer 42 formed on the lower surface of the substrate main body 41. The substrate main body 41 may be made of an insulating resin such as a polyimide resin or a polyester resin. The adhesive layer 42 may be made of an epoxy, polyimide, or silicone adhesive. The thermal expansion coefficient of the upper substrate 40 may be, for example, in the range of 20 ppm / °C to 27 ppm / °C. The thickness of the substrate main body 41 may be, for example, in the range of 30 μm to 50 μm. The thickness of the adhesive layer 42 may be, for example, in the range of 15 μm to 45 μm.

[0032] The substrate main body 41 is adhered to the semiconductor element 30 by, for example, an adhesive layer 42. The adhesive layer 42 is adhered to the upper surface of the semiconductor element 30 and also to the lower surface of the substrate main body 41. The adhesive layer 42 is provided, for example, to incorporate a portion of the semiconductor element 30. In other words, a portion of the semiconductor element 30 is embedded in the adhesive layer 42. For example, the electrode pads 32, 33 of the semiconductor element 30 are embedded in the adhesive layer 42. For example, the upper portion of the semiconductor element 30 is embedded in the adhesive layer 42. The adhesive layer 42 is formed, for example, to cover the side surfaces of the upper portion of the semiconductor element 30.

[0033] The upper substrate 40 has a plurality of openings 43 formed therein, penetrating the upper substrate 40 in the thickness direction. Each opening 43 is formed, for example, by penetrating the substrate main body 41 and the adhesive layer 42 in the thickness direction. Each opening 43 is formed, for example, in a tapered shape in which the opening width (opening diameter) decreases from the upper side (the upper surface side of the upper substrate 40) to the lower side (the lower substrate 20 side) in FIG. 1(b). For example, each opening 43 is formed in an inverted truncated cone shape in which the opening diameter at the lower opening end is smaller than the opening diameter at the upper opening end. Some of the openings 43 are formed, for example, so as to expose part of the upper surfaces of the electrode pads 32 and 33. As shown in FIG. 1(a), some of the openings 43 are formed, for example, so as to expose part of the upper surface of the connection member 75.

[0034] The upper substrate 40 has a through hole 44 formed therein, which penetrates the upper substrate 40 in the thickness direction. The through hole 44 is formed, for example, by penetrating the substrate main body 41 and the adhesive layer 42 in the thickness direction. The through hole 44 is provided, for example, at a position that does not overlap the semiconductor element 30 and the connection member 75 in a plan view.

[0035] (Configuration of wiring layer 60) The wiring layer 60 is formed on the upper surface of the upper substrate 40. The wiring layer 60 has one or more (here, one) wiring patterns 61 and one or more (here, two) wiring patterns 62.

[0036] The wiring patterns 61, 62 may be made of, for example, copper or a copper alloy. If necessary, a surface treatment layer may be formed on the surfaces (top and side surfaces, or only the top surfaces) of the wiring patterns 61, 62. Examples of the surface treatment layer include a metal layer such as an Au layer, a Ni layer / Au layer, or a Ni layer / Pd layer / Au layer. The thermal expansion coefficient of the wiring layer 60 may be, for example, in the range of 15 ppm / °C to 18 ppm / °C. The thickness of the wiring patterns 61, 62 may be, for example, in the range of 50 μm to 200 μm.

[0037] 2 and 3, the wiring patterns 61 and 62 are provided spaced apart from each other on the upper surface of the upper substrate 40. The planar shapes of the wiring patterns 61 and 62 can be any shape and any size.

[0038] (Configuration of wiring pattern 61) The wiring pattern 61 has, for example, a main body portion 61A and an extension portion 61B extending in a planar direction from the main body portion 61A. The main body portion 61A has, for example, a rectangular planar shape. The main body portion 61A is provided, for example, so as to overlap the semiconductor element 30 in a planar view. For example, the main body portion 61A is provided so as to overlap the electrode pads 32 (see FIG. 1(a)) of the semiconductor element 30 in a planar view.

[0039] As shown in FIG. 1(b), the main body 61A of the wiring pattern 61 is electrically connected to the electrode pad 32, for example, via a via wiring V1 formed in an opening 43 that exposes a portion of the upper surface of the electrode pad 32. The wiring pattern 61 is formed integrally with the via wiring V1, for example. The wiring pattern 61 of this embodiment is formed integrally with a plurality of via wirings V1. The plurality of via wirings V1 are provided spaced apart from each other in the planar direction (the left-right direction in the figure), for example. Each via wiring V1 is formed so as to fill the opening 43, for example. Each via wiring V1 is formed to penetrate the substrate main body 41 and adhesive layer 42 of the upper substrate 40 in the thickness direction.

[0040] As shown in FIG. 3, each extension portion 61B extends, for example, from the side surface of the main body portion 61A facing the wiring pattern 62 toward the wiring pattern 23. Two extension portions 61B are formed, for example, at each end of the main body portion 61A in the vertical direction in the figure. Each extension portion 61B extends, for example, along the horizontal direction in the figure. The tip of each extension portion 61B is formed, for example, to extend to a position where it overlaps with the wiring pattern 23 in a plan view. The planar shape of each extension portion 61B is formed, for example, in a rectangular shape. The planar shape of each extension portion 61B is formed, for example, in a strip shape having a predetermined width in the vertical direction in the figure and extending in the horizontal direction in the figure.

[0041] As shown in FIG. 5, the extending portion 61B of the wiring pattern 61 is electrically connected to the connection member 75, for example, via a via wiring V2 formed in an opening 43 that exposes a portion of the upper surface of the connection member 75. The wiring pattern 61 is formed, for example, integrally with the via wiring V2. The via wiring V2 is formed, for example, so as to fill the opening 43. The wiring pattern 61 is electrically connected to the wiring pattern 23 via the via wiring V2, the connection member 75, and the joint portion 72. As a result, the wiring pattern 23 is electrically connected to the electrode pad 32 (source electrode) of the semiconductor element 30 via the joint portion 72, the connection member 75, the via wiring V2, the wiring pattern 61, and the via wiring V1 shown in FIG. 1(b).

[0042] (Configuration of wiring pattern 62) 3, the planar shape of each wiring pattern 62 is formed, for example, in a rectangular shape. Each wiring pattern 62 is formed, for example, in a strip shape having a predetermined width in the vertical direction in the figure and extending in the horizontal direction in the figure. Each wiring pattern 62 is formed, for example, so as to extend parallel to the extending portion 61B of each wiring pattern 61. For example, the two wiring patterns 62 are provided more inward than the extending portion 61B of the wiring pattern 61 in the vertical direction in the figure. A first end portion (left end portion in the figure) of each wiring pattern 62 is provided at a position overlapping a part of each semiconductor element 30 in a planar view.

[0043] 1(a), a first end of each wiring pattern 62 is provided at a position overlapping with an electrode pad 33 of each semiconductor element 30 in a plan view. The first end of each wiring pattern 62 is electrically connected to the electrode pad 33, for example, via a via wiring V3 formed in an opening 43 that exposes a portion of the upper surface of the electrode pad 33. The wiring pattern 62 is formed, for example, integrally with the via wiring V3. Each via wiring V3 is formed, for example, so as to fill the opening 43.

[0044] As shown in FIG. 3, a second end (right end in the figure) of each wiring pattern 62 opposite to the first end is formed so as to extend to a position overlapping the wiring pattern 24 in a plan view, for example.

[0045] 5, the second end of the wiring pattern 62 is electrically connected to the connection member 75, for example, via a via wiring V4 formed in an opening 43 that exposes a portion of the upper surface of the connection member 75. The wiring pattern 62 is formed, for example, integrally with the via wiring V4. The via wiring V4 is formed, for example, so as to fill the opening 43. The wiring pattern 62 is electrically connected to the wiring pattern 24 via the via wiring V4, the connection member 75, and the joint 72. As a result, the wiring pattern 24 is electrically connected to the electrode pad 33 (gate electrode) of the semiconductor element 30 via the joint 72, the joint 75, the via wiring V4, the wiring pattern 62, and the via wiring V3 shown in FIG. 1(a).

[0046] (Configuration of the through-hole 44) 2 and 3, the through holes 44 have, for example, one or more first through holes 45 provided around (near) the semiconductor element 30 in a plan view, and one or more second through holes 46 provided around the wiring layer 60 in a plan view. The through holes 44 of this embodiment have 14 first through holes 45 and 15 second through holes 46.

[0047] (Configuration of the first through hole 45) The plurality of first through holes 45 are provided, for example, around the corners of each semiconductor element 30 in a plan view. In this embodiment, a first through hole 45 is provided around each of the four corners (four corners) of each semiconductor element 30. The plurality of first through holes 45 are provided, for example, around each of the four sides that form the outer shape of each semiconductor element 30 in a plan view. In this embodiment, two first through holes 45 are provided for each of the four sides that form the outer shape of each semiconductor element 30. That is, two first through holes 45 are provided for each of the sides of each semiconductor element 30. The two first through holes 45 provided around each side of each semiconductor element 30 are provided, for example, around two different corners of each semiconductor element 30. In other words, two first through holes 45 are provided for each of the four corners of each semiconductor element 30. Between two semiconductor elements 30 arranged vertically in the figure, for example, two first through holes 45 are provided in common to the two semiconductor elements 30. That is, two first through holes 45 are provided in common on the lower side of the semiconductor element 30 arranged on the upper side in the figure and on the upper side of the semiconductor element 30 arranged on the lower side in the figure.

[0048] The planar shape of each first through hole 45 can be formed to any shape and any size. The planar shape of each first through hole 45 is formed to be, for example, a circular shape. The planar shapes of the multiple first through holes 45 may be the same shape as each other or different shapes from each other.

[0049] As shown in FIG. 1(b), each first through hole 45 is formed, for example, to penetrate the upper substrate 40 and the wiring layer 60 in the thickness direction. Each first through hole 45 is formed, for example, to penetrate the substrate main body 41, the adhesive layer 42, and the wiring pattern 61 in the thickness direction. Each first through hole 45 is formed, for example, to penetrate the main body portion 61A of the wiring pattern 61 in the thickness direction. The depth of each first through hole 45 is formed, for example, to be deeper than the depth of each second through hole 46. Each first through hole 45 is formed, for example, in a tapered shape such that the opening width (opening diameter) decreases from the upper side (the wiring pattern 61 side) to the lower side (the lower substrate 20 side) in FIG. 1(b). For example, each first through hole 45 is formed in the shape of an inverted truncated cone, with the opening diameter at the lower opening end being smaller than the opening diameter at the upper opening end. The inner surface of each first through hole 45 is formed to be inclined, for example, from the upper surface of the wiring pattern 61 toward the lower surface of the adhesive layer 42 so as to approach the planar center of the first through hole 45. The inner surface of each first through hole 45 is formed, for example, as an inclined plane extending linearly without steps in the thickness direction of the substrate main body 41, the adhesive layer 42, and the wiring pattern 61. That is, the inner surface of each first through hole 45 in this example is formed to be inclined at a certain angle. Note that the inner surface of each first through hole 45 does not need to be flat, and part or all of the inner surface of the first through hole 45 may be a convexly curved surface or a concavely curved surface.

[0050] (Configuration of second through hole 46) 2 and 3, each second through hole 46 is provided, for example, in a position that does not overlap with the wiring layer 60 in a plan view, around the wiring layer 60. The multiple second through holes 46 are provided, for example, in a plan view, around each extension portion 61B of the wiring pattern 61 or around the wiring pattern 62. The multiple second through holes 46 are provided, for example, at predetermined intervals along the extension direction of each extension portion 61B (left-right direction in the figure) in a plan view. In this embodiment, five second through holes 46 are provided at predetermined intervals along the extension direction of each extension portion 61B. Of the five second through holes 46 arranged side by side along the extension direction of each extension portion 61B, one second through hole 46 is provided, for example, around the tip end of each extension portion 61B in a plan view. Furthermore, the multiple second through holes 46 are provided at predetermined intervals in the extension direction (left-right direction in the figure) of the wiring pattern 62 in a plan view, for example. In this embodiment, five second through holes 46 are provided at predetermined intervals in the extension direction of the wiring pattern 62. Of the five second through holes 46 provided side by side in the extension direction of the wiring pattern 62, one second through hole 46 is provided, for example, in the periphery of a second end (right end in the figure) of the wiring pattern 62 in a plan view. Between two wiring patterns 62 lined up in the vertical direction in the figure, for example, five second through holes 46 are provided in common to the two wiring patterns 62.

[0051] The planar shape of each second through hole 46 can be formed to any shape and any size. The planar shape of each second through hole 46 is formed to be, for example, a circular shape. The planar shapes of the multiple second through holes 46 may be the same shape as each other or different shapes from each other.

[0052] As shown in FIG. 1(b), each second through hole 46 is formed, for example, to penetrate the upper substrate 40 in the thickness direction. Each second through hole 46 is formed, for example, to penetrate the substrate main body 41 and the adhesive layer 42 in the thickness direction. Each second through hole 46 is formed, for example, in a tapered shape in which the opening width (opening diameter) decreases from the upper side (the upper surface side of the upper substrate 40) to the lower side (the lower substrate 20 side) in FIG. 1(b). For example, each second through hole 46 is formed in an inverted truncated cone shape in which the opening diameter of the lower opening end is smaller than the opening diameter of the upper opening end. The inner surface of each second through hole 46 is formed, for example, to be inclined so as to approach the planar center of the second through hole 46 as it moves from the upper surface of the substrate main body 41 to the lower surface of the adhesive layer 42. The inner surface of each second through hole 46 is formed, for example, as an inclined plane that extends linearly without steps in the thickness direction of the substrate main body 41 and the adhesive layer 42. That is, in this example, the inner surface of each second through hole 46 is formed so as to be inclined at a certain angle. Note that the inner surface of each second through hole 46 does not need to be flat, and a part or all of the inner surface of the second through hole 46 may be a convexly curved surface or a concavely curved surface.

[0053] (Configuration of sealing resin 50) 1(a), the sealing resin 50 is formed to seal, for example, the semiconductor elements 30, the connecting members 75, and the bonding portions 71 and 72 provided between the lower substrate 20 and the upper substrate 40. The sealing resin 50 is formed to seal, for example, a plurality of semiconductor elements 30 collectively. The sealing resin 50 is formed to cover, for example, the side surfaces of each semiconductor element 30, the side surfaces of the connecting members 75, the upper surfaces of the bonding portions 71 exposed from each semiconductor element 30, the side surfaces of the bonding portions 71, the upper surfaces of the bonding portions 72 exposed from the connecting members 75, and the side surfaces of the bonding portions 72. The sealing resin 50 is formed to cover, for example, the side surfaces of the wiring layer 21 and the upper surface of the lower substrate 20 exposed from the wiring layer 21 in the portion overlapping with the upper substrate 40 in a plan view.

[0054] The sealing resin 50 is formed, for example, to cover a portion of the wiring layer 21 in a portion that does not overlap with the upper substrate 40 in a planar view. The sealing resin 50 is formed, for example, to expose a portion of the wiring layer 21 in a portion that does not overlap with the upper substrate 40 in a planar view. The sealing resin 50 is formed, for example, to cover a portion of the upper surface of the lower substrate 20 in a portion that does not overlap with the upper substrate 40 in a planar view. As shown in FIG. 2 , the sealing resin 50 is formed, for example, to expose a portion of the upper surface of the lower substrate 20 in a portion that does not overlap with the upper substrate 40 in a planar view. The sealing resin 50 covers, for example, the side surface of the lower substrate 20. The sealing resin 50 covers, for example, the entire side surface of the lower substrate 20. The sealing resin 50 covers, for example, the entire periphery of the side surface of the lower substrate 20. The sealing resin 50 is formed, for example, to surround the lower substrate 20 from the outside.

[0055] As shown in FIG. 1( a), the sealing resin 50 is formed, for example, to cover the lower surface of the lower substrate 20. The sealing resin 50 covers, for example, the entire lower surface of the lower substrate 20 exposed from the metal layer 26. The sealing resin 50 is formed, for example, to cover the side surfaces of the metal layer 26. The sealing resin 50 covers, for example, the entire side surfaces of the metal layer 26. The sealing resin 50 is formed, for example, to expose the lower surface of the metal layer 26. The lower surface of the sealing resin 50 is formed, for example, to be flush with the lower surface of the metal layer 26.

[0056] The sealing resin 50 is formed, for example, so as to cover the side surfaces of the upper substrate 40. The sealing resin 50 covers, for example, the entire side surfaces of the upper substrate 40. As shown in Fig. 2, the sealing resin 50 covers, for example, the entire periphery of the side surfaces of the upper substrate 40. The sealing resin 50 is formed, for example, so as to surround the upper substrate 40 from the outside.

[0057] The sealing resin 50 is formed, for example, to cover the upper surface of the upper substrate 40. The sealing resin 50 covers, for example, the entire upper surface of the upper substrate 40 exposed from the wiring layer 60. As shown in FIG. 1( a), the sealing resin 50 is formed, for example, to cover the side surfaces of the wiring layer 60. The sealing resin 50 covers, for example, the entire side surfaces of the wiring layer 60. The sealing resin 50 is in contact with, for example, the side surfaces of the wiring layer 60. The sealing resin 50 is formed, for example, to surround the wiring patterns 61 and 62. The sealing resin 50 is formed, for example, to expose the upper surface of the wiring layer 60. The upper surface of the sealing resin 50 is formed, for example, to be flush with the upper surface of the wiring layer 60.

[0058] As shown in FIG. 1( b), the sealing resin 50 is formed to fill the through hole 44. The sealing resin 50 is formed to fill the first through hole 45. The sealing resin 50 filled in the first through hole 45 is formed in the same shape as the first through hole 45 (inverted truncated cone shape in this example). The sealing resin 50 filled in the first through hole 45 is formed to continuously cover the adhesive layer 42 constituting the inner surface of the first through hole 45, the substrate main body 41 constituting the inner surface of the first through hole 45, and the wiring pattern 61 constituting the inner surface of the first through hole 45. The sealing resin 50 filled in the first through hole 45 is in contact with the inner surface of the first through hole 45. The sealing resin 50 filled in the first through hole 45 is formed, for example, continuously and integrally with the sealing resin 50 of the portion that seals the semiconductor element 30. For example, the sealing resin 50 filled in the first through hole 45 is formed integrally and continuously with the sealing resin 50 of the portion covering the side surface of the semiconductor element 30. The upper surface of the sealing resin 50 filled in the first through hole 45 is formed to be flush with the upper surface of the wiring layer 60, for example.

[0059] The sealing resin 50 is formed to fill the second through hole 46. The sealing resin 50 filled in the second through hole 46 is formed in the same shape as the second through hole 46 (inverted truncated cone shape in this example). The sealing resin 50 filled in the second through hole 46 is formed to continuously cover the substrate main body 41 that forms the inner surface of the second through hole 46 and the adhesive layer 42 that forms the inner surface of the second through hole 46. The sealing resin 50 filled in the second through hole 46 is in contact with the inner surface of the second through hole 46. The sealing resin 50 filled in the second through hole 46 is, for example, formed integrally and continuously with the sealing resin 50 covering the lower surface of the upper substrate 40, and is also formed integrally and continuously with the sealing resin 50 covering the upper surface of the upper substrate 40. In other words, the sealing resin 50 covering the lower surface of the upper substrate 40 and the sealing resin 50 covering the upper surface of the upper substrate 40 are formed integrally through the sealing resin 50 filled in the second through hole 46. In other words, the sealing resin 50 filled in the second through-holes 46 connects the sealing resin 50 covering the lower surface of the upper substrate 40 with the sealing resin 50 covering the upper surface of the upper substrate 40 .

[0060] 1(a), the sealing resin 50 has, for example, an extension portion 51 extending in a planar direction (left-right direction in the figure) from a side surface 50S of a portion covering the wiring layer 21 exposed from the upper substrate 40. The extension portion 51 is formed, for example, so as to cover the upper surface of the wiring pattern 22 of the wiring layer 21. As shown in FIG. 2, the extension portion 51 extends, for example, from the side surface 50S to the outer surface of the semiconductor device 10. The extension portion 51 has, for example, a predetermined width in the up-down direction in the figure and is formed in a strip shape extending left-right in the figure.

[0061] The sealing resin 50 may be made of, for example, a non-photosensitive insulating resin containing a thermosetting resin as its main component. The sealing resin 50 may be made of, for example, an insulating resin such as an epoxy resin or a polyimide resin, or a resin material obtained by mixing a filler such as silica or alumina into such a resin. The sealing resin 50 may be made of, for example, a mold resin. The thermal expansion coefficient of the sealing resin 50 may be, for example, in the range of 5 ppm / °C to 18 ppm / °C.

[0062] 1(a) is drawn out beyond the sealing resin 50 via a wiring pattern 22. The electrode pad 32 is drawn out beyond the sealing resin 50 via a wiring pattern 61 and a wiring pattern 23 (see FIG. 3). The electrode pad 33 is drawn out beyond the sealing resin 50 via a wiring pattern 62 and a wiring pattern 24. The wiring patterns 22, 23, and 24 drawn out beyond the sealing resin 50 and exposed from the sealing resin 50 function as test pads. For example, a probe pin (not shown) of an electrical characteristic measuring device is brought into contact with the test pads.

[0063] (Method of manufacturing the semiconductor device 10) Next, a description will be given of a method for manufacturing the semiconductor device 10. For convenience of explanation, the parts that will ultimately become the components of the semiconductor device 10 will be described using the reference numerals of the final components.

[0064] 6(a), a lower substrate 20 is prepared, having a wiring layer 21 formed on its upper surface and a metal layer 26 formed on its lower surface. At this time, the wiring layer 21 has a wiring pattern 22, a wiring pattern 23 (see FIG. 3), and a wiring pattern 24.

[0065] 6(b), bonding portions 71 and 72 are formed on the upper surface of the wiring layer 21. The bonding portions 71 and 72 can be formed, for example, by applying a paste-like sintering material (sintering paste) by a printing method or a dispenser method. As the sintering paste, for example, a silver sintering paste in which silver particles are dispersed in an organic solvent can be used. As the printing method, for example, a screen printing method or a stencil printing method can be used.

[0066] Next, the semiconductor element 30 is placed on the upper surface of the bonding portion 71, and the connecting member 75 is placed on the upper surface of the bonding portion 72. At this time, the semiconductor element 30 is placed on the upper surface of the bonding portion 71 so that the electrode pads 31 formed on the lower surface of the semiconductor element 30 contact the upper surface of the bonding portion 71.

[0067] Next, the bonding portions 71, 72 are heated to sinter the bonding portions 71, 72. As a result, the wiring pattern 22 of the wiring layer 21 and the electrode pad 31 of the semiconductor element 30 are bonded by the bonding portions 71, and the semiconductor element 30 is bonded onto the wiring pattern 22 via the bonding portions 71. Furthermore, the wiring patterns 23, 24 (see FIG. 5) of the wiring layer 21 and the connecting member 75 are bonded by the bonding portions 72, and the connecting member 75 is bonded onto the wiring patterns 23, 24 via the bonding portions 72.

[0068] 7(a), the upper substrate 40 is mounted on the upper surfaces of the semiconductor element 30 and the connecting member 75. For example, the upper substrate 40 is bonded to the upper surfaces of the semiconductor element 30 and the connecting member 75 by the adhesive layer 42 shown in FIG. 1(b). For example, the sheet-like upper substrate 40 is laminated on the upper surfaces of the semiconductor element 30 and the connecting member 75 by thermocompression bonding.

[0069] Next, openings 43 are formed in required locations on the upper substrate 40 so that portions of the upper surfaces of the electrode pads 32, 33 of the semiconductor element 30 are exposed, and openings 43 are also formed in required locations on the upper substrate 40 so that portions of the upper surface of the connecting member 75 are exposed. The openings 43 can be formed by laser processing using, for example, a CO2 laser, a UV-YAG laser, or the like. Next, if the openings 43 have been formed by laser processing, a desmearing process is performed to remove resin smears adhering to the exposed surfaces of the electrode pads 32, 33 and the connecting member 75 exposed at the bottom of the openings 43.

[0070] Next, via wirings V1 to V4 are formed in the openings 43, and a wiring layer 60 electrically connected to the electrode pads 32, 33 or the connection member 75 through the via wirings V1 to V4 is formed on the upper surface of the upper substrate 40. At this time, the wiring layer 60 has a wiring pattern 61 and a wiring pattern 62. The via wirings V1 to V4 and the wiring layer 60 can be formed using various wiring formation methods, such as a semi-additive method.

[0071] Next, through holes 44 are formed in required locations of the upper substrate 40. For example, first through holes 45 are formed in required locations of the upper substrate 40 and the wiring layer 60, penetrating the upper substrate 40 and the wiring layer 60 in the thickness direction. Furthermore, second through holes 46 are formed in required locations of the upper substrate 40 exposed from the wiring layer 60, penetrating the upper substrate 40 in the thickness direction. The first through holes 45 and the second through holes 46 can be formed by, for example, punching or laser processing. Note that the second through holes 46 may be formed simultaneously with, for example, the openings 43. Furthermore, after the wiring layer 60, the via wirings V1 to V4, the first through holes 45, and the second through holes 46 are formed in the upper substrate 40, the upper substrate 40 may be mounted on the upper surface of the semiconductor element 30 and the upper surface of the connecting member 75.

[0072] Next, in the step shown in FIG. 7( b), a sealing resin 50 is formed to seal the semiconductor element 30 and the connecting member 75, etc., provided between the lower substrate 20 and the upper substrate 40, cover the upper surface of the upper substrate 40, and fill the through-holes 44. The sealing resin 50 is formed, for example, to cover the entire upper substrate 40 and the side and lower surfaces of the lower substrate 20. The sealing resin 50 is formed, for example, to fill the first through-holes 45 and the second through-holes 46. The sealing resin 50 can be formed, for example, by a resin molding method. For example, when a thermosetting molding resin is used as the material for the sealing resin 50, the structure shown in FIG. 7( a) is placed on the lower mold of a mold consisting of a pair of upper and lower molds, and the structure is housed in the mold by being sandwiched between the upper and lower molds from above. Next, pressure (for example, a pressure in the range of 5 MPa to 10 MPa) is applied to introduce the fluidized molding resin into the mold through a gate portion (not shown) of the mold. The molding resin is then heated to a temperature of approximately 180°C to harden, thereby forming the sealing resin 50. At this time, although not shown, the mold has a passageway connecting the region where the sealing resin 50 covering the side surfaces of the lower substrate 20 is formed and the region where the sealing resin 50 covering the entire upper substrate 40 is formed. By introducing the molding resin into this passageway, an extension 51 is formed in the sealing resin 50. Although not shown, the upper mold is in contact with the upper surface of the wiring layer 60, and the lower mold is in contact with the lower surface of the metal layer 26. The molding resin introduced into the mold is introduced into the space surrounded by the upper and lower molds through the passageway and spreads within the space. For example, the molding resin spreads into the space between the lower substrate 20 and the upper substrate 40, as well as into the space between the upper substrate 40 and the upper mold. The molding resin that spreads into the space between the lower substrate 20 and the upper substrate 40 also spreads into the space between the upper substrate 40 and the upper mold through the second through-hole 46. This allows the molding resin to flow into the space between the upper substrate 40 and the upper mold through the second through-holes 46. This allows the molding resin to be suitably filled into the narrow space that exists between the upper substrate 40 and the upper mold, for example, the narrow space between the wiring patterns 61 and 62.After the required sealing process is completed, the structure with the sealing resin 50 formed thereon is removed from the mold. Note that the method of filling the mold resin may be, for example, a transfer molding method, a compression molding method, or an injection molding method.

[0073] The semiconductor device 10 of this embodiment can be manufactured by the above manufacturing process. The semiconductor device 10 can be used upside down or placed at any angle.

[0074] Next, the effects of this embodiment will be described. (1) The upper substrate 40 has a through hole 44 penetrating the upper substrate 40 in the thickness direction. The sealing resin 50 that seals the semiconductor element 30 disposed between the lower substrate 20 and the upper substrate 40 is formed to cover the upper surface of the upper substrate 40 and fill the through hole 44. With this configuration, both the top and bottom surfaces of the upper substrate 40 are covered with the sealing resin 50, and the upper substrate 40 that forms the inner surface of the through hole 44 is also covered with the sealing resin 50. This allows the upper substrate 40 to be sandwiched between the sealing resins 50 from above and below, and allows the upper substrate 40 and the sealing resin 50 to be connected in the thickness direction of the upper substrate 40. Therefore, the sealing resin 50 can physically prevent movement of the upper substrate 40 in each direction (thickness direction and planar direction). Therefore, when heat is applied to the semiconductor device 10, for example, during a temperature cycle test, distortion of the upper substrate 40 caused by the difference in thermal expansion coefficients between the semiconductor element 30 and the upper substrate 40 can be alleviated. As a result, the upper substrate 40 can be effectively prevented from peeling off from the semiconductor element 30 .

[0075] (2) Furthermore, since it is possible to alleviate distortion of the upper substrate 40 caused by the difference in thermal expansion coefficient between the semiconductor element 30 and the upper substrate 40 and the sealing resin 50, it is possible to prevent cracks from occurring in the wiring layer 60 formed on the upper surface of the upper substrate 40. Furthermore, since it is possible to alleviate distortion of the upper substrate 40, it is possible to reduce stress acting on the via wirings V1 to V4 caused by the distortion. This makes it possible to prevent cracks from occurring in the via wirings V1 to V4.

[0076] (3) The upper substrate 40 has a substrate main body 41 and an adhesive layer 42 provided on the lower surface of the substrate main body 41. The through-hole 44 is formed to penetrate the substrate main body 41 and the adhesive layer 42 in the thickness direction. With this configuration, the substrate main body 41 and the adhesive layer 42, which form the inner surface of the through-hole 44, are covered with the sealing resin 50. This allows the substrate main body 41 and the adhesive layer 42 to be sandwiched between the sealing resin 50 from above and below, and allows the substrate main body 41 and the adhesive layer 42 to be connected to the sealing resin 50 in the thickness direction of the upper substrate 40. This makes it possible to alleviate distortion of the adhesive layer 42 caused by the difference in thermal expansion coefficient between the semiconductor element 30 and the adhesive layer 42, and effectively prevents the upper substrate 40 from peeling off from the semiconductor element 30.

[0077] (4) The through holes 44 include first through holes 45 provided around the semiconductor element 30 in a plan view. The first through holes 45 penetrate the wiring layer 60 and the upper substrate 40 in the thickness direction. With this configuration, the first through holes 45 are provided around the semiconductor element 30, where thermal stress is likely to occur due to the difference in thermal expansion coefficients between the semiconductor element 30 and the upper substrate 40, and the first through holes 45 are filled with sealing resin 50. The first through holes 45 and the sealing resin 50 filled in the first through holes 45 can suitably alleviate distortion of the upper substrate 40 caused by the difference in thermal expansion coefficients between the semiconductor element 30 and the upper substrate 40. As a result, peeling of the upper substrate 40 from the semiconductor element 30 can be more suitably prevented.

[0078] (5) The semiconductor element 30 has a rectangular planar shape. The through holes 44 have, in a planar view, at least a first through hole 45 provided corresponding to the corner of the semiconductor element 30 that is located furthest outward from the upper substrate 40 among the four corners of the semiconductor element 30. According to this configuration, the first through hole 45 is provided around the corner of the semiconductor element 30 that is most likely to experience thermal stress concentration among the four corners, and the first through hole 45 is filled with a sealing resin 50. The first through hole 45 and the sealing resin 50 can effectively alleviate distortion of the upper substrate 40 that occurs due to the difference in thermal expansion coefficient between the semiconductor element 30 and the upper substrate 40.

[0079] (6) The first through holes 45 are provided corresponding to each of the four corners of the semiconductor element 30. That is, the first through holes 45 are provided around each of the four corners of the semiconductor element 30. According to this configuration, the first through holes 45 are provided around the corners of the semiconductor element 30 where thermal stress is likely to concentrate in the peripheral region of the semiconductor element 30, and the first through holes 45 are filled with the sealing resin 50. The first through holes 45 and the sealing resin 50 can suitably alleviate distortion of the upper substrate 40 caused by the difference in thermal expansion coefficient between the semiconductor element 30 and the upper substrate 40.

[0080] (7) The through hole 44 has a second through hole 46 provided around the wiring layer 60 at a position that does not overlap with the wiring layer 60 in a plan view. The second through hole 46 penetrates the upper substrate 40 in the thickness direction. The sealing resin 50 is formed to fill the second through hole 46. With this configuration, the sealing resin 50 filled in the second through hole 46 and the sealing resin 50 covering the upper surface of the upper substrate 40 are formed continuously. This allows the sealing resin 50 covering the upper surface of the upper substrate 40 to be connected to the sealing resin 50 sealing the semiconductor element 30 through the sealing resin 50 filled in the second through hole 46. In other words, the sealing resins 50 sandwiching the upper substrate 40 from above and below can be connected by the sealing resin 50 filled in the second through hole 46. Therefore, the sealing resin 50 can effectively inhibit movement of the upper substrate 40 in each direction. This can effectively alleviate distortion of the upper substrate 40 caused by the difference in thermal expansion coefficient between the semiconductor element 30 and the upper substrate 40.

[0081] (8) By providing the second through holes 46, it is possible to improve the wraparound of the molding resin when forming the sealing resin 50, for example. This allows the molding resin to be suitably filled into narrow spaces formed, for example, between the wiring patterns 61 and 62. Therefore, even when a molding resin with low fluidity (i.e., high viscosity) is used, it is possible to suitably fill the desired space with the molding resin. In other words, by providing the second through holes 46, it is possible to form the sealing resin 50 using a molding resin with low fluidity, for example, even when a narrow space exists between the wiring patterns 61 and 62. This improves the degree of freedom in selecting the material of the molding resin.

[0082] (9) The second through-holes 46 penetrate the upper substrate 40 in the thickness direction. This configuration allows gas to escape more easily through the second through-holes 46. For example, in the manufacturing process of the semiconductor device 10, gas generated inside the sealing resin 50, etc. during heating can be released to the outside through the second through-holes 46. This makes it possible to effectively prevent voids from occurring inside the sealing resin 50.

[0083] (10) The side surfaces of the wiring layer 60 are covered with the sealing resin 50. Therefore, the movement of the wiring layer 60 can be physically hindered by the sealing resin 50. This can alleviate distortion of the wiring layer 60, thereby preferably suppressing the occurrence of cracks in the wiring layer 60.

[0084] (11) The portion that seals the semiconductor element 30, the portion that covers the upper surface of the upper substrate 40, and the portion that fills the through-holes 44 are integrally formed with a single layer of sealing resin 50. With this configuration, the upper substrate 40 can be sandwiched from above and below with the same sealing resin 50, and the through-holes 44 can be filled. This makes it possible to effectively alleviate distortion of the upper substrate 40 that occurs due to differences in the thermal expansion coefficients of the semiconductor element 30, the upper substrate 40, and the sealing resin 50. This makes it possible to effectively prevent the upper substrate 40 from peeling off from the semiconductor element 30.

[0085] (12) The through holes 44 are formed in a tapered shape such that the opening width decreases from the upper surface side of the upper substrate 40 toward the lower substrate 20. The sealing resin 50 filled in the through holes 44 is formed in the same tapered shape as the through holes 44. Therefore, the sealing resin 50 filled in the through holes 44 is formed so as to overlap the upper part of the upper substrate 40 that forms the inner surface of the through holes 44. Therefore, the upward movement of the upper substrate 40 is restricted by the sealing resin 50 filled in the through holes 44, and peeling of the upper substrate 40 from the semiconductor element 30 can be suitably prevented.

[0086] (13) The sealing resin 50 is formed to cover the side surfaces of the upper substrate 40. With this configuration, the sealing resin 50 can surround the outer periphery of the upper substrate 40. Therefore, distortion of the upper substrate 40 caused by differences in the thermal expansion coefficients of the semiconductor element 30, the upper substrate 40, and the sealing resin 50 can be suitably alleviated.

[0087] (14) The sealing resin 50 is formed to cover the side surfaces of the lower substrate 20 and the lower surface of the lower substrate 20. With this configuration, the sealing resin 50 can surround the outer periphery of the lower substrate 20. Therefore, distortion of the lower substrate 20 due to the difference in thermal expansion coefficient between the semiconductor element 30 and the sealing resin 50 can be effectively suppressed.

[0088] (Other embodiments) The above embodiment can be modified as follows: The above embodiment and the following modifications can be combined with each other within the scope of technical compatibility.

[0089] 8, a solder resist layer 80 that covers the upper surface of the wiring layer 60 may be formed on the upper surface of the sealing resin 50. The solder resist layer 80 is formed, for example, so as to cover the upper surface of the sealing resin 50 that is formed flush with the upper surface of the wiring layer 60. The solder resist layer 80 has openings 80X that penetrate the solder resist layer 80 in the thickness direction, for example, and expose part of the upper surface of the wiring layer 60 as external connection pads P1.

[0090] According to this configuration, the upper surface of the wiring layer 60 and the upper surface of the sealing resin 50 are formed flush with each other, so that the thickness of the solder resist layer 80 formed on the upper surfaces of the wiring layer 60 and the sealing resin 50 can be made uniform.

[0091] As shown in FIG. 8, external connection terminals 81 used when mounting the semiconductor device 10 on a mounting substrate (not shown) such as a motherboard may be provided on the upper surface of the wiring layer 60 exposed at the bottom of the opening 80X, i.e., on the external connection pads P1. The external connection terminals 81 are, for example, connection terminals that are electrically connected to pads provided on the mounting substrate. For example, solder balls or lead pins can be used as the external connection terminals 81. In this modified example, solder balls are used as the external connection terminals 81.

[0092] 9, a sealing resin 50 may be formed to cover the upper surface of the wiring layer 60. For example, openings 50X are formed in the sealing resin 50 to expose parts of the upper surface of the wiring layer 60 as external connection pads P1. External connection terminals 81 may be provided on the external connection pads P1.

[0093] As shown in FIG. 10, the opening 50X is formed, for example, to expose a portion of the upper surface of the main body 61A of the wiring pattern 61. The opening 50X is formed, for example, to expose a portion of the upper surface at the tip of each extension portion 61B of the wiring pattern 61. The opening 50X is formed, for example, to expose a portion of the upper surface at the second end of each wiring pattern 62. The planar shape of each opening 50X can be formed to any shape and any size. The planar shape of each opening 50X is formed, for example, to be circular. The opening 80X shown in FIG. 8 is also formed in the same manner as the opening 50X.

[0094] According to this configuration, the upper surface of the wiring layer 60 is covered with the sealing resin 50, and the openings 50X are formed in the sealing resin 50, so that the formation of the solder resist layer 80 shown in FIG. 8 can be omitted.

[0095] As shown in FIG. 11 , the wiring patterns 23, 24 formed on the upper surface of the lower substrate 20 may be omitted. That is, the wiring patterns 23, 24 for drawing the wiring patterns 61, 62 electrically connected to the electrode pads 32, 33 (see FIG. 1(a)) of the semiconductor element 30 to the outside of the sealing resin 50 may be omitted. In this case, the connecting member 75 shown in FIG. 1(a) can be omitted. Also, in this case, for example, the wiring patterns 61, 62 exposed from the opening 50X may be used as test pads. Alternatively, openings may be provided in the sealing resin 50 or the solder resist layer 80 (see FIG. 8) in addition to the opening 50X to expose portions of the upper surfaces of the wiring patterns 61, 62 as test pads.

[0096] In the above embodiment, the portion of the wiring pattern 22 that is drawn outward beyond the sealing resin 50 may be omitted. Also, the portion of the wiring pattern 22 that is drawn outward beyond the upper substrate 40 may be omitted.

[0097] In the above embodiment, the upper substrate 40 is formed to have a smaller planar shape than the lower substrate 20, but this is not limiting. For example, the upper substrate 40 may be formed to have a larger planar shape than the lower substrate 20.

[0098] 12, the planar shape of the upper substrate 40 may be formed to be the same size as the planar shape of the lower substrate 20. For example, the planar shape of the upper substrate 40 may be formed to be the same shape and size as the planar shape of the lower substrate 20. The upper substrate 40 of this modified example is provided so that its entirety overlaps the lower substrate 20 in a plan view.

[0099] In the above embodiment, the sealing resin 50 that seals the semiconductor element 30 provided between the lower substrate 20 and the upper substrate 40 is formed so as to cover the upper surface of the upper substrate 40 and fill the through-holes 44. In other words, the portion that seals the semiconductor element 30, the portion that covers the upper surface of the upper substrate 40, and the portion that fills the through-holes 44 are integrally formed by a single layer of sealing resin 50. However, the present invention is not limited to this.

[0100] For example, as shown in FIG. 13 , a coating resin 90 may be provided that covers the upper surface of the upper substrate 40 and fills the through holes 44, separate from the sealing resin 50 that seals the semiconductor element 30. That is, the sealing resin 50 that seals the semiconductor element 30 and the coating resin 90 that covers the upper surface of the upper substrate 40 and fills the through holes 44 may be formed as separate components. In this case, the material for the coating resin 90 may be, for example, a different material from that of the sealing resin 50, or the same material as that of the sealing resin 50. For example, the material for the coating resin 90 may have a thermal expansion coefficient similar to that of the sealing resin 50. Here, in this specification, the term "similar" in "similar thermal expansion coefficient" refers to a difference between the thermal expansion coefficients of the sealing resin 50 and the coating resin 90 of 10 ppm / °C or less. The thermal expansion coefficient of the coating resin 90 may be, for example, in the range of 5 ppm / °C to 28 ppm / °C. For example, the thermal expansion coefficient of the coating resin 90 is set so that the difference between the thermal expansion coefficient of the coating resin 90 and the thermal expansion coefficient of the sealing resin 50 is smaller than the difference between the thermal expansion coefficient of the coating resin 90 and the thermal expansion coefficient of the semiconductor element 30. For example, the thermal expansion coefficient of the coating resin 90 is set so that the difference between the thermal expansion coefficient of the coating resin 90 and the thermal expansion coefficient of the sealing resin 50 is smaller than the difference between the thermal expansion coefficient of the coating resin 90 and the thermal expansion coefficient of the upper substrate 40. The material for the coating resin 90 can be, for example, a non-photosensitive insulating resin containing a thermosetting resin as its main component. The material for the coating resin 90 can be, for example, an insulating resin such as an epoxy resin or a polyimide resin, or a resin material obtained by mixing a filler such as silica or alumina into such a resin. The coating resin 90 can be, for example, a molding resin, an underfill resin, or a potting resin. The coating resin 90 can be formed by, for example, a resin molding method or a potting method.

[0101] The coating resin 90 of this modified example is formed to cover the upper surface of the upper substrate 40 and fill the through holes 44. The coating resin 90, for example, covers the entire upper surface of the sealing resin 50 exposed at the bottom of the through holes 44. The coating resin 90, for example, is formed to cover the entire upper surface of the upper substrate 40 exposed from the wiring layer 60. The coating resin 90, for example, covers the entire side surface of the wiring layer 60. The coating resin 90 is in contact with the side surface of the wiring layer 60. The coating resin 90, for example, is formed to expose the upper surface of the wiring layer 60. The upper surface of the coating resin 90 is formed, for example, to be flush with the upper surface of the wiring layer 60.

[0102] According to this configuration, the upper substrate 40 can be sandwiched from above and below by the sealing resin 50 that seals the semiconductor element 30 provided between the lower substrate 20 and the upper substrate 40, and the coating resin 90 that coats the upper surface of the upper substrate 40. Furthermore, the coating resin 90 filled in the through hole 44 can coat the upper substrate 40 that forms the inner surface of the through hole 44. Therefore, the sealing resin 50 and the coating resin 90 can physically inhibit movement of the upper substrate 40 in each direction. Therefore, when heat is applied to the semiconductor device 10 during, for example, a temperature cycle test, distortion of the upper substrate 40 caused by the difference in thermal expansion coefficients between the semiconductor element 30 and the upper substrate 40 can be alleviated. As a result, peeling of the upper substrate 40 from the semiconductor element 30 can be effectively prevented.

[0103] Furthermore, since the sealing resin 50 and the coating resin 90 are made of separate members, it is possible to improve the degree of freedom in selecting the materials for the sealing resin 50 and the coating resin 90. Furthermore, since the sealing resin 50 and the coating resin 90 are made of separate members, it is possible to improve the degree of freedom in selecting the shapes of the sealing resin 50 and the coating resin 90.

[0104] 13, the upper surface of the coating resin 90 is formed to be flush with the upper surface of the wiring layer 60, but the coating resin 90 may be formed to cover the upper surface of the wiring layer 60. In this case, for example, an opening is formed in the coating resin 90 to expose a part of the upper surface of the wiring layer 60 as a pad for external connection.

[0105] The upper surface of the coating resin 90 may be located lower than the upper surface of the wiring layer 60. In this case, the coating resin 90 is formed so as to cover part of the side surface of the wiring layer 60 in the stacking direction of the semiconductor device 10 (the up-down direction in the figure). In other words, the coating resin 90 is formed so as to expose the side surface of the upper part of the wiring layer 60 in the stacking direction of the semiconductor device 10.

[0106] As shown in FIG. 13 , an insulating resin 91 that covers the lower surface of the lower substrate 20 may be provided separately from the sealing resin 50 that seals the semiconductor element 30. That is, the sealing resin 50 that seals the semiconductor element 30 and the insulating resin 91 that covers the lower surface of the lower substrate 20 may be formed as separate members. In this case, the insulating resin 91 may be made of, for example, a material different from that of the sealing resin 50, or the same material as that of the sealing resin 50. For example, a material having a thermal expansion coefficient similar to that of the sealing resin 50 may be used as the material for the insulating resin 91. The thermal expansion coefficient of the insulating resin 91 may be, for example, in the range of 5 ppm / °C to 28 ppm / °C. For example, the insulating resin 91 may be made of the same material as that of the coating resin 90. The insulating resin 91 may be formed by, for example, a resin molding method or a potting method.

[0107] The insulating resin 91 is formed, for example, so as to cover the side surfaces of the metal layer 26. The insulating resin 91 covers, for example, the entire side surfaces of the metal layer 26. The insulating resin 91 is formed, for example, so as to expose the lower surface of the metal layer 26. The lower surface of the insulating resin 91 is formed, for example, so as to be flush with the lower surface of the metal layer 26. The insulating resin 91 is formed, for example, so as to cover the entire lower surface of the lower substrate 20 that is exposed from the metal layer 26.

[0108] In the modification shown in FIG. 13, an insulating resin 91 may be formed so as to cover the lower surface of the metal layer 26. In the above embodiment, the sealing resin 50 may be formed so as to cover the lower surface of the metal layer 26 .

[0109] In the above embodiment, the sealing resin 50 is formed so as to cover the side surface of the lower substrate 20, but this is not limiting. For example, as shown in FIG. 13, the sealing resin 50 may be formed so as to expose the side surface of the lower substrate 20. In this case, the side surface of the sealing resin 50 is formed so as to be flush with the side surface of the lower substrate 20. In the modified example shown in FIG. 13, the side surface of the insulating resin 91 covering the lower surface of the lower substrate 20 is formed so as to be flush with the side surface of the lower substrate 20.

[0110] In the above embodiment, the sealing resin 50 is formed so as to cover the side surface of the upper substrate 40, but this is not limiting. For example, as shown in FIG. 13, the sealing resin 50 may be formed so as to expose the side surface of the upper substrate 40. In this case, the side surface of the sealing resin 50 is formed so as to be flush with the side surface of the upper substrate 40. In the modified example shown in FIG. 13, the side surface of the coating resin 90 formed on the top surface of the upper substrate 40 is formed so as to be flush with the side surface of the upper substrate 40.

[0111] In the modified example shown in FIG. 13 , the sealing resin 50 that seals the semiconductor element 30, the coating resin 90 that covers the upper surface of the upper substrate 40 and fills the through holes 44, and the insulating resin 91 that covers the lower surface of the lower substrate 20 are each formed as separate members, but this is not limiting. For example, of the sealing resin 50, the coating resin 90, and the insulating resin 91, the sealing resin 50 and the coating resin 90 may be formed integrally. Here, for example, if the sealing resin 50 and the coating resin 90 are formed so that the side surface of the upper substrate 40 is exposed, the side surface of the upper substrate 40 is covered by a mold when the sealing resin 50 and the coating resin 90 are formed. Therefore, if the second through holes 46 are not formed in the upper substrate 40, the sealing resin 50 and the coating resin 90 must be formed separately. In contrast, in the semiconductor device 10 shown in FIG. 13 , the second through holes 46 (see FIG. 1 ) are provided in the upper substrate 40, so that the sealing resin 50 flowing into the space between the lower substrate 20 and the upper substrate 40 can flow around to the upper surface of the upper substrate 40 through the second through holes 46. The upper surface of the upper substrate 40 and the side surfaces of the wiring layer 60 can be covered with the sealing resin 50 that has flowed around to the upper surface of the upper substrate 40 through the second through holes 46. This eliminates the need to separately form the sealing resin 50 and the coating resin 90, and allows the sealing resin 50 and the coating resin 90 to be formed integrally. In other words, even in a semiconductor device 10 in which the entire side surface of the upper substrate 40 is exposed and not sealed, the upper and lower surfaces of the upper substrate 40 can be sealed integrally with the single sealing resin 50.

[0112] In the modification shown in FIG. 13, insulating resin 91 may be formed so as to cover the side surfaces of lower substrate 20. In the modification shown in FIG. 13, the coating resin 90 may be formed so as to cover the side surface of the upper substrate 40.

[0113] In the modification shown in FIG. 13, the coating resin 90 is formed so as to cover the entire upper surface of the upper substrate 40 exposed from the wiring layer 60, but the present invention is not limited to this. 14, for example, the coating resin 90 may be formed so as to cover only a portion of the upper surface of the upper substrate 40 that is exposed from the wiring layer 60. Even in this case, the coating resin 90 is formed so as to fill the through holes 44. Furthermore, the coating resin 90 in this modified example is formed so as to come into contact with and cover the side surfaces of the wiring layer 60.

[0114] 15, for example, the coating resin 90 may be formed so as to surround the outer periphery of the wiring patterns 61, 62 in a plan view. The coating resin 90 in this modified example is formed so as to expose a part of the upper surface of the upper substrate 40. The coating resin 90 is formed so as to expose, for example, the outer peripheral edge portion of the upper surface of the upper substrate 40.

[0115] Even with this configuration, the effects (1) to (10) of the above embodiment can be obtained. Furthermore, since the amount of resin in the coating resin 90 can be reduced, the manufacturing cost of the semiconductor device 10 can be reduced.

[0116] The insulating resin 91 shown in FIGS. 13 and 14 may be omitted. As shown in FIG. 16, the metal layer 26 may be omitted. As shown in FIG. 16, the sealing resin 50 may be formed so as to expose the lower surface of the lower substrate 20.

[0117] As shown in FIG. 17 , the lower substrate 20 may be configured with a metal plate 27. In this case, for example, a semiconductor element 30 is mounted on the upper surface of the metal plate 27. The metal plate 27 may be made of, for example, copper or a copper alloy. If necessary, a surface treatment layer may be formed on the surface of the metal plate 27. Examples of the surface treatment layer include a metal layer such as an Au layer, a Ni layer / Au layer, or a Ni layer / Pd layer / Au layer. The thermal expansion coefficient of the metal plate 27 may be, for example, in the range of 15 ppm / °C to 18 ppm / °C.

[0118] According to this configuration, since the lower substrate 20 is made of the metal plate 27, the heat dissipation properties of the entire semiconductor device 10 can be improved. 17 may be used as wiring or electrodes. That is, the lower substrate 20 may be configured with wiring or electrodes.

[0119] 18 and 19, the lower substrate 20 may be configured with a wiring layer 28. With this configuration, compared to when a wiring layer is formed on the lower substrate 20 made of a ceramic substrate, the wiring layer 28 itself becomes the lower substrate 20, so that the ceramic substrate or the like can be omitted. As a result, the entire semiconductor device 10 can be made thinner.

[0120] As shown in FIG. 19 , the wiring layer 28 has, for example, wiring patterns 22, 23, and 24. The wiring patterns 22, 23, and 24 are, for example, spaced apart on the same plane. The thermal expansion coefficients of the wiring patterns 22, 23, and 24 can be, for example, in the range of 15 ppm / °C to 18 ppm / °C. In this modified example, the outer surfaces of the wiring layer 28 are formed so as to be exposed from the sealing resin 50. The outer surfaces of the wiring patterns 22, 23, and 24 are formed so as to be flush with the outer surface of the sealing resin 50. In other words, the wiring patterns 22, 23, and 24 in this modified example are not formed so as to extend outside the sealing resin 50. This allows the planar shape of the entire semiconductor device 10 to be reduced in size.

[0121] 18, the lower surface of the wiring layer 28 in this modified example is formed so as to be exposed from the sealing resin 50. The lower surface of the wiring layer 28 is formed so as to be flush with the lower surface of the sealing resin 50. As a result, the side surfaces and lower surface of the wiring layer 28 are exposed from the sealing resin 50, thereby improving the heat dissipation performance of the entire semiconductor device 10.

[0122] In the modification shown in FIG. 18, a sealing resin 50 may be formed so as to cover the outer surface of the wiring layer 28. In the modification shown in FIG. 18, the wiring patterns 22, 23, and 24 may be formed so as to extend beyond the sealing resin 50.

[0123] 18, a sealing resin 50 may be formed so as to cover the lower surface of the wiring layer 28. Also, a solder resist layer may be formed so as to cover the lower surface of the wiring layer 28. In this case, an opening may be provided in the sealing resin 50 or the solder resist layer to expose a part of the lower surface of the wiring layer 28 as an electrode pad.

[0124] The structure of the first through-hole 45 in the above embodiment is not particularly limited. For example, the inner surface of the first through-hole 45 may be formed to extend perpendicular to the top surface of the upper substrate 40. The structure of the second through-hole 46 in the above embodiment is not particularly limited. For example, the inner surface of the second through-hole 46 may be formed to extend perpendicular to the upper surface of the upper substrate 40.

[0125] In the above embodiment, there is no particular limitation on the number and positions of the through holes 44. For example, the through holes 44 may be provided around the main body 61A of the wiring pattern 61 in a plan view.

[0126] In the above embodiment, two first through holes 45 are provided between two semiconductor elements 30 in common to the two semiconductor elements 30, but the present invention is not limited to this. 20, for example, a first through hole 45 corresponding to the lower side of the semiconductor element 30 arranged on the upper side in the figure and a first through hole 45 corresponding to the upper side of the semiconductor element 30 arranged on the lower side in the figure may be separately provided. In the upper substrate 40 of this modified example, two first through holes 45 are provided on each of the lower side of the semiconductor element 30 arranged on the upper side in the figure and the upper side of the semiconductor element 30 arranged on the lower side in the figure. In other words, in the upper substrate 40 of this modified example, four first through holes 45 are provided between two semiconductor elements 30.

[0127] In the above embodiment, five second through holes 46 are provided between the two wiring patterns 62 in common to the two wiring patterns 62, but the present invention is not limited to this. 20, for example, second through holes 46 corresponding to the wiring pattern 62 arranged on the upper side in the figure and second through holes 46 corresponding to the wiring pattern 62 arranged on the lower side in the figure may be provided separately. In the upper substrate 40 of this modified example, five second through holes 46 are provided for each of the wiring pattern 62 arranged on the upper side in the figure and the wiring pattern 62 arranged on the lower side in the figure. In other words, in the upper substrate 40 of this modified example, ten second through holes 46 are provided between two wiring patterns 62.

[0128] In the upper substrate 40 of the above embodiment, the plurality of second through holes 46 are arranged in a line along the extending direction of the extending portion 61B and the wiring pattern 62, but the present invention is not limited to this. 21, the second through holes 46 may be provided, in plan view, only around the tip end of the extension portion 61B and the second end portion of the wiring pattern 62. For example, the second through holes 46 may be provided, in plan view, only around the connection member 75 (see FIG. 1(a)).

[0129] In the upper substrate 40 of the above embodiment, two first through holes 45 are provided corresponding to each of the four corners of each semiconductor element 30, but this is not limiting. For example, one first through hole 45 may be provided corresponding to each of the four corners of each semiconductor element 30. For example, first through holes 45 may be provided corresponding to only some of the four corners of each semiconductor element 30.

[0130] For example, as shown in FIG. 21, first through holes 45 may be provided corresponding to only two of the four corners of each semiconductor element 30 that are located on one diagonal line. For example, as shown in FIG. 22, first through holes 45 may be provided only in the corners of the four corners of each semiconductor element 30 that are located furthest outward on the upper substrate 40 .

[0131] In the upper substrate 40 of the above embodiment, the first through holes 45 are provided around the corners of each semiconductor element 30 in a plan view, but this is not limitative. The positions where the first through holes 45 are formed are not particularly limited as long as they are in the areas around each semiconductor element 30 in a plan view.

[0132] For example, as shown in FIG. 22, the second through-hole 46 may be omitted from the through-hole 44. In the above embodiment, two semiconductor elements 30 are mounted on the upper surface of the lower substrate 20, but the number of semiconductor elements 30 is not particularly limited. For example, one semiconductor element 30 may be mounted on the upper surface of the lower substrate 20. Furthermore, three or more semiconductor elements 30 may be mounted on the upper surface of the lower substrate 20.

[0133] In the above embodiment, the substrate body 41 of the upper substrate 40 has a single-layer structure, but is not limited to this. For example, the substrate body 41 may have a laminated structure in which one or more wiring layers and multiple insulating layers are laminated.

[0134] In the above embodiment, the semiconductor device 10 is embodied as a power semiconductor device, but is not limited thereto. For example, the semiconductor device 10 may be embodied as various semiconductor devices other than power semiconductor devices. For example, the semiconductor device 10 is not particularly limited in structure, function, etc., as long as it has a sealing resin 50 that seals the semiconductor element 30 provided between the lower substrate 20 and the upper substrate 40, and a wiring layer 60 formed on the upper surface of the upper substrate 40.

[0135] In the above embodiment, the semiconductor element 30 is embodied as a power semiconductor element, but is not limited to this. For example, the semiconductor element 30 may be embodied as various semiconductor elements other than power semiconductor elements.

[0136] In the above embodiment, the semiconductor element 30 has three electrode pads 31, 32, and 33, but the number of electrode pads 31, 32, and 33 is not particularly limited. For example, the present invention may be embodied in a semiconductor element having two electrode pads. In this case, if the two electrode pads are provided only on the upper surface of the semiconductor element, the wiring pattern 22 can be omitted. In this case, for example, the semiconductor element 30 is mounted on the upper surface of the lower substrate 20 via a bonding portion 71. [Explanation of symbols]

[0137] 10 Semiconductor devices 20 Lower board 30 Semiconductor elements 40 Upper board 41 Board body 42 Adhesive layer 44 through holes 45 First through hole 46 Second through hole 50 Sealing resin 50X opening 60 wiring layer 90 Coating Resin

Claims

1. A lower substrate; a semiconductor element mounted on the upper surface of the lower substrate; an upper substrate provided on an upper surface of the semiconductor element; a through hole penetrating the upper substrate in a thickness direction; a sealing resin provided between the lower substrate and the upper substrate and sealing the semiconductor element; a wiring layer provided on the upper surface of the upper substrate; a coating resin that covers the upper surface of the upper substrate and fills the through-holes, the upper substrate has a substrate body and an adhesive layer provided on a lower surface of the substrate body, The through-hole is formed so as to penetrate the substrate body and the adhesive layer in the thickness direction.

2. The semiconductor device according to claim 1 , wherein the upper surface of the semiconductor element is adhered to the adhesive layer.

3. the through holes include a first through hole provided along an outer periphery of the semiconductor element in a plan view, the first through-hole is formed to penetrate the wiring layer and the upper substrate in a thickness direction, 3. The semiconductor device according to claim 1, wherein the coating resin is formed so as to fill the first through hole.

4. The semiconductor element has a rectangular planar shape, 4. The semiconductor device according to claim 3, wherein the through holes include the first through hole provided along the corner that is positioned furthest outward from the upper substrate among four corners of the semiconductor element in a plan view.

5. The semiconductor device according to claim 4 , wherein the through holes include the first through holes provided along four corners of the semiconductor element in a plan view.

6. 6. The semiconductor device according to claim 4, wherein the through holes include two first through holes provided on each of four sides that define the outer shape of the semiconductor element in a plan view.

7. A semiconductor device described in any one of claims 3 to 6, wherein the first through hole is provided in a position that does not overlap with the semiconductor element in a planar view.

8. the through hole has a second through hole provided at a position not overlapping the wiring layer in a plan view and provided along an outer periphery of the wiring layer; the second through-hole is formed to penetrate the upper substrate in a thickness direction, The semiconductor device according to claim 1 , wherein the coating resin is formed so as to fill the second through hole.

9. 9. The semiconductor device according to claim 1, wherein the coating resin covers the entire upper surface of the upper substrate exposed from the wiring layer, and also covers side surfaces of the wiring layer.

10. the coating resin covers an upper surface of the wiring layer, 10. The semiconductor device according to claim 1, wherein the coating resin has an opening that exposes a part of the upper surface of the wiring layer.

11. The semiconductor device according to claim 1 , wherein the sealing resin and the coating resin are formed integrally and continuously.

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